Vovanium/stm32-ada
1
0
Fork 0
Code Issues Pull requests Projects Releases Wiki Activity

+ Examples/LCD_Demo utilize interrupts to wait for DMA2D

Browse source
This commit is contained in:
Vovanium 2021-11-24 17:02:18 +03:00
parent a40c45528c
commit 43c52fa192
1 changed files with 53 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

57
examples/lcd_demo/blit.adb
View file

@ -1,5 +1,7 @@
with System.Storage_Elements;
use type System.Storage_Elements.Storage_Offset;
with Ada.Interrupts.Names;
use Ada.Interrupts.Names;
--with System.Storage_Elements;
--use type System.Storage_Elements.Storage_Offset;
with Chip.Units;
use Chip.Units;
@ -15,7 +17,45 @@ use Pixels;
package body Blit is
protected Interrupts is
procedure Handler with Attach_Handler => DMA2D_Interrupt;
entry Wait_Event (Status : out Interrupt_Status_Register);
private
Event : Boolean := False;
Int_Status : Interrupt_Status_Register := (others => <>);
end Interrupts;
protected body Interrupts is
procedure Handler is
Status : constant Interrupt_Status_Register := DMA2D.ISR;
begin
DMA2D.IFCR := Status;
Int_Status := (
CEIF => Int_Status.CEIF or Status.CEIF,
CTCIF => Int_Status.CTCIF or Status.CTCIF,
CAEIF => Int_Status.CAEIF or Status.CAEIF,
TWIF => Int_Status.TWIF or Status.TWIF,
TCIF => Int_Status.TCIF or Status.TCIF,
TEIF => Int_Status.TEIF or Status.TEIF,
others => <>
);
Event := True;
end;
entry Wait_Event (Status : out Interrupt_Status_Register) when Event is
begin
Event := False;
Status := Int_Status;
Int_Status := (others => <>);
DMA2D.IFCR := Status;
end;
end Interrupts;
procedure Blit_Rect (Target : in out Pixels.Pixel_Array; X1, X2, Y1, Y2 : Integer; Color : STM32.Graphics.RGB888_Pixel) is
Status : Interrupt_Status_Register;
N : Natural := 0;
begin
DMA2D.OMAR := Target (Y1, X1)'Address;
@ -35,11 +75,12 @@ package body Blit is
end;
while DMA2D.CR.START loop
null;
Interrupts.Wait_Event (Status);
end loop;
end Blit_Rect;
procedure Copy_Rect (Target : in out Pixels.Pixel_Array; X1, X2, Y1, Y2, X1_Source, Y1_Source : Integer) is
Status : Interrupt_Status_Register;
begin
DMA2D.FGMAR := Target (Y1_Source, X1_Source)'Address;
DMA2D.FGOR := (LO => Target'Length(2) - (X2 - X1 + 1), others => <>);
@ -60,7 +101,7 @@ package body Blit is
end;
while DMA2D.CR.START loop
null;
Interrupts.Wait_Event (Status);
end loop;
end;
@ -70,4 +111,12 @@ begin
RCC.AHB1RSTR(Index.DMA2D) := True;
RCC.AHB1RSTR(Index.DMA2D) := False;
declare
R : Control_Register := DMA2D.CR;
begin
R.TCIE := True;
-- Enable other interrupts here if required
DMA2D.CR := R;
end;
end Blit;