* added base addresses to all written modules
This commit is contained in:
parent
23aa9b0233
commit
6f8e2b3b7d
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@ -25,6 +25,7 @@ package STM32.Address_Map is
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TIM12 : constant Address := APB1 + 16#1800#;
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TIM13 : constant Address := APB1 + 16#1C00#;
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TIM14 : constant Address := APB1 + 16#2000#;
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LPTIM1 : constant Address := APB1 + 16#2400#;
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RTC_and_BKP : constant Address := APB1 + 16#2800#;
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WWDG : constant Address := APB1 + 16#2C00#;
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IWDG : constant Address := APB1 + 16#3000#;
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@ -106,16 +107,19 @@ package STM32.Address_Map is
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-- AHB 3
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AHB3 : constant Address := To_Address (16#6000_0000#);
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FMC_Bank_1 : constant Address := To_Address (16#6000_0000#);
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FSMC_Bank1_1 : constant Address := To_Address (16#6000_0000#);
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FSMC_Bank1_2 : constant Address := To_Address (16#6400_0000#);
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FSMC_Bank1_3 : constant Address := To_Address (16#6800_0000#);
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FSMC_Bank1_4 : constant Address := To_Address (16#6C00_0000#);
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FMC_Bank_2 : constant Address := To_Address (16#7000_0000#);
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FMC_Bank_3 : constant Address := To_Address (16#8000_0000#);
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FMC_Bank_4 : constant Address := To_Address (16#9000_0000#);
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FMC_FSMC : constant Address := To_Address (16#A000_0000#);
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FMC_Bank_5 : constant Address := To_Address (16#C000_0000#);
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FMC_Bank_6 : constant Address := To_Address (16#D000_0000#);
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FMC_Bank_1 : constant Address := AHB3;
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FSMC_Bank1_1 : constant Address := FMC_Bank_1;
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FSMC_Bank1_2 : constant Address := FMC_Bank_1 + 16#0400_0000#;
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FSMC_Bank1_3 : constant Address := FMC_Bank_1 + 16#0800_0000#;
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FSMC_Bank1_4 : constant Address := FMC_Bank_1 + 16#0C00_0000#;
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FMC_Bank_2 : constant Address := AHB3 + 16#1000_0000#;
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FMC_Bank_3 : constant Address := AHB3 + 16#2000_0000#;
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FMC_Bank_4 : constant Address := AHB3 + 16#3000_0000#;
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FMC_FSMC : constant Address := AHB3 + 16#4000_0000#;
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FMC_Bank_5 : constant Address := AHB3 + 16#6000_0000#;
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FMC_Bank_6 : constant Address := AHB3 + 16#7000_0000#;
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CPU_Internal : constant Address := To_Address (16#E000_0000#);
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DBG : constant Address := CPU_Internal + 16#4_2000#;
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end STM32.Address_Map;
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@ -1,20 +1,28 @@
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package STM32.Debug with Pure is
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with STM32.Address_Map;
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-- Debug support
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package STM32.Debug is
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-- IDCODE
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DEV_ID_STM32F405 : constant := 16#413#;
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DEV_ID_STM32F407 : constant := 16#413#;
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DEV_ID_STM32F415 : constant := 16#413#;
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DEV_ID_STM32F417 : constant := 16#413#;
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DEV_ID_STM32F427 : constant := 16#419#;
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DEV_ID_STM32F429 : constant := 16#419#;
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DEV_ID_STM32F437 : constant := 16#419#;
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DEV_ID_STM32F439 : constant := 16#419#;
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type Device_ID is mod 2**12;
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DEV_ID_STM32F405 : constant Device_ID := 16#413#;
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DEV_ID_STM32F407 : constant Device_ID := 16#413#;
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DEV_ID_STM32F415 : constant Device_ID := 16#413#;
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DEV_ID_STM32F417 : constant Device_ID := 16#413#;
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DEV_ID_STM32F427 : constant Device_ID := 16#419#;
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DEV_ID_STM32F429 : constant Device_ID := 16#419#;
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DEV_ID_STM32F437 : constant Device_ID := 16#419#;
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DEV_ID_STM32F439 : constant Device_ID := 16#419#;
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type Revision_ID is range 0 .. 2**16 - 1;
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type Device_ID_Register is record
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DEV_ID : Integer range 0 .. 2**12 - 1; -- Device identifier
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Unused_12 : Integer range 0 .. 15;
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REV_ID : Integer range 0 .. 2**16 - 1; -- Revision identifier
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DEV_ID : Device_ID; -- Device identifier
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Unused_12 : Unused_4_Bits;
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REV_ID : Revision_ID; -- Revision identifier
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end record with Size => 32;
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for Device_ID_Register use record
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DEV_ID at 0 range 0 .. 11;
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@ -155,4 +163,6 @@ package STM32.Debug with Pure is
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APB2_FZ at 16#0C# range 0 .. 31;
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end record;
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DBG : DBG_Registers with Volatile, Import, Address => Address_Map.DBG;
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end STM32.Debug;
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@ -1,4 +1,8 @@
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package STM32.Direct_Memory_Access with Pure is
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with STM32.Address_Map;
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-- DMA Controller
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package STM32.Direct_Memory_Access is
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-- LISR, HISR, LIFCR, HIFCR
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-- This Register definition is a bit weird,
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@ -37,16 +41,16 @@ package STM32.Direct_Memory_Access with Pure is
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array (Integer range 0 .. 1) of Interrupt_Status_Register;
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-- SxCR
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type Data_Transfer_Direction is (
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Peripherial_to_Memory,
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Memory_to_Peripherial,
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Memory_to_Memory
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type Transfer_Direction is (
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Peripheral_to_Memory, -- Peripheral to Memory Transfer
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Memory_to_Peripheral, -- Memory to Peripheral Transfer
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Memory_to_Memory -- Memory to Memory Transfer (only available on DMA2)
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) with Size => 2;
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for Data_Transfer_Direction use (
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Peripherial_to_Memory => 2#00#,
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Memory_to_Peripherial => 2#01#,
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Memory_to_Memory => 2#10#
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for Transfer_Direction use (
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Peripheral_to_Memory => 2#00#,
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Memory_to_Peripheral => 2#01#,
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Memory_to_Memory => 2#10#
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);
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type Data_Size is (
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@ -61,6 +65,10 @@ package STM32.Direct_Memory_Access with Pure is
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Word => 2#10#
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);
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subtype Priority_Level is Integer range 0 .. 3;
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subtype Target_Memory is Integer range 0 .. 1;
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type Burst_Transfer is (
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Single,
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INCR4,
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@ -68,59 +76,54 @@ package STM32.Direct_Memory_Access with Pure is
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INCR16
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) with Size => 2;
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for Burst_Transfer use (
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Single => 2#00#,
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INCR4 => 2#01#,
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INCR8 => 2#10#,
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INCR16 => 2#11#
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);
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subtype Channel_Number is Integer range 0 .. 15;
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-- note: channels 8 .. 15 are only available on F4x3 devices
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type Stream_Configuration_Register is record
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EN : Boolean;
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DMEIE : Boolean;
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TEIE : Boolean;
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HTIE : Boolean;
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TCIE : Boolean;
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PFCTRL : Boolean;
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DIR : Data_Transfer_Direction;
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CIRC : Boolean;
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PINC : Boolean;
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MINC : Boolean;
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PSIZE : Data_Size;
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MSIZE : Data_Size;
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PINCOS : Boolean;
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PL : Integer range 0 .. 3;
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DBM : Boolean;
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CT : Integer range 0 .. 1;
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Reserved_20 : Integer range 0 .. 1;
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PBURST : Burst_Transfer;
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MBURST : Burst_Transfer;
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CHSEL : Integer range 0 .. 7;
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Reserved_28 : Integer range 0 .. 2**4 - 1;
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EN : Boolean := False;
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DMEIE : Boolean := False;
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TEIE : Boolean := False;
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HTIE : Boolean := False;
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TCIE : Boolean := False;
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PFCTRL : Boolean := False;
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DIR : Transfer_Direction := Peripheral_to_Memory;
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CIRC : Boolean := False;
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PINC : Boolean := False;
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MINC : Boolean := False;
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PSIZE : Data_Size := Byte;
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MSIZE : Data_Size := Byte;
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PINCOS : Boolean := False;
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PL : Priority_Level := 0;
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DBM : Boolean := False;
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CT : Target_Memory := 0;
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Unused_20 : Unused_1_Bit := 0;
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PBURST : Burst_Transfer := Single;
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MBURST : Burst_Transfer := Single;
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CHSEL : Channel_Number := 0;
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Unused_29 : Unused_3_Bits := 0;
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end record with Size => 32;
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for Stream_Configuration_Register use record
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EN at 0 range 0 .. 0;
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DMEIE at 0 range 1 .. 1;
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TEIE at 0 range 2 .. 2;
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HTIE at 0 range 3 .. 3;
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TCIE at 0 range 4 .. 4;
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PFCTRL at 0 range 5 .. 5;
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DIR at 0 range 6 .. 7;
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CIRC at 0 range 8 .. 8;
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PINC at 0 range 9 .. 9;
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MINC at 0 range 10 .. 10;
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PSIZE at 0 range 11 .. 12;
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MSIZE at 0 range 13 .. 14;
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PINCOS at 0 range 15 .. 15;
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PL at 0 range 16 .. 17;
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DBM at 0 range 18 .. 18;
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CT at 0 range 19 .. 19;
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Reserved_20 at 0 range 20 .. 20;
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PBURST at 0 range 21 .. 22;
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MBURST at 0 range 23 .. 24;
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CHSEL at 0 range 25 .. 27;
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Reserved_28 at 0 range 28 .. 31;
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EN at 0 range 0 .. 0;
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DMEIE at 0 range 1 .. 1;
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TEIE at 0 range 2 .. 2;
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HTIE at 0 range 3 .. 3;
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TCIE at 0 range 4 .. 4;
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PFCTRL at 0 range 5 .. 5;
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DIR at 0 range 6 .. 7;
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CIRC at 0 range 8 .. 8;
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PINC at 0 range 9 .. 9;
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MINC at 0 range 10 .. 10;
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PSIZE at 0 range 11 .. 12;
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MSIZE at 0 range 13 .. 14;
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PINCOS at 0 range 15 .. 15;
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PL at 0 range 16 .. 17;
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DBM at 0 range 18 .. 18;
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CT at 0 range 19 .. 19;
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Unused_20 at 0 range 20 .. 20;
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PBURST at 0 range 21 .. 22;
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MBURST at 0 range 23 .. 24;
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CHSEL at 0 range 25 .. 28;
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Unused_29 at 0 range 29 .. 31;
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end record;
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-- NDTR
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@ -192,8 +195,8 @@ package STM32.Direct_Memory_Access with Pure is
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pragma Volatile_Full_Access(CR);
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NDTR : Stream_Number_Of_Data_Register;
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pragma Volatile_Full_Access(NDTR);
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PAR : Address_Register;
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MAR : Memory_Address_Register_Pair;
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PAR : Address_Register; -- Address in peripheral and also source in MtM transfer
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MAR : Memory_Address_Register_Pair; -- Address in memory to transfer
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FCR : FIFO_Control_Register;
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pragma Volatile_Full_Access(FCR);
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end record with Size => DMA_Stream_Registers_Size, Volatile;
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@ -221,4 +224,8 @@ package STM32.Direct_Memory_Access with Pure is
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IFCR at 16#08# range 0 .. 63;
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S at 16#10# range 0 .. DMA_Streams * DMA_Stream_Registers_Size - 1;
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end record;
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DMA1 : DMA_Registers with Volatile, Import, Address => Address_Map.DMA1;
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DMA2 : DMA_Registers with Volatile, Import, Address => Address_Map.DMA2;
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end STM32.Direct_Memory_Access;
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@ -1,4 +1,8 @@
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package STM32.Embedded_Flash with Pure is
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with STM32.Address_Map;
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-- Embedded Flash Memory Interface
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package STM32.Embedded_Flash is
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-- ACR
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type Access_Control_Register is record
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@ -251,4 +255,6 @@ package STM32.Embedded_Flash with Pure is
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OPTCR1 at 16#18# range 0 .. 31;
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end record;
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FLASH : Flash_Registers with Volatile, Import, Address => Address_Map.Flash_IR;
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end STM32.Embedded_Flash;
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@ -1,4 +1,8 @@
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package STM32.Hash_Processor with Pure is
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with STM32.Address_Map;
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-- Hash Processor
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package STM32.Hash_Processor is
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-- CR
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@ -8,21 +12,11 @@ package STM32.Hash_Processor with Pure is
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Data_8_Bit, -- Each word consist of four bytes in reverse order
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Data_1_Bit -- Each word is reversed bit-wise
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) with Size => 2;
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for Data_Type use (
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Data_32_Bit => 2#00#,
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Data_16_Bit => 2#01#,
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Data_8_Bit => 2#10#,
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Data_1_Bit => 2#11#
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);
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type Hash_Mode is (
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Hash,
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HMAC
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type Mode_Select is (
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Hash_Mode,
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HMAC_Mode
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) with Size => 1;
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for Hash_Mode use (
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Hash => 0,
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HMAC => 1
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);
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type Algorithm_0 is mod 2;
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type Algorithm_1 is mod 2;
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@ -60,7 +54,7 @@ package STM32.Hash_Processor with Pure is
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INIT : Boolean := False; -- Initialize message digest
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DMAE : Boolean := False; -- DMA enable
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DATATYPE : Data_Type := Data_32_Bit; -- Data type selection
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MODE : Hash_Mode := Hash; -- Mode selection
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MODE : Mode_Select := Hash_Mode; -- Mode selection
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ALGO0 : Algorithm_0 := 0; -- Algorithm selection bit 0
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NBW : Integer range 0 .. 15 := 0; -- Number of words already
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DINNE : Boolean := False; -- DIN not empty
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@ -90,11 +84,13 @@ package STM32.Hash_Processor with Pure is
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-- STR
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subtype Valid_Bit_Count is Integer range 0 .. 2**5 - 1;
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type Start_Register is record
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NBLW : Integer range 0 .. 2**5 - 1 := 0; -- Number of valid bits in the la
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Unused_5 : Integer range 0 .. 7 := 0;
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DCAL : Boolean := False; -- Digest calculation
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Unused_9 : Integer range 0 .. 2**23 - 1 := 0;
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NBLW : Valid_Bit_Count := 0; -- Number of valid bits in the la
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Unused_5 : Unused_3_Bits := 0;
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DCAL : Boolean := False; -- Digest calculation
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Unused_9 : Unused_23_Bits := 0;
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end record with Size => 32;
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for Start_Register use record
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NBLW at 0 range 0 .. 4;
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@ -112,7 +108,7 @@ package STM32.Hash_Processor with Pure is
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type Interrupt_Enable_Register is record
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DINIE : Boolean := False; -- Data input interrupt enable
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DCIE : Boolean := False; -- Digest calculation completion interrupt enable
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Unused : Integer range 0 .. 2**30 - 1 := 0;
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Unused : Unused_30_Bits := 0;
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end record with Size => 32;
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for Interrupt_Enable_Register use record
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DINIE at 0 range 0 .. 0;
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@ -127,7 +123,7 @@ package STM32.Hash_Processor with Pure is
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DCIS : Boolean := True; -- Digest calculation completion interrupt status
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DMAS : Boolean := False; -- DMA Status
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BUSY : Boolean := False; -- Busy bit
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Unused_4 : Integer range 0 .. 2**28 - 1 := 0;
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Unused_4 : Unused_28_Bits := 0;
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end record with Size => 32;
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for Status_Register use record
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DINIS at 0 range 0 .. 0;
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@ -137,600 +133,6 @@ package STM32.Hash_Processor with Pure is
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Unused_4 at 0 range 4 .. 31;
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end record;
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-- CSR0
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type CSR0_Register is record
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CSR0 : Unsigned_32; -- CSR0
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end record with Size => 32;
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for CSR0_Register use record
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CSR0 at 0 range 0 .. 31;
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end record;
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-- CSR1
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type CSR1_Register is record
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CSR1 : Unsigned_32; -- CSR1
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end record with Size => 32;
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for CSR1_Register use record
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CSR1 at 0 range 0 .. 31;
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end record;
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-- CSR2
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type CSR2_Register is record
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CSR2 : Unsigned_32; -- CSR2
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end record with Size => 32;
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for CSR2_Register use record
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CSR2 at 0 range 0 .. 31;
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end record;
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-- CSR3
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type CSR3_Register is record
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CSR3 : Unsigned_32; -- CSR3
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end record with Size => 32;
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for CSR3_Register use record
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CSR3 at 0 range 0 .. 31;
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end record;
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-- CSR4
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type CSR4_Register is record
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CSR4 : Unsigned_32; -- CSR4
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end record with Size => 32;
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for CSR4_Register use record
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CSR4 at 0 range 0 .. 31;
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end record;
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-- CSR5
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type CSR5_Register is record
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CSR5 : Unsigned_32; -- CSR5
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end record with Size => 32;
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for CSR5_Register use record
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CSR5 at 0 range 0 .. 31;
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end record;
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-- CSR6
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type CSR6_Register is record
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CSR6 : Unsigned_32; -- CSR6
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end record with Size => 32;
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for CSR6_Register use record
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CSR6 at 0 range 0 .. 31;
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end record;
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-- CSR7
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type CSR7_Register is record
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CSR7 : Unsigned_32; -- CSR7
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end record with Size => 32;
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for CSR7_Register use record
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CSR7 at 0 range 0 .. 31;
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end record;
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-- CSR8
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type CSR8_Register is record
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CSR8 : Unsigned_32; -- CSR8
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end record with Size => 32;
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for CSR8_Register use record
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CSR8 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR9
|
||||
|
||||
type CSR9_Register is record
|
||||
CSR9 : Unsigned_32; -- CSR9
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR9_Register use record
|
||||
CSR9 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR10
|
||||
|
||||
type CSR10_Register is record
|
||||
CSR10 : Unsigned_32; -- CSR10
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR10_Register use record
|
||||
CSR10 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR11
|
||||
|
||||
type CSR11_Register is record
|
||||
CSR11 : Unsigned_32; -- CSR11
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR11_Register use record
|
||||
CSR11 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR12
|
||||
|
||||
type CSR12_Register is record
|
||||
CSR12 : Unsigned_32; -- CSR12
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR12_Register use record
|
||||
CSR12 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR13
|
||||
|
||||
type CSR13_Register is record
|
||||
CSR13 : Unsigned_32; -- CSR13
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR13_Register use record
|
||||
CSR13 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR14
|
||||
|
||||
type CSR14_Register is record
|
||||
CSR14 : Unsigned_32; -- CSR14
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR14_Register use record
|
||||
CSR14 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR15
|
||||
|
||||
type CSR15_Register is record
|
||||
CSR15 : Unsigned_32; -- CSR15
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR15_Register use record
|
||||
CSR15 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR16
|
||||
|
||||
type CSR16_Register is record
|
||||
CSR16 : Unsigned_32; -- CSR16
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR16_Register use record
|
||||
CSR16 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR17
|
||||
|
||||
type CSR17_Register is record
|
||||
CSR17 : Unsigned_32; -- CSR17
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR17_Register use record
|
||||
CSR17 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR18
|
||||
|
||||
type CSR18_Register is record
|
||||
CSR18 : Unsigned_32; -- CSR18
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR18_Register use record
|
||||
CSR18 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR19
|
||||
|
||||
type CSR19_Register is record
|
||||
CSR19 : Unsigned_32; -- CSR19
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR19_Register use record
|
||||
CSR19 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR20
|
||||
|
||||
type CSR20_Register is record
|
||||
CSR20 : Unsigned_32; -- CSR20
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR20_Register use record
|
||||
CSR20 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR21
|
||||
|
||||
type CSR21_Register is record
|
||||
CSR21 : Unsigned_32; -- CSR21
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR21_Register use record
|
||||
CSR21 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR22
|
||||
|
||||
type CSR22_Register is record
|
||||
CSR22 : Unsigned_32; -- CSR22
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR22_Register use record
|
||||
CSR22 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR23
|
||||
|
||||
type CSR23_Register is record
|
||||
CSR23 : Unsigned_32; -- CSR23
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR23_Register use record
|
||||
CSR23 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR24
|
||||
|
||||
type CSR24_Register is record
|
||||
CSR24 : Unsigned_32; -- CSR24
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR24_Register use record
|
||||
CSR24 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR25
|
||||
|
||||
type CSR25_Register is record
|
||||
CSR25 : Unsigned_32; -- CSR25
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR25_Register use record
|
||||
CSR25 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR26
|
||||
|
||||
type CSR26_Register is record
|
||||
CSR26 : Unsigned_32; -- CSR26
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR26_Register use record
|
||||
CSR26 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR27
|
||||
|
||||
type CSR27_Register is record
|
||||
CSR27 : Unsigned_32; -- CSR27
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR27_Register use record
|
||||
CSR27 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR28
|
||||
|
||||
type CSR28_Register is record
|
||||
CSR28 : Unsigned_32; -- CSR28
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR28_Register use record
|
||||
CSR28 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR29
|
||||
|
||||
type CSR29_Register is record
|
||||
CSR29 : Unsigned_32; -- CSR29
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR29_Register use record
|
||||
CSR29 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR30
|
||||
|
||||
type CSR30_Register is record
|
||||
CSR30 : Unsigned_32; -- CSR30
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR30_Register use record
|
||||
CSR30 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR31
|
||||
|
||||
type CSR31_Register is record
|
||||
CSR31 : Unsigned_32; -- CSR31
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR31_Register use record
|
||||
CSR31 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR32
|
||||
|
||||
type CSR32_Register is record
|
||||
CSR32 : Unsigned_32; -- CSR32
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR32_Register use record
|
||||
CSR32 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR33
|
||||
|
||||
type CSR33_Register is record
|
||||
CSR33 : Unsigned_32; -- CSR33
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR33_Register use record
|
||||
CSR33 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR34
|
||||
|
||||
type CSR34_Register is record
|
||||
CSR34 : Unsigned_32; -- CSR34
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR34_Register use record
|
||||
CSR34 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR35
|
||||
|
||||
type CSR35_Register is record
|
||||
CSR35 : Unsigned_32; -- CSR35
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR35_Register use record
|
||||
CSR35 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR36
|
||||
|
||||
type CSR36_Register is record
|
||||
CSR36 : Unsigned_32; -- CSR36
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR36_Register use record
|
||||
CSR36 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR37
|
||||
|
||||
type CSR37_Register is record
|
||||
CSR37 : Unsigned_32; -- CSR37
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR37_Register use record
|
||||
CSR37 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR38
|
||||
|
||||
type CSR38_Register is record
|
||||
CSR38 : Unsigned_32; -- CSR38
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR38_Register use record
|
||||
CSR38 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR39
|
||||
|
||||
type CSR39_Register is record
|
||||
CSR39 : Unsigned_32; -- CSR39
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR39_Register use record
|
||||
CSR39 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR40
|
||||
|
||||
type CSR40_Register is record
|
||||
CSR40 : Unsigned_32; -- CSR40
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR40_Register use record
|
||||
CSR40 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR41
|
||||
|
||||
type CSR41_Register is record
|
||||
CSR41 : Unsigned_32; -- CSR41
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR41_Register use record
|
||||
CSR41 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR42
|
||||
|
||||
type CSR42_Register is record
|
||||
CSR42 : Unsigned_32; -- CSR42
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR42_Register use record
|
||||
CSR42 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR43
|
||||
|
||||
type CSR43_Register is record
|
||||
CSR43 : Unsigned_32; -- CSR43
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR43_Register use record
|
||||
CSR43 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR44
|
||||
|
||||
type CSR44_Register is record
|
||||
CSR44 : Unsigned_32; -- CSR44
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR44_Register use record
|
||||
CSR44 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR45
|
||||
|
||||
type CSR45_Register is record
|
||||
CSR45 : Unsigned_32; -- CSR45
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR45_Register use record
|
||||
CSR45 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR46
|
||||
|
||||
type CSR46_Register is record
|
||||
CSR46 : Unsigned_32; -- CSR46
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR46_Register use record
|
||||
CSR46 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR47
|
||||
|
||||
type CSR47_Register is record
|
||||
CSR47 : Unsigned_32; -- CSR47
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR47_Register use record
|
||||
CSR47 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR48
|
||||
|
||||
type CSR48_Register is record
|
||||
CSR48 : Unsigned_32; -- CSR48
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR48_Register use record
|
||||
CSR48 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR49
|
||||
|
||||
type CSR49_Register is record
|
||||
CSR49 : Unsigned_32; -- CSR49
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR49_Register use record
|
||||
CSR49 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR50
|
||||
|
||||
type CSR50_Register is record
|
||||
CSR50 : Unsigned_32; -- CSR50
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR50_Register use record
|
||||
CSR50 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR51
|
||||
|
||||
type CSR51_Register is record
|
||||
CSR51 : Unsigned_32; -- CSR51
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR51_Register use record
|
||||
CSR51 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR52
|
||||
|
||||
type CSR52_Register is record
|
||||
CSR52 : Unsigned_32; -- CSR52
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR52_Register use record
|
||||
CSR52 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
-- CSR53
|
||||
|
||||
type CSR53_Register is record
|
||||
CSR53 : Unsigned_32; -- CSR53
|
||||
|
||||
end record with Size => 32;
|
||||
for CSR53_Register use record
|
||||
CSR53 at 0 range 0 .. 31;
|
||||
|
||||
end record;
|
||||
|
||||
type HASH_Registers is record
|
||||
CR : Control_Register;
|
||||
DIN : Unsigned_32;
|
||||
|
|
@ -752,4 +154,6 @@ package STM32.Hash_Processor with Pure is
|
|||
HASH_HR at 16#0310# range 0 .. 32 * 8 - 1;
|
||||
end record;
|
||||
|
||||
HASH : HASH_Registers with Volatile, Import, Address => Address_Map.HASH;
|
||||
|
||||
end STM32.Hash_Processor;
|
||||
|
|
|
|||
|
|
@ -1,4 +1,8 @@
|
|||
package STM32.Independent_Watchdog with Pure is
|
||||
with STM32.Address_Map;
|
||||
|
||||
-- Independent Watchdog
|
||||
|
||||
package STM32.Independent_Watchdog is
|
||||
|
||||
-- KR
|
||||
|
||||
|
|
@ -94,4 +98,6 @@ package STM32.Independent_Watchdog with Pure is
|
|||
|
||||
end record;
|
||||
|
||||
IWDG : aliased IWDG_Registers with Volatile, Import, Address => Address_Map.IWDG;
|
||||
|
||||
end STM32.Independent_Watchdog;
|
||||
|
|
|
|||
|
|
@ -1,4 +1,6 @@
|
|||
package STM32.Random_Number_Generator with Pure is
|
||||
with STM32.Address_Map;
|
||||
|
||||
package STM32.Random_Number_Generator is
|
||||
|
||||
-- CR
|
||||
|
||||
|
|
@ -52,5 +54,6 @@ package STM32.Random_Number_Generator with Pure is
|
|||
|
||||
end record;
|
||||
|
||||
end STM32.Random_Number_Generator;
|
||||
RNG : RNG_Registers with Volatile, Import, Address => Address_Map.RNG;
|
||||
|
||||
end STM32.Random_Number_Generator;
|
||||
|
|
|
|||
|
|
@ -357,12 +357,7 @@ package STM32.Real_Time_Clock is
|
|||
Tamper_on_8_Samples => 2#11#
|
||||
);
|
||||
|
||||
type Precharge_Duration is (
|
||||
Precharge_1_Cycle,
|
||||
Precharge_2_Cycles,
|
||||
Precharge_4_Cycles,
|
||||
Precharge_8_Cycles
|
||||
) with Size => 2;
|
||||
type Precharge_Duration is new Logarithmic range Value_1 .. Value_8 with Size => 2;
|
||||
|
||||
type Pin_Mapping is (
|
||||
AF1,
|
||||
|
|
@ -383,7 +378,7 @@ package STM32.Real_Time_Clock is
|
|||
TAMPTS : Boolean := False; -- Activate timestamp on tamper d
|
||||
TAMPFREQ : Integer range 0 .. 7 := 0; -- Tamper sampling frequency equals fRTC / 2**(15 - x)
|
||||
TAMPFLT : Tamper_Filter := Tamper_on_Edge; -- Tamper filter count
|
||||
TAMPPRCH : Precharge_Duration := Precharge_1_Cycle; -- Tamper precharge duration
|
||||
TAMPPRCH : Precharge_Duration := Value_1; -- Tamper precharge duration
|
||||
TAMPPUDIS : Boolean := False; -- TAMPER pull-up disable
|
||||
TAMP1INSEL : Pin_Mapping := AF1; -- TAMPER1 mapping
|
||||
TSINSEL : Pin_Mapping := AF1; -- TIMESTAMP mapping
|
||||
|
|
|
|||
|
|
@ -1,4 +1,8 @@
|
|||
package STM32.Window_Watchdog with Pure is
|
||||
with STM32.Address_Map;
|
||||
|
||||
-- Window watchdog
|
||||
|
||||
package STM32.Window_Watchdog is
|
||||
|
||||
-- CR
|
||||
|
||||
|
|
@ -67,4 +71,6 @@ package STM32.Window_Watchdog with Pure is
|
|||
SR at 16#08# range 0 .. 31;
|
||||
end record;
|
||||
|
||||
WWDG : WWDG_Registers with Volatile, Import, Address => Address_Map.WWDG;
|
||||
|
||||
end STM32.Window_Watchdog;
|
||||
|
|
|
|||
|
|
@ -19,7 +19,10 @@ package STM32 is
|
|||
type Unused_17_Bits is mod 2**17 with Size => 17;
|
||||
type Unused_20_Bits is mod 2**20 with Size => 20;
|
||||
type Unused_22_Bits is mod 2**22 with Size => 22;
|
||||
type Unused_23_Bits is mod 2**23 with Size => 23;
|
||||
type Unused_24_Bits is mod 2**24 with Size => 24;
|
||||
type Unused_28_Bits is mod 2**28 with Size => 28;
|
||||
type Unused_30_Bits is mod 2**30 with Size => 30;
|
||||
|
||||
type Logarithmic is (
|
||||
Value_1, Value_2, Value_4, Value_8,
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@ HDMI_CEC
|
|||
* I2C
|
||||
I2S2ext
|
||||
I2S3ext
|
||||
IWDG
|
||||
* IWDG
|
||||
LPTIM
|
||||
* LTDC
|
||||
MPU
|
||||
|
|
@ -46,17 +46,17 @@ OTG_HS_PWRCLK
|
|||
QUADSPI
|
||||
* RCC
|
||||
* RNG
|
||||
RTC
|
||||
* RTC
|
||||
SAI
|
||||
SCB
|
||||
SCB_ACTRL
|
||||
SDIO
|
||||
* SDIO
|
||||
SDMMC
|
||||
SPDIF_RX
|
||||
* SPI
|
||||
STK
|
||||
* SYSCFG
|
||||
TIM
|
||||
UART
|
||||
* TIM
|
||||
* UART
|
||||
* USART
|
||||
* WWDG
|
||||
|
|
|
|||
Loading…
Reference in New Issue