+ USB OTG Host
This commit is contained in:
parent
38c8bfff81
commit
789214bc4c
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@ -32,8 +32,7 @@ package STM32.USB_OTG.Device is
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-- DAINTMSK IEPM IEP
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-- DAINTMSK OEPM OEP
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-- DIEPEMPMSK INEPTXFEM IEP
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type Device_Address is range 0 .. 127;
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-- DSTS DEVLNSTS DEVLNSTS_DP, DEVLNSTS_DM
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-- DCFG
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@ -93,22 +92,6 @@ package STM32.USB_OTG.Device is
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-- DCTL
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type Test_Mode is (
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No_Test,
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Test_J,
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Test_K,
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Test_SE0_NAK,
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Test_Packet,
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Test_Force_Enable)
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with Size => 3;
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for Test_Mode use (
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No_Test => 2#000#,
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Test_J => 2#001#,
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Test_K => 2#010#,
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Test_SE0_NAK => 2#011#,
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Test_Packet => 2#100#,
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Test_Force_Enable => 2#101#);
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type Device_Control_Register is record
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RWUSIG : Boolean := False; -- Remote wakeup signaling
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SDIS : Boolean := False; -- Soft disconnect
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@ -241,8 +224,6 @@ package STM32.USB_OTG.Device is
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-- DAINT, DAINTMSK, DIEPEMPMSK
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type Channel_Set is array (Channel_Number) of Boolean with Pack, Default_Component_Value => False;
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type Device_Endpoint_Set_Register is record
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IEP : Channel_Set; -- IN endpoints
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OEP : Channel_Set; -- OUT endpoints
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@ -291,13 +272,6 @@ package STM32.USB_OTG.Device is
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Max_16_Bytes : constant Endpoint_0_Maximum_Packet_Size := 2;
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Max_8_Bytes : constant Endpoint_0_Maximum_Packet_Size := 3;
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type Endpoint_Type is (
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Control_Endpoint,
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Isochronous_Endpoint,
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Bulk_Endpoint,
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Interrupt_Endpoint)
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with Size => 2;
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type Device_In_Endpoint_Control_Register is record
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MPSIZ : Packet_Byte_Count := 0; -- Maximum packet size (Special meaning in EP 0!)
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Unused_11 : Unused_4_Bits := 0;
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@ -472,7 +446,7 @@ package STM32.USB_OTG.Device is
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DIEPEACHMSK1 : Device_In_Endpoint_Interrupt_Register;
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DOEPEACHMSK1 : Device_Out_Endpoint_Interrupt_Register;
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DIEP : Device_In_Endpoint_Register_Array;
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DOEP : Device_In_Endpoint_Register_Array;
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DOEP : Device_Out_Endpoint_Register_Array;
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end record;
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for DEVICE_Registers use record
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DCFG at 16#00# range 0 .. 31;
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@ -0,0 +1,291 @@
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--
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-- Host-mode-related registers of USB OTG (HS / FS) controller
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--
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package STM32.USB_OTG.Host is
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-- Registers renamed
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-- Orig. register Register name here
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--
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-- HCCHARx HC (x).CHAR
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-- HCSPLTx HC (x).SPLT
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-- HCINTx HC (x).INT
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-- HCINTMSKx HC (x).INTMSK
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-- HCTSIZx HC (x).TSIZ
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-- HCDMA HC (x).DMA
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-- Fields renamed
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-- Register Orig. field Field name here
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--
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-- HAINTMSK HAINTM HAINT (array)
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-- HCINTMSK * corresponding fields in HCINT
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-- HCFG
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type PHY_Clock_Select is (
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PHY_Clock_Reserved_0,
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PHY_Clock_48_MHz,
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PHY_Clock_6_MHz,
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PHY_Clock_Reserved_3) with Size => 2;
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type Configuration_Register is record
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FSLSPCS : PHY_Clock_Select; -- FS/LS PHY clock select
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FSLSS : Boolean := False; -- FS- and LS-only support
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Unused_3 : Unused_29_Bits := 0;
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end record with Size => 32;
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for Configuration_Register use record
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FSLSPCS at 0 range 0 .. 1;
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FSLSS at 0 range 2 .. 2;
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Unused_3 at 0 range 3 .. 31;
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end record;
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-- HFIR
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type Frame_Interval_Register is record
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FRIVL : Integer range 0 .. 2**16 - 1 := 16#EA60#; -- Frame interval
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RLDCTRL : Boolean := False;
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Unused_17 : Unused_15_Bits := 0;
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end record with Size => 32;
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for Frame_Interval_Register use record
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FRIVL at 0 range 0 .. 15;
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RLDCTRL at 0 range 16 .. 16;
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Unused_17 at 0 range 17 .. 31;
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end record;
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-- HFNUM
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type Frame_Number_Register is record
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FRNUM : Integer range 0 .. 2**16 - 1 := 16#3FFF#; -- Frame number
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FTREM : Integer range 0 .. 2**16 - 1 := 0; -- Frame time remaining
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end record with Size => 32;
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for Frame_Number_Register use record
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FRNUM at 0 range 0 .. 15;
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FTREM at 0 range 16 .. 31;
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end record;
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-- HPTXSTS
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type Periodic_Transmit_Status_Register is record
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PTXFSAVL : Integer range 0 .. 2**16 - 1 := 16#100#; -- Periodic tx data FIFO space available
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PTXQSAV : Integer range 0 .. 2**8 - 1 := 8; -- Periodic tx request queue space available
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PTXQTOP : Integer range 0 .. 2**8 - 1 := 0; -- Top of the periodic transmit request queue
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end record with Size => 32;
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for Periodic_Transmit_Status_Register use record
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PTXFSAVL at 0 range 0 .. 15;
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PTXQSAV at 0 range 16 .. 23;
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PTXQTOP at 0 range 24 .. 31;
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end record;
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-- HAINT, HAINTMSK
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type All_Channels_Interrupt_Register is record
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HAINT : Channel_Set; -- Channel interrupts
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Unused_16 : Unused_16_Bits;
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end record with Size => 32;
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for All_Channels_Interrupt_Register use record
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HAINT at 0 range 0 .. 15;
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Unused_16 at 0 range 16 .. 31;
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end record;
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-- HPRT
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type Port_Speed is (
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High_Speed,
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Full_Speed,
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Low_Speed)
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with Size => 2;
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for Port_Speed use (
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High_Speed => 2#00#,
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Full_Speed => 2#01#,
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Low_Speed => 2#10#);
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type Port_Control_Status_Register is record
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PCSTS : Boolean := False; -- Port connect status
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PCDET : Boolean := False; -- Port connect detected
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PENA : Boolean := False; -- Port enable
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PENCHNG : Boolean := False; -- Port enable/disable change
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POCA : Boolean := False; -- Port overcurrent active
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POCCHNG : Boolean := False; -- Port overcurrent change
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PRES : Boolean := False; -- Port resume
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PSUSP : Boolean := False; -- Port suspend
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PRST : Boolean := False; -- Port reset
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Unused_9 : Unused_1_Bit := 0;
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PLSTS_DP : Integer range 0 .. 1 := 0; -- Port line DP status
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PLSTS_DM : Integer range 0 .. 1 := 0; -- Port line DM status
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PPWR : Boolean := False; -- Port power
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PTCTL : Test_Mode := No_Test; -- Port test control
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PSPD : Port_Speed := High_Speed; -- Port speed
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Unused_19 : Unused_13_Bits := 0;
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end record with Size => 32;
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for Port_Control_Status_Register use record
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PCSTS at 0 range 0 .. 0;
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PCDET at 0 range 1 .. 1;
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PENA at 0 range 2 .. 2;
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PENCHNG at 0 range 3 .. 3;
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POCA at 0 range 4 .. 4;
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POCCHNG at 0 range 5 .. 5;
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PRES at 0 range 6 .. 6;
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PSUSP at 0 range 7 .. 7;
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PRST at 0 range 8 .. 8;
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Unused_9 at 0 range 9 .. 9;
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PLSTS_DP at 0 range 10 .. 10;
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PLSTS_DM at 0 range 11 .. 11;
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PPWR at 0 range 12 .. 12;
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PTCTL at 0 range 13 .. 16;
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PSPD at 0 range 17 .. 18;
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Unused_19 at 0 range 19 .. 31;
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end record;
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-- HCCHARx
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type Endpoint_Direction is (
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Out_Endpoint,
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In_Endpoint)
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with Size => 1;
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type Channel_Characteristics_Register is record
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MPSIZ : Packet_Byte_Count := 0; -- Maximum packet size
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EPNUM : Integer range 0 .. 15 := 0; -- Endpoint number
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EPDIR : Endpoint_Direction := Out_Endpoint; -- Endpoint direction
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Unused_16 : Unused_1_Bit := 0;
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LSDEV : Boolean := False; -- Low-speed device
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EPTYP : Endpoint_Type := Control_Endpoint; -- Endpoint type
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MCNT : Integer range 0 .. 3 := 0; -- Multicount
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DAD : Device_Address := 0; -- Device address
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ODDFRM : Boolean := False; -- Odd frame
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CHDIS : Boolean := False; -- Channel disable
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CHENA : Boolean := False; -- Channel enable
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end record with Size => 32;
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for Channel_Characteristics_Register use record
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MPSIZ at 0 range 0 .. 10;
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EPNUM at 0 range 11 .. 14;
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EPDIR at 0 range 15 .. 15;
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Unused_16 at 0 range 16 .. 16;
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LSDEV at 0 range 17 .. 17;
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EPTYP at 0 range 18 .. 19;
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MCNT at 0 range 20 .. 21;
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DAD at 0 range 22 .. 28;
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ODDFRM at 0 range 29 .. 29;
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CHDIS at 0 range 30 .. 30;
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CHENA at 0 range 31 .. 31;
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end record;
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-- HCSPLTx
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type Transaction_Part is (
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Payload_Middle,
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Payload_End,
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Payload_Begin,
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Payload_All)
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with Size => 2;
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type Channel_Split_Control_Register is record
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PRTADDR : Device_Address := 0; -- Port address
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HUBADDR : Device_Address := 0; -- Hub address
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XACTPOS : Transaction_Part := Payload_Middle; -- Transaction position
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COMPLSPLT : Boolean := False; -- Do complete split
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Unused_17 : Unused_14_Bits := 0;
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SPLITEN : Boolean := False; -- Split enable
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end record with Size => 32;
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for Channel_Split_Control_Register use record
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PRTADDR at 0 range 0 .. 6;
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HUBADDR at 0 range 7 .. 13;
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XACTPOS at 0 range 14 .. 15;
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COMPLSPLT at 0 range 16 .. 16;
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Unused_17 at 0 range 17 .. 30;
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SPLITEN at 0 range 31 .. 31;
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end record;
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-- HCINTx, HCINTMSKx
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type Channel_Interrupt_Register is record
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XFRC : Boolean := False; -- Transfer completed
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CHH : Boolean := False; -- Channel halted
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AHBERR : Boolean := False; -- AHB error (HS only)
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STALL : Boolean := False; -- STALL response received
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NAK : Boolean := False; -- NAK response received
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ACK : Boolean := False; -- ACK response received/transmitted
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NYET : Boolean := False; -- Not yet ready response received (HS only)
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TXERR : Boolean := False; -- Transaction error
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BBERR : Boolean := False; -- Babble error
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FRMOR : Boolean := False; -- Frame overrun
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DTERR : Boolean := False; -- Data toggle error
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Unused_11 : Unused_21_Bits := 0;
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end record with Size => 32;
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for Channel_Interrupt_Register use record
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XFRC at 0 range 0 .. 0;
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CHH at 0 range 1 .. 1;
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AHBERR at 0 range 2 .. 2;
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STALL at 0 range 3 .. 3;
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NAK at 0 range 4 .. 4;
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ACK at 0 range 5 .. 5;
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NYET at 0 range 6 .. 6;
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TXERR at 0 range 7 .. 7;
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BBERR at 0 range 8 .. 8;
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FRMOR at 0 range 9 .. 9;
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DTERR at 0 range 10 .. 10;
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Unused_11 at 0 range 11 .. 31;
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end record;
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-- HCTSIZx
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subtype Transfer_Byte_Count is Storage_Count range 0 .. 2**19 - 1;
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subtype Packet_Count is Integer range 0 .. 2**10 - 1;
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type Channel_Transfer_Size_Register is record
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XFRSIZ : Transfer_Byte_Count := 0; -- Transfer size
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PKTCNT : Packet_Count := 0; -- Packet count
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DPID : Data_PID := DATA0; -- Data PID
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Unused_31 : Unused_1_Bit := 0;
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end record with Size => 32;
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for Channel_Transfer_Size_Register use record
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XFRSIZ at 0 range 0 .. 18;
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PKTCNT at 0 range 19 .. 28;
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DPID at 0 range 29 .. 30;
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Unused_31 at 0 range 31 .. 31;
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end record;
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type Channel_Registers is record
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CHAR : Channel_Characteristics_Register;
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SPLT : Channel_Split_Control_Register;
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INT : Channel_Interrupt_Register;
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INTMSK : Channel_Interrupt_Register;
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TSIZ : Channel_Transfer_Size_Register;
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DMA : Address_Register;
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end record with Size => 8 * 32;
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for Channel_Registers use record
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CHAR at 16#00# range 0 .. 31;
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SPLT at 16#04# range 0 .. 31;
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INT at 16#08# range 0 .. 31;
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INTMSK at 16#0C# range 0 .. 31;
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TSIZ at 16#10# range 0 .. 31;
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DMA at 16#14# range 0 .. 31;
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end record;
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type Channel_Register_Array is array (Channel_Number) of Channel_Registers;
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--
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type USB_OTG_Host_Registers is record
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HCFG : Configuration_Register;
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HPTXSTS : Periodic_Transmit_Status_Register;
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HAINT : All_Channels_Interrupt_Register;
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HAINTMSK : All_Channels_Interrupt_Register;
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HFIR : Frame_Interval_Register;
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HPRT : Port_Control_Status_Register;
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HFNUM : Frame_Number_Register;
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HC : Channel_Register_Array;
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end record;
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for USB_OTG_Host_Registers use record
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HCFG at 16#0000# range 0 .. 31;
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HFIR at 16#0004# range 0 .. 31;
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HFNUM at 16#0008# range 0 .. 31;
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HPTXSTS at 16#0010# range 0 .. 31;
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HAINT at 16#0014# range 0 .. 31;
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HAINTMSK at 16#0018# range 0 .. 31;
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HPRT at 16#0040# range 0 .. 31;
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HC at 16#0100# range 0 .. 16 * 8 * 32 - 1;
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end record;
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end STM32.USB_OTG.Host;
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@ -1,4 +1,3 @@
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with System.Storage_Elements;
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use System.Storage_Elements;
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@ -10,6 +9,10 @@ package STM32.USB_OTG is
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type OTG_Role is (USB_Device, USB_Host) with Size => 1;
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type Device_Address is range 0 .. 127; -- USB device address
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-- Channels
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type Extended_Channel_Number is range 0 .. 31; -- Channel / Tx FIFO / Endpoint numbers
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Non_Periodic_Tx_FIFO : constant Extended_Channel_Number := 2#00000#; -- Non-periodic Tx FIFO in host mode
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Periodic_Tx_FIFO : constant Extended_Channel_Number := 2#00001#; -- Periodic Tx FIFO in host mode
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@ -17,6 +20,35 @@ package STM32.USB_OTG is
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subtype Channel_Number is Extended_Channel_Number range 0 .. 15;
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type Channel_Set is array (Channel_Number) of Boolean with Pack, Default_Component_Value => False;
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-- Used in DCTL and HPRT registers
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type Test_Mode is (
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No_Test,
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Test_J,
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Test_K,
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Test_SE0_NAK,
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Test_Packet,
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Test_Force_Enable)
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with Size => 3;
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for Test_Mode use (
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No_Test => 2#000#,
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Test_J => 2#001#,
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Test_K => 2#010#,
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Test_SE0_NAK => 2#011#,
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Test_Packet => 2#100#,
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Test_Force_Enable => 2#101#);
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-- Used in DIEPCTLx, HCCHARx
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type Endpoint_Type is (
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Control_Endpoint,
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Isochronous_Endpoint,
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Bulk_Endpoint,
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Interrupt_Endpoint)
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with Size => 2;
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-- GOTGCTL
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type Connector_Status is (
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@ -289,6 +321,7 @@ package STM32.USB_OTG is
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subtype Packet_Byte_Count is Storage_Count range 0 .. 2**11 - 1;
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type Data_PID is (DATA0, DATA1, DATA2, MDATA) with Size => 2;
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SETUP : constant Data_PID := MDATA;
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type Packet_Status is (
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No_Packet_Status,
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@ -528,33 +561,36 @@ package STM32.USB_OTG is
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DIEPTXF at 16#104# range 0 .. 32 * 7 - 1;
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end record;
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type Power_and_Clock_Gating_Register is record
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STPPCLK : Boolean := False; -- Stop PHY clock
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GATEHCLK : Boolean := False; -- Gate HCLK
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Unused_2 : Unused_2_Bits := 0;
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PHYSUSP : Boolean := False; -- PHY suspended
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ENL1GTG : Boolean := False; -- Enable sleep clock gating
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PHYSLEEP : Boolean := False; -- PHY in sleep mode
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SUSP : Boolean := False; -- Deep sleep
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Unused_8 : Unused_24_Bits := 16#200B_80#;
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package Power_and_Clock is
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end record with Size => 32;
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for Power_and_Clock_Gating_Register use record
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STPPCLK at 0 range 0 .. 0;
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GATEHCLK at 0 range 1 .. 1;
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Unused_2 at 0 range 2 .. 3;
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PHYSUSP at 0 range 4 .. 4;
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ENL1GTG at 0 range 5 .. 5;
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PHYSLEEP at 0 range 6 .. 6;
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SUSP at 0 range 7 .. 7;
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Unused_8 at 0 range 8 .. 31;
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end record;
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type Power_and_Clock_Gating_Register is record
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STPPCLK : Boolean := False; -- Stop PHY clock
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GATEHCLK : Boolean := False; -- Gate HCLK
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Unused_2 : Unused_2_Bits := 0;
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PHYSUSP : Boolean := False; -- PHY suspended
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ENL1GTG : Boolean := False; -- Enable sleep clock gating
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PHYSLEEP : Boolean := False; -- PHY in sleep mode
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SUSP : Boolean := False; -- Deep sleep
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Unused_8 : Unused_24_Bits := 16#200B_80#;
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end record with Size => 32;
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for Power_and_Clock_Gating_Register use record
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STPPCLK at 0 range 0 .. 0;
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GATEHCLK at 0 range 1 .. 1;
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Unused_2 at 0 range 2 .. 3;
|
||||
PHYSUSP at 0 range 4 .. 4;
|
||||
ENL1GTG at 0 range 5 .. 5;
|
||||
PHYSLEEP at 0 range 6 .. 6;
|
||||
SUSP at 0 range 7 .. 7;
|
||||
Unused_8 at 0 range 8 .. 31;
|
||||
end record;
|
||||
|
||||
type OTG_PWRCLK_Registers is record
|
||||
PCGCR : Power_and_Clock_Gating_Register;
|
||||
end record;
|
||||
for OTG_PWRCLK_Registers use record
|
||||
PCGCR at 16#00# range 0 .. 31;
|
||||
end record;
|
||||
type OTG_PWRCLK_Registers is record
|
||||
PCGCR : Power_and_Clock_Gating_Register;
|
||||
end record;
|
||||
for OTG_PWRCLK_Registers use record
|
||||
PCGCR at 16#00# range 0 .. 31;
|
||||
end record;
|
||||
|
||||
end Power_and_Clock;
|
||||
|
||||
end STM32.USB_OTG;
|
||||
|
|
|
@ -19,11 +19,14 @@ package STM32 is
|
|||
type Unused_10_Bits is mod 2**10 with Size => 10;
|
||||
type Unused_12_Bits is mod 2**12 with Size => 12;
|
||||
type Unused_13_Bits is mod 2**13 with Size => 13;
|
||||
type Unused_14_Bits is mod 2**14 with Size => 14;
|
||||
type Unused_15_Bits is mod 2**15 with Size => 15;
|
||||
type Unused_16_Bits is mod 2**16 with Size => 16;
|
||||
type Unused_17_Bits is mod 2**17 with Size => 17;
|
||||
type Unused_18_Bits is mod 2**18 with Size => 18;
|
||||
type Unused_19_Bits is mod 2**19 with Size => 19;
|
||||
type Unused_20_Bits is mod 2**20 with Size => 20;
|
||||
type Unused_21_Bits is mod 2**21 with Size => 21;
|
||||
type Unused_22_Bits is mod 2**22 with Size => 22;
|
||||
type Unused_23_Bits is mod 2**23 with Size => 23;
|
||||
type Unused_24_Bits is mod 2**24 with Size => 24;
|
||||
|
|
Loading…
Reference in New Issue