>< DMA > Direct_Memory_Access, HASH > Hash_Processor, IWDG > Independent_Watchdog, WWDG > Window_Watchdog, RNG > Random_Number_Generator
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package STM32.DMA with Pure is
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package STM32.Direct_Memory_Access with Pure is
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-- LISR, HISR, LIFCR, HIFCR
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-- This Register definition is a bit weird,
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@ -221,4 +221,4 @@ package STM32.DMA with Pure is
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IFCR at 16#08# range 0 .. 63;
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S at 16#10# range 0 .. DMA_Streams * DMA_Stream_Registers_Size - 1;
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end record;
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end STM32.DMA;
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end STM32.Direct_Memory_Access;
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@ -1,12 +0,0 @@
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with System.Storage_Elements;
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with STM32.Address_Map;
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with STM32.HASH;
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package STM32.F429.HASH is
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package Base renames STM32.HASH;
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HASH_HW : Base.HASH_Registers with Volatile, Import,
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Address => System.Storage_Elements.To_Address (STM32.Address_Map.HASH);
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end STM32.F429.HASH;
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@ -1,4 +1,4 @@
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package STM32.HASH with Pure is
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package STM32.Hash_Processor with Pure is
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-- CR
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@ -752,5 +752,4 @@ package STM32.HASH with Pure is
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HASH_HR at 16#0310# range 0 .. 32 * 8 - 1;
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end record;
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end STM32.HASH;
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end STM32.Hash_Processor;
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@ -1,4 +1,4 @@
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package STM32.IWDG with Pure is
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package STM32.Independent_Watchdog with Pure is
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-- KR
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@ -94,4 +94,4 @@ package STM32.IWDG with Pure is
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end record;
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end STM32.IWDG;
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end STM32.Independent_Watchdog;
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@ -1,4 +1,4 @@
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package STM32.RNG with Pure is
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package STM32.Random_Number_Generator with Pure is
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-- CR
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@ -52,5 +52,5 @@ package STM32.RNG with Pure is
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end record;
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end STM32.RNG;
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end STM32.Random_Number_Generator;
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@ -1,4 +1,4 @@
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package STM32.WWDG with Pure is
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package STM32.Window_Watchdog with Pure is
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-- CR
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@ -67,4 +67,4 @@ package STM32.WWDG with Pure is
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SR at 16#08# range 0 .. 31;
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end record;
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end STM32.WWDG;
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end STM32.Window_Watchdog;
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