diff --git a/library/.keep b/library/.keep
new file mode 100644
index 0000000..e69de29
diff --git a/objects/.keep b/objects/.keep
new file mode 100644
index 0000000..e69de29
diff --git a/source/stm32-general_purpose_io.adb b/source/stm32-general_purpose_io.adb
new file mode 100644
index 0000000..a8baecc
--- /dev/null
+++ b/source/stm32-general_purpose_io.adb
@@ -0,0 +1,43 @@
+with Interfaces;
+use Interfaces;
+
+package body STM32.General_Purpose_IO is
+
+	package body GPIO_Port_Boolean is
+
+		procedure Set(Value: Boolean) is
+		begin
+			Register.BSRR := (
+				BR => 2**Bit,
+				BS => 2**Bit * Boolean'Pos(Value)
+			);
+		end;
+
+		function Value return Boolean is
+		begin
+			return (Register.IDR and 2**Bit) /= 0;
+		end;
+
+	end GPIO_Port_Boolean;
+
+	package body GPIO_Port_Modular is
+
+		Size: constant Positive := 1 + Last_Bit - First_Bit;
+		Mask: constant Unsigned_16 := 2**(Last_Bit + 1) - 2**First_Bit;
+
+		procedure Set(Value: Format) is
+		begin
+			Register.BSRR := (
+				BR => Mask,
+				BS => 2**First_Bit * Unsigned_16(Value)
+			);
+		end;
+
+		function Value return Format is
+		begin
+			return Format((Register.IDR / 2**First_Bit) and (2**Size - 1));
+		end;
+
+	end GPIO_Port_Modular;
+
+end STM32.General_Purpose_IO;
diff --git a/source/stm32-general_purpose_io.ads b/source/stm32-general_purpose_io.ads
new file mode 100644
index 0000000..5faf636
--- /dev/null
+++ b/source/stm32-general_purpose_io.ads
@@ -0,0 +1,25 @@
+with Interfaces;
+with STM32.Registers.GPIO;
+
+package STM32.General_Purpose_IO is
+	-- Single GPIO pin
+	generic
+		Register: in out Registers.GPIO.GPIO_Registers;
+		Bit: Registers.GPIO.Port_Bit_Number;
+	package GPIO_Port_Boolean is
+		procedure Set(Value: Boolean) with Inline; -- Output to port
+		function Value return Boolean with Inline; -- Read port
+	end GPIO_Port_Boolean;
+
+	-- Multi-pin GPIO
+	generic
+		type Format is mod <>;
+		Register: in out Registers.GPIO.GPIO_Registers;
+		First_Bit: Registers.GPIO.Port_Bit_Number;
+		Last_Bit: Registers.GPIO.Port_Bit_NUmber;
+	package GPIO_Port_Modular is
+		procedure Set(Value: Format) with Inline;
+		function Value return Format with Inline;
+	end GPIO_Port_Modular;
+
+end STM32.General_Purpose_IO;
diff --git a/source/stm32-registers-exti.ads b/source/stm32-registers-exti.ads
new file mode 100644
index 0000000..a229b0a
--- /dev/null
+++ b/source/stm32-registers-exti.ads
@@ -0,0 +1,47 @@
+package STM32.Registers.EXTI is
+	pragma Preelaborate;
+
+	type Event_Number is range 0 .. 22;
+	package Events is
+		PVD:               constant Event_Number := 16;
+		RTC_Alarm:         constant Event_Number := 17;
+		USB_OTG_FS_Wakeup: constant Event_Number := 18;
+		Ethernet_Wakeup:   constant Event_Number := 19;
+		USB_OTG_HS_Wakeup: constant Event_Number := 20;
+		RTC_Tamper:        constant Event_Number := 21;
+		RTC_Timestamp:     constant Event_Number := 21; -- alias for RTC_Tamper
+		RTC_Wakeup:        constant Event_Number := 22;
+	end Events;
+
+	type Event_Array is array (Event_Number) of Boolean
+	with Pack, Size=>23;
+
+	type Event_Set_Register is record
+		MR: Event_Array;
+		Reserved_23: Integer range 0 .. 2**9-1;
+	end record with Size => 32;
+
+	for Event_Set_Register use record
+		MR at 0 range 0 .. 22;
+		Reserved_23 at 0 range 23 .. 31;
+	end record;
+
+	type EXTI_Registers is record
+		IMR:   Event_Set_Register;
+		EMR:   Event_Set_Register;
+		RTSR:  Event_Set_Register;
+		FTSR:  Event_Set_Register;
+		SWIER: Event_Set_Register;
+		PR:    Event_Set_Register;
+	end record;
+
+	for EXTI_Registers use record
+		IMR   at 16#00# range 0 .. 31;
+		EMR   at 16#04# range 0 .. 31;
+		RTSR  at 16#08# range 0 .. 31;
+		FTSR  at 16#0C# range 0 .. 31;
+		SWIER at 16#10# range 0 .. 31;
+		PR    at 16#14# range 0 .. 31;
+	end record;
+
+end STM32.Registers.EXTI;
diff --git a/source/stm32-registers-fsmc.ads b/source/stm32-registers-fsmc.ads
new file mode 100644
index 0000000..013003c
--- /dev/null
+++ b/source/stm32-registers-fsmc.ads
@@ -0,0 +1,313 @@
+with Interfaces;
+package STM32.Registers.FSMC is
+	pragma Pure;
+	type Memory_Type is (
+		SRAM,
+		PSRAM,
+		NOR_Flash
+	);
+
+	type Memory_Databus_Width is (
+		Databus_8_bit,
+		Databus_16_bit
+	);
+
+	for Memory_Databus_Width use (
+		Databus_8_bit => 2#00#,
+		Databus_16_bit => 2#01#
+	);
+
+	type CRAM_Page_Size is (
+		CRAM_No_Burst_Split,
+		CRAM_Page_128_Bytes,
+		CRAM_Page_256_Bytes,
+		CRAM_Page_512_Bytes,
+		CRAM_Page_1024_Bytes
+	);
+
+	for CRAM_Page_Size use (
+		CRAM_No_Burst_Split => 2#000#,
+		CRAM_Page_128_Bytes => 2#001#,
+		CRAM_Page_256_Bytes => 2#010#,
+		CRAM_Page_512_Bytes => 2#011#,
+		CRAM_Page_1024_Bytes => 2#100#
+	);
+
+	type FSMC_BCR is record
+		MBKEN: Boolean;
+		MUXEN: Boolean;
+		MTYP: Memory_Type;
+		MWID: Memory_Databus_Width;
+		FACCEN: Boolean;
+		Reserved_7: Integer range 0 .. 2**1 - 1;
+		BURSTEN: Boolean;
+		WAITPOL: Boolean;
+		WRAPMOD: Boolean;
+		WAITCFG: Boolean;
+		WREN: Boolean;
+		WAITEN: Boolean;
+		EXTMOD: Boolean;
+		ASYNCWAIT: Boolean;
+		CPSIZE: CRAM_Page_Size;
+		CBURSTRW: Boolean;
+		Reserved_20: Integer range 0 .. 2**12 - 1;
+	end record with Size => 32;
+
+	for FSMC_BCR use record
+		MBKEN at 0 range 0 .. 0;
+		MUXEN at 0 range 1 .. 1;
+		MTYP at 0 range 2 .. 3;
+		MWID at 0 range 4 .. 5;
+		FACCEN at 0 range 6 .. 6;
+		Reserved_7 at 0 range 7 .. 7;
+		BURSTEN at 0 range 8 .. 8;
+		WAITPOL at 0 range 9 .. 9;
+		WRAPMOD at 0 range 10 .. 10;
+		WAITCFG at 0 range 11 .. 11;
+		WREN at 0 range 12 .. 12;
+		WAITEN at 0 range 13 .. 13;
+		EXTMOD at 0 range 14 .. 14;
+		ASYNCWAIT at 0 range 15 .. 15;
+		CPSIZE at 0 range 16 .. 18;
+		CBURSTRW at 0 range 19 .. 19;
+		Reserved_20 at 0 range 20 .. 31;
+	end record;
+
+	type FSMC_Access_Mode is (
+		Access_Mode_A,
+		Access_Mode_B,
+		Access_Mode_C,
+		Access_Mode_D
+	);
+
+	for FSMC_Access_Mode use (
+		Access_Mode_A => 0,
+		Access_Mode_B => 1,
+		Access_Mode_C => 2,
+		Access_Mode_D => 3
+	);
+
+	type FSMC_BTR is record
+		ADDSET: Integer range 0 .. 2**4 - 1; -- Address setup duration
+		ADDHLD: Integer range 1 .. 2**4 - 1; -- Address hold phase duration
+		DATAST: Integer range 1 .. 2**8 - 1; -- Data phase duration
+		BUSTURN: Integer range 0 .. 2**4 - 1; -- Bus turnaround delay
+		CLKDIV: Integer range 0 .. 2**4 - 1; -- Clock divide ratio (offset by 1)
+		DATLAT: Integer range 0 .. 2**4 - 1; -- Data latenct (offset by 2)
+		ACCMOD: FSMC_Access_Mode;
+		Reserved_30: Integer range 0 .. 2**2 - 1;
+	end record with Size => 32;
+
+	for FSMC_BTR use record
+		ADDSET at 0 range 0 .. 3;
+		ADDHLD at 0 range 4 .. 7;
+		DATAST at 0 range 8 .. 15;
+		BUSTURN at 0 range 16 .. 19;
+		CLKDIV at 0 range 20 .. 23;
+		DATLAT at 0 range 24 .. 27;
+		ACCMOD at 0 range 28 .. 29;
+		Reserved_30 at 0 range 30 .. 31;
+	end record;
+
+	type FSMC_BWTR is record
+		ADDSET: Integer range 0 .. 2**4 - 1;
+		ADDHLD: Integer range 0 .. 2**4 - 1;
+		DATAST: Integer range 0 .. 2**8 - 1;
+		BUSTURN: Integer range 0 .. 2**4 - 1;
+		Reserved_20: Integer range 0 .. 2**8 - 1;
+		ACCMOD: Integer range 0 .. 2**2 - 1;
+		Reserved_30: Integer range 0 .. 2**2 - 1;
+	end record with Size => 32;
+
+	for FSMC_BWTR use record
+		ADDSET at 0 range 0 .. 3;
+		ADDHLD at 0 range 4 .. 7;
+		DATAST at 0 range 8 .. 15;
+		BUSTURN at 0 range 16 .. 19;
+		Reserved_20 at 0 range 20 .. 27;
+		ACCMOD at 0 range 28 .. 29;
+		Reserved_30 at 0 range 30 .. 31;
+	end record;
+
+	type P_Memory_Type is (
+		PC_Card,
+		NAND_Flash
+	);
+
+	for P_Memory_Type use (
+		PC_Card => 0,
+		NAND_Flash => 1
+	);
+
+	type ECC_Page_Size is (
+		ECC_Page_256_Bytes,
+		ECC_Page_512_Bytes,
+		ECC_Page_1024_Bytes,
+		ECC_Page_2048_Bytes,
+		ECC_Page_4096_Bytes,
+		ECC_Page_8192_Bytes
+	);
+
+	for ECC_Page_Size use (
+		ECC_Page_256_Bytes => 2#000#,
+		ECC_Page_512_Bytes => 2#001#,
+		ECC_Page_1024_Bytes => 2#010#,
+		ECC_Page_2048_Bytes => 2#011#,
+		ECC_Page_4096_Bytes => 2#100#,
+		ECC_Page_8192_Bytes => 2#101#
+	);
+
+	-- PC Card / NAND flash control registers
+	type FSMC_PCR is record
+		Reserved_0: Integer range 0 .. 1;
+		PWAITEN: Boolean;
+		PBKEN: Boolean;
+		PTYP: P_Memory_Type;
+		PWID: Memory_Databus_Width;
+		ECCEN: Boolean; -- ECC computation enable
+		Reserved_7: Integer range 0 .. 2**2 - 1;
+		TCLR: Integer range 0 .. 2**4 - 1; -- CLE-RE delay (offset by 1)
+		TAR: Integer range 0 .. 2**4 - 1; -- ALE-RE delay (offset by 1)
+		ECCPS: ECC_Page_Size;
+		Reserved_20: Integer range 0 .. 2**12 - 1;
+	end record with Size => 32;
+
+	for FSMC_PCR use record
+		Reserved_0 at 0 range 0 .. 0;
+		PWAITEN at 0 range 1 .. 1;
+		PBKEN at 0 range 2 .. 2;
+		PTYP at 0 range 3 .. 3;
+		PWID at 0 range 4 .. 5;
+		ECCEN at 0 range 6 .. 6;
+		Reserved_7 at 0 range 7 .. 8;
+		TCLR at 0 range 9 .. 12;
+		TAR at 0 range 13 .. 16;
+		ECCPS at 0 range 17 .. 19;
+		Reserved_20 at 0 range 20 .. 31;
+	end record;
+
+	type FSMC_SR is record
+		IRS: Boolean;
+		ILS: Boolean;
+		IFS: Boolean;
+		IREN: Boolean;
+		ILEN: Boolean;
+		IFEN: Boolean;
+		FEMPT: Boolean;
+		Reserved_7: Integer range 0 .. 2**25 - 1;
+	end record with Size => 32;
+
+	for FSMC_SR use record
+		IRS        at 0 range 0 .. 0;
+		ILS        at 0 range 1 .. 1;
+		IFS        at 0 range 2 .. 2;
+		IREN       at 0 range 3 .. 3;
+		ILEN       at 0 range 4 .. 4;
+		IFEN       at 0 range 5 .. 5;
+		FEMPT      at 0 range 6 .. 6;
+		Reserved_7 at 0 range 7 .. 31;
+	end record;
+
+	type FSMC_PMEM is record
+		MEMSET: Integer range 0 .. 2**8 - 1;
+		MEMWAIT: Integer range 0 .. 2**8 - 1;
+		MEMHOLD: Integer range 0 .. 2**8 - 1;
+		MEMHIZ: Integer range 0 .. 2**8 - 1;
+	end record with Size => 32;
+
+	for FSMC_PMEM use record
+		MEMSET  at 0 range  0 .. 7;
+		MEMWAIT at 0 range  8 .. 15;
+		MEMHOLD at 0 range 16 .. 23;
+		MEMHIZ  at 0 range 24 .. 31;
+	end record;
+
+	type FSMC_PATT is record
+		ATTSET: Integer range 0 .. 2**8 - 1;
+		ATTWAIT: Integer range 0 .. 2**8 - 1;
+		ATTHOLD: Integer range 0 .. 2**8 - 1;
+		ATTHIZ: Integer range 0 .. 2**8 - 1;
+	end record with Size => 32;
+
+	for FSMC_PATT use record
+		ATTSET  at 0 range  0 .. 7;
+		ATTWAIT at 0 range  8 .. 15;
+		ATTHOLD at 0 range 16 .. 23;
+		ATTHIZ  at 0 range 24 .. 31;
+	end record;
+
+	type FSMC_PIO is record
+		IOSET: Integer range 0 .. 2**8 - 1;
+		IOWAIT: Integer range 0 .. 2**8 - 1;
+		IOHOLD: Integer range 0 .. 2**8 - 1;
+		IOHIZ: Integer range 0 .. 2**8 - 1;
+	end record with Size => 32;
+
+	for FSMC_PIO use record
+		IOSET  at 0 range  0 .. 7;
+		IOWAIT at 0 range  8 .. 15;
+		IOHOLD at 0 range 16 .. 23;
+		IOHIZ  at 0 range 24 .. 31;
+	end record;
+
+	type FSMC_Registers is record
+		BCR1: FSMC_BCR;
+		BCR2: FSMC_BCR;
+		BCR3: FSMC_BCR;
+		BCR4: FSMC_BCR;
+		BTR1: FSMC_BTR;
+		BTR2: FSMC_BTR;
+		BTR3: FSMC_BTR;
+		BTR4: FSMC_BTR;
+		BWTR1: FSMC_BWTR;
+		BWTR2: FSMC_BWTR;
+		BWTR3: FSMC_BWTR;
+		BWTR4: FSMC_BWTR;
+		PCR2: FSMC_PCR;
+		PCR3: FSMC_PCR;
+		PCR4: FSMC_PCR;
+		SR2: FSMC_SR;
+		SR3: FSMC_SR;
+		SR4: FSMC_SR;
+		PMEM2: FSMC_PMEM;
+		PMEM3: FSMC_PMEM;
+		PMEM4: FSMC_PMEM;
+		PATT2: FSMC_PATT;
+		PATT3: FSMC_PATT;
+		PATT4: FSMC_PATT;
+		PIO4: FSMC_PIO;
+		ECCR2: Interfaces.Unsigned_32;
+		ECCR3: Interfaces.Unsigned_32;
+	end record with Volatile;
+
+	for FSMC_Registers use record
+		BCR1  at 16#0000# range 0 .. 31;
+		BCR2  at 16#0008# range 0 .. 31;
+		BCR3  at 16#0010# range 0 .. 31;
+		BCR4  at 16#0018# range 0 .. 31;
+		BTR1  at 16#0004# range 0 .. 31;
+		BTR2  at 16#000C# range 0 .. 31;
+		BTR3  at 16#0014# range 0 .. 31;
+		BTR4  at 16#001C# range 0 .. 31;
+		BWTR1 at 16#0104# range 0 .. 31;
+		BWTR2 at 16#010C# range 0 .. 31;
+		BWTR3 at 16#0114# range 0 .. 31;
+		BWTR4 at 16#011C# range 0 .. 31;
+		PCR2  at 16#0060# range 0 .. 31;
+		PCR3  at 16#0080# range 0 .. 31;
+		PCR4  at 16#00A0# range 0 .. 31;
+		SR2   at 16#0064# range 0 .. 31;
+		SR3   at 16#0084# range 0 .. 31;
+		SR4   at 16#00A4# range 0 .. 31;
+		PMEM2 at 16#0068# range 0 .. 31;
+		PMEM3 at 16#0088# range 0 .. 31;
+		PMEM4 at 16#00A8# range 0 .. 31;
+		PATT2 at 16#006C# range 0 .. 31;
+		PATT3 at 16#008C# range 0 .. 31;
+		PATT4 at 16#00AC# range 0 .. 31;
+		PIO4  at 16#00B0# range 0 .. 31;
+		ECCR2 at 16#0074# range 0 .. 31;
+		ECCR3 at 16#0094# range 0 .. 31;
+	end record;
+
+end STM32.Registers.FSMC;
diff --git a/source/stm32-registers-gpio.ads b/source/stm32-registers-gpio.ads
new file mode 100644
index 0000000..94b364d
--- /dev/null
+++ b/source/stm32-registers-gpio.ads
@@ -0,0 +1,178 @@
+with Interfaces;
+use Interfaces;
+
+package STM32.Registers.GPIO is
+	pragma Pure;
+
+	subtype Port_Bit_Number is Natural range 0 .. 15;
+
+	--  MODER
+	type Port_Mode is (
+		Input_Mode,
+		Output_Mode,
+		Alternate_Mode,
+		Analog_mode
+	) with Size => 2;
+
+	for Port_Mode use (
+		Input_Mode => 2#00#,
+		Output_Mode => 2#01#,
+		Alternate_Mode => 2#10#,
+		Analog_Mode => 2#11#
+	);
+	
+	type Port_Mode_Register is array(Port_Bit_Number) of Port_Mode
+	with Pack, Size => 32;
+
+	--  OTYPER
+	type Output_Type is (
+		Push_Pull_Type,
+		Open_Low_Type
+	) with Size => 1;
+
+	for Output_Type use (
+		Push_Pull_Type => 2#0#,
+		Open_Low_Type => 2#1#
+	);
+
+	pragma Warnings(Off, "16 bits of ""Output_Type_Register"" unused");
+
+	type Output_Type_Register is array(Port_Bit_Number) of Output_Type
+	with Pack, Size => 32;
+
+	pragma Warnings(On, "16 bits of ""Output_Type_Register"" unused");
+
+	--  OSPEEDR
+	type Output_Speed is (
+		Low_Speed,      -- 50pF ---100--- ns
+		Medium_Speed,   -- 50pF  20 10 6  ns
+		High_Speed,     -- 40pF  10  6 4  ns
+		Very_High_Speed -- 30pF   6  4 2.5ns
+	) with Size => 2;
+
+	for Output_Speed use (
+		Low_Speed       => 2#00#,
+		Medium_Speed    => 2#01#,
+		High_Speed      => 2#10#,
+		Very_High_Speed => 2#11#
+	);
+
+	type Output_Speed_Register is array(Port_Bit_Number) of Output_Speed
+	with Pack, Size => 32;
+
+	--  PUPDR
+	type Port_Pull is (
+		No_Pull,
+		Pull_Up,
+		Pull_Down
+	) with Size => 2;
+
+	for Port_Pull use (
+		No_Pull   => 2#00#,
+		Pull_Up   => 2#01#,
+		Pull_Down => 2#10#
+	);
+
+	type Port_Pull_Register is array(Port_Bit_Number) of Port_Pull
+	with Pack, Size => 32;
+
+	-- BSRR
+	type Bit_Set_Reset_Register is record
+		BS: Unsigned_16;
+		BR: Unsigned_16;
+	end record with Size => 32;
+
+	for Bit_Set_Reset_Register use record
+		BS at 0 range 0 .. 15;
+		BR at 0 range 16 .. 31;
+	end record;
+
+	-- LCKR
+	type Lock_Bit_Array is array (Port_Bit_Number) of Boolean with Pack, Size => 16;
+	type Configuration_Lock_Register is record
+		LCK: Lock_Bit_Array;
+		LCKK: Boolean;
+	end record with Size => 32;
+
+	for Configuration_Lock_Register use record
+		LCK  at 0 range  0 .. 15;
+		LCKK at 0 range 16 .. 16;
+	end record;
+
+	-- AFRL/AFRH
+	type Alternate_Function is mod 16;
+
+	package Alternate_Functions is
+
+		--  AFL constants
+		SYS       : constant Alternate_Function :=  0;
+		TIM1      : constant Alternate_Function :=  1;
+		TIM2      : constant Alternate_Function :=  1;
+		TIM3      : constant Alternate_Function :=  2;
+		TIM4      : constant Alternate_Function :=  2;
+		TIM5      : constant Alternate_Function :=  2;
+		TIM8      : constant Alternate_Function :=  3;
+		TIM9      : constant Alternate_Function :=  3;
+		TIM10     : constant Alternate_Function :=  3;
+		TIM11     : constant Alternate_Function :=  3;
+		I2C1      : constant Alternate_Function :=  4;
+		I2C2      : constant Alternate_Function :=  4;
+		I2C3      : constant Alternate_Function :=  4;
+		SPI1      : constant Alternate_Function :=  5;
+		SPI2      : constant Alternate_Function :=  5;
+		I2S2      : constant Alternate_Function :=  5;
+		I2S2Ext   : constant Alternate_Function :=  5;
+		SPI3      : constant Alternate_Function :=  6;
+		I2SExt    : constant Alternate_Function :=  6;
+		I2S3      : constant Alternate_Function :=  6;
+		USART1    : constant Alternate_Function :=  7;
+		USART2    : constant Alternate_Function :=  7;
+		USART3    : constant Alternate_Function :=  7;
+		I2S3Ext   : constant Alternate_Function :=  7;
+		UART4     : constant Alternate_Function :=  8;
+		UART5     : constant Alternate_Function :=  8;
+		USART6    : constant Alternate_Function :=  8;
+		CAN1      : constant Alternate_Function :=  9;
+		CAN2      : constant Alternate_Function :=  9;
+		TIM12     : constant Alternate_Function :=  9;
+		TIM13     : constant Alternate_Function :=  9;
+		TIM14     : constant Alternate_Function :=  9;
+		OTG_FS    : constant Alternate_Function := 10;
+		OTG_HS    : constant Alternate_Function := 10;
+		ETH       : constant Alternate_Function := 11;
+		FSMC      : constant Alternate_Function := 12;
+		SDIO      : constant Alternate_Function := 12;
+		OTG_FS_B  : constant Alternate_Function := 12;
+		DCMI      : constant Alternate_Function := 13;
+		EVENTOUT  : constant Alternate_Function := 15;
+	
+	end Alternate_Functions;
+
+	type Alternate_Function_Register is array (0 .. 15) of Alternate_Function
+	with Pack, Size => 64;
+
+	type GPIO_Registers is record
+		MODER: Port_Mode_Register;
+		OTYPER: Output_Type_Register;
+		OSPEEDR: Output_Speed_Register;
+		PUPDR: Port_Pull_Register;
+		IDR: Interfaces.Unsigned_32;
+		ODR: Interfaces.Unsigned_32;
+		BSRR: Bit_Set_Reset_Register;
+		LCKR: Configuration_Lock_Register;
+		AFR: Alternate_Function_Register;
+	end record with Volatile;
+
+	for GPIO_Registers use record
+		MODER   at 16#00# range 0 .. 31;
+		OTYPER  at 16#04# range 0 .. 31;
+		OSPEEDR at 16#08# range 0 .. 31;
+		PUPDR   at 16#0C# range 0 .. 31;
+		IDR     at 16#10# range 0 .. 31;
+		ODR     at 16#14# range 0 .. 31;
+		BSRR    at 16#18# range 0 .. 31;
+		LCKR    at 16#1C# range 0 .. 31;
+		AFR     at 16#20# range 0 .. 63;
+	end record;
+
+end STM32.Registers.GPIO;
\ No newline at end of file
diff --git a/source/stm32-registers-rcc.ads b/source/stm32-registers-rcc.ads
new file mode 100644
index 0000000..69479d2
--- /dev/null
+++ b/source/stm32-registers-rcc.ads
@@ -0,0 +1,599 @@
+with Interfaces;
+
+package STM32.Registers.RCC is
+	pragma Preelaborate;
+
+	-- CR
+	type Clock_Control_Register is record
+		HSION: Boolean;
+		HSIRDY: Boolean;
+		HSITRIM: Integer range 0 .. 2**5 - 1;
+		HSICAL: Integer range 0 .. 2**8 - 1;
+		HSEON: Boolean;
+		HSERDY: Boolean;
+		HSEBYP: Boolean;
+		CSSON: Boolean;
+		PLLON: Boolean;
+		PLLRDY: Boolean;
+		PLLI2SON: Boolean;
+		PLLI2SRDY: Boolean;
+	end record with Size => 32;
+
+	for Clock_Control_Register use record
+		HSION     at 0 range 0 .. 0;
+		HSIRDY    at 0 range 1 .. 1;
+		HSITRIM   at 0 range 3 .. 7;
+		HSICAL    at 0 range 8 .. 15;
+		HSEON     at 0 range 16 .. 16;
+		HSERDY    at 0 range 17 .. 17;
+		HSEBYP    at 0 range 18 .. 18;
+		CSSON     at 0 range 19 .. 19;
+		PLLON     at 0 range 24 .. 24;
+		PLLRDY    at 0 range 25 .. 25;
+		PLLI2SON  at 0 range 26 .. 26;
+		PLLI2SRDY at 0 range 27 .. 27;
+	end record;
+
+	--- PLLCFGR
+	type PLL_Division_Factor is (
+		PLL_DIV_2,
+		PLL_DIV_4,
+		PLL_DIV_6,
+		PLL_DIV_8
+	);
+
+	for PLL_Division_Factor use (
+		PLL_DIV_2 => 2#00#,
+		PLL_DIV_4 => 2#01#,
+		PLL_DIV_6 => 2#10#,
+		PLL_DIV_8 => 2#11#
+	);
+
+	type PLL_Clock_Source is (
+		PLLSRC_HSI,
+		PLLSRC_HSE
+	);
+
+	for PLL_Clock_Source use (
+		PLLSRC_HSI => 0,
+		PLLSRC_HSE => 1
+	);
+
+	type PLL_Configuration_Register is record
+		PLLM: Integer range 2 .. 63;
+		PLLN: Integer range 50 .. 432;
+		PLLP: PLL_Division_Factor;
+		PLLSRC: PLL_Clock_Source;
+		PLLQ: Integer range 2 .. 15;
+	end record with Size => 32;
+
+	for PLL_Configuration_Register use record
+		PLLM at 0 range 0 .. 5;
+		PLLN at 0 range 6 .. 14;
+		PLLP at 0 range 16 .. 17;
+		PLLSRC at 0 range 22 .. 22;
+		PLLQ at 0 range 24 .. 27;
+	end record;
+
+	-- CFGR
+	type System_Clock_Switch is (
+		System_Clock_HSI,
+		System_Clock_HSE,
+		System_Clock_PLL
+	) with Size => 2;
+
+	for System_Clock_Switch use (
+		System_Clock_HSI => 2#00#,
+		System_Clock_HSE => 2#01#,
+		System_Clock_PLL => 2#10#
+	);
+
+	type AHB_Prescaler_Factor is (
+		AHB_Prescaler_1,
+		AHB_Prescaler_2,
+		AHB_Prescaler_4,
+		AHB_Prescaler_8,
+		AHB_Prescaler_16,
+		AHB_Prescaler_32,
+		AHB_Prescaler_64,
+		AHB_Prescaler_128,
+		AHB_Prescaler_256
+	) with Size => 4;
+
+	for AHB_Prescaler_Factor use (
+		AHB_Prescaler_1 => 2#0000#,
+		AHB_Prescaler_2 => 2#1000#,
+		AHB_Prescaler_4 => 2#1001#,
+		AHB_Prescaler_8 => 2#1010#,
+		AHB_Prescaler_16 => 2#1011#,
+		AHB_Prescaler_32 => 2#1100#,
+		AHB_Prescaler_64 => 2#1101#,
+		AHB_Prescaler_128 => 2#1110#,
+		AHB_Prescaler_256 => 2#1111#
+	);
+
+	type APB_Prescaler_Factor is (
+		APB_Prescaler_1,
+		APB_Prescaler_2,
+		APB_Prescaler_4,
+		APB_Prescaler_8,
+		APB_Prescaler_16
+	) with Size => 3;
+
+	for APB_Prescaler_Factor use (
+		APB_Prescaler_1 => 2#000#,
+		APB_Prescaler_2 => 2#100#,
+		APB_Prescaler_4 => 2#101#,
+		APB_Prescaler_8 => 2#110#,
+		APB_Prescaler_16 => 2#111#
+	);
+
+	type Clock_Output_1 is (
+		Clock_Output_1_HSI,
+		Clock_Output_1_LSE,
+		Clock_Output_1_HSE,
+		Clock_Output_1_PLL
+	) with Size => 2;
+
+	for Clock_Output_1 use (
+		Clock_Output_1_HSI => 2#00#,
+		Clock_Output_1_LSE => 2#01#,
+		Clock_Output_1_HSE => 2#10#,
+		Clock_Output_1_PLL => 2#11#
+	);
+
+	type I2S_Clock_Source is (
+		I2S_Clock_PLLI2S,
+		I2S_Clock_CLKIN
+	) with Size => 1;
+
+	for I2S_Clock_Source use (
+		I2S_Clock_PLLI2S => 0,
+		I2S_Clock_CLKIN => 1
+	);
+
+	type Clock_Output_Prescaler_Factor is (
+		MCO_Prescaler_1,
+		MCO_Prescaler_2,
+		MCO_Prescaler_3,
+		MCO_Prescaler_4,
+		MCO_Prescaler_5
+	) with Size => 3;
+
+	for Clock_Output_Prescaler_Factor use (
+		MCO_Prescaler_1 => 2#000#,
+		MCO_Prescaler_2 => 2#100#,
+		MCO_Prescaler_3 => 2#101#,
+		MCO_Prescaler_4 => 2#110#,
+		MCO_Prescaler_5 => 2#111#
+	);
+
+	type Clock_Output_2 is (
+		Clock_Output_2_SYSCLK,
+		Clock_Output_2_PLLI2S,
+		Clock_Output_2_HSE,
+		Clock_Output_2_PLL
+	) with Size => 2;
+
+	for Clock_Output_2 use (
+		Clock_Output_2_SYSCLK => 2#00#,
+		Clock_Output_2_PLLI2S => 2#01#,
+		Clock_Output_2_HSE => 2#10#,
+		Clock_Output_2_PLL => 2#11#
+	);
+
+	type Clock_Configuration_Register is record
+		SW: System_Clock_Switch;
+		SWS: System_Clock_Switch;
+		HPRE: AHB_Prescaler_Factor;
+		Reserved_8: Integer range 0 .. 3;
+		PPRE1: APB_Prescaler_Factor;
+		PPRE2: APB_Prescaler_Factor;
+		RTCPRE: Integer range 0 .. 31;
+		MCO1: Clock_Output_1;
+		I2SSCR: I2S_Clock_Source;
+		MCO1PRE: Clock_Output_Prescaler_Factor;
+		MCO2PRE: Clock_Output_Prescaler_Factor;
+		MCO2: Clock_Output_2;
+	end record with Size => 32;
+
+	for Clock_Configuration_Register use record
+		SW         at 0 range  0 .. 1;
+		SWS        at 0 range  2 .. 3;
+		HPRE       at 0 range  4 .. 7;
+		Reserved_8 at 0 range  8 .. 9;
+		PPRE1      at 0 range 10 .. 12;
+		PPRE2      at 0 range 13 .. 15;
+		RTCPRE     at 0 range 16 .. 20;
+		MCO1       at 0 range 21 .. 22;
+		I2SSCR     at 0 range 23 .. 23;
+		MCO1PRE    at 0 range 24 .. 26;
+		MCO2PRE    at 0 range 27 .. 29;
+		MCO2       at 0 range 30 .. 31;
+	end record;
+
+	-- CIR
+	type Clock_Interrupt_Register is record
+		LSIRDYF: Boolean;
+		LSERDYF: Boolean;
+		HSIRDYF: Boolean;
+		HSERDYF: Boolean;
+		PLLRDYF: Boolean;
+		PLLI2SRDYF: Boolean;
+		Reserved_6: Integer range 0 .. 1;
+		CSSF: Boolean;
+		LSIRDYIE: Boolean;
+		LSERDYIE: Boolean;
+		HSIRDYIE: Boolean;
+		HSERDYIE: Boolean;
+		PLLRDYIE: Boolean;
+		PLLI2SRDYIE: Boolean;
+		Reserved_14: Integer range 0 .. 2**2 - 1;
+		LSIRDYC: Boolean;
+		LSERDYC: Boolean;
+		HSIRDYC: Boolean;
+		HSERDYC: Boolean;
+		PLLRDYC: Boolean;
+		PLLI2SRDYC: Boolean;
+		Reserved_22: Integer range 0 .. 1;
+		CSSC: Boolean;
+		Reserved_24: Integer range 0 .. 2**8 - 1;
+	end record with Size => 32;
+
+	for Clock_Interrupt_Register use record
+		LSIRDYF     at 0 range  0 .. 0;
+		LSERDYF     at 0 range  1 .. 1;
+		HSIRDYF     at 0 range  2 .. 2;
+		HSERDYF     at 0 range  3 .. 3;
+		PLLRDYF     at 0 range  4 .. 4;
+		PLLI2SRDYF  at 0 range  5 .. 5;
+		Reserved_6  at 0 range  6 .. 6;
+		CSSF        at 0 range  7 .. 7;
+		LSIRDYIE    at 0 range  8 .. 8;
+		LSERDYIE    at 0 range  9 .. 9;
+		HSIRDYIE    at 0 range 10 .. 10;
+		HSERDYIE    at 0 range 11 .. 11;
+		PLLRDYIE    at 0 range 12 .. 12;
+		PLLI2SRDYIE at 0 range 13 .. 13;
+		Reserved_14 at 0 range 14 .. 15;
+		LSIRDYC     at 0 range 16 .. 16;
+		LSERDYC     at 0 range 17 .. 17;
+		HSIRDYC     at 0 range 18 .. 18;
+		HSERDYC     at 0 range 19 .. 19;
+		PLLRDYC     at 0 range 20 .. 20;
+		PLLI2SRDYC  at 0 range 21 .. 21;
+		Reserved_22 at 0 range 22 .. 22;
+		CSSC        at 0 range 23 .. 23;
+		Reserved_24 at 0 range 24 .. 31;
+	end record;
+
+	-- AHB1RSTR, AHB1ENR
+	type AHB1_Register is record
+		GPIOA: Boolean;
+		GPIOB: Boolean;
+		GPIOC: Boolean;
+		GPIOD: Boolean;
+		GPIOE: Boolean;
+		GPIOF: Boolean;
+		GPIOG: Boolean;
+		GPIOH: Boolean;
+		GPIOI: Boolean;
+		CRC: Boolean;
+		FLITF: Boolean;
+		SRAM1: Boolean;
+		SRAM2: Boolean;
+		BKPSRAM: Boolean;
+		CCMDATARAM: Boolean;
+		DMA1: Boolean;
+		DMA2: Boolean;
+		ETHMAC: Boolean;
+		ETHMACTX: Boolean;
+		ETHMACRX: Boolean;
+		ETHMACPTP: Boolean;
+		OTGHS: Boolean;
+		OTGHSULPI: Boolean;
+	end record with Size => 32;
+
+	for AHB1_Register use record
+		GPIOA      at 0 range  0 .. 0;
+		GPIOB      at 0 range  1 .. 1;
+		GPIOC      at 0 range  2 .. 2;
+		GPIOD      at 0 range  3 .. 3;
+		GPIOE      at 0 range  4 .. 4;
+		GPIOF      at 0 range  5 .. 5;
+		GPIOG      at 0 range  6 .. 6;
+		GPIOH      at 0 range  7 .. 7;
+		GPIOI      at 0 range  8 .. 8;
+		CRC        at 0 range 12 .. 12;
+		FLITF      at 0 range 15 .. 15;
+		SRAM1      at 0 range 16 .. 16;
+		SRAM2      at 0 range 17 .. 17;
+		BKPSRAM    at 0 range 18 .. 18;
+		CCMDATARAM at 0 range 20 .. 20;
+		DMA1       at 0 range 21 .. 21;
+		DMA2       at 0 range 22 .. 22;
+		ETHMAC     at 0 range 25 .. 25;
+		ETHMACTX   at 0 range 26 .. 26;
+		ETHMACRX   at 0 range 27 .. 27;
+		ETHMACPTP  at 0 range 28 .. 28;
+		OTGHS      at 0 range 29 .. 29;
+		OTGHSULPI  at 0 range 30 .. 30;
+	end record;
+
+	-- AHB2RSTR, AHB2ENR
+	type AHB2_Register is record
+		DCMI: Boolean;
+		CRYP: Boolean;
+		HASH: Boolean;
+		RNG: Boolean;
+		OTGFS: Boolean;
+	end record with Size => 32;
+
+	for AHB2_Register use record
+		DCMI  at 0 range 0 .. 0;
+		CRYP  at 0 range 4 .. 4;
+		HASH  at 0 range 5 .. 5;
+		RNG   at 0 range 6 .. 6;
+		OTGFS at 0 range 7 .. 7;
+	end record;
+
+	-- AHB3RSTR, AHB3ENR
+	type AHB3_Register is record
+		FSMC: Boolean;
+	end record with Size => 32;
+
+	for AHB3_Register use record
+		FSMC at 0 range 0 .. 0;
+	end record;
+
+	-- APB1RSTR, APB1ENR
+	type APB1_Register is record
+		TIM2: Boolean;
+		TIM3: Boolean;
+		TIM4: Boolean;
+		TIM5: Boolean;
+		TIM6: Boolean;
+		TIM7: Boolean;
+		TIM12: Boolean;
+		TIM13: Boolean;
+		TIM14: Boolean;
+		WWDG: Boolean;
+		SPI2: Boolean;
+		SPI3: Boolean;
+		USART2: Boolean;
+		USART3: Boolean;
+		UART4: Boolean;
+		UART5: Boolean;
+		I2C1: Boolean;
+		I2C2: Boolean;
+		I2C3: Boolean;
+		CAN1: Boolean;
+		CAN2: Boolean;
+		PWR: Boolean;
+		DAC: Boolean;
+	end record with Size => 32;
+
+	for APB1_Register use record
+		TIM2   at 0 range  0 .. 0;
+		TIM3   at 0 range  1 .. 1;
+		TIM4   at 0 range  2 .. 2;
+		TIM5   at 0 range  3 .. 3;
+		TIM6   at 0 range  4 .. 4;
+		TIM7   at 0 range  5 .. 5;
+		TIM12  at 0 range  6 .. 6;
+		TIM13  at 0 range  7 .. 7;
+		TIM14  at 0 range  8 .. 8;
+		WWDG   at 0 range 11 .. 11;
+		SPI2   at 0 range 14 .. 14;
+		SPI3   at 0 range 15 .. 15;
+		USART2 at 0 range 17 .. 17;
+		USART3 at 0 range 18 .. 18;
+		UART4  at 0 range 19 .. 19;
+		UART5  at 0 range 20 .. 20;
+		I2C1   at 0 range 21 .. 21;
+		I2C2   at 0 range 22 .. 22;
+		I2C3   at 0 range 23 .. 23;
+		CAN1   at 0 range 25 .. 25;
+		CAN2   at 0 range 26 .. 26;
+		PWR    at 0 range 28 .. 28;
+		DAC    at 0 range 29 .. 29;
+	end record;
+
+	-- APB2RSTR, APB2ENR
+	type APB2_Register is record
+		TIM1: Boolean;
+		TIM8: Boolean;
+		USART1: Boolean;
+		USART6: Boolean;
+		ADC1: Boolean; -- RST resets all ADCs
+		ADC2: Boolean;
+		ADC3: Boolean;
+		SDIO: Boolean;
+		SPI1: Boolean;
+		SYSCFG: Boolean;
+		TIM9: Boolean;
+		TIM10: Boolean;
+		TIM11: Boolean;
+	end record with Size => 32;
+
+	for APB2_Register use record
+		TIM1   at 0 range 0 .. 0;
+		TIM8   at 0 range 1 .. 1;
+		USART1 at 0 range 4 .. 4;
+		USART6 at 0 range 5 .. 5;
+		ADC1   at 0 range 8 .. 8;
+		ADC2   at 0 range 9 .. 9;
+		ADC3   at 0 range 10 .. 10;
+		SDIO   at 0 range 11 .. 11;
+		SPI1   at 0 range 12 .. 12;
+		SYSCFG at 0 range 14 .. 14;
+		TIM9   at 0 range 16 .. 16;
+		TIM10  at 0 range 17 .. 17;
+		TIM11  at 0 range 18 .. 18;
+	end record;
+
+	-- BCDR
+	type RTC_Clock_Source is (
+		RTC_Not_Clocked,
+		RTC_Clock_LSE,
+		RTC_Clock_LSI,
+		RTC_Clock_HSE
+	) with Size => 2;
+
+	for RTC_Clock_Source use (
+		RTC_Not_Clocked => 2#00#,
+		RTC_Clock_LSE => 2#01#,
+		RTC_Clock_LSI => 2#10#,
+		RTC_Clock_HSE => 2#11#
+	);
+
+	type Backup_Domain_Control_Register is record
+		LSEON: Boolean;
+		LSERDY: Boolean;
+		LSEBYP: Boolean;
+		Reserved_3: Integer range 0 .. 2**5 - 1;
+		RTCSEL: RTC_Clock_Source;
+		Reserved_10: Integer range 0 .. 2**5 - 1;
+		RTCEN: Boolean;
+		BDRST: Boolean;
+		Reserved_17: Integer range 0 .. 2**15 - 1;
+	end record with Size => 32;
+
+	for Backup_Domain_Control_Register use record
+		LSEON       at 0 range  0 .. 0;
+		LSERDY      at 0 range  1 .. 1;
+		LSEBYP      at 0 range  2 .. 2;
+		Reserved_3  at 0 range  3 .. 7;
+		RTCSEL      at 0 range  8 .. 9;
+		Reserved_10 at 0 range 10 .. 14;
+		RTCEN       at 0 range 15 .. 15;
+		BDRST       at 0 range 16 .. 16;
+		Reserved_17 at 0 range 17 .. 31;
+	end record;
+
+	-- CSR
+	type Clock_Control_and_Status_Register is record
+		LSION: Boolean;
+		LSIRDY: Boolean;
+		Reserved_2: Integer range 0 .. 2**22 - 1;
+		RMVF: Boolean;
+		BORRSTF: Boolean;
+		PINRSTF: Boolean;
+		PORRSTF: Boolean;
+		SFTRSTF: Boolean;
+		IWDGRSTF: Boolean;
+		WWDGRSTF: Boolean;
+		LPWRRSTF: Boolean;
+	end record with Size => 32;
+
+	for Clock_Control_and_Status_Register use record
+		LSION      at 0 range  0 .. 0;
+		LSIRDY     at 0 range  1 .. 1;
+		Reserved_2 at 0 range  2 .. 23;
+		RMVF       at 0 range 24 .. 24;
+		BORRSTF    at 0 range 25 .. 25;
+		PINRSTF    at 0 range 26 .. 26;
+		PORRSTF    at 0 range 27 .. 27;
+		SFTRSTF    at 0 range 28 .. 28;
+		IWDGRSTF   at 0 range 29 .. 29;
+		WWDGRSTF   at 0 range 30 .. 30;
+		LPWRRSTF   at 0 range 31 .. 31;
+	end record;
+
+	-- SSCGR
+	type Spread_Select is (
+		Center_Spread,
+		Down_Spread
+	) with Size => 1;
+
+	for Spread_Select use (
+		Center_Spread => 0,
+		Down_Spread => 1
+	);
+
+	type Spread_Spectrum_Clock_Generation_Register is record
+		MODPER: Integer range 0 .. 2**13 - 1;
+		INCSTEP: Integer range 0 .. 2**15 - 1;
+		Reserved_28: Integer range 0 .. 3;
+		SPREADSEL: Spread_Select;
+		SSCGEN: Boolean;
+	end record with Size => 32;
+
+	for Spread_Spectrum_Clock_Generation_Register use record
+		MODPER at 0 range 0 .. 12;
+		INCSTEP at 0 range 13 .. 27;
+		Reserved_28 at 0 range 28 .. 29;
+		SPREADSEL at 0 range 30 .. 30;
+		SSCGEN at 0 range 31 .. 31;
+	end record;
+
+	-- PLLI2SCFGR
+	type PLLI2S_Configuration_Register is record
+		Reserved_0: Integer range 0 .. 2**6 - 1;
+		PLLI2SN: Integer range 2 .. 432;
+		Reserved_15: Integer range 0 .. 2**13 - 1;
+		PLLI2SR: Integer range 2 .. 7;
+		Reserved_31: Integer range 0 .. 1;
+	end record with Size => 32;
+
+	for PLLI2S_Configuration_Register use record
+		Reserved_0 at 0 range 0 .. 5;
+		PLLI2SN at 0 range 6 .. 14;
+		Reserved_15 at 0 range 15 .. 27;
+		PLLI2SR at 0 range 28 .. 30;
+		Reserved_31 at 0 range 31 .. 31;
+	end record;
+
+	type RCC_Registers is record
+		CR:         Clock_Control_Register;
+		PLLCFGR:    PLL_Configuration_Register;
+		CFGR:       Clock_Configuration_Register;
+		CIR:        Clock_Interrupt_Register;
+		AHB1RSTR:   AHB1_Register;
+		AHB2RSTR:   AHB2_Register;
+		AHB3RSTR:   AHB3_Register;
+		APB1RSTR:   APB1_Register;
+		APB2RSTR:   APB2_Register;
+		AHB1ENR:    AHB1_Register;
+		AHB2ENR:    AHB2_Register;
+		AHB3ENR:    AHB3_Register;
+		APB1ENR:    APB1_Register;
+		APB2ENR:    APB2_Register;
+		AHB1LPENR:  AHB1_Register;
+		AHB2LPENR:  AHB2_Register;
+		AHB3LPENR:  AHB3_Register;
+		APB1LPENR:  APB1_Register;
+		APB2LPENR:  APB2_Register;
+		BDCR:       Backup_Domain_Control_Register;
+		CSR:        Clock_Control_and_Status_Register;
+		SSCGR:      Spread_Spectrum_Clock_Generation_Register;
+		PLLI2SCFGR: PLLI2S_Configuration_Register;
+	end record with Volatile;
+
+	for RCC_Registers use record
+		CR         at 16#00# range 0 .. 31;
+		PLLCFGR    at 16#04# range 0 .. 31;
+		CFGR       at 16#08# range 0 .. 31;
+		CIR        at 16#0C# range 0 .. 31;
+		AHB1RSTR   at 16#10# range 0 .. 31;
+		AHB2RSTR   at 16#14# range 0 .. 31;
+		AHB3RSTR   at 16#18# range 0 .. 31;
+		APB1RSTR   at 16#20# range 0 .. 31;
+		APB2RSTR   at 16#24# range 0 .. 31;
+		AHB1ENR    at 16#30# range 0 .. 31;
+		AHB2ENR    at 16#34# range 0 .. 31;
+		AHB3ENR    at 16#38# range 0 .. 31;
+		APB1ENR    at 16#40# range 0 .. 31;
+		APB2ENR    at 16#44# range 0 .. 31;
+		AHB1LPENR  at 16#50# range 0 .. 31;
+		AHB2LPENR  at 16#54# range 0 .. 31;
+		AHB3LPENR  at 16#58# range 0 .. 31;
+		APB1LPENR  at 16#60# range 0 .. 31;
+		APB2LPENR  at 16#64# range 0 .. 31;
+		BDCR       at 16#70# range 0 .. 31;
+		CSR        at 16#74# range 0 .. 31;
+		SSCGR      at 16#80# range 0 .. 31;
+		PLLI2SCFGR at 16#84# range 0 .. 31;
+	end record;
+
+end STM32.Registers.RCC;
diff --git a/source/stm32-registers-stm32f4_map.ads b/source/stm32-registers-stm32f4_map.ads
new file mode 100644
index 0000000..8a5f4dc
--- /dev/null
+++ b/source/stm32-registers-stm32f4_map.ads
@@ -0,0 +1,70 @@
+package STM32.Registers.STM32F4_Map is
+	pragma Pure;
+
+
+	TIM2:        constant := 16#4000_0000#;
+	TIM3:        constant := 16#4000_0400#;
+	TIM4:        constant := 16#4000_0800#;
+	TIM5:        constant := 16#4000_0C00#;
+	TIM6:        constant := 16#4000_1000#;
+	TIM7:        constant := 16#4000_1400#;
+	TIM12:       constant := 16#4000_1800#;
+	TIM13:       constant := 16#4000_1C00#;
+	TIM14:       constant := 16#4000_2000#;
+	RTC_and_BKP: constant := 16#4000_2800#;
+	WWDG:        constant := 16#4000_2C00#;
+	IWDG:        constant := 16#4000_3000#;
+	I2S2ext:     constant := 16#4000_3400#;
+	SPI2_I2S2:   constant := 16#4000_3800#;
+	SPI3_I2S3:   constant := 16#4000_3C00#;
+	I2S3ext:     constant := 16#4000_4000#;
+	USART2:      constant := 16#4000_4400#;
+	USART3:      constant := 16#4000_4800#;
+	UART4:       constant := 16#4000_4C00#;
+	UART5:       constant := 16#4000_5000#;
+	I2C1:        constant := 16#4000_5400#;
+	I2C2:        constant := 16#4000_5800#;
+	I2C3:        constant := 16#4000_5C00#;
+	CAN1:        constant := 16#4000_6400#;
+	CAN2:        constant := 16#4000_6800#;
+	PWR:         constant := 16#4000_7000#;
+	DAC:         constant := 16#4000_7400#;
+	TIM1:        constant := 16#4001_0000#;
+	TIM8:        constant := 16#4001_0400#;
+	USART1:      constant := 16#4001_1000#;
+	USART6:      constant := 16#4001_1400#;
+	ADC1_2_3:    constant := 16#4001_2000#;
+	SDIO:        constant := 16#4001_2C00#;
+	SPI1:        constant := 16#4001_3000#;
+	SYSCFG:      constant := 16#4001_3800#;
+	EXTI:        constant := 16#4001_3C00#;
+	TIM9:        constant := 16#4001_4000#;
+	TIM10:       constant := 16#4001_4400#;
+	TIM11:       constant := 16#4001_4800#;
+	GPIOA:       constant := 16#4002_0000#;
+	GPIOB:       constant := 16#4002_0400#;
+	GPIOC:       constant := 16#4002_0800#;
+	GPIOD:       constant := 16#4002_0C00#;
+	GPIOE:       constant := 16#4002_1000#;
+	GPIOF:       constant := 16#4002_1400#;
+	GPIOG:       constant := 16#4002_1800#;
+	GPIOH:       constant := 16#4002_1C00#;
+	GPIOI:       constant := 16#4002_2000#;
+	CRC:         constant := 16#4002_3000#;
+	RCC:         constant := 16#4002_3800#;
+	Flash_IR:    constant := 16#4002_3C00#;
+	BKPSRAM:     constant := 16#4002_4000#;
+	DMA1:        constant := 16#4002_6000#;
+	DMA2:        constant := 16#4002_6400#;
+	Ethernet_MAC:constant := 16#4002_8000#;
+	USB_OTG_HS:  constant := 16#4004_0000#;
+	USB_OTG_FS:  constant := 16#5000_0000#;
+	DCMI:        constant := 16#5005_0000#;
+	RNG:         constant := 16#5006_0800#;
+	FSMC_Bank1:  constant := 16#6000_0000#;
+	FSMC_Bank2:  constant := 16#7000_0000#;
+	FSMC_Bank3:  constant := 16#8000_0000#;
+	FSMC_Bank4:  constant := 16#9000_0000#;
+	FSMC:        constant := 16#A000_0000#;
+
+end STM32.Registers.STM32F4_Map;
diff --git a/source/stm32-registers-syscfg.ads b/source/stm32-registers-syscfg.ads
new file mode 100644
index 0000000..0b98dc5
--- /dev/null
+++ b/source/stm32-registers-syscfg.ads
@@ -0,0 +1,136 @@
+package STM32.Registers.SysCfg is
+	pragma Pure;
+
+	type Memory_Mapping is (
+		Main_Flash,
+		System_Flash,
+		FSMC_Bank_1,
+		Embedded_SRAM
+	);
+
+	for Memory_Mapping use (
+		Main_Flash => 2#00#,
+		System_Flash => 2#01#,
+		FSMC_Bank_1 => 2#10#,
+		Embedded_SRAM => 2#11#
+	);
+
+	type Memory_Remap_Register is record
+		MEM_MODE: Memory_Mapping;
+		Reserved_2: Integer range 0 .. 2**30 - 1;
+	end record with Size => 32;
+
+	for Memory_Remap_Register use record
+		MEM_MODE at 0 range 0 .. 1;
+		Reserved_2 at 0 range 2 .. 31;
+	end record;
+
+	type Ethernet_Phy_Interface is (
+		MII,
+		RMII
+	);
+
+	for Ethernet_Phy_Interface use (
+		MII => 0,
+		RMII => 1
+	);
+	type Peripherial_Mode_Register is record
+		Reserved_0: Integer range 0 .. 2**23 - 1;
+		MII_RMII_SEL: Ethernet_Phy_Interface;
+		Reserved_24: Integer range 0 .. 2**8 - 1;
+	end record with Size => 32;
+
+	for Peripherial_Mode_Register use record
+		Reserved_0 at 0 range 0 .. 22;
+		MII_RMII_SEL at 0 range 23 .. 23;
+		Reserved_24 at 0 range 24 .. 31;
+	end record;
+
+	type Peripherial_Interrupt_Pin is (
+		PA_Pin, PB_Pin, PC_Pin, PD_Pin,
+		PE_Pin, PF_Pin, PG_Pin, PH_Pin,
+		PI_Pin
+	);
+
+	for Peripherial_Interrupt_Pin use (
+		PA_Pin => 2#0000#, PB_Pin => 2#0001#,
+		PC_Pin => 2#0010#, PD_Pin => 2#0011#,
+		PE_Pin => 2#0100#, PF_Pin => 2#0101#,
+		PG_Pin => 2#0110#, PH_Pin => 2#0111#,
+		PI_Pin => 2#1000#
+	);
+
+	generic
+		Base: Integer;
+	package External_Interrupt_Configuration is
+		type Configuration_Array is
+		array (Base .. Base+3) of Peripherial_Interrupt_Pin with Pack, Size => 16;
+
+		type Register is record
+			EXTI: Configuration_Array;
+			Reserved_16: Integer range 0 .. 2**16 - 1;
+		end record with Size => 32;
+
+		for Register use record
+			EXTI at 0 range 0 .. 15;
+			Reserved_16 at 0 range 16 .. 31;
+		end record;
+	end External_Interrupt_Configuration;
+
+	package External_Interrupt_Configuration_1 is
+	new External_Interrupt_Configuration(0);
+
+	package External_Interrupt_Configuration_2 is
+	new External_Interrupt_Configuration(4);
+
+	package External_Interrupt_Configuration_3 is
+	new External_Interrupt_Configuration(8);
+
+	package External_Interrupt_Configuration_4 is
+	new External_Interrupt_Configuration(12);
+
+	type Compensation_Cell_Power_Down_Mode is (
+		Compensation_Cell_Power_Down,
+		Compensation_Cell_Enabled
+	);
+
+	for Compensation_Cell_Power_Down_Mode use (
+		Compensation_Cell_Power_Down => 0,
+		Compensation_Cell_Enabled => 1
+	);
+
+	type Compensation_Cell_Control_Register is record
+		CMP_PD: Compensation_Cell_Power_Down_Mode;
+		Reserved_1: Integer range 0 .. 2**7 - 1;
+		READY: Boolean;
+		Reserved_9: Integer range 0 .. 2**23 - 1;
+	end record with Size => 32;
+
+	for Compensation_Cell_Control_Register use record
+		CMP_PD at 0 range 0 .. 0;
+		Reserved_1 at 0 range 1 .. 7;
+		READY at 0 range 8 .. 8;
+		Reserved_9 at 0 range 9 .. 31;
+	end record;
+
+	type SYSCFG_Registers is record
+		MEMRMP: Memory_Remap_Register;
+		PMC: Peripherial_Mode_Register;
+		EXTICR1: External_Interrupt_Configuration_1.Register;
+		EXTICR2: External_Interrupt_Configuration_2.Register;
+		EXTICR3: External_Interrupt_Configuration_3.Register;
+		EXTICR4: External_Interrupt_Configuration_4.Register;
+		CMPCR: Compensation_Cell_Control_Register;
+	end record;
+
+	for SYSCFG_Registers use record
+		MEMRMP  at 16#00# range 0 .. 31;
+		PMC     at 16#04# range 0 .. 31;
+		EXTICR1 at 16#08# range 0 .. 31;
+		EXTICR2 at 16#0C# range 0 .. 31;
+		EXTICR3 at 16#10# range 0 .. 31;
+		EXTICR4 at 16#14# range 0 .. 31;
+		CMPCR   at 16#20# range 0 .. 31;
+	end record;
+
+end STM32.Registers.SysCfg;
diff --git a/source/stm32-registers.ads b/source/stm32-registers.ads
new file mode 100644
index 0000000..c55a753
--- /dev/null
+++ b/source/stm32-registers.ads
@@ -0,0 +1,3 @@
+package STM32.Registers is
+	pragma Pure;
+end STM32.Registers;
\ No newline at end of file
diff --git a/source/stm32-stm32f407z.ads b/source/stm32-stm32f407z.ads
new file mode 100644
index 0000000..df0d052
--- /dev/null
+++ b/source/stm32-stm32f407z.ads
@@ -0,0 +1,58 @@
+with System;
+with STM32.Registers.GPIO;
+with STM32.Registers.RCC;
+with STM32.Registers.EXTI;
+with STM32.Registers.SYSCFG;
+with STM32.Registers.FSMC;
+with STM32.Registers.STM32F4_Map;
+
+package STM32.STM32F407Z is
+	pragma Preelaborate;
+
+	--pragma Warnings (Off, "* may call Last_Chance_Handler");
+	--pragma Warnings (Off, "* may be incompatible with alignment of object");
+
+	EXTI: Registers.EXTI.EXTI_Registers
+	with Volatile, Import,
+	Address => System'To_Address(Registers.STM32F4_Map.EXTI);
+
+	FSMC: Registers.FSMC.FSMC_Registers
+	with Volatile, Import,
+	Address => System'To_Address(Registers.STM32F4_Map.FSMC);
+
+	GPIOA: Registers.GPIO.GPIO_Registers
+	with Volatile, Import,
+	Address => System'To_Address(Registers.STM32F4_Map.GPIOA);
+
+	GPIOC: Registers.GPIO.GPIO_Registers
+	with Volatile, Import,
+	Address => System'To_Address(Registers.STM32F4_Map.GPIOC);
+
+	GPIOD: Registers.GPIO.GPIO_Registers
+	with Volatile, Import,
+	Address => System'To_Address(Registers.STM32F4_Map.GPIOD);
+
+	GPIOE: Registers.GPIO.GPIO_Registers
+	with Volatile, Import,
+	Address => System'To_Address(Registers.STM32F4_Map.GPIOE);
+
+	GPIOF: Registers.GPIO.GPIO_Registers
+	with Volatile, Import,
+	Address => System'To_Address(Registers.STM32F4_Map.GPIOF);
+
+	GPIOG: Registers.GPIO.GPIO_Registers
+	with Volatile, Import,
+	Address => System'To_Address(Registers.STM32F4_Map.GPIOG);
+
+	RCC: Registers.RCC.RCC_Registers
+	with Volatile, Import,
+	Address => System'To_Address(Registers.STM32F4_Map.RCC);
+
+	SYSCFG: Registers.SYSCFG.SYSCFG_Registers
+	with Volatile, Import,
+	Address => System'To_Address(Registers.STM32F4_Map.SYSCFG);
+
+	--pragma Warnings (On, "* may call Last_Chance_Handler");
+	--pragma Warnings (On, "* may be incompatible with alignment of object");
+
+end STM32.STM32F407Z;
\ No newline at end of file
diff --git a/source/stm32.ads b/source/stm32.ads
new file mode 100644
index 0000000..dcd8f1e
--- /dev/null
+++ b/source/stm32.ads
@@ -0,0 +1,3 @@
+package STM32 is
+	pragma Pure;
+end STM32;
diff --git a/stm32_library.gpr b/stm32_library.gpr
new file mode 100644
index 0000000..79a9fde
--- /dev/null
+++ b/stm32_library.gpr
@@ -0,0 +1,17 @@
+project STM32_Library is
+	for Source_Dirs use ("source");
+	for Object_Dir use "objects";
+	for Library_Dir use "library";
+	for Library_Name use "stm32";
+	for Library_Kind use "static";
+	--for Library_Interface use ("STM32", "STM32.STM32F407Z");
+	for Target use "arm-eabi";
+	--for Runtime("ada") use "ravenscar-sfp-stm32f4";
+	package Builder is
+		for Default_Switches("Ada") use (
+			"-gnato",
+			"-O2",
+			"-gnatW8"
+		);
+	end Builder;
+end STM32_Library;
\ No newline at end of file