231 lines
6.4 KiB
Ada
231 lines
6.4 KiB
Ada
with STM32.Address_Map;
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-- DMA Controller
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package STM32.Direct_Memory_Access is
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-- LISR, HISR, LIFCR, HIFCR
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-- This Register definition is a bit weird,
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-- but gives ability to access a variable field
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-- that is FEIF5 = ISR(1)(0).Channel(1)(FEIF)
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type Channel_Interrupt_Status_Index is (
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FEIF, Reserved, DMEIF, TEIF, HTIF, TCIF
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);
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type Channel_Interrupt_Status is
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array (Channel_Interrupt_Status_Index) of Boolean
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with Pack, Size => 6;
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type Channel_Interrupt_Status_Pair is
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array (Integer range 0 .. 1) of Channel_Interrupt_Status
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with Pack, Size => 12;
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type Two_Channel_Interrupt_Status is record
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Channel : Channel_Interrupt_Status_Pair;
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Reserved_12 : Integer range 0 .. 2**4 - 1;
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end record with Size => 16;
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for Two_Channel_Interrupt_Status use record
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Channel at 0 range 0 .. 11;
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Reserved_12 at 0 range 12 .. 15;
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end record;
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type Interrupt_Status_Register is
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array (Integer range 0 .. 1) of Two_Channel_Interrupt_Status
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with Pack, Size => 32;
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Pragma Volatile_Full_Access(Interrupt_Status_Register);
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-- LI*R is index 0, HI*R is index 1
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type Interrupt_Status_Register_Pair is
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array (Integer range 0 .. 1) of Interrupt_Status_Register;
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-- SxCR
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type Transfer_Direction is (
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Peripheral_to_Memory, -- Peripheral to Memory Transfer
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Memory_to_Peripheral, -- Memory to Peripheral Transfer
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Memory_to_Memory -- Memory to Memory Transfer (only available on DMA2)
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) with Size => 2;
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for Transfer_Direction use (
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Peripheral_to_Memory => 2#00#,
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Memory_to_Peripheral => 2#01#,
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Memory_to_Memory => 2#10#
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);
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type Data_Size is (
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Byte,
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Half_Word,
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Word
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) with Size => 2;
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for Data_Size use (
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Byte => 2#00#,
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Half_Word => 2#01#,
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Word => 2#10#
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);
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subtype Priority_Level is Integer range 0 .. 3;
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subtype Target_Memory is Integer range 0 .. 1;
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type Burst_Transfer is (
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Single,
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INCR4,
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INCR8,
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INCR16
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) with Size => 2;
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subtype Channel_Number is Integer range 0 .. 15;
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-- note: channels 8 .. 15 are only available on F4x3 devices
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type Stream_Configuration_Register is record
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EN : Boolean := False;
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DMEIE : Boolean := False;
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TEIE : Boolean := False;
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HTIE : Boolean := False;
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TCIE : Boolean := False;
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PFCTRL : Boolean := False;
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DIR : Transfer_Direction := Peripheral_to_Memory;
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CIRC : Boolean := False;
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PINC : Boolean := False;
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MINC : Boolean := False;
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PSIZE : Data_Size := Byte;
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MSIZE : Data_Size := Byte;
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PINCOS : Boolean := False;
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PL : Priority_Level := 0;
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DBM : Boolean := False;
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CT : Target_Memory := 0;
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Unused_20 : Unused_1_Bit := 0;
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PBURST : Burst_Transfer := Single;
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MBURST : Burst_Transfer := Single;
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CHSEL : Channel_Number := 0;
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Unused_29 : Unused_3_Bits := 0;
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end record with Size => 32;
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for Stream_Configuration_Register use record
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EN at 0 range 0 .. 0;
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DMEIE at 0 range 1 .. 1;
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TEIE at 0 range 2 .. 2;
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HTIE at 0 range 3 .. 3;
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TCIE at 0 range 4 .. 4;
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PFCTRL at 0 range 5 .. 5;
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DIR at 0 range 6 .. 7;
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CIRC at 0 range 8 .. 8;
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PINC at 0 range 9 .. 9;
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MINC at 0 range 10 .. 10;
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PSIZE at 0 range 11 .. 12;
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MSIZE at 0 range 13 .. 14;
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PINCOS at 0 range 15 .. 15;
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PL at 0 range 16 .. 17;
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DBM at 0 range 18 .. 18;
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CT at 0 range 19 .. 19;
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Unused_20 at 0 range 20 .. 20;
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PBURST at 0 range 21 .. 22;
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MBURST at 0 range 23 .. 24;
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CHSEL at 0 range 25 .. 28;
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Unused_29 at 0 range 29 .. 31;
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end record;
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-- NDTR
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subtype Stream_Number_of_Data_Register is
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Interfaces.Unsigned_32 range 0 .. 2**16 - 1;
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-- This way high part will always be clear
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-- MxAR
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type Memory_Address_Register_Pair is
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array (Integer range 0 .. 1) of Address_Register
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with Size => 64;
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-- SxFCR
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type FIFO_Threshold is (
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Quarter,
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Half,
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Three_Quarters,
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Full
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) with Size => 2;
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for FIFO_Threshold use (
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Quarter => 2#00#,
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Half => 2#01#,
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Three_Quarters => 2#10#,
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Full => 2#11#
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);
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type FIFO_Status is (
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Almost_Empty,
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Below_Half,
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Above_Half,
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Almost_Full,
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Empty,
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Full
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) with Size => 3;
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for FIFO_Status use (
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Almost_Empty => 2#000#,
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Below_Half => 2#001#,
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Above_Half => 2#010#,
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Almost_Full => 2#011#,
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Empty => 2#100#,
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Full => 2#101#
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);
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type FIFO_Control_Register is record
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FTH : FIFO_Threshold;
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DMDIS : Boolean;
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FS : FIFO_Status;
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Reserved_6 : Integer range 0 .. 1;
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FEIE : Boolean;
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Reserved_8 : Integer range 0 .. 2**24 - 1;
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end record with Size => 32;
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for FIFO_Control_Register use record
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FTH at 0 range 0 .. 1;
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DMDIS at 0 range 2 .. 2;
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FS at 0 range 3 .. 5;
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Reserved_6 at 0 range 6 .. 6;
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FEIE at 0 range 7 .. 7;
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Reserved_8 at 0 range 8 .. 31;
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end record;
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DMA_Stream_Registers_Size : constant := 8 * 16#18#;
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DMA_Streams : constant := 8;
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type DMA_Stream_Registers is record
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CR : Stream_Configuration_Register;
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pragma Volatile_Full_Access(CR);
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NDTR : Stream_Number_Of_Data_Register;
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pragma Volatile_Full_Access(NDTR);
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PAR : Address_Register; -- Address in peripheral and also source in MtM transfer
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MAR : Memory_Address_Register_Pair; -- Address in memory to transfer
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FCR : FIFO_Control_Register;
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pragma Volatile_Full_Access(FCR);
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end record with Size => DMA_Stream_Registers_Size, Volatile;
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for DMA_Stream_Registers use record
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CR at 16#00# range 0 .. 31;
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NDTR at 16#04# range 0 .. 31;
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PAR at 16#08# range 0 .. 31;
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MAR at 16#0C# range 0 .. 63;
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FCR at 16#14# range 0 .. 31;
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end record;
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type DMA_Stream_Array is
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array (Integer range 0 .. DMA_Streams - 1) of DMA_Stream_Registers
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with Size => DMA_Streams * DMA_Stream_Registers_Size;
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type DMA_Registers is record
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ISR : Interrupt_Status_Register_Pair;
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IFCR : Interrupt_Status_Register_Pair;
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S : DMA_Stream_Array;
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end record with Volatile;
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for DMA_Registers use record
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ISR at 16#00# range 0 .. 63;
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IFCR at 16#08# range 0 .. 63;
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S at 16#10# range 0 .. DMA_Streams * DMA_Stream_Registers_Size - 1;
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end record;
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DMA1 : DMA_Registers with Volatile, Import, Address => Address_Map.DMA1;
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DMA2 : DMA_Registers with Volatile, Import, Address => Address_Map.DMA2;
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end STM32.Direct_Memory_Access; |