528 lines
16 KiB
Ada
528 lines
16 KiB
Ada
package STM32.ADC with Pure is
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-- SR
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type Status_Register is record
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AWD : Boolean; -- Analog watchdog flag
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EOC : Boolean; -- Regular channel end of conversion
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JEOC : Boolean; -- Injected channel end of conversion
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JSTRT : Boolean; -- Injected channel start flag
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STRT : Boolean; -- Regular channel start flag
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OVR : Boolean; -- Overrun
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Reserved : Integer range 0 .. 2**26 - 1;
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end record with Size => 32;
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for Status_Register use record
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AWD at 0 range 0 .. 0;
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EOC at 0 range 1 .. 1;
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JEOC at 0 range 2 .. 2;
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JSTRT at 0 range 3 .. 3;
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STRT at 0 range 4 .. 4;
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OVR at 0 range 5 .. 5;
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Reserved at 0 range 6 .. 31;
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end record;
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-- CR1
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type Resolution is (
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Resolution_12_Bits,
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Resolution_10_Bits,
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Resolution_8_Bits,
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Resolution_6_Bits
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) with Size => 2;
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for Resolution use (
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Resolution_12_Bits => 2#00#,
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Resolution_10_Bits => 2#01#,
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Resolution_8_Bits => 2#10#,
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Resolution_6_Bits => 2#11#
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);
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type Control_Register_1 is record
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AWDCH : Integer range 0 .. 18 := 0; -- Analog watchdog channel select
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EOCIE : Boolean := False; -- Interrupt enable for EOC
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AWDIE : Boolean := False; -- Analog watchdog interrupt enable
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JEOCIE : Boolean := False; -- Interrupt enable for injected channels
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SCAN : Boolean := False; -- Scan mode enable
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AWDSGL : Boolean := False; -- Enable watchdog on a single channel in scan mode
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JAUTO : Boolean := False; -- Automatic injected group conversion
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DISCEN : Boolean := False; -- Discontinuous mode on regular channels enable
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JDISCEN : Boolean := False; -- Discontinuous mode on injected channels enable
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DISCNUM : Integer range 0 .. 2**3 - 1 := 0; -- Discontinuous mode channel count minus 1
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Reserved_16 : Integer range 0 .. 2**6 - 1 := 0;
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JAWDEN : Boolean := False; -- Analog watchdog enable on injected channels
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AWDEN : Boolean := False; -- Analog watchdog enable on regular channels
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RES : Resolution := Resolution_12_Bits; -- ADC resolution
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OVRIE : Boolean := False; -- Overrun interrupt enable
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Reserved_27 : Integer range 0 .. 2**5 - 1 := 0;
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end record with Size => 32;
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for Control_Register_1 use record
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AWDCH at 0 range 0 .. 4;
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EOCIE at 0 range 5 .. 5;
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AWDIE at 0 range 6 .. 6;
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JEOCIE at 0 range 7 .. 7;
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SCAN at 0 range 8 .. 8;
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AWDSGL at 0 range 9 .. 9;
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JAUTO at 0 range 10 .. 10;
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DISCEN at 0 range 11 .. 11;
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JDISCEN at 0 range 12 .. 12;
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DISCNUM at 0 range 13 .. 15;
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Reserved_16 at 0 range 16 .. 21;
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JAWDEN at 0 range 22 .. 22;
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AWDEN at 0 range 23 .. 23;
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RES at 0 range 24 .. 25;
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OVRIE at 0 range 26 .. 26;
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Reserved_27 at 0 range 27 .. 31;
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end record;
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-- CR2
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type DMA_Disable is (
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Stop_after_Last,
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Continue
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) with Size => 1;
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for DMA_Disable use (
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Stop_after_Last => 0,
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Continue => 1
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);
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type End_of_Conversion_Select is (
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End_of_Sequence,
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End_of_Conversion
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) with Size => 1;
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for End_of_Conversion_Select use (
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End_of_Sequence => 0,
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End_of_Conversion => 1
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);
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type Data_Alignment is (
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Right,
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Left
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) with Size => 1;
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for Data_Alignment use (
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Right => 0,
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Left => 1
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);
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type External_Event_Injected is (
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Timer_1_CC4,
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Timer_1_TRGO,
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Timer_2_CC1,
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Timer_2_TRGO,
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Timer_3_CC2,
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Timer_3_CC4,
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Timer_4_CC1,
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Timer_4_CC2,
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Timer_4_CC3,
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Timer_4_TRGO,
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Timer_5_CC4,
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Timer_5_TRGO,
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Timer_8_CC2,
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Timer_8_CC3,
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Timer_8_CC4,
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EXTI_Line15
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) with Size => 4;
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for External_Event_Injected use (
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Timer_1_CC4 => 2#0000#,
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Timer_1_TRGO => 2#0001#,
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Timer_2_CC1 => 2#0010#,
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Timer_2_TRGO => 2#0011#,
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Timer_3_CC2 => 2#0100#,
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Timer_3_CC4 => 2#0101#,
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Timer_4_CC1 => 2#0110#,
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Timer_4_CC2 => 2#0111#,
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Timer_4_CC3 => 2#1000#,
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Timer_4_TRGO => 2#1001#,
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Timer_5_CC4 => 2#1010#,
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Timer_5_TRGO => 2#1011#,
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Timer_8_CC2 => 2#1100#,
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Timer_8_CC3 => 2#1101#,
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Timer_8_CC4 => 2#1110#,
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EXTI_Line15 => 2#1111#
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);
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type External_Event_Regular is (
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Timer_1_CC1,
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Timer_1_CC2,
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Timer_1_CC3,
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Timer_2_CC2,
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Timer_2_CC3,
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Timer_2_CC4,
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Timer_2_TRGO,
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Timer_3_CC1,
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Timer_3_TRGO,
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Timer_4_CC4,
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Timer_5_CC1,
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Timer_5_CC2,
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Timer_5_CC3,
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Timer_8_CC1,
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Timer_8_TRGO,
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EXTI_Line11
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) with Size => 4;
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for External_Event_Regular use (
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Timer_1_CC1 => 2#0000#,
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Timer_1_CC2 => 2#0001#,
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Timer_1_CC3 => 2#0010#,
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Timer_2_CC2 => 2#0011#,
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Timer_2_CC3 => 2#0100#,
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Timer_2_CC4 => 2#0101#,
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Timer_2_TRGO => 2#0110#,
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Timer_3_CC1 => 2#0111#,
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Timer_3_TRGO => 2#1000#,
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Timer_4_CC4 => 2#1001#,
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Timer_5_CC1 => 2#1010#,
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Timer_5_CC2 => 2#1011#,
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Timer_5_CC3 => 2#1100#,
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Timer_8_CC1 => 2#1101#,
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Timer_8_TRGO => 2#1110#,
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EXTI_Line11 => 2#1111#
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);
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type External_Trigger_Enable is (
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Disabled,
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Rising_Edge,
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Falling_Edge,
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Both_Edges
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) with Size => 2;
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for External_Trigger_Enable use (
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Disabled => 2#00#,
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Rising_Edge => 2#01#,
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Falling_Edge => 2#10#,
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Both_Edges => 2#11#
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);
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type Control_Register_2 is record
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ADON : Boolean := False;
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CONT : Boolean := False;
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Reserved_2 : Integer range 0 .. 2**6 - 1 := 0;
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DMA : Boolean := False;
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DDS : DMA_Disable := Stop_after_Last;
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EOCS : End_of_Conversion_Select := End_of_Sequence;
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ALIGN : Data_Alignment := Right;
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Reserved_12 : Integer range 0 .. 15 := 0;
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JEXTSEL : External_Event_Injected := Timer_1_CC4;
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JEXTEN : External_Trigger_Enable := Disabled;
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JSWSTART : Boolean := False; -- Start conversion of injected channels
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EXTSEL : External_Event_Regular := Timer_1_CC1;
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EXTEN : External_Trigger_Enable := Disabled; -- External trigger enable for regular channels
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SWSTART : Boolean := False; -- Start conversion of regular channels
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Reserved_31 : Integer range 0 .. 1 := 0;
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end record with Size => 32;
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for Control_Register_2 use record
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ADON at 0 range 0 .. 0;
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CONT at 0 range 1 .. 1;
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Reserved_2 at 0 range 2 .. 7;
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DMA at 0 range 8 .. 8;
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DDS at 0 range 9 .. 9;
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EOCS at 0 range 10 .. 10;
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ALIGN at 0 range 11 .. 11;
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Reserved_12 at 0 range 12 .. 15;
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JEXTSEL at 0 range 16 .. 19;
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JEXTEN at 0 range 20 .. 21;
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JSWSTART at 0 range 22 .. 22;
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EXTSEL at 0 range 24 .. 27;
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EXTEN at 0 range 28 .. 29;
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SWSTART at 0 range 30 .. 30;
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Reserved_31 at 0 range 31 .. 31;
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end record;
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-- SMPRx
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type Sampling_Time is (
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Sample_3_Cycles,
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Sample_15_Cycles,
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Sample_28_Cycles,
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Sample_56_Cycles,
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Sample_84_Cycles,
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Sample_112_Cycles,
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Sample_144_Cycles,
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Sample_480_Cycles
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) with Size => 3;
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for Sampling_Time use (
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Sample_3_Cycles => 2#000#,
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Sample_15_Cycles => 2#001#,
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Sample_28_Cycles => 2#010#,
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Sample_56_Cycles => 2#011#,
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Sample_84_Cycles => 2#100#,
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Sample_112_Cycles => 2#101#,
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Sample_144_Cycles => 2#110#,
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Sample_480_Cycles => 2#111#
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);
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type Sample_Time_Array is array (Integer range <>) of Sampling_Time with Pack;
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type Sample_Time_Register_1 is record
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SMP : Sample_Time_Array (10 .. 18) := (others => Sample_3_Cycles);
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Reserved : Integer range 0 .. 2**5 - 1 := 0;
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end record with Size => 32;
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for Sample_Time_Register_1 use record
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SMP at 0 range 0 .. 26;
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Reserved at 0 range 27 .. 31;
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end record;
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type Sample_Time_Register_2 is record
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SMP : Sample_Time_Array (0 .. 9) := (others => Sample_3_Cycles);
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Reserved : Integer range 0 .. 3 := 0;
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end record with Size => 32;
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for Sample_Time_Register_2 use record
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SMP at 0 range 0 .. 29;
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Reserved at 0 range 30 .. 31;
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end record;
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-- SQRx
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subtype Channel is Integer range 0 .. 18;
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type Channel_Sequence_Array is array (Integer range <>) of Channel with Pack, Component_Size => 5;
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type Regular_Sequence_Register_1 is record
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SQ : Channel_Sequence_Array (13 .. 16) := (others => 0);
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L : Integer range 0 .. 2**4 - 1 := 0; -- Regular channel sequence length minus 1
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Reserved : Integer range 0 .. 2**8 - 1 := 0;
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end record with Size => 32;
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for Regular_Sequence_Register_1 use record
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SQ at 0 range 0 .. 19;
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L at 0 range 20 .. 23;
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Reserved at 0 range 24 .. 31;
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end record;
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type Regular_Sequence_Register_2 is record
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SQ : Channel_Sequence_Array (7 .. 12) := (others => 0);
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Reserved : Integer range 0 .. 3 := 0;
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end record with Size => 32;
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for Regular_Sequence_Register_2 use record
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SQ at 0 range 0 .. 29;
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Reserved at 0 range 30 .. 31;
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end record;
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type Regular_Sequence_Register_3 is record
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SQ : Channel_Sequence_Array (1 .. 6) := (others => 0);
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Reserved : Integer range 0 .. 3 := 0;
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end record with Size => 32;
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for Regular_Sequence_Register_3 use record
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SQ at 0 range 0 .. 29;
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Reserved at 0 range 30 .. 31;
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end record;
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type Injected_Sequence_Register is record
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JSQ : Channel_Sequence_Array (1 .. 4) := (others => 0);
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JL : Integer range 0 .. 3 := 0; -- Injected channel sequence length minus 1
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Reserved : Integer range 0 .. 2**10 - 1 := 0;
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end record with Size => 32;
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for Injected_Sequence_Register use record
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JSQ at 0 range 0 .. 19;
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JL at 0 range 20 .. 21;
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Reserved at 0 range 22 .. 31;
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end record;
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type DR_Register is record
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DATA : Integer range 0 .. 2**16 - 1;
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end record with Size => 32;
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for DR_Register use record
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DATA at 0 range 0 .. 15;
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end record;
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type ADC_Registers is record
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SR : Status_Register;
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pragma Volatile_Full_Access (SR);
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CR1 : Control_Register_1;
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pragma Volatile_Full_Access (CR1);
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CR2 : Control_Register_2;
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pragma Volatile_Full_Access (CR2);
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SMPR1 : Sample_Time_Register_1;
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pragma Volatile_Full_Access (SMPR1);
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SMPR2 : Sample_Time_Register_2;
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pragma Volatile_Full_Access (SMPR2);
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JOFR1 : Integer range 0 .. 2**12 - 1 := 0;
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pragma Volatile_Full_Access (JOFR1);
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JOFR2 : Integer range 0 .. 2**12 - 1 := 0;
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pragma Volatile_Full_Access (JOFR2);
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JOFR3 : Integer range 0 .. 2**12 - 1 := 0;
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pragma Volatile_Full_Access (JOFR3);
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JOFR4 : Integer range 0 .. 2**12 - 1 := 0;
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pragma Volatile_Full_Access (JOFR4);
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HTR : Integer range 0 .. 2**12 - 1 := 16#0000_0FFF#;
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pragma Volatile_Full_Access (HTR);
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LTR : Integer range 0 .. 2**12 - 1 := 16#0000_0000#;
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pragma Volatile_Full_Access (LTR);
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SQR1 : Regular_Sequence_Register_1;
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pragma Volatile_Full_Access (SQR1);
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SQR2 : Regular_Sequence_Register_2;
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pragma Volatile_Full_Access (SQR2);
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SQR3 : Regular_Sequence_Register_3;
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pragma Volatile_Full_Access (SQR3);
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JSQR : Injected_Sequence_Register;
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pragma Volatile_Full_Access (JSQR);
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JDR1 : Integer range 0 .. 2**16 - 1 := 0;
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pragma Volatile_Full_Access (JDR1);
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JDR2 : Integer range 0 .. 2**16 - 1 := 0;
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pragma Volatile_Full_Access (JDR2);
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JDR3 : Integer range 0 .. 2**16 - 1 := 0;
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pragma Volatile_Full_Access (JDR3);
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JDR4 : Integer range 0 .. 2**16 - 1 := 0;
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pragma Volatile_Full_Access (JDR4);
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DR : Integer range 0 .. 2**16 - 1 := 0;
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pragma Volatile_Full_Access (DR);
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end record;
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for ADC_Registers use record
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SR at 16#00# range 0 .. 31;
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CR1 at 16#04# range 0 .. 31;
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CR2 at 16#08# range 0 .. 31;
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SMPR1 at 16#0C# range 0 .. 31;
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SMPR2 at 16#10# range 0 .. 31;
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JOFR1 at 16#14# range 0 .. 31;
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JOFR2 at 16#18# range 0 .. 31;
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JOFR3 at 16#1C# range 0 .. 31;
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JOFR4 at 16#20# range 0 .. 31;
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HTR at 16#24# range 0 .. 31;
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LTR at 16#28# range 0 .. 31;
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SQR1 at 16#2C# range 0 .. 31;
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SQR2 at 16#30# range 0 .. 31;
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SQR3 at 16#34# range 0 .. 31;
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JSQR at 16#38# range 0 .. 31;
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JDR1 at 16#3C# range 0 .. 31;
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JDR2 at 16#40# range 0 .. 31;
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JDR3 at 16#44# range 0 .. 31;
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JDR4 at 16#48# range 0 .. 31;
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DR at 16#4C# range 0 .. 31;
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end record;
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-- CSR
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type ADC_Status is record
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AWD : Boolean;
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EOC : Boolean;
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JEOC : Boolean;
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JSTRT : Boolean;
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STRT : Boolean;
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OVR : Boolean;
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Reserved : Integer range 0 .. 3;
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end record with Size => 8;
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for ADC_Status use record
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AWD at 0 range 0 .. 0;
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EOC at 0 range 1 .. 1;
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JEOC at 0 range 2 .. 2;
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JSTRT at 0 range 3 .. 3;
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STRT at 0 range 4 .. 4;
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OVR at 0 range 5 .. 5;
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Reserved at 0 range 6 .. 7;
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end record;
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type ADC_Status_Array is array (Integer range <>) of ADC_Status with Pack;
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type Common_Status_Register is record
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ADC : ADC_Status_Array (1 .. 3);
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Reserved : Integer range 0 .. 2**8 - 1;
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end record with Size => 32;
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for Common_Status_Register use record
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ADC at 0 range 0 .. 23;
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Reserved at 0 range 24 .. 31;
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end record;
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-- CCR
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type Multi_ADC_Mode is (
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Independent,
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Dual_Regular_and_Injected,
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Dual_Regular_and_Alternate_Trigger,
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Dual_Injected,
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Dual_Regular,
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Dual_Interleaved,
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Dual_Alternate_Trigger,
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Triple_Regular_and_Injected,
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Triple_Regular_and_Alternate_Trigger,
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Triple_Injected,
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Triple_Regular,
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Triple_Interleaved,
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Triple_Alternate_Trigger
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) with Size => 5;
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for Multi_ADC_Mode use (
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Independent => 2#00000#,
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Dual_Regular_and_Injected => 2#00001#,
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Dual_Regular_and_Alternate_Trigger => 2#00010#,
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Dual_Injected => 2#00101#,
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Dual_Regular => 2#00110#,
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Dual_Interleaved => 2#00111#,
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Dual_Alternate_Trigger => 2#01001#,
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Triple_Regular_and_Injected => 2#10001#,
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Triple_Regular_and_Alternate_Trigger => 2#10010#,
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Triple_Injected => 2#10101#,
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Triple_Regular => 2#10110#,
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Triple_Interleaved => 2#10111#,
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Triple_Alternate_Trigger => 2#11001#
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);
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type DMA_Mode is (
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Disabled,
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Half_Words_Single,
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Half_Words_Pairs,
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Bytes_Pairs
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) with Size => 2;
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for DMA_Mode use (
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Disabled => 2#00#,
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Half_Words_Single => 2#01#,
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Half_Words_Pairs => 2#10#,
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Bytes_Pairs => 2#11#
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);
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type ADC_Prescaler is (
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PCLK_Div_2,
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PCLK_Div_4,
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PCLK_Div_6,
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PCLK_Div_8
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) with Size => 2;
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for ADC_Prescaler use (
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PCLK_Div_2 => 2#00#,
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PCLK_Div_4 => 2#01#,
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PCLK_Div_6 => 2#10#,
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PCLK_Div_8 => 2#11#
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);
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type Common_Control_Register is record
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MULTI : Multi_ADC_Mode := Independent; -- Multi ADC mode selection
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Reserved_5 : Integer range 0 .. 7 := 0;
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DLAY : Integer range 0 .. 2**4 - 1 := 0; -- Delay between 2 sampling phases minus 5
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Reserved_12 : Integer range 0 .. 1 := 0;
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DDS : DMA_Disable := Stop_After_Last; -- DMA disable selection in multi ADC mode
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DMA : DMA_Mode := Disabled; -- DMA mode
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ADCPRE : ADC_Prescaler := PCLK_Div_2; -- ADC prescaler
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Reserved_18 : Integer range 0 .. 15 := 0;
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VBATE : Boolean := False; -- Vbat enable
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TSVREFE : Boolean := False; -- Temperature sensor and Vrefint enable
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Reserved_24 : Integer range 0 .. 2**8 - 1 := 0;
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|
end record with Size => 32;
|
|
for Common_Control_Register use record
|
|
MULTI at 0 range 0 .. 4;
|
|
Reserved_5 at 0 range 5 .. 7;
|
|
DLAY at 0 range 8 .. 11;
|
|
Reserved_12 at 0 range 12 .. 12;
|
|
DDS at 0 range 13 .. 13;
|
|
DMA at 0 range 14 .. 15;
|
|
ADCPRE at 0 range 16 .. 17;
|
|
Reserved_18 at 0 range 18 .. 21;
|
|
VBATE at 0 range 22 .. 22;
|
|
TSVREFE at 0 range 23 .. 23;
|
|
Reserved_24 at 0 range 24 .. 31;
|
|
end record;
|
|
|
|
type Common_Data_Register is record
|
|
DATA1 : Integer range 0 .. 2**16 - 1;
|
|
DATA2 : Integer range 0 .. 2**16 - 1;
|
|
end record with Size => 32;
|
|
for Common_Data_Register use record
|
|
DATA1 at 0 range 0 .. 15;
|
|
DATA2 at 0 range 16 .. 31;
|
|
end record;
|
|
|
|
type Common_ADC_Registers is record
|
|
CSR : Common_Status_Register;
|
|
pragma Volatile_Full_Access (CSR);
|
|
CCR : Common_Control_Register;
|
|
pragma Volatile_Full_Access (CCR);
|
|
CDR : Common_Data_Register;
|
|
pragma Volatile_Full_Access (CDR);
|
|
end record with Volatile;
|
|
for Common_ADC_Registers use record
|
|
CSR at 16#00# range 0 .. 31;
|
|
CCR at 16#04# range 0 .. 31;
|
|
CDR at 16#08# range 0 .. 31;
|
|
end record;
|
|
|
|
end STM32.ADC;
|