roms main(): confirm what serprog images are built

just like we do for coreboot images, do it for serprog.

Signed-off-by: Leah Rowe <leah@libreboot.org>

.gitignore

@@ -2,7 +2,6 @@
 *.o
 /cbmk.err.log
 /docs/
-/cbutils/
 /util/dell-flash-unlock/dell_flash_unlock
 /TODO
 /tmp/
@@ -23,3 +22,6 @@
 /versiondate
 /util/nvmutil/nvm
 /src/
+/CHANGELOG
+/todo.txt
+/lock

README.md

@@ -12,211 +12,34 @@ well-supported. It replaces proprietary BIOS/UEFI firmware. Help is available
 via [\#canoeboot IRC](https://web.libera.chat/#canoeboot)
 on [Libera](https://libera.chat/) IRC.
 
-Why use Canoeboot?
-==================
+Canoeboot is maintained in parallel with Libreboot, by the same developer.
+Strictly speaking, it is a *fork* of Libreboot, but with a twist:
 
-Why should you use *canoeboot*?
-----------------------------
+Canoeboot is provided for the purists who absolutely wish to have no proprietary
+software of any kind. Regardless of any other firmware that exists outside of it,
+the boot flash on your system will be *entirely free software* if you install
+Canoeboot on it. That includes a complete lack of CPU microcode updates, as per
+FSF policy.
 
-Canoeboot gives you freedoms that you otherwise can't get with most other
-boot firmware. It's extremely powerful and configurable for many use cases.
+More specifically: Canoeboot is engineered to comply with the GNU Free System
+Distribution Guidelines. It has, as of November 2023 releases, been strictly
+audited by FSF licensing staff (Craig Topham lead the audit), and it is listed
+on the FSF's own Free Software Directory.
 
-You have rights. The right to privacy, freedom of thought, freedom of speech
-and the right to read. In this context, Canoeboot gives you these rights.
-Your freedom matters.
-[Right to repair](https://vid.puffyan.us/watch?v=Npd_xDuNi9k) matters.
-Many people use proprietary (non-libre)
-boot firmware, even if they use [a libre OS](https://www.openbsd.org/).
-Proprietary firmware often contains backdoors (more info on the FAQ), and it
-and can be buggy. The canoeboot project was founded in October 2023,
-with the express purpose of making coreboot firmware accessible for
-non-technical users.
-
-The `canoeboot` project uses [coreboot](https://www.coreboot.org/) for [hardware
-initialisation](https://doc.coreboot.org/getting_started/architecture.html).
-Coreboot is notoriously difficult to install for most non-technical users; it
-handles only basic initialization and jumps to a separate
-[payload](https://doc.coreboot.org/payloads.html) program (e.g.
-[GRUB](https://www.gnu.org/software/grub/),
-[Tianocore](https://www.tianocore.org/)), which must also be configured.
-*The canoeboot software solves this problem*; it is a *coreboot distribution* with
-an automated build system (named *cbmk*) that builds complete *ROM images*, for
-more robust installation. Documentation is provided.
-
-How does Canoeboot differ from coreboot?
-========================================
-
-In the same way that *Debian* is a GNU+Linux distribution, `canoeboot` is
-a *coreboot distribution*. If you want to build a ROM image from scratch, you
-otherwise have to perform expert-level configuration of coreboot, GRUB and
-whatever other software you need, to prepare the ROM image. With *canoeboot*,
-you can literally download from Git or a source archive, and run `make`, and it
-will build entire ROM images. An automated build system, named `cbmk`
-(Canoeboot MaKe), builds these ROM images automatically, without any user input
-or intervention required. Configuration has already been performed in advance.
-
-If you were to build regular coreboot, without using canoeboot's automated
-build system, it would require a lot more intervention and decent technical
-knowledge to produce a working configuration.
-
-Regular binary releases of `canoeboot` provide these
-ROM images pre-compiled, and you can simply install them, with no special
-knowledge or skill except the ability to follow installation instructions
-and run commands BSD/Linux.
-
-Canoeboot vs Libreboot
-----------------------
-
-Libreboot and Canoeboot are both lead by the same founder, Leah Rowe, kept in
-sync whenever feasible; for each Libreboot release, a Canoeboot release follows.
-
-Canoeboot is a fork of [Libreboot](https://libreboot.org/), provided as a proof
-of concept demonstrating Libreboot in its current state per release, while
-removing any and all parts that do not comply with the GNU Free System
-Distribution Guideline (GNU FSDG). GNU FSDG is the policy that Libreboot used to
-be based on, but Libreboot adopted a more pragmatic [Binary Blob Reduction
-Policy](https://libreboot.org/news/policy.html) in November 2022, resulting
-in greater hardware support.
-
-Canoeboot supports fewer mainboards than Libreboot,
-because it takes a hardline approach by limiting itself only to those mainboards
-which can be booted entirely without binary blob code *in the main boot flash*.
-The distinction of *in the main boot flash* is extremely important, because many
-examples exist where coreboot interacts with certain proprietary software; for
-example, the EC (Embedded Controller) firmware on some ThinkPads that both
-Libreboot and Canoeboot support. GNU FSDG is full of contradictions like this;
-for example, the HP Elitebooks supported by Libreboot 20231021 use proprietary
-EC firmware too, but it's in the main boot flash, whereas on many other machines
-it would be on a separate chip, and not the main boot flash.
-
-Coreboot can boot with Free Software exclusively on many boards, but quite a few
-more mainboards exist where that is not the case. For example, a given mainboard
-may require a blob to configure the memory controller. Libreboot provides as few
-binary blobs as possible while allowing any mainboard to be supported, whereas
-Canoeboot provides *no* binary blobs and thus can only support a limited subset
-of what coreboot supports.
-
-Libreboot started with the no-blob policy, in December 2013. In December 2020,
-another project lead by Leah Rowe was created, named *osboot*. The osboot
-project had the same policy as current Libreboot, and was later merged into
-Libreboot, during November 2022. Thus, Libreboot *became* osboot, and it has
-improved substantially since then. This was done, in an effort to bring coreboot
-to more people, since Libreboot was much better established at that point. Since
-then, the decision has proven to be quite successful, with many more users.
-
-While the no-blob approach may seem noble, it stifles the adopt of Free
-Software, in this case coreboot, by alienating those users who like the idea of
-free software but do not have such "pure" hardware. The FSF's definition of
-purity (in this context) is deeply flawed, as it contains many contradictions.
-
-Binary blobs are *bad*. Free software is *good*, and everyone deserves to have
-freedom in their computing. The irony is that there are some who would denounce
-the current Libreboot project, under the logic that it is *enabling* proprietary
-software, but this is not so; Libreboot is *removing* proprietary software, when
-you install it.
-
-Therefore, the nuance in the type of thinking behind *Libreboot* policy is that
-while proprietary software *is* bad, and should be avoided, that choice may not
-always be available; in such cases then, it can be used but with the stipulation
-that it be replaced (with free software) at a future date, and that strong
-education is given about it in the meantime. Indeed, many projects out there,
-for example many Linux and/or GNU-based systems, will *include* such proprietary
-software (such as wifi firmware blobs) and *not tell you about it*, or not
-clearly document its existence. Libreboot very clearly documents what and where
-these blobs are, in this document:
-<https://libreboot.org/freedom-status.html>
-
-The mentality behind Libreboot policy is that *some* software freedom is better
-than none. For example, if you're running a ThinkPad X230 or T440p, both of these
-can boot entirely without binary blobs in coreboot, but you do still need the
-neutered Intel ME image outside of that (in the ME region of the flash, whereas
-coreboot goes in the BIOS region). More information about that is available,
-on the Freedom Status page of the Libreboot project:
-<https://libreboot.org/freedom-status.html>
-
-Libreboot still supports all of the same mainboards that Canoeboot supports, and
-provides the exact same configuration as options in each release. In other words,
-the no-blob configuration is still possible in Libreboot, and that will always
-be true, when possible on a given mainboard. Libreboot's *preference* is
-precisely to promote Free Software, hence the Binary Blob Reduction Policy.
-Again for posterity, here is a link to the text of that policy:
-<https://libreboot.org/news/policy.html>
-
-By contrast, many projects (that handle blobs) do not have such a stipulation.
-They either have no policy, a loosely defined policy, or they actively
-encourage the use of blobs. Libreboot does not encourage use of binary blobs,
-unless absolutely necessary on a given mainboard; whereas, a project like
-Debian will provide the `nouveau` driver for nvidia graphics cards, while also
-providing the binary drivers from Nvidia (which is proprietary); if Libreboot
-were to become a Debian, it would only recommend the `nouveau` driver if that
-works well enough. And now an example closer to home: in Libreboot, let's say
-you have a board with Intel graphics. Libreboot provides free initialisation
-of the framebuffer (using coreboot's `libgfxinit`), which has some limitations
-but does work well with Linux/BSD, and you could add Tianocore for an efi
-framebuffer if you wanted; an alternative to this is the proprietary VGA Option
-ROM from intel, which can provide full VGA mode setting as a BIOS callback,
-which would enable more operating systems (e.g. ReactOS, games in FreeDOS, etc).
-Libreboot does not provide the Intel VGA ROM, because it is not needed. Linux
-and BSD are fine, you you can play DOS games in dosbox if you really want to.
-You do not need to boot DOOM on FreeDOS.
-
-To summarise the above point:
-if Libreboot had a policy like the Debian one, it would provide that VGA ROM.
-Libreboot is not Debian. But it does not follow GNU's hardline approach either.
-Both approaches are bad. Libreboot policy is based on FSF ideology, but without
-dogma. So, the difference with Canoeboot is that it *also implements the dogma*.
-The FSF and GNU dogma is that proprietary software must *always* be avoided,
-under all circumstances. Libreboot does not implement such dogma.
-
-The purpose of Canoeboot is therefore to demonstrate what can be done under
-such dogma, while providing criticism of it in favour of Libreboot policy.
-The Libreboot policy is correct because it provides more software freedom
-overall to more people. In any software community, a certain fixed percentage
-of people will become programmers, and so bringing coreboot to more people will
-inevitably lead to more people becoming coreboot developers; this may then
-encourage more people to reverse engineer the blobs to produce free source code.
-
-To put the above point another way:
-the GNU FSDG policy, dictated by the FSF, is causing *active harm* to the
-adoption of Free Software. For example, if a Windows user is introduced to Linux
-for the first time, but they are introduced to an FSDG-compliant distro like
-Trisquel, they may find that certain hardware doesn't work. They aren't master
-hackers, they are clueless novices, and everything needs to work or they are
-going to ditch Linux and keep using Windows. That is just a fact, with most
-people, even principled people who believe in the ideals. When someone is just
-starting out, they need the experience to be as smooth as possible.
-
-That novice user could one day reverse engineer graphics drivers and bring about
-the next revolution in software freedom, but a bad early experience will deter
-them early on, and thus stifle future development of free software. This is the
-argument put forward by Libreboot, as of November 2022 with the merging of osboot.
-
-tl;dr just imagine a universe where osboot never existed, and know that
-Canoeboot is essentially what Libreboot *might* have been at this point in
-time. It is a representation of what *was*, and what could have been. Canoeboot
-is one possible answer to that *what if*, although the actual universe where
-osboot didn't exist may not have produced exactly the same result as Canoeboot
-today; it could be slightly different. Libreboot butterflies...
-
-Libreboot today is far superior to Canoeboot, and it's what you should use, but
-there are a few who prefer the old Libreboot policy, who absolutely do not want
-any proprietary software even to be present, let alone installed and/or
-executed. Thus, canoeboot was born.
-
-Canoeboot provides the same level of automation that Libreboot does in the
-downloading, patching and building of coreboot ROM images, but it excludes any
-binary blobs that may otherwise be present in upstream projects. Canoeboot will
-also remove non-blobs that are still proprietary software; there are some cases
-where software may be provided by a vendor with source code, but under some
-license that puts restrictions on its use or distribution. Canoeboot will only
-knowingly provide software that adheres to the GNU Free Software Definition, in
-compliance with the GNU Free System Distribution Guidelines.
+Libreboot previously complied with that same policy, but changed to a different
+one permitting binary blobs in limited circumstances, so as to support more newer
+machines. Canoeboot is, then, a continuation of the traditional Libreboot
+project prior to that policy change. Some users still want it, so, Canoeboot
+releases are rigoriously maintained, re-basing on newer Libreboot releases over
+time, just like how, say, Trisquel, re-bases itself on each new Ubuntu release.
 
 Project goals
 =============
 
--   *Support as much hardware as possible!* (within the restrictions imposed
-    by GNU FSDG policy)
+-   Obviously, support as much hardware as possible (within the limitations
+    imposed by GNU FSDG, and using what coreboot happens to have in its source
+    tree - Canoeboot also heavily patches coreboot, sometimes adding new
+    mainboards out-of-tree).
 -   *Make coreboot easy to use*. Coreboot is notoriously difficult
     to install, due to an overall lack of user-focused documentation
     and support. Most people will simply give up before attempting to
@@ -228,7 +51,7 @@ automating much of the coreboot image creation and customization.
 Secondly, the project produces documentation aimed at non-technical users.
 Thirdly, the project attempts to provide excellent user support via IRC.
 
-Canoeboot already comes with a payload (GRUB), flashrom and other
+Canoeboot already comes with a payload (GRUB), flashprog and other
 needed parts. Everything is fully integrated, in a way where most of
 the complicated steps that are otherwise required, are instead done
 for the user in advance.
@@ -242,7 +65,8 @@ Not a coreboot fork!
 --------------------
 
 Canoeboot is not a fork of coreboot. Every so often, the project
-re-bases on the latest version of coreboot, with the number of custom
+re-bases on the latest version of coreboot, by virtue of maintaining sync
+with Libreboot releases (minus un-GNU parts), with the number of custom
 patches in use minimized. Tested, *stable* (static) releases are then provided
 in Canoeboot, based on specific coreboot revisions.
 

build

@@ -1,150 +1,135 @@
 #!/usr/bin/env sh
 # SPDX-License-Identifier: GPL-3.0-or-later
-# SPDX-FileCopyrightText: 2014,2015,2020,2021,2023 Leah Rowe <leah@libreboot.org>
-# SPDX-FileCopyrightText: 2015 Patrick "P. J." McDermott <pj@pehjota.net>
-# SPDX-FileCopyrightText: 2015, 2016 Klemens Nanni <contact@autoboot.org>
-# SPDX-FileCopyrightText: 2022, Caleb La Grange <thonkpeasant@protonmail.com>
+# Copyright (c) 2014-2015,2020-2024 Leah Rowe <leah@libreboot.org>
+# Copyright (c) 2015 Patrick "P. J." McDermott <pj@pehjota.net>
+# Copyright (c) 2015-2016 Klemens Nanni <contact@autoboot.org>
+# Copyright (c) 2022 Caleb La Grange <thonkpeasant@protonmail.com>
 
 set -u -e
 
-export LC_COLLATE=C
-export LC_ALL=C
-
-. "include/err.sh"
-. "include/option.sh"
-
-eval "$(setvars "" option aur_notice tmpdir)"
-
-tmpdir_was_set="y"
-set | grep TMPDIR 1>/dev/null 2>/dev/null || tmpdir_was_set="n"
-if [ "${tmpdir_was_set}" = "y" ]; then
-	[ "${TMPDIR%_*}" = "/tmp/cbmk" ] || tmpdir_was_set="n"
-fi
-if [ "${tmpdir_was_set}" = "n" ]; then
-	export TMPDIR="/tmp"
-	tmpdir="$(mktemp -d -t cbmk_XXXXXXXX)"
-	export TMPDIR="${tmpdir}"
-else
-	export TMPDIR="${TMPDIR}"
-	tmpdir="${TMPDIR}"
+if [ "./${0##*/}" != "${0}" ] || [ ! -f "build" ] || [ -L "build" ]; then
+	printf "You must run this in the proper work directory.\n" 1>&2
+	exit 1
 fi
 
-linkpath="${0}"
-linkname="${linkpath##*/}"
-buildpath="./script/${linkname}"
+. "include/lib.sh"
+
+eval `setvars "" vdir src_dirname srcdir _xm mode xp`
+err="fail"
 
 main()
 {
-	xx_ id -u 1>/dev/null 2>/dev/null
-	[ $# -lt 1 ] && fail "Too few arguments. Try: ${0} help"
+	[ $# -lt 1 ] && $err "bad command"
+	spath="script/$1"
 
-	[ "$1" = "dependencies" ] && xx_ install_packages $@ && cbmk_exit 0
-
-	for cmd in initcmd check_git check_project git_init excmd; do
-		eval "${cmd} \$@"
+	for g in "which git" "git config --global user.name" \
+	    "git config --global user.email" "git_init"; do
+		eval "$g 1>/dev/null 2>/dev/null || git_err \"$g\""
 	done
-	cbmk_exit 0
-}
-
-initcmd()
-{
-	[ "$(id -u)" != "0" ] || fail "this command as root is not permitted"
-
-	check_project
 
 	case "${1}" in
-	help) usage ${0} ;;
-	list) items "${buildpath}" ;;
-	version) mkversion ;;
+	version) printf "%s\nWebsite: %s\n" "$relname" "$projectsite" ;;
+	release) shift 1; mkrelease $@ ;;
 	*)
-		option="${1}"
-		return 0 ;;
+		[ -f "$spath" ] || $err "bad command"
+		shift 1; "$spath" $@ || $err "excmd: $spath $@" ;;
 	esac
-	cbmk_exit 0
 }
 
-install_packages()
-{
-	if [ $# -lt 2 ]; then
-		printf "You must specify a distro, namely:\n" 1>&2
-		printf "Look at files under config/dependencies/\n" 1>&2
-		printf "Example: ./build dependencies debian\n" 1>&2
-		fail "install_packages: target not specified"
-	fi
-
-	[ -f "config/dependencies/${2}" ] || fail "Unsupported target"
-
-	. "config/dependencies/${2}"
-
-	xx_ ${pkg_add} ${pkglist}
-	[ -z "${aur_notice}" ] && return 0
-	printf "You must install AUR packages: %s\n" "$aur_notice" 1>&2
-}
-
-# release archives contain .gitignore, but not .git.
-# cbmk can be run from cbmk.git, or an archive.
 git_init()
 {
-	[ -L ".git" ] && fail "Reference .git is a symlink"
+	[ -L ".git" ] && return 1
 	[ -e ".git" ] && return 0
-	eval "$(setvars "$(date -Rd @${versiondate})" cdate _nogit)"
+	eval `setvars "$(date -Rud @$versiondate)" cdate _nogit`
 
-	git init || fail "${PWD}: cannot initialise Git repository"
-	git add -A . || fail "${PWD}: cannot add files to Git repository"
-	git commit -m "${projectname} ${version}" --date "${cdate}" \
-	    --author="cbmk <cbmk@canoeboot.org>" || \
-	    fail "$PWD: can't commit ${projectname}/${version}, date $cdate"
-	git tag -a "${version}" -m "${projectname} ${version}" || \
-	    fail "${PWD}: cannot git-tag ${projectname}/${version}"
+	git init || return 1
+	git add -A . || return 1
+	git commit -m "$projectname $version" --date "$cdate" \
+	    --author="xbmk <xbmk@example.com>" || return 1
+	git tag -a "$version" -m "$projectname $version" || return 1
 }
 
-excmd()
+mkrelease()
 {
-	cbmkcmd="${buildpath}/${option}"
-	[ -f "${cbmkcmd}" ] || fail "Invalid command. Run: ${linkpath} help"
-	shift 1; "$cbmkcmd" $@ || fail "excmd: ${cbmkcmd} ${@}"
+	export XBMK_RELEASE="y"
+
+	vdir="release"
+	while getopts d:m: option; do
+		[ -z "$OPTARG" ] && $err "empty argument not allowed"
+		case "$option" in
+		d) vdir="$OPTARG" ;;
+		m) mode="$OPTARG" ;;
+		*) $err "invalid option '-$option'" ;;
+		esac
+	done
+
+	vdir="$vdir/$version"
+	src_dirname="${relname}_src"
+	srcdir="$vdir/$src_dirname"
+
+	[ -e "$vdir" ] && $err "already exists: \"$vdir\""
+	mkdir -p "$vdir" || $err "mkvdir: !mkdir -p \"$vdir\""
+	git clone . "$srcdir" || $err "mkdir: !gitclone \"$srcdir\""
+	touch "$srcdir/lock" || $err "can't make lock file in $srcdir/"
+
+	build_release
+
+	printf "\n\nDONE! Check release files under %s\n" "$vdir"
 }
 
-usage()
+build_release()
 {
-	progname=${0}
-	cat <<- EOF
-	$(mkversion)
+	_xm="build_release $vdir"
+	(
+	cd "$srcdir" || $err "$_xm: !cd \"$srcdir\""
+	fetch_trees
+	x_ mv src/docs docs
+	) || $err "can't create release files"
 
-	USAGE:	${progname} <OPTION>
+	git log --graph --pretty=format:'%Cred%h%Creset %s %Creset' \
+	    --abbrev-commit > "$srcdir/CHANGELOG" || $err "!gitlog $srcdir"
+	rm -f "$srcdir/lock" || $err "can't remove lock file in $srcdir"
 
-	possible values for 'OPTION':
-	$(items "${buildpath}")
+	(
+	cd "${srcdir%/*}" || $err "$_xm: mktarball \"$srcdir\""
+	mktarball "${srcdir##*/}" "${srcdir##*/}.tar.xz" || $err "$_xm: mksrc"
+	) || $err "can't create src tarball"
+	[ "$mode" = "src" ] && return 0
 
-	To know what ${projectname} version you're on, type:
-	${progname} version
+	touch "$srcdir/lock" || $err "can't make lock file in $srcdir/"
 
-	Refer to ${projectname} documentation for more info.
-	EOF
+	(
+	cd "$srcdir" || $err "$_xm: 2 !cd \"$srcdir\""
+	./build roms all || $err "$_xm: roms-all"
+	./build roms serprog rp2040 || $err "$_xm: rp2040"
+	./build roms serprog stm32 || $err "$_xm: stm32"
+	x_ mv bin ../roms
+	) || $err "can't build rom images"
+
+	rm -Rf "$srcdir" || $err "!rm -Rf $srcdir"
 }
 
-mkversion()
+fetch_trees()
 {
-	printf "revision: %s %s\n" "$projectname" "$version"
-	printf "revision date: %s\n" "$(date -Rud @${versiondate})"
-}
-
-cbmk_exit()
-{
-	tmp_cleanup || err "cbmk_exit: can't rm tmpdir upon exit $1: $tmpdir"
-	exit $1
+	for x in $(ls -1 config/git); do
+		./update trees -f "$x" || $err "$_xm: fetch $x"
+		singletree "$x" || x_ rm -Rf "src/$x/$x"
+	done
+	rmgit .
 }
 
 fail()
 {
-	tmp_cleanup || printf "WARNING: can't rm tmpdir: %s\n" "$tmpdir" 1>&2
-	err "${1}"
+	tmp_cleanup || printf "WARNING: can't rm tmpfiles: %s\n" "$tmpdir" 1>&2
+	err_ "${1}"
 }
 
 tmp_cleanup()
 {
-	[ "${tmpdir_was_set}" = "n" ] || return 0
-	rm -Rf "${tmpdir}" || return 1
+	[ "$tmpdir_was_set" = "n" ] || return 0
+	rm -Rf "$tmpdir" || return 1
+	rm -f lock || return 1
 }
 
 main $@
+tmp_cleanup || err_ "can't rm tmpdir upon non-zero exit: $tmpdir"

config/coreboot/d510mo/config/libgfxinit_txtmode

@@ -22,6 +22,7 @@ CONFIG_USE_OPTION_TABLE=y
 CONFIG_STATIC_OPTION_TABLE=y
 CONFIG_COMPRESS_RAMSTAGE_LZMA=y
 # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
+CONFIG_SEPARATE_ROMSTAGE=y
 CONFIG_INCLUDE_CONFIG_FILE=y
 CONFIG_COLLECT_TIMESTAMPS=y
 # CONFIG_TIMESTAMPS_ON_CONSOLE is not set
@@ -139,7 +140,6 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
 CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_DRIVERS_INTEL_WIFI is not set
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_VBT_DATA_SIZE_KB=8
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -187,6 +187,7 @@ CONFIG_BOARD_INTEL_D510MO=y
 # CONFIG_BOARD_INTEL_MINNOW3 is not set
 # CONFIG_BOARD_INTEL_MTLRVP_P is not set
 # CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
+# CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
 # CONFIG_BOARD_INTEL_SKLSDLBRK is not set
 # CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
@@ -207,7 +208,6 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_1024=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -221,6 +221,7 @@ CONFIG_COREBOOT_ROMSIZE_KB_1024=y
 # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
 CONFIG_COREBOOT_ROMSIZE_KB=1024
@@ -246,6 +247,7 @@ CONFIG_ROMSTAGE_ADDR=0x2000000
 CONFIG_VERSTAGE_ADDR=0x2000000
 CONFIG_SMM_RESERVED_SIZE=0x80000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
+CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
 CONFIG_EHCI_BAR=0xfef00000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -254,17 +256,18 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
+CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
 # CONFIG_PCIEXP_COMMON_CLOCK is not set
+CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
 CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_CBFS_CACHE_ALIGN=8
 CONFIG_INTEL_HAS_TOP_SWAP=y
 # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
 CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 
 #
 # CPU
@@ -353,6 +356,8 @@ CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
 CONFIG_AP_IN_SIPI_WAIT=y
 CONFIG_SIPI_VECTOR_IN_ROM=y
 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
+CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
+CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
 CONFIG_PC80_SYSTEM=y
 CONFIG_HAVE_CMOS_DEFAULT=y
 CONFIG_POSTCAR_STAGE=y
@@ -384,7 +389,7 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y
 CONFIG_PCI=y
 CONFIG_ECAM_MMCONF_SUPPORT=y
 CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_PLUGIN_SUPPORT=y
+CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
 CONFIG_PCIEXP_PLUGIN_SUPPORT=y
 CONFIG_ECAM_MMCONF_LENGTH=0x10000000
 CONFIG_PCI_ALLOW_BUS_MASTER=y
@@ -395,8 +400,6 @@ CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
 CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
 # CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
 CONFIG_PCIEXP_HOTPLUG_IO=0x2000
-CONFIG_FIRMWARE_CONNECTION_MANAGER=y
-# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
 # CONFIG_EARLY_PCI_BRIDGE is not set
 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
@@ -426,6 +429,7 @@ CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_ISSI=y
 # CONFIG_DRIVERS_UART_OXPCIE is not set
 CONFIG_HAVE_USBDEBUG=y
 # CONFIG_USBDEBUG is not set
@@ -440,6 +444,10 @@ CONFIG_DRIVERS_I2C_CK505=y
 CONFIG_INTEL_EDID=y
 CONFIG_INTEL_INT15=y
 CONFIG_INTEL_GMA_ACPI=y
+CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
+# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
+# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
+CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
 # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
 # CONFIG_DRIVERS_PS2_KEYBOARD is not set
 CONFIG_DRIVERS_MC146818=y
@@ -471,6 +479,7 @@ CONFIG_NO_TPM=y
 CONFIG_PCR_BOOT_MODE=1
 CONFIG_PCR_HWID=1
 CONFIG_PCR_SRTM=2
+CONFIG_PCR_FW_VER=10
 CONFIG_PCR_RUNTIME_DATA=3
 # end of Trusted Platform Module
 
@@ -498,6 +507,7 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
+CONFIG_HEAP_SIZE=0x100000
 
 #
 # Console
@@ -561,6 +571,10 @@ CONFIG_PAYLOAD_NONE=y
 #
 # CONFIG_DISPLAY_MTRRS is not set
 
+#
+# Vendorcode Debug Settings
+#
+
 #
 # BLOB Debug Settings
 #

config/coreboot/d510mo/target.cfg

@@ -1,6 +1,5 @@
 tree="default"
 xarch="i386-elf"
-payload_grub="n"
-payload_grub_withseabios="n"
 payload_seabios="y"
 payload_memtest="y"
+release="n"

config/coreboot/d510mo_16mb/config/libgfxinit_txtmode

@@ -22,6 +22,7 @@ CONFIG_USE_OPTION_TABLE=y
 CONFIG_STATIC_OPTION_TABLE=y
 CONFIG_COMPRESS_RAMSTAGE_LZMA=y
 # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
+CONFIG_SEPARATE_ROMSTAGE=y
 CONFIG_INCLUDE_CONFIG_FILE=y
 CONFIG_COLLECT_TIMESTAMPS=y
 # CONFIG_TIMESTAMPS_ON_CONSOLE is not set
@@ -139,7 +140,6 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
 CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_DRIVERS_INTEL_WIFI is not set
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_VBT_DATA_SIZE_KB=8
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -187,6 +187,7 @@ CONFIG_BOARD_INTEL_D510MO=y
 # CONFIG_BOARD_INTEL_MINNOW3 is not set
 # CONFIG_BOARD_INTEL_MTLRVP_P is not set
 # CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
+# CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
 # CONFIG_BOARD_INTEL_SKLSDLBRK is not set
 # CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
@@ -207,7 +208,6 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_1024=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -221,6 +221,7 @@ CONFIG_BOARD_ROMSIZE_KB_1024=y
 # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
 CONFIG_COREBOOT_ROMSIZE_KB_16384=y
+# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
 CONFIG_COREBOOT_ROMSIZE_KB=16384
@@ -246,6 +247,7 @@ CONFIG_ROMSTAGE_ADDR=0x2000000
 CONFIG_VERSTAGE_ADDR=0x2000000
 CONFIG_SMM_RESERVED_SIZE=0x80000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
+CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
 CONFIG_EHCI_BAR=0xfef00000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -254,17 +256,18 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
+CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
 # CONFIG_PCIEXP_COMMON_CLOCK is not set
+CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
 CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_CBFS_CACHE_ALIGN=8
 CONFIG_INTEL_HAS_TOP_SWAP=y
 # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
 CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 
 #
 # CPU
@@ -353,6 +356,8 @@ CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
 CONFIG_AP_IN_SIPI_WAIT=y
 CONFIG_SIPI_VECTOR_IN_ROM=y
 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
+CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
+CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
 CONFIG_PC80_SYSTEM=y
 CONFIG_HAVE_CMOS_DEFAULT=y
 CONFIG_POSTCAR_STAGE=y
@@ -384,7 +389,7 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y
 CONFIG_PCI=y
 CONFIG_ECAM_MMCONF_SUPPORT=y
 CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_PLUGIN_SUPPORT=y
+CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
 CONFIG_PCIEXP_PLUGIN_SUPPORT=y
 CONFIG_ECAM_MMCONF_LENGTH=0x10000000
 CONFIG_PCI_ALLOW_BUS_MASTER=y
@@ -395,8 +400,6 @@ CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
 CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
 # CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
 CONFIG_PCIEXP_HOTPLUG_IO=0x2000
-CONFIG_FIRMWARE_CONNECTION_MANAGER=y
-# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
 # CONFIG_EARLY_PCI_BRIDGE is not set
 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
@@ -426,6 +429,7 @@ CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_ISSI=y
 # CONFIG_DRIVERS_UART_OXPCIE is not set
 CONFIG_HAVE_USBDEBUG=y
 # CONFIG_USBDEBUG is not set
@@ -440,6 +444,10 @@ CONFIG_DRIVERS_I2C_CK505=y
 CONFIG_INTEL_EDID=y
 CONFIG_INTEL_INT15=y
 CONFIG_INTEL_GMA_ACPI=y
+CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
+# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
+# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
+CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
 # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
 # CONFIG_DRIVERS_PS2_KEYBOARD is not set
 CONFIG_DRIVERS_MC146818=y
@@ -471,6 +479,7 @@ CONFIG_NO_TPM=y
 CONFIG_PCR_BOOT_MODE=1
 CONFIG_PCR_HWID=1
 CONFIG_PCR_SRTM=2
+CONFIG_PCR_FW_VER=10
 CONFIG_PCR_RUNTIME_DATA=3
 # end of Trusted Platform Module
 
@@ -498,6 +507,7 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
+CONFIG_HEAP_SIZE=0x100000
 
 #
 # Console
@@ -561,6 +571,10 @@ CONFIG_PAYLOAD_NONE=y
 #
 # CONFIG_DISPLAY_MTRRS is not set
 
+#
+# Vendorcode Debug Settings
+#
+
 #
 # BLOB Debug Settings
 #

config/coreboot/d510mo_16mb/target.cfg

@@ -1,5 +1,6 @@
 tree="default"
 xarch="i386-elf"
 payload_seabios="y"
-payload_seabios_withgrub="y"
+payload_grub="y"
 payload_memtest="y"
+release="n"

config/coreboot/d945gclf_512kb/config/libgfxinit_txtmode

@@ -22,6 +22,7 @@ CONFIG_USE_OPTION_TABLE=y
 CONFIG_STATIC_OPTION_TABLE=y
 CONFIG_COMPRESS_RAMSTAGE_LZMA=y
 # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
+CONFIG_SEPARATE_ROMSTAGE=y
 CONFIG_INCLUDE_CONFIG_FILE=y
 CONFIG_COLLECT_TIMESTAMPS=y
 # CONFIG_TIMESTAMPS_ON_CONSOLE is not set
@@ -140,7 +141,6 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
 CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_DRIVERS_INTEL_WIFI is not set
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_VBT_DATA_SIZE_KB=8
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -188,6 +188,7 @@ CONFIG_BOARD_INTEL_D945GCLF=y
 # CONFIG_BOARD_INTEL_MINNOW3 is not set
 # CONFIG_BOARD_INTEL_MTLRVP_P is not set
 # CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
+# CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
 # CONFIG_BOARD_INTEL_SKLSDLBRK is not set
 # CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
@@ -206,7 +207,6 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
-CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_512=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -220,6 +220,7 @@ CONFIG_COREBOOT_ROMSIZE_KB_512=y
 # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
 CONFIG_COREBOOT_ROMSIZE_KB=512
@@ -245,6 +246,7 @@ CONFIG_ROMSTAGE_ADDR=0x2000000
 CONFIG_VERSTAGE_ADDR=0x2000000
 CONFIG_SMM_RESERVED_SIZE=0x100000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
+CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
 CONFIG_EHCI_BAR=0xfef00000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -253,17 +255,18 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
+CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
 # CONFIG_PCIEXP_COMMON_CLOCK is not set
+CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
 CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_CBFS_CACHE_ALIGN=8
 CONFIG_INTEL_HAS_TOP_SWAP=y
 # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
 CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 
 #
 # CPU
@@ -352,6 +355,8 @@ CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
 CONFIG_AP_IN_SIPI_WAIT=y
 CONFIG_SIPI_VECTOR_IN_ROM=y
 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
+CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
+CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
 CONFIG_PC80_SYSTEM=y
 CONFIG_HAVE_CMOS_DEFAULT=y
 CONFIG_POSTCAR_STAGE=y
@@ -383,7 +388,7 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y
 CONFIG_PCI=y
 CONFIG_ECAM_MMCONF_SUPPORT=y
 CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_PLUGIN_SUPPORT=y
+CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
 CONFIG_PCIEXP_PLUGIN_SUPPORT=y
 CONFIG_ECAM_MMCONF_LENGTH=0x04000000
 CONFIG_PCI_ALLOW_BUS_MASTER=y
@@ -391,8 +396,6 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
 CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
 # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
 # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-CONFIG_FIRMWARE_CONNECTION_MANAGER=y
-# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
 # CONFIG_EARLY_PCI_BRIDGE is not set
 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
@@ -421,6 +424,7 @@ CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_ISSI=y
 # CONFIG_DRIVERS_UART_OXPCIE is not set
 CONFIG_HAVE_USBDEBUG=y
 # CONFIG_USBDEBUG is not set
@@ -434,6 +438,10 @@ CONFIG_HAVE_USBDEBUG=y
 CONFIG_INTEL_EDID=y
 CONFIG_INTEL_GMA_ACPI=y
 CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y
+CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
+# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
+# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
+CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
 # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
 # CONFIG_DRIVERS_PS2_KEYBOARD is not set
 CONFIG_DRIVERS_MC146818=y
@@ -465,6 +473,7 @@ CONFIG_NO_TPM=y
 CONFIG_PCR_BOOT_MODE=1
 CONFIG_PCR_HWID=1
 CONFIG_PCR_SRTM=2
+CONFIG_PCR_FW_VER=10
 CONFIG_PCR_RUNTIME_DATA=3
 # end of Trusted Platform Module
 
@@ -492,6 +501,7 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
+CONFIG_HEAP_SIZE=0x100000
 
 #
 # Console
@@ -559,6 +569,10 @@ CONFIG_PAYLOAD_NONE=y
 #
 # CONFIG_DISPLAY_MTRRS is not set
 
+#
+# Vendorcode Debug Settings
+#
+
 #
 # BLOB Debug Settings
 #

config/coreboot/d945gclf_512kb/target.cfg

@@ -1,6 +1,4 @@
 tree="default"
 xarch="i386-elf"
-payload_grub="n"
-payload_grub_withseabios="n"
 payload_seabios="y"
-payload_memtest="n"
+release="n"

config/coreboot/d945gclf_8mb/config/libgfxinit_txtmode

@@ -22,6 +22,7 @@ CONFIG_USE_OPTION_TABLE=y
 CONFIG_STATIC_OPTION_TABLE=y
 CONFIG_COMPRESS_RAMSTAGE_LZMA=y
 # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
+CONFIG_SEPARATE_ROMSTAGE=y
 CONFIG_INCLUDE_CONFIG_FILE=y
 CONFIG_COLLECT_TIMESTAMPS=y
 # CONFIG_TIMESTAMPS_ON_CONSOLE is not set
@@ -140,7 +141,6 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
 CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_DRIVERS_INTEL_WIFI is not set
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_VBT_DATA_SIZE_KB=8
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -188,6 +188,7 @@ CONFIG_BOARD_INTEL_D945GCLF=y
 # CONFIG_BOARD_INTEL_MINNOW3 is not set
 # CONFIG_BOARD_INTEL_MTLRVP_P is not set
 # CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
+# CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
 # CONFIG_BOARD_INTEL_SKLSDLBRK is not set
 # CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
@@ -206,7 +207,6 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
-CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_512=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -220,6 +220,7 @@ CONFIG_COREBOOT_ROMSIZE_KB_8192=y
 # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
 CONFIG_COREBOOT_ROMSIZE_KB=8192
@@ -245,6 +246,7 @@ CONFIG_ROMSTAGE_ADDR=0x2000000
 CONFIG_VERSTAGE_ADDR=0x2000000
 CONFIG_SMM_RESERVED_SIZE=0x100000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
+CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
 CONFIG_EHCI_BAR=0xfef00000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -253,17 +255,18 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
+CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
 # CONFIG_PCIEXP_COMMON_CLOCK is not set
+CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
 CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_CBFS_CACHE_ALIGN=8
 CONFIG_INTEL_HAS_TOP_SWAP=y
 # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
 CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 
 #
 # CPU
@@ -352,6 +355,8 @@ CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
 CONFIG_AP_IN_SIPI_WAIT=y
 CONFIG_SIPI_VECTOR_IN_ROM=y
 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
+CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
+CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
 CONFIG_PC80_SYSTEM=y
 CONFIG_HAVE_CMOS_DEFAULT=y
 CONFIG_POSTCAR_STAGE=y
@@ -383,7 +388,7 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y
 CONFIG_PCI=y
 CONFIG_ECAM_MMCONF_SUPPORT=y
 CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_PLUGIN_SUPPORT=y
+CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
 CONFIG_PCIEXP_PLUGIN_SUPPORT=y
 CONFIG_ECAM_MMCONF_LENGTH=0x04000000
 CONFIG_PCI_ALLOW_BUS_MASTER=y
@@ -391,8 +396,6 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
 CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
 # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
 # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-CONFIG_FIRMWARE_CONNECTION_MANAGER=y
-# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
 # CONFIG_EARLY_PCI_BRIDGE is not set
 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
@@ -421,6 +424,7 @@ CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_ISSI=y
 # CONFIG_DRIVERS_UART_OXPCIE is not set
 CONFIG_HAVE_USBDEBUG=y
 # CONFIG_USBDEBUG is not set
@@ -434,6 +438,10 @@ CONFIG_HAVE_USBDEBUG=y
 CONFIG_INTEL_EDID=y
 CONFIG_INTEL_GMA_ACPI=y
 CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y
+CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
+# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
+# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
+CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
 # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
 # CONFIG_DRIVERS_PS2_KEYBOARD is not set
 CONFIG_DRIVERS_MC146818=y
@@ -465,6 +473,7 @@ CONFIG_NO_TPM=y
 CONFIG_PCR_BOOT_MODE=1
 CONFIG_PCR_HWID=1
 CONFIG_PCR_SRTM=2
+CONFIG_PCR_FW_VER=10
 CONFIG_PCR_RUNTIME_DATA=3
 # end of Trusted Platform Module
 
@@ -492,6 +501,7 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
+CONFIG_HEAP_SIZE=0x100000
 
 #
 # Console
@@ -559,6 +569,10 @@ CONFIG_PAYLOAD_NONE=y
 #
 # CONFIG_DISPLAY_MTRRS is not set
 
+#
+# Vendorcode Debug Settings
+#
+
 #
 # BLOB Debug Settings
 #

config/coreboot/d945gclf_8mb/target.cfg

@@ -1,6 +1,5 @@
 tree="default"
 xarch="i386-elf"
-payload_grub="n"
-payload_grub_withseabios="n"
 payload_seabios="y"
-payload_memtest="n"
+payload_grub="y"
+release="n"

config/coreboot/default/nuke.list

@@ -9,3 +9,5 @@ Documentation
 3rdparty/chromeec/third_party/bmi260/accelgyro_bmi260_config_tbin.h
 3rdparty/vboot/tests/futility/data/bios_peppy_dev.bin
 3rdparty/stm/Test/FrmPkg/Core/Init/Dmar.h
+3rdparty/vboot/tests/futility/data/bios_brya_mp.bin
+3rdparty/vboot/tests/futility/data/bios_brya_mp_invalid_vblock_b.bin

config/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch

@@ -1,7 +1,7 @@
-From e8f5f6c372152c7deddd3080954d0f4fdd39ae2b Mon Sep 17 00:00:00 2001
+From 055aa5908de03c21989474c58e44de596b0a8cd1 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@retroboot.org>
 Date: Fri, 19 Mar 2021 05:54:58 +0000
-Subject: [PATCH 01/22] apple/macbook21: Set default VRAM to 64MiB instead of
+Subject: [PATCH 01/16] apple/macbook21: Set default VRAM to 64MiB instead of
  8MiB
 
 ---

config/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch

@@ -1,7 +1,7 @@
-From fdd756a8217548981a1eb62e504cc37371c9fd51 Mon Sep 17 00:00:00 2001
+From dd21a7a6c1961d314db7fdabd6982d71930b0f1a Mon Sep 17 00:00:00 2001
 From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com>
 Date: Wed, 27 Oct 2021 13:36:01 +0200
-Subject: [PATCH 02/22] add c3 and clockgen to apple/macbook21
+Subject: [PATCH 02/16] add c3 and clockgen to apple/macbook21
 
 ---
  src/mainboard/apple/macbook21/Kconfig       |  1 +

config/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch

@@ -1,7 +1,7 @@
-From c8332a8bac4986afec6c639f55c5876f83e50b76 Mon Sep 17 00:00:00 2001
+From b21dd52d01aa8d4d8984b4b4ec5b4e850d7a2637 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@osboot.org>
 Date: Sun, 3 Jan 2021 03:34:01 +0000
-Subject: [PATCH 03/22] lenovo/x60: 64MiB Video RAM changed to default
+Subject: [PATCH 03/16] lenovo/x60: 64MiB Video RAM changed to default
  (previously it was 8MiB)
 
 ---

config/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch

@@ -1,7 +1,7 @@
-From 2e3ad35c24a86cb3109f4e5139b9ffba931eb80b Mon Sep 17 00:00:00 2001
+From 7b402976cb0047cf70dabf6b90e5625b4e9d2775 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@osboot.org>
 Date: Mon, 22 Feb 2021 22:16:59 +0000
-Subject: [PATCH 04/22] lenovo/t60: make 64MiB VRAM the default in cmos.default
+Subject: [PATCH 04/16] lenovo/t60: make 64MiB VRAM the default in cmos.default
 
 ---
  src/mainboard/lenovo/t60/cmos.default | 2 +-

config/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-256MiB-VRAM-by-default.patch

@@ -1,7 +1,7 @@
-From 5fc03fbf8c7fa30588dab93c76b5532ce03b1610 Mon Sep 17 00:00:00 2001
+From d0abb102ec610a3314d9e8b6f9f8bf951fe5ab3d Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Fri, 14 May 2021 13:10:33 +0100
-Subject: [PATCH 05/22] lenovo/t400: set VRAM to 256MiB VRAM by default
+Subject: [PATCH 05/16] lenovo/t400: set VRAM to 256MiB VRAM by default
 
 Signed-off-by: Leah Rowe <leah@libreboot.org>
 ---

config/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-256MiB-by-default.patch

@@ -1,7 +1,7 @@
-From 93f607fed477b3e63b7929808937436ac2898b34 Mon Sep 17 00:00:00 2001
+From 0262681a1871a70c66512182163bd7035f008f2f Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Fri, 14 May 2021 13:11:59 +0100
-Subject: [PATCH 06/22] lenovo/x200: set VRAM to 256MiB by default
+Subject: [PATCH 06/16] lenovo/x200: set VRAM to 256MiB by default
 
 Signed-off-by: Leah Rowe <leah@libreboot.org>
 ---

config/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-256MiB-by-default.patch

@@ -1,7 +1,7 @@
-From 9faa780b2ac45bc1bf61aa252364ee3158c4cb10 Mon Sep 17 00:00:00 2001
+From b8eaf580f5d8242692b78aa6b771ee3051f08278 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Fri, 14 May 2021 13:18:26 +0100
-Subject: [PATCH 07/22] gigabyte/ga-g41m-es2l: set VRAM to 256MiB by default
+Subject: [PATCH 07/16] gigabyte/ga-g41m-es2l: set VRAM to 256MiB by default
 
 Signed-off-by: Leah Rowe <leah@libreboot.org>
 ---

config/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-256MiB-by-default.patch

@@ -1,7 +1,7 @@
-From f1c59cd67446303a5cdf9107461247a63f894de3 Mon Sep 17 00:00:00 2001
+From 0c54eb497ee49b09be2aa6e7cba816f069dac31c Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Fri, 14 May 2021 13:21:39 +0100
-Subject: [PATCH 08/22] acer/g43t-am3: set VRAM to 256MiB by default
+Subject: [PATCH 08/16] acer/g43t-am3: set VRAM to 256MiB by default
 
 Signed-off-by: Leah Rowe <leah@libreboot.org>
 ---

config/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch

@@ -1,7 +1,7 @@
-From 75858ba200a2a5835bca0af9b5f508a52ed978de Mon Sep 17 00:00:00 2001
+From 8c47a1e2fe58a7f841f85bc48a2b3857f529e562 Mon Sep 17 00:00:00 2001
 From: persmule <persmule@gmail.com>
 Date: Sun, 31 Oct 2021 23:33:26 +0000
-Subject: [PATCH 09/22] lenovo/t400: Enable all SATA ports
+Subject: [PATCH 09/16] lenovo/t400: Enable all SATA ports
 
 There are 2 SATA ports on the chassis of t400(s), but at least one dock for
 t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its

config/coreboot/default/patches/0010-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch

@@ -1,7 +1,7 @@
-From 3ec06fa2393995b87af1dbc0387c5d3255d5c0db Mon Sep 17 00:00:00 2001
+From 4c1d8640d9d7070220a2282ca922554fd1732b2d Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Wed, 1 Dec 2021 02:53:00 +0000
-Subject: [PATCH 16/22] fix speedstep on x200/t400: Revert
+Subject: [PATCH 10/16] fix speedstep on x200/t400: Revert
  "cpu/intel/model_1067x: enable PECI"
 
 This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f.

config/coreboot/default/patches/0011-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch

@@ -1,7 +1,7 @@
-From fdde15b69bd5c8bf54339adf3581a32fa992a503 Mon Sep 17 00:00:00 2001
+From a51465970b87d4d8464ae66affa144217c70b185 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Mon, 17 Apr 2023 15:49:57 +0100
-Subject: [PATCH 17/22] GM45-type CPUs: don't enable alternative SMRR
+Subject: [PATCH 11/16] GM45-type CPUs: don't enable alternative SMRR
 
 This reverts the changes in coreboot revision:
 df7aecd92643d207feaf7fd840f8835097346644

config/coreboot/default/patches/0012-Remove-warning-for-coreboot-images-built-without-a-p.patch

@@ -1,7 +1,7 @@
-From 7d5452bc3358cf82eea48fde312494bcb4ca8101 Mon Sep 17 00:00:00 2001
+From 79b5f92cd7fa77f9139268aaf6aa0c2bcf5c8e9f Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Fri, 12 May 2023 19:55:15 -0600
-Subject: [PATCH 19/22] Remove warning for coreboot images built without a
+Subject: [PATCH 12/16] Remove warning for coreboot images built without a
  payload
 
 I added this in upstream to prevent people from accidentally flashing
@@ -9,19 +9,19 @@ roms without a payload resulting in a no boot situation, but in
 libreboot lbmk handles the payload and thus this warning always comes
 up. This has caused confusion and concern so just patch it out.
 ---
- payloads/Makefile.inc | 13 +------------
+ payloads/Makefile.mk | 13 +------------
  1 file changed, 1 insertion(+), 12 deletions(-)
 
-diff --git a/payloads/Makefile.inc b/payloads/Makefile.inc
-index e735443a76..4f1692a873 100644
---- a/payloads/Makefile.inc
-+++ b/payloads/Makefile.inc
+diff --git a/payloads/Makefile.mk b/payloads/Makefile.mk
+index a2336aa876..4f1692a873 100644
+--- a/payloads/Makefile.mk
++++ b/payloads/Makefile.mk
 @@ -49,16 +49,5 @@ distclean-payloads:
  print-repo-info-payloads:
  	-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
  
 -ifeq ($(CONFIG_PAYLOAD_NONE),y)
--files_added:: warn_no_payload
+-show_notices:: warn_no_payload
 -endif
 -
 -warn_no_payload:

config/coreboot/default/patches/0013-HACK-Disable-coreboot-related-BL31-features.patch

@@ -1,19 +1,19 @@
-From 9f52555eac217623ad2edc72492f9ded6a5b538d Mon Sep 17 00:00:00 2001
+From ababcb1acecf09a736aaeb659e3ca4851b27341b Mon Sep 17 00:00:00 2001
 From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
 Date: Thu, 22 Jun 2023 16:44:27 +0300
-Subject: [PATCH] HACK: Disable coreboot related BL31 features
+Subject: [PATCH 13/16] HACK: Disable coreboot related BL31 features
 
 I don't know why, but removing this BL31 make argument lets gru-kevin
 power off properly when shut down from Linux. Needs investigation.
 ---
- src/arch/arm64/Makefile.inc | 3 ---
+ src/arch/arm64/Makefile.mk | 3 ---
  1 file changed, 3 deletions(-)
 
-diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc
-index 6b49743633c3..e1982d92cc5c 100644
---- a/src/arch/arm64/Makefile.inc
-+++ b/src/arch/arm64/Makefile.inc
-@@ -158,9 +158,6 @@ BL31_MAKEARGS += LOG_LEVEL=40
+diff --git a/src/arch/arm64/Makefile.mk b/src/arch/arm64/Makefile.mk
+index 538d254ace..18e451d63c 100644
+--- a/src/arch/arm64/Makefile.mk
++++ b/src/arch/arm64/Makefile.mk
+@@ -159,9 +159,6 @@ BL31_MAKEARGS += LOG_LEVEL=40
  # Always enable crash reporting, even on a release build
  BL31_MAKEARGS += CRASH_REPORTING=1
  
@@ -24,5 +24,5 @@ index 6b49743633c3..e1982d92cc5c 100644
  BL31_MAKEARGS += BUILD_PLAT="$(BL31_BUILD)"
  
 -- 
-2.40.1
+2.39.2
 

config/coreboot/default/patches/0014-don-t-use-github-for-the-acpica-download.patch

@@ -1,7 +1,7 @@
-From cddb709fd01e3e93a7879488d0d4024360e1e3d9 Mon Sep 17 00:00:00 2001
+From 259ee5e7e502bf741c91ebfd79e83e6a5c8db5ae Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Sun, 22 Oct 2023 15:02:25 +0100
-Subject: [PATCH 1/1] don't use github for the acpica download
+Subject: [PATCH 14/16] don't use github for the acpica download
 
 i have the tarball from a previous download, and i placed
 it on libreboot rsync, which then got mirrored to princeton.
@@ -22,7 +22,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org>
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
-index ebc9fcb49a..a857110b4b 100755
+index 23a5caf2bb..36565a906c 100755
 --- a/util/crossgcc/buildgcc
 +++ b/util/crossgcc/buildgcc
 @@ -72,7 +72,7 @@ MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"

config/coreboot/default/patches/0015-use-mirrorservice.org-for-gcc-downloads.patch

@@ -1,7 +1,7 @@
-From 89c47fad6e97fc6a7113ebbdedfcc42ae2b6fc7f Mon Sep 17 00:00:00 2001
+From a962fdfe4437b266540ff6d1696993827a16508d Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Sun, 5 Nov 2023 22:57:08 +0000
-Subject: [PATCH 1/1] use mirrorservice.org for gcc downloads
+Subject: [PATCH 15/16] use mirrorservice.org for gcc downloads
 
 the gnu.org 302 redirect often fails
 
@@ -11,7 +11,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org>
  1 file changed, 5 insertions(+), 5 deletions(-)
 
 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
-index 87f80ba7f6..b3aad5df7d 100755
+index 36565a906c..4d4ca06113 100755
 --- a/util/crossgcc/buildgcc
 +++ b/util/crossgcc/buildgcc
 @@ -67,11 +67,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2"

config/coreboot/default/patches/0016-never-enable-cpu-microcode-even-if-told-to.patch

@@ -0,0 +1,120 @@
+From f0ede0cbf8cf33f77e91348dd46bee61dc0a2ccf Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Thu, 12 Oct 2023 01:20:23 +0100
+Subject: [PATCH 16/16] never enable cpu microcode, even if told to
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ src/cpu/Makefile.mk           | 55 -----------------------------------
+ src/cpu/intel/fit/Makefile.mk | 31 --------------------
+ 2 files changed, 86 deletions(-)
+
+diff --git a/src/cpu/Makefile.mk b/src/cpu/Makefile.mk
+index b1c1b1bb3e..571cd1d0e5 100644
+--- a/src/cpu/Makefile.mk
++++ b/src/cpu/Makefile.mk
+@@ -11,61 +11,6 @@ subdirs-$(CONFIG_ARCH_X86) += x86
+ subdirs-$(CONFIG_CPU_QEMU_X86) += qemu-x86
+ subdirs-$(CONFIG_CPU_POWER9) += power9
+ 
+-$(eval $(call create_class_compiler,cpu_microcode,x86_32))
+-################################################################################
+-## Rules for building the microcode blob in CBFS
+-################################################################################
+-
+-cbfs-files-$(CONFIG_USE_CPU_MICROCODE_CBFS_BINS) += cpu_microcode_blob.bin
+-
+-ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y)
+-cbfs-files-y  += cpu_microcode_blob.bin
+-cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin
+-
+-$(objgenerated)/microcode.bin: $(call strip_quotes,$(CONFIG_CPU_MICROCODE_HEADER_FILES))
+-	echo "   util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\""
+-	util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES)
+-endif
+-
+-ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS),y)
+-$(obj)/cpu_microcode_blob.bin: cpu_microcode_bins := $(call strip_quotes,$(CONFIG_CPU_UCODE_BINARIES))
+-endif
+-# otherwise `cpu_microcode_bins` should be filled by platform makefiles
+-
+-# We just mash all microcode binaries together into one binary to rule them all.
+-# This approach assumes that the microcode binaries are properly padded, and
+-# their headers specify the correct size. This works fairly well on isolatied
+-# updates, such as Intel and some AMD microcode, but won't work very well if the
+-# updates are wrapped in a container, like AMD's microcode update container. If
+-# there is only one microcode binary (i.e. one container), then we don't have
+-# this issue, and this rule will continue to work.
+-$(obj)/cpu_microcode_blob.bin: $$(wildcard $$(cpu_microcode_bins)) $(DOTCONFIG)
+-	for bin in $(cpu_microcode_bins); do \
+-		if [ ! -f "$$bin" ]; then \
+-			echo "Microcode error: $$bin does not exist"; \
+-			NO_MICROCODE_FILE=1; \
+-		fi; \
+-	done; \
+-	if [ -n "$$NO_MICROCODE_FILE" ]; then \
+-		if [ -z "$(CONFIG_USE_BLOBS)" ] && [ -n "$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS)" ]; then \
+-			echo "Try enabling binary-only repository in Kconfig 'General setup' menu."; \
+-		fi; \
+-		false; \
+-	fi
+-	$(if $(cpu_microcode_bins),,false) # fail if no file is given at all
+-	@printf "    MICROCODE  $(subst $(obj)/,,$(@))\n"
+-	@echo $(cpu_microcode_bins)
+-	cat $(cpu_microcode_bins) > $@
+-
+-cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin
+-cpu_microcode_blob.bin-type := microcode
+-# The AMD LPC SPI DMA controller requires source files to be 64 byte aligned.
+-ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y)
+-cpu_microcode_blob.bin-align := 64
+-else
+-cpu_microcode_blob.bin-align := 16
+-endif
+-
+ ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),)
+ cpu_microcode_blob.bin-COREBOOT-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC)
+ endif
+diff --git a/src/cpu/intel/fit/Makefile.mk b/src/cpu/intel/fit/Makefile.mk
+index a86a22e6d6..edca120c14 100644
+--- a/src/cpu/intel/fit/Makefile.mk
++++ b/src/cpu/intel/fit/Makefile.mk
+@@ -19,35 +19,4 @@ $(call add_intermediate, set_fit_ptr, $(IFITTOOL))
+ 
+ FIT_ENTRY=$(call strip_quotes, $(CONFIG_INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG))
+ 
+-ifneq ($(CONFIG_UPDATE_IMAGE),y) # never update the bootblock
+-
+-ifneq ($(CONFIG_CPU_MICROCODE_CBFS_NONE)$(CONFIG_CPU_INTEL_MICROCODE_CBFS_SPLIT_BINS),y)
+-
+-$(call add_intermediate, add_mcu_fit, set_fit_ptr $(IFITTOOL))
+-	@printf "    UPDATE-FIT Microcode\n"
+-	$(IFITTOOL) -f $< -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -r COREBOOT
+-
+-# Second FIT in TOP_SWAP bootblock
+-ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y)
+-
+-$(call add_intermediate, set_ts_fit_ptr, $(IFITTOOL))
+-	@printf "    UPDATE-FIT Top Swap: set FIT pointer to table\n"
+-	$(IFITTOOL) -f $< -F -n intel_fit_ts -r COREBOOT $(TS_OPTIONS)
+-
+-$(call add_intermediate, add_ts_mcu_fit, set_ts_fit_ptr $(IFITTOOL))
+-	@printf "    UPDATE-FIT Top Swap: Microcode\n"
+-ifneq ($(FIT_ENTRY),)
+-	$(IFITTOOL) -f $< -A -n $(FIT_ENTRY) -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) $(TS_OPTIONS) -r COREBOOT
+-endif # FIT_ENTRY
+-	$(IFITTOOL) -f $< -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) $(TS_OPTIONS) -r COREBOOT
+-
+-cbfs-files-y += intel_fit_ts
+-intel_fit_ts-file := fit_table.c:struct
+-intel_fit_ts-type := intel_fit
+-intel_fit_ts-align := 16
+-
+-endif # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK
+-
+-endif # CONFIG_CPU_MICROCODE_CBFS_NONE
+-
+ endif # CONFIG_UPDATE_IMAGE
+-- 
+2.39.2
+

config/coreboot/default/patches/0017-Never-download-blobs-even-if-USE_BLOBS-y.patch

@@ -0,0 +1,47 @@
+From c7d9dcec39fbda870b7cddbeb87771bac0fb68b8 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <info@minifree.org>
+Date: Fri, 3 May 2024 06:24:49 +0100
+Subject: [PATCH 1/1] Never download blobs, even if USE_BLOBS=y
+
+same idea as my never-microcode patches. i maintain
+canoeboot and i like to re-use the same configs from
+lbmk. with this and the never-microcode patch, it should
+now be possible to re-use lbmk coreboot configs unmodified!
+
+when those configs are used in cbmk, the relevant blobs
+are never downloaded, ever.
+
+Signed-off-by: Leah Rowe <info@minifree.org>
+---
+ Makefile.mk | 15 ---------------
+ 1 file changed, 15 deletions(-)
+
+diff --git a/Makefile.mk b/Makefile.mk
+index 87c6bcb247..3747eaa556 100644
+--- a/Makefile.mk
++++ b/Makefile.mk
+@@ -222,21 +222,6 @@ $(info Updating git submodules.)
+ forgetthis:=$(shell git submodule update --init $(quiet_errors))
+ # Checkout Cmocka repository
+ forgetthis:=$(shell git submodule update --init --checkout 3rdparty/cmocka $(quiet_errors))
+-ifeq ($(CONFIG_USE_BLOBS),y)
+-# These items are necessary because each has update=none in .gitmodules.  They are ignored
+-# until expressly requested and enabled with --checkout
+-forgetthis:=$(shell git submodule update --init --checkout 3rdparty/blobs $(quiet_errors))
+-forgetthis:=$(shell git submodule update --init --checkout 3rdparty/intel-microcode $(quiet_errors))
+-ifeq ($(CONFIG_FSP_USE_REPO),y)
+-forgetthis:=$(shell git submodule update --init --checkout 3rdparty/fsp $(quiet_errors))
+-endif
+-ifeq ($(CONFIG_USE_AMD_BLOBS),y)
+-forgetthis:=$(shell git submodule update --init --checkout 3rdparty/amd_blobs $(quiet_errors))
+-endif
+-ifeq ($(CONFIG_USE_QC_BLOBS),y)
+-forgetthis:=$(shell git submodule update --init --checkout 3rdparty/qc_blobs $(quiet_errors))
+-endif
+-endif
+ UPDATED_SUBMODULES:=1
+ COREBOOT_EXPORTS += UPDATED_SUBMODULES
+ 
+-- 
+2.39.2
+

config/coreboot/default/patches/0020-ec-dell-mec5035-Add-command-to-enable-disable-radios.patch

@@ -1,61 +0,0 @@
-From f0db13a15c76c2947eec8919fd121450048914ce Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Sun, 27 Aug 2023 17:36:36 -0600
-Subject: [PATCH 20/22] ec/dell/mec5035: Add command to enable/disable radios
-
-These were determined by sniffing the LPC bus while toggling the
-hardware wireless switch on the Latitude E6400. To differentiate devices
-options in the vendor BIOS to change which radios the switch controlled
-were used.
-
-Change-Id: I173dc197d63cda232dd7ede0cb798ab0a364482b
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
----
- src/ec/dell/mec5035/mec5035.c | 9 +++++++++
- src/ec/dell/mec5035/mec5035.h | 8 ++++++++
- 2 files changed, 17 insertions(+)
-
-diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
-index 8da11e5b1c..e0335a4635 100644
---- a/src/ec/dell/mec5035/mec5035.c
-+++ b/src/ec/dell/mec5035/mec5035.c
-@@ -84,6 +84,15 @@ u8 mec5035_mouse_touchpad(u8 setting)
- 	return buf[0];
- }
- 
-+void mec5035_radio_enable(enum mec5035_radio_dev dev, u8 on)
-+{
-+	/* From LPC traces and userspace testing with other values,
-+	   the second byte has to be 2 for an unknown reason. */
-+	u8 buf[3] = {dev, 2, on};
-+	write_mailbox_regs(buf, 2, 3);
-+	ec_command(CMD_RADIO_EN);
-+}
-+
- void mec5035_early_init(void)
- {
- 	/* If this isn't sent the EC shuts down the system after about 15
-diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h
-index e7a05b64d4..16512e2cc2 100644
---- a/src/ec/dell/mec5035/mec5035.h
-+++ b/src/ec/dell/mec5035/mec5035.h
-@@ -16,8 +16,16 @@
- 
- #define CMD_CPU_OK	0xc2
- 
-+#define CMD_RADIO_EN	0x2b
-+enum mec5035_radio_dev {
-+	RADIO_WLAN = 0,
-+	RADIO_WWAN = 1,
-+	RADIO_WPAN = 2,
-+};
-+
- u8 mec5035_mouse_touchpad(u8 setting);
- void mec5035_cpu_ok(void);
- void mec5035_early_init(void);
-+void mec5035_radio_enable(enum mec5035_radio_dev device, u8 on);
- 
- #endif /* _EC_DELL_MEC5035_H_ */
--- 
-2.39.2
-

config/coreboot/default/patches/0021-ec-dell-mec5035-Hook-up-radio-enables-to-option-API.patch

@@ -1,37 +0,0 @@
-From 4537c365dae010645404fdb5d2d4e5f478dede67 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Sun, 27 Aug 2023 19:15:37 -0600
-Subject: [PATCH 21/22] ec/dell/mec5035: Hook up radio enables to option API
-
-Change-Id: I52de5ea3d24b400a93adee7a6207a4439eac61db
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
----
- src/ec/dell/mec5035/mec5035.c | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
-index e0335a4635..20a33cc0ad 100644
---- a/src/ec/dell/mec5035/mec5035.c
-+++ b/src/ec/dell/mec5035/mec5035.c
-@@ -4,6 +4,7 @@
- #include <console/console.h>
- #include <device/device.h>
- #include <device/pnp.h>
-+#include <option.h>
- #include <pc80/keyboard.h>
- #include <stdint.h>
- #include "mec5035.h"
-@@ -108,6 +109,10 @@ static void mec5035_init(struct device *dev)
- 	mec5035_mouse_touchpad(TP_PS2_MOUSE);
- 
- 	pc_keyboard_init(NO_AUX_DEVICE);
-+
-+	mec5035_radio_enable(RADIO_WLAN, get_uint_option("wlan", 1));
-+	mec5035_radio_enable(RADIO_WWAN, get_uint_option("wwan", 1));
-+	mec5035_radio_enable(RADIO_WPAN, get_uint_option("bluetooth", 1));
- }
- 
- static struct device_operations ops = {
--- 
-2.39.2
-

config/coreboot/default/patches/0025-Revert-Kconfig-Bring-HEAP_SIZE-to-a-common-large-val.patch

@@ -1,341 +0,0 @@
-From f1b5b0051718139cf59ad047d42d1360b8452ec5 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Sun, 29 Oct 2023 01:18:50 +0000
-Subject: [PATCH 1/1] Revert "Kconfig: Bring HEAP_SIZE to a common, large
- value"
-
-This reverts commit 44a48ce7a46c36df69f7b2cf3552bf10fa5f61b6.
-
-NOTE:
-
-this is done instead of merging:
-https://review.coreboot.org/c/coreboot/+/78623
-
-which is still under review for now
-
-the patch i'm reverting is this one:
-https://review.coreboot.org/c/coreboot/+/78270
-
-this was actually only merged the day before i
-updated coreboot revs in lbmk to the 12 october rev,
-so there's no harm in quickly reverting this for now
-
-however, later on, we will rely on the other patch
----
- src/Kconfig                                   | 3 ++-
- src/cpu/qemu-x86/Kconfig                      | 3 +++
- src/mainboard/sifive/hifive-unleashed/Kconfig | 3 +++
- src/northbridge/amd/pi/Kconfig                | 4 ++++
- src/soc/amd/picasso/Kconfig                   | 4 ++++
- src/soc/amd/stoneyridge/Kconfig               | 4 ++++
- src/soc/cavium/cn81xx/Kconfig                 | 3 +++
- src/soc/intel/alderlake/Kconfig               | 5 +++++
- src/soc/intel/apollolake/Kconfig              | 4 ++++
- src/soc/intel/cannonlake/Kconfig              | 4 ++++
- src/soc/intel/elkhartlake/Kconfig             | 4 ++++
- src/soc/intel/jasperlake/Kconfig              | 4 ++++
- src/soc/intel/meteorlake/Kconfig              | 5 +++++
- src/soc/intel/skylake/Kconfig                 | 4 ++++
- src/soc/intel/tigerlake/Kconfig               | 4 ++++
- src/soc/intel/xeon_sp/Kconfig                 | 4 ++++
- src/soc/intel/xeon_sp/cpx/Kconfig             | 4 ++++
- src/soc/intel/xeon_sp/skx/Kconfig             | 4 ++++
- src/soc/intel/xeon_sp/spr/Kconfig             | 4 ++++
- src/soc/qualcomm/ipq40xx/Kconfig              | 4 ++++
- 20 files changed, 77 insertions(+), 1 deletion(-)
-
-diff --git a/src/Kconfig b/src/Kconfig
-index ae8024089e..1549719dd0 100644
---- a/src/Kconfig
-+++ b/src/Kconfig
-@@ -751,7 +751,8 @@ config RTC
- 
- config HEAP_SIZE
- 	hex
--	default 0x100000
-+	default 0x100000 if FLATTENED_DEVICE_TREE
-+	default 0x4000
- 
- config STACK_SIZE
- 	hex
-diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig
-index 0fa999e1ac..f3e2c4cea9 100644
---- a/src/cpu/qemu-x86/Kconfig
-+++ b/src/cpu/qemu-x86/Kconfig
-@@ -35,4 +35,7 @@ config MAX_CPUS
- 	default 32 if SMM_TSEG
- 	default 4
- 
-+config HEAP_SIZE
-+	default 0x8000
-+
- endif
-diff --git a/src/mainboard/sifive/hifive-unleashed/Kconfig b/src/mainboard/sifive/hifive-unleashed/Kconfig
-index 7bc3b0bcbb..7f9300f2a7 100644
---- a/src/mainboard/sifive/hifive-unleashed/Kconfig
-+++ b/src/mainboard/sifive/hifive-unleashed/Kconfig
-@@ -10,6 +10,9 @@ config BOARD_SPECIFIC_OPTIONS
- 	select FLATTENED_DEVICE_TREE
- 	select SPI_SDCARD
- 
-+config HEAP_SIZE
-+	default 0x10000
-+
- config MAINBOARD_DIR
- 	default "sifive/hifive-unleashed"
- 
-diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig
-index 4ffe82a15f..4518db149b 100644
---- a/src/northbridge/amd/pi/Kconfig
-+++ b/src/northbridge/amd/pi/Kconfig
-@@ -29,4 +29,8 @@ config HW_MEM_HOLE_SIZEK
- 	hex
- 	default 0x200000
- 
-+config HEAP_SIZE
-+	hex
-+	default 0xc0000
-+
- endif # NORTHBRIDGE_AMD_PI
-diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
-index c33f287067..796fe4eb13 100644
---- a/src/soc/amd/picasso/Kconfig
-+++ b/src/soc/amd/picasso/Kconfig
-@@ -264,6 +264,10 @@ config S3_VGA_ROM_RUN
- 	bool
- 	default n
- 
-+config HEAP_SIZE
-+	hex
-+	default 0xc0000
-+
- config SERIRQ_CONTINUOUS_MODE
- 	bool
- 	default n
-diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
-index 6ff135e6a8..9af7455bae 100644
---- a/src/soc/amd/stoneyridge/Kconfig
-+++ b/src/soc/amd/stoneyridge/Kconfig
-@@ -152,6 +152,10 @@ config S3_VGA_ROM_RUN
- 	bool
- 	default n
- 
-+config HEAP_SIZE
-+	hex
-+	default 0xc0000
-+
- config EHCI_BAR
- 	hex
- 	default 0xfef00000
-diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig
-index 77ca97202b..368581f8f1 100644
---- a/src/soc/cavium/cn81xx/Kconfig
-+++ b/src/soc/cavium/cn81xx/Kconfig
-@@ -30,6 +30,9 @@ config ARCH_ARMV8_EXTENSION
- 	int
- 	default 1
- 
-+config HEAP_SIZE
-+	default 0x10000
-+
- config STACK_SIZE
- 	default 0x2000
- 
-diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
-index 4b960c1d22..82ec8f263e 100644
---- a/src/soc/intel/alderlake/Kconfig
-+++ b/src/soc/intel/alderlake/Kconfig
-@@ -215,6 +215,11 @@ config IED_REGION_SIZE
- 	hex
- 	default 0x400000
- 
-+config HEAP_SIZE
-+	hex
-+	default 0x80000 if BMP_LOGO
-+	default 0x10000
-+
- config GFX_GMA_DEFAULT_MMIO
- 	default 0xaf000000 if MAINBOARD_HAS_EARLY_LIBGFXINIT
- 
-diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
-index 78ec2987ce..bce935d800 100644
---- a/src/soc/intel/apollolake/Kconfig
-+++ b/src/soc/intel/apollolake/Kconfig
-@@ -252,6 +252,10 @@ config IFWI_FILE_NAME
- 	help
- 	  Name of file to store in the IFWI region.
- 
-+config HEAP_SIZE
-+	hex
-+	default 0x8000
-+
- config MAX_ROOT_PORTS
- 	int
- 	default 6
-diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
-index a42a3c365b..80237f9810 100644
---- a/src/soc/intel/cannonlake/Kconfig
-+++ b/src/soc/intel/cannonlake/Kconfig
-@@ -160,6 +160,10 @@ config IED_REGION_SIZE
- 	hex
- 	default 0x400000
- 
-+config HEAP_SIZE
-+	hex
-+	default 0x8000
-+
- config NHLT_DMIC_1CH_16B
- 	bool
- 	depends on ACPI_NHLT
-diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig
-index 3361c0ddb9..7f1c767379 100644
---- a/src/soc/intel/elkhartlake/Kconfig
-+++ b/src/soc/intel/elkhartlake/Kconfig
-@@ -104,6 +104,10 @@ config IED_REGION_SIZE
- 	hex
- 	default 0x0
- 
-+config HEAP_SIZE
-+	hex
-+	default 0x8000
-+
- config MAX_ROOT_PORTS
- 	int
- 	default 7
-diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
-index 3d84991e09..ff5def3263 100644
---- a/src/soc/intel/jasperlake/Kconfig
-+++ b/src/soc/intel/jasperlake/Kconfig
-@@ -106,6 +106,10 @@ config IED_REGION_SIZE
- 	hex
- 	default 0x400000
- 
-+config HEAP_SIZE
-+	hex
-+	default 0x8000
-+
- config MAX_ROOT_PORTS
- 	int
- 	default 8
-diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
-index 590e8b80e1..48030a1911 100644
---- a/src/soc/intel/meteorlake/Kconfig
-+++ b/src/soc/intel/meteorlake/Kconfig
-@@ -197,6 +197,11 @@ config IED_REGION_SIZE
- 	hex
- 	default 0x400000
- 
-+config HEAP_SIZE
-+	hex
-+	default 0x80000 if BMP_LOGO
-+	default 0x10000
-+
- # Intel recommends reserving the PCIe TBT root port resources as below:
- # - 42 buses
- # - 194 MiB Non-prefetchable memory
-diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
-index e0df501460..d6a11363ee 100644
---- a/src/soc/intel/skylake/Kconfig
-+++ b/src/soc/intel/skylake/Kconfig
-@@ -151,6 +151,10 @@ config EXCLUDE_NATIVE_SD_INTERFACE
- 	help
- 	  If you set this option to n, will not use native SD controller.
- 
-+config HEAP_SIZE
-+	hex
-+	default 0x80000
-+
- config IED_REGION_SIZE
- 	hex
- 	default 0x400000
-diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
-index c07a0d8365..0a4b7bfdb8 100644
---- a/src/soc/intel/tigerlake/Kconfig
-+++ b/src/soc/intel/tigerlake/Kconfig
-@@ -152,6 +152,10 @@ config IED_REGION_SIZE
- config INTEL_TME
- 	default n
- 
-+config HEAP_SIZE
-+	hex
-+	default 0x10000
-+
- config MAX_ROOT_PORTS
- 	int
- 	default 24 if SOC_INTEL_TIGERLAKE_PCH_H
-diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
-index e63bee5451..63ced01067 100644
---- a/src/soc/intel/xeon_sp/Kconfig
-+++ b/src/soc/intel/xeon_sp/Kconfig
-@@ -91,6 +91,10 @@ config ECAM_MMCONF_BASE_ADDRESS
- config ECAM_MMCONF_BUS_NUMBER
- 	default 256
- 
-+config HEAP_SIZE
-+	hex
-+	default 0x80000
-+
- config HPET_MIN_TICKS
- 	hex
- 	default 0x80
-diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig
-index ac166c3038..f54f7716b6 100644
---- a/src/soc/intel/xeon_sp/cpx/Kconfig
-+++ b/src/soc/intel/xeon_sp/cpx/Kconfig
-@@ -71,6 +71,10 @@ config CPU_MICROCODE_CBFS_LEN
- 	hex
- 	default 0x7C00
- 
-+config HEAP_SIZE
-+	hex
-+	default 0x80000
-+
- config STACK_SIZE
- 	hex
- 	default 0x4000
-diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig
-index 5d843878e1..c2c3d4e2e8 100644
---- a/src/soc/intel/xeon_sp/skx/Kconfig
-+++ b/src/soc/intel/xeon_sp/skx/Kconfig
-@@ -55,6 +55,10 @@ config CPU_MICROCODE_CBFS_LEN
- 	hex
- 	default 0x7C00
- 
-+config HEAP_SIZE
-+	hex
-+	default 0x80000
-+
- config IED_REGION_SIZE
- 	hex
- 	default 0x400000
-diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
-index 43b87ade14..b1c4c783b7 100644
---- a/src/soc/intel/xeon_sp/spr/Kconfig
-+++ b/src/soc/intel/xeon_sp/spr/Kconfig
-@@ -79,6 +79,10 @@ config CPU_MICROCODE_CBFS_LEN
- 	hex
- 	default 0x8c00
- 
-+config HEAP_SIZE
-+	hex
-+	default 0x80000
-+
- config STACK_SIZE
- 	hex
- 	default 0x4000
-diff --git a/src/soc/qualcomm/ipq40xx/Kconfig b/src/soc/qualcomm/ipq40xx/Kconfig
-index 0ce92731c0..0eabb00752 100644
---- a/src/soc/qualcomm/ipq40xx/Kconfig
-+++ b/src/soc/qualcomm/ipq40xx/Kconfig
-@@ -57,4 +57,8 @@ config SBL_UTIL_PATH
- 	help
- 	  Path for utils to combine SBL_ELF and bootblock
- 
-+config HEAP_SIZE
-+	hex
-+	default 0x8000
-+
- endif
--- 
-2.39.2
-

config/coreboot/default/patches/0045-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch

@@ -0,0 +1,117 @@
+From a8c4f7004ea1c9b8268a87dd0b700c250ec4747d Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Fri, 3 May 2024 11:03:32 -0600
+Subject: [PATCH] ec/dell/mec5035: Add S3 suspend SMI handler
+
+Change-Id: I655868aba46911d128f6c24f410dc6fdf83f3070
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/ec/dell/mec5035/Makefile.mk  |  1 +
+ src/ec/dell/mec5035/mec5035.c    | 14 ++++++++++++++
+ src/ec/dell/mec5035/mec5035.h    | 19 +++++++++++++++++++
+ src/ec/dell/mec5035/smihandler.c | 17 +++++++++++++++++
+ 4 files changed, 51 insertions(+)
+ create mode 100644 src/ec/dell/mec5035/smihandler.c
+
+diff --git a/src/ec/dell/mec5035/Makefile.mk b/src/ec/dell/mec5035/Makefile.mk
+index 4ebdd811f9..be557e4599 100644
+--- a/src/ec/dell/mec5035/Makefile.mk
++++ b/src/ec/dell/mec5035/Makefile.mk
+@@ -5,5 +5,6 @@ ifeq ($(CONFIG_EC_DELL_MEC5035),y)
+ bootblock-y += mec5035.c
+ romstage-y += mec5035.c
+ ramstage-y += mec5035.c
++smm-y += mec5035.c smihandler.c
+ 
+ endif
+diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
+index 68b6b2f7fb..33bf046634 100644
+--- a/src/ec/dell/mec5035/mec5035.c
++++ b/src/ec/dell/mec5035/mec5035.c
+@@ -94,6 +94,20 @@ void mec5035_control_radio(enum ec_radio_dev dev, enum ec_radio_state state)
+ 	ec_command(CMD_RADIO_CTRL);
+ }
+ 
++void mec5035_sleep_enable(void)
++{
++	u8 buf[SLEEP_EN_NUM_ARGS] = {3, 0};
++	write_mailbox_regs(buf, 2, SLEEP_EN_NUM_ARGS);
++	ec_command(CMD_SLEEP_ENABLE);
++}
++
++void mec5035_change_wake(u8 source, enum ec_wake_change change)
++{
++	u8 buf[ACPI_WAKEUP_NUM_ARGS] = {change, source, 0, 0x40};
++	write_mailbox_regs(buf, 2, ACPI_WAKEUP_NUM_ARGS);
++	ec_command(CMD_ACPI_WAKEUP_CHANGE);
++}
++
+ void mec5035_early_init(void)
+ {
+ 	/* If this isn't sent the EC shuts down the system after about 15
+diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h
+index fa15a9d621..069616fbc5 100644
+--- a/src/ec/dell/mec5035/mec5035.h
++++ b/src/ec/dell/mec5035/mec5035.h
+@@ -4,6 +4,7 @@
+ #define _EC_DELL_MEC5035_H_
+ 
+ #include <stdint.h>
++#include <types.h>
+ 
+ #define NUM_REGISTERS	32
+ 
+@@ -29,9 +30,27 @@ enum ec_radio_state {
+ 	RADIO_ON
+ };
+ 
++#define CMD_ACPI_WAKEUP_CHANGE 0x4a
++#define ACPI_WAKEUP_NUM_ARGS 4
++enum ec_wake_change {
++	WAKE_OFF = 0,
++	WAKE_ON
++};
++enum ec_acpi_wake_events {
++	EC_ACPI_WAKE_PWRB = BIT(0),     /* Wake up by power button */
++	EC_ACPI_WAKE_LID = BIT(1),      /* Wake up by lid switch */
++	EC_ACPI_WAKE_RTC = BIT(5),      /* Wake up by RTC */
++};
++
++#define CMD_SLEEP_ENABLE 0x64
++#define SLEEP_EN_NUM_ARGS 2
++
+ u8 mec5035_mouse_touchpad(u8 setting);
+ void mec5035_cpu_ok(void);
+ void mec5035_early_init(void);
+ void mec5035_control_radio(enum ec_radio_dev device, enum ec_radio_state state);
++void mec5035_sleep(int slp_type);
++void mec5035_change_wake(u8 source, enum ec_wake_change change);
++void mec5035_sleep_enable(void);
+ 
+ #endif /* _EC_DELL_MEC5035_H_ */
+diff --git a/src/ec/dell/mec5035/smihandler.c b/src/ec/dell/mec5035/smihandler.c
+new file mode 100644
+index 0000000000..1db834773d
+--- /dev/null
++++ b/src/ec/dell/mec5035/smihandler.c
+@@ -0,0 +1,17 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <acpi/acpi.h>
++#include <console/console.h>
++#include <ec/acpi/ec.h>
++#include "mec5035.h"
++
++void mec5035_sleep(int slp_type)
++{
++	switch (slp_type) {
++	case ACPI_S3:
++		/* System does not yet resume properly if woken by lid */
++		mec5035_change_wake(EC_ACPI_WAKE_LID, WAKE_OFF);
++		mec5035_sleep_enable();
++		break;
++	}
++}
+-- 
+2.44.0
+

config/coreboot/default/patches/0046-mb-dell-Add-S3-SMI-handler-for-SNB-IVB-Latitudes.patch

@@ -0,0 +1,133 @@
+From 9ff35368733c5e5a852ebd6295f262710553913b Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Fri, 3 May 2024 16:31:12 -0600
+Subject: [PATCH] mb/dell/: Add S3 SMI handler for SNB/IVB Latitudes
+
+This should fix S3 suspend on these systems
+
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/mainboard/dell/e5420/smihandler.c | 9 +++++++++
+ src/mainboard/dell/e5520/smihandler.c | 9 +++++++++
+ src/mainboard/dell/e5530/smihandler.c | 9 +++++++++
+ src/mainboard/dell/e6420/smihandler.c | 9 +++++++++
+ src/mainboard/dell/e6430/smihandler.c | 9 +++++++++
+ src/mainboard/dell/e6520/smihandler.c | 9 +++++++++
+ src/mainboard/dell/e6530/smihandler.c | 9 +++++++++
+ 7 files changed, 63 insertions(+)
+ create mode 100644 src/mainboard/dell/e5420/smihandler.c
+ create mode 100644 src/mainboard/dell/e5520/smihandler.c
+ create mode 100644 src/mainboard/dell/e5530/smihandler.c
+ create mode 100644 src/mainboard/dell/e6420/smihandler.c
+ create mode 100644 src/mainboard/dell/e6430/smihandler.c
+ create mode 100644 src/mainboard/dell/e6520/smihandler.c
+ create mode 100644 src/mainboard/dell/e6530/smihandler.c
+
+diff --git a/src/mainboard/dell/e5420/smihandler.c b/src/mainboard/dell/e5420/smihandler.c
+new file mode 100644
+index 0000000000..334d7b1a5f
+--- /dev/null
++++ b/src/mainboard/dell/e5420/smihandler.c
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <cpu/x86/smm.h>
++#include <ec/dell/mec5035/mec5035.h>
++
++void mainboard_smi_sleep(u8 slp_typ)
++{
++	mec5035_sleep(slp_typ);
++}
+diff --git a/src/mainboard/dell/e5520/smihandler.c b/src/mainboard/dell/e5520/smihandler.c
+new file mode 100644
+index 0000000000..334d7b1a5f
+--- /dev/null
++++ b/src/mainboard/dell/e5520/smihandler.c
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <cpu/x86/smm.h>
++#include <ec/dell/mec5035/mec5035.h>
++
++void mainboard_smi_sleep(u8 slp_typ)
++{
++	mec5035_sleep(slp_typ);
++}
+diff --git a/src/mainboard/dell/e5530/smihandler.c b/src/mainboard/dell/e5530/smihandler.c
+new file mode 100644
+index 0000000000..334d7b1a5f
+--- /dev/null
++++ b/src/mainboard/dell/e5530/smihandler.c
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <cpu/x86/smm.h>
++#include <ec/dell/mec5035/mec5035.h>
++
++void mainboard_smi_sleep(u8 slp_typ)
++{
++	mec5035_sleep(slp_typ);
++}
+diff --git a/src/mainboard/dell/e6420/smihandler.c b/src/mainboard/dell/e6420/smihandler.c
+new file mode 100644
+index 0000000000..334d7b1a5f
+--- /dev/null
++++ b/src/mainboard/dell/e6420/smihandler.c
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <cpu/x86/smm.h>
++#include <ec/dell/mec5035/mec5035.h>
++
++void mainboard_smi_sleep(u8 slp_typ)
++{
++	mec5035_sleep(slp_typ);
++}
+diff --git a/src/mainboard/dell/e6430/smihandler.c b/src/mainboard/dell/e6430/smihandler.c
+new file mode 100644
+index 0000000000..334d7b1a5f
+--- /dev/null
++++ b/src/mainboard/dell/e6430/smihandler.c
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <cpu/x86/smm.h>
++#include <ec/dell/mec5035/mec5035.h>
++
++void mainboard_smi_sleep(u8 slp_typ)
++{
++	mec5035_sleep(slp_typ);
++}
+diff --git a/src/mainboard/dell/e6520/smihandler.c b/src/mainboard/dell/e6520/smihandler.c
+new file mode 100644
+index 0000000000..334d7b1a5f
+--- /dev/null
++++ b/src/mainboard/dell/e6520/smihandler.c
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <cpu/x86/smm.h>
++#include <ec/dell/mec5035/mec5035.h>
++
++void mainboard_smi_sleep(u8 slp_typ)
++{
++	mec5035_sleep(slp_typ);
++}
+diff --git a/src/mainboard/dell/e6530/smihandler.c b/src/mainboard/dell/e6530/smihandler.c
+new file mode 100644
+index 0000000000..334d7b1a5f
+--- /dev/null
++++ b/src/mainboard/dell/e6530/smihandler.c
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <cpu/x86/smm.h>
++#include <ec/dell/mec5035/mec5035.h>
++
++void mainboard_smi_sleep(u8 slp_typ)
++{
++	mec5035_sleep(slp_typ);
++}
+-- 
+2.44.0
+

config/coreboot/default/target.cfg

@@ -1,3 +1,2 @@
 tree="default"
-rev="d862695f5f432b5c78dada5f16c293a4c3f9fce6"
-xarch="i386-elf"
+rev="b6cbfa977f63d57d5d6b9e9f7c1cef30162f575a"

config/coreboot/dell/patches/0001-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch

@@ -1,7 +1,7 @@
-From 3ec06fa2393995b87af1dbc0387c5d3255d5c0db Mon Sep 17 00:00:00 2001
+From 9615da65cc281155f71c9e59aafba03a5d2752a6 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Wed, 1 Dec 2021 02:53:00 +0000
-Subject: [PATCH 16/22] fix speedstep on x200/t400: Revert
+Subject: [PATCH 1/9] fix speedstep on x200/t400: Revert
  "cpu/intel/model_1067x: enable PECI"
 
 This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f.

config/coreboot/dell/patches/0002-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch

@@ -1,7 +1,7 @@
-From fdde15b69bd5c8bf54339adf3581a32fa992a503 Mon Sep 17 00:00:00 2001
+From 7daaafae1b9cd78f324488132753e25bfdbfc9f7 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Mon, 17 Apr 2023 15:49:57 +0100
-Subject: [PATCH 17/22] GM45-type CPUs: don't enable alternative SMRR
+Subject: [PATCH 2/9] GM45-type CPUs: don't enable alternative SMRR
 
 This reverts the changes in coreboot revision:
 df7aecd92643d207feaf7fd840f8835097346644

config/coreboot/dell/patches/0003-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch

@@ -1,8 +1,8 @@
-From a65797a9e7e610b1c916cb4d275b72848622c218 Mon Sep 17 00:00:00 2001
+From e2070df8fe94e3ad4b5d6a544fb7f7fc1b61c5f9 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Sat, 6 May 2023 15:53:41 -0600
-Subject: [PATCH 18/22] mb/dell/e6400: Enable 01.0 device in devicetree for
- dGPU models
+Subject: [PATCH 3/9] mb/dell/e6400: Enable 01.0 device in devicetree for dGPU
+ models
 
 Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed
 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>

config/coreboot/dell/patches/0004-Remove-warning-for-coreboot-images-built-without-a-p.patch

@@ -0,0 +1,39 @@
+From 52dd181998f9f55b66d38ba05025a4833a1247ba Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Fri, 12 May 2023 19:55:15 -0600
+Subject: [PATCH 4/9] Remove warning for coreboot images built without a
+ payload
+
+I added this in upstream to prevent people from accidentally flashing
+roms without a payload resulting in a no boot situation, but in
+libreboot lbmk handles the payload and thus this warning always comes
+up. This has caused confusion and concern so just patch it out.
+---
+ payloads/Makefile.mk | 13 +------------
+ 1 file changed, 1 insertion(+), 12 deletions(-)
+
+diff --git a/payloads/Makefile.mk b/payloads/Makefile.mk
+index a2336aa876..4f1692a873 100644
+--- a/payloads/Makefile.mk
++++ b/payloads/Makefile.mk
+@@ -49,16 +49,5 @@ distclean-payloads:
+ print-repo-info-payloads:
+ 	-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
+ 
+-ifeq ($(CONFIG_PAYLOAD_NONE),y)
+-show_notices:: warn_no_payload
+-endif
+-
+-warn_no_payload:
+-	printf "\n\t** WARNING **\n"
+-	printf "coreboot has been built without a payload. Writing\n"
+-	printf "a coreboot image without a payload to your board's\n"
+-	printf "flash chip will result in a non-booting system. You\n"
+-	printf "can use cbfstool to add a payload to the image.\n\n"
+-
+ .PHONY: force-payload coreinfo nvramcui
+-.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload
++.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
+-- 
+2.39.2
+

config/coreboot/dell/patches/0005-don-t-use-github-for-the-acpica-download.patch

@@ -1,7 +1,7 @@
-From cddb709fd01e3e93a7879488d0d4024360e1e3d9 Mon Sep 17 00:00:00 2001
+From db85939c346436d2a77ad47586edc4cacd48105d Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Sun, 22 Oct 2023 15:02:25 +0100
-Subject: [PATCH 1/1] don't use github for the acpica download
+Subject: [PATCH 5/9] don't use github for the acpica download
 
 i have the tarball from a previous download, and i placed
 it on libreboot rsync, which then got mirrored to princeton.
@@ -22,7 +22,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org>
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
-index ebc9fcb49a..a857110b4b 100755
+index 23a5caf2bb..36565a906c 100755
 --- a/util/crossgcc/buildgcc
 +++ b/util/crossgcc/buildgcc
 @@ -72,7 +72,7 @@ MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"

config/coreboot/dell/patches/0006-use-mirrorservice.org-for-gcc-downloads.patch

@@ -1,7 +1,7 @@
-From 89c47fad6e97fc6a7113ebbdedfcc42ae2b6fc7f Mon Sep 17 00:00:00 2001
+From 9f1f72d0c9eaeff4f70accffc22c1c2183ebf2e6 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Sun, 5 Nov 2023 22:57:08 +0000
-Subject: [PATCH 1/1] use mirrorservice.org for gcc downloads
+Subject: [PATCH 6/9] use mirrorservice.org for gcc downloads
 
 the gnu.org 302 redirect often fails
 
@@ -11,7 +11,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org>
  1 file changed, 5 insertions(+), 5 deletions(-)
 
 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
-index 87f80ba7f6..b3aad5df7d 100755
+index 36565a906c..4d4ca06113 100755
 --- a/util/crossgcc/buildgcc
 +++ b/util/crossgcc/buildgcc
 @@ -67,11 +67,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2"

config/coreboot/dell/patches/0007-nb-intel-gm45-Make-DDR2-raminit-work.patch

@@ -1,7 +1,7 @@
-From e047dc3c95063f27517cd6754e9cbe496ac9313d Mon Sep 17 00:00:00 2001
+From a8ad22b83fbced140cc2fda699af57de869e2063 Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Mon, 10 May 2021 22:40:59 +0200
-Subject: [PATCH] [NOT FOR MERGE] nb/intel/gm45: Make DDR2 raminit work
+Subject: [PATCH 7/9] nb/intel/gm45: Make DDR2 raminit work
 
 List of changes:
  - Update some timing and ODT values
@@ -14,12 +14,16 @@ Tested on Toshiba Satellite A300-1ME with two 2 GiB DDR2-800 SO-DIMMs.
 Change-Id: Ibaee524b8ff652ddadd66cb0eb680401b988ff7c
 Signed-off-by: Angel Pons <th3fanbus@gmail.com>
 ---
+ src/northbridge/intel/gm45/gm45.h             |  2 +-
+ src/northbridge/intel/gm45/raminit.c          | 90 +++++++++++++++++--
+ .../intel/gm45/raminit_rcomp_calibration.c    | 27 ++++--
+ 3 files changed, 106 insertions(+), 13 deletions(-)
 
 diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
-index f28c6d1..bdf0432 100644
+index d929533d92..997f8a0e5a 100644
 --- a/src/northbridge/intel/gm45/gm45.h
 +++ b/src/northbridge/intel/gm45/gm45.h
-@@ -419,7 +419,7 @@
+@@ -419,7 +419,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo);
  int raminit_read_vco_index(void);
  u32 raminit_get_rank_addr(unsigned int channel, unsigned int rank);
  
@@ -29,10 +33,10 @@ index f28c6d1..bdf0432 100644
  void raminit_receive_enable_calibration(int ddr_type, const timings_t *, const dimminfo_t *);
  void raminit_write_training(const mem_clock_t, const dimminfo_t *, int s3resume);
 diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
-index ecada7b..2b8c44e 100644
+index b7e013959a..df8f46fbbc 100644
 --- a/src/northbridge/intel/gm45/raminit.c
 +++ b/src/northbridge/intel/gm45/raminit.c
-@@ -1049,7 +1049,7 @@
+@@ -1047,7 +1047,7 @@ static void rcomp_initialization(const int spd_type, const stepping_t stepping,
  	}
  
  	/* Perform RCOMP calibration for DDR3. */
@@ -41,7 +45,7 @@ index ecada7b..2b8c44e 100644
  
  	/* Run initial RCOMP. */
  	mchbar_setbits32(0x418, 1 << 17);
-@@ -1119,7 +1119,7 @@
+@@ -1117,7 +1117,7 @@ static void dram_program_timings(const int spd_type, const timings_t *const timi
  				reg = (reg & ~(0xf << 10)) | (2 << 10);
  			else
  				reg = (reg & ~(0xf << 10)) | (3 << 10);
@@ -50,7 +54,7 @@ index ecada7b..2b8c44e 100644
  		} else if (timings->mem_clock != MEM_CLOCK_1067MT) {
  			reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15);
  			reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10);
-@@ -1288,11 +1288,11 @@
+@@ -1286,11 +1286,11 @@ static void ddr2_odt_setup(const timings_t *const timings, const int sff)
  		reg = (reg & ~(0xf << (44 - 32))) | (8 << (44 - 32));
  		reg = (reg & ~(0xf << (40 - 32))) | (7 << (40 - 32));
  		if (timings->mem_clock == MEM_CLOCK_667MT) {
@@ -66,7 +70,7 @@ index ecada7b..2b8c44e 100644
  		}
  		mchbar_write32(CxODT_HIGH(ch), reg);
  
-@@ -2217,6 +2217,84 @@
+@@ -2209,6 +2209,84 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
  		raminit_write_training(timings->mem_clock, dimms, s3resume);
  	}
  
@@ -152,10 +156,10 @@ index ecada7b..2b8c44e 100644
  
  	/* Program final memory map (with real values). */
 diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
-index aef863f..b74765f 100644
+index aef863f05a..b74765fd9c 100644
 --- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
 +++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
-@@ -161,11 +161,13 @@
+@@ -161,11 +161,13 @@ static void lookup_and_write(const int a1step,
  		mchbar += 4;
  	}
  }
@@ -170,7 +174,7 @@ index aef863f..b74765f 100644
  	enum {
  		PULL_UP = 0,
  		PULL_DOWN = 1,
-@@ -196,6 +198,10 @@
+@@ -196,6 +198,10 @@ void raminit_rcomp_calibration(const stepping_t stepping) {
  		reg = mchbar_read32(0x518);
  		lut_idx[channel][group][PULL_UP] = (reg >> 24) & 0x7f;
  		lut_idx[channel][group][PULL_DOWN] = (reg >> 16) & 0x7f;
@@ -181,7 +185,7 @@ index aef863f..b74765f 100644
  	}
  	/* Cleanup? */
  	mchbar_setbits32(0x400, 1 << 3);
-@@ -216,13 +222,19 @@
+@@ -216,13 +222,19 @@ void raminit_rcomp_calibration(const stepping_t stepping) {
  	for (channel = 0; channel < 2; ++channel) {
  		for (group = 0; group < 6; ++group) {
  			for (pu_pd = PULL_DOWN; pu_pd >= PULL_UP; --pu_pd) {
@@ -206,7 +210,7 @@ index aef863f..b74765f 100644
  			mchbar += 0x0010;
  			/* Channel B knows only the first two groups. */
  			if ((1 == channel) && (1 == group))
-@@ -230,4 +242,7 @@
+@@ -230,4 +242,7 @@ void raminit_rcomp_calibration(const stepping_t stepping) {
  		}
  		mchbar += 0x0040;
  	}
@@ -214,3 +218,6 @@ index aef863f..b74765f 100644
 +	mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26);
 +	mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20);
  }
+-- 
+2.39.2
+

config/coreboot/dell/patches/0008-dell-e6400-crank-up-vram-to-256MB-max.patch

@@ -1,7 +1,7 @@
-From 1116145917035a92cc92a34e6a914a9506d17680 Mon Sep 17 00:00:00 2001
+From 1d15c4659abe93d7c75be47a56fb69fcf2dfb46b Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Wed, 1 Nov 2023 16:33:11 +0000
-Subject: [PATCH 1/1] dell/e6400: crank up vram to 256MB (max)
+Subject: [PATCH 8/9] dell/e6400: crank up vram to 256MB (max)
 
 Signed-off-by: Leah Rowe <leah@libreboot.org>
 ---

config/coreboot/dell/patches/0009-never-enable-cpu-microcode-even-if-told-to.patch

@@ -1,19 +1,19 @@
-From eaec1bbb21283fa409a2d1610688c05a62c7b1bc Mon Sep 17 00:00:00 2001
+From e570de21e2463cfca9b2ab25ae67efd65f8e3315 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Thu, 12 Oct 2023 01:20:23 +0100
-Subject: [PATCH 1/1] never enable cpu microcode, even if told to
+Subject: [PATCH 9/9] never enable cpu microcode, even if told to
 
 Signed-off-by: Leah Rowe <leah@libreboot.org>
 ---
- src/cpu/Makefile.inc           | 55 ----------------------------------
- src/cpu/intel/fit/Makefile.inc | 31 -------------------
+ src/cpu/Makefile.mk           | 55 -----------------------------------
+ src/cpu/intel/fit/Makefile.mk | 31 --------------------
  2 files changed, 86 deletions(-)
 
-diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
-index 12c682d43d..e5fb13b33d 100644
---- a/src/cpu/Makefile.inc
-+++ b/src/cpu/Makefile.inc
-@@ -9,61 +9,6 @@ subdirs-$(CONFIG_ARCH_X86) += x86
+diff --git a/src/cpu/Makefile.mk b/src/cpu/Makefile.mk
+index b1c1b1bb3e..571cd1d0e5 100644
+--- a/src/cpu/Makefile.mk
++++ b/src/cpu/Makefile.mk
+@@ -11,61 +11,6 @@ subdirs-$(CONFIG_ARCH_X86) += x86
  subdirs-$(CONFIG_CPU_QEMU_X86) += qemu-x86
  subdirs-$(CONFIG_CPU_POWER9) += power9
  
@@ -75,11 +75,11 @@ index 12c682d43d..e5fb13b33d 100644
  ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),)
  cpu_microcode_blob.bin-COREBOOT-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC)
  endif
-diff --git a/src/cpu/intel/fit/Makefile.inc b/src/cpu/intel/fit/Makefile.inc
-index da4549e5d1..c31102872e 100644
---- a/src/cpu/intel/fit/Makefile.inc
-+++ b/src/cpu/intel/fit/Makefile.inc
-@@ -17,35 +17,4 @@ $(call add_intermediate, set_fit_ptr, $(IFITTOOL))
+diff --git a/src/cpu/intel/fit/Makefile.mk b/src/cpu/intel/fit/Makefile.mk
+index a86a22e6d6..edca120c14 100644
+--- a/src/cpu/intel/fit/Makefile.mk
++++ b/src/cpu/intel/fit/Makefile.mk
+@@ -19,35 +19,4 @@ $(call add_intermediate, set_fit_ptr, $(IFITTOOL))
  
  FIT_ENTRY=$(call strip_quotes, $(CONFIG_INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG))
  

config/coreboot/dell/patches/0010-Never-download-blobs-even-if-USE_BLOBS-y.patch

@@ -0,0 +1,47 @@
+From c7d9dcec39fbda870b7cddbeb87771bac0fb68b8 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <info@minifree.org>
+Date: Fri, 3 May 2024 06:24:49 +0100
+Subject: [PATCH 1/1] Never download blobs, even if USE_BLOBS=y
+
+same idea as my never-microcode patches. i maintain
+canoeboot and i like to re-use the same configs from
+lbmk. with this and the never-microcode patch, it should
+now be possible to re-use lbmk coreboot configs unmodified!
+
+when those configs are used in cbmk, the relevant blobs
+are never downloaded, ever.
+
+Signed-off-by: Leah Rowe <info@minifree.org>
+---
+ Makefile.mk | 15 ---------------
+ 1 file changed, 15 deletions(-)
+
+diff --git a/Makefile.mk b/Makefile.mk
+index 87c6bcb247..3747eaa556 100644
+--- a/Makefile.mk
++++ b/Makefile.mk
+@@ -222,21 +222,6 @@ $(info Updating git submodules.)
+ forgetthis:=$(shell git submodule update --init $(quiet_errors))
+ # Checkout Cmocka repository
+ forgetthis:=$(shell git submodule update --init --checkout 3rdparty/cmocka $(quiet_errors))
+-ifeq ($(CONFIG_USE_BLOBS),y)
+-# These items are necessary because each has update=none in .gitmodules.  They are ignored
+-# until expressly requested and enabled with --checkout
+-forgetthis:=$(shell git submodule update --init --checkout 3rdparty/blobs $(quiet_errors))
+-forgetthis:=$(shell git submodule update --init --checkout 3rdparty/intel-microcode $(quiet_errors))
+-ifeq ($(CONFIG_FSP_USE_REPO),y)
+-forgetthis:=$(shell git submodule update --init --checkout 3rdparty/fsp $(quiet_errors))
+-endif
+-ifeq ($(CONFIG_USE_AMD_BLOBS),y)
+-forgetthis:=$(shell git submodule update --init --checkout 3rdparty/amd_blobs $(quiet_errors))
+-endif
+-ifeq ($(CONFIG_USE_QC_BLOBS),y)
+-forgetthis:=$(shell git submodule update --init --checkout 3rdparty/qc_blobs $(quiet_errors))
+-endif
+-endif
+ UPDATED_SUBMODULES:=1
+ COREBOOT_EXPORTS += UPDATED_SUBMODULES
+ 
+-- 
+2.39.2
+

config/coreboot/dell/patches/0010-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch

@@ -0,0 +1,52 @@
+From 6f4968919cf4e801caacf8392492457b79efa9c6 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Mon, 20 May 2024 10:24:16 -0600
+Subject: [PATCH] mb/dell/e6400: Use 100 MHz reference clock for display
+
+The E6400 uses a 100 MHz reference clock for spread spectrum support on
+LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For
+the more common 1280 x 800 display panels, the numerical error was not
+large enough to cause noticable issues, but the actual pixel clock
+frequency derived from a 100 MHz reference using PLL configs calculated
+assuming a 96 MHz reference was not close enough for 1440 x 900 panels,
+which require a much higher pixel clock. This resulted in a garbled
+display in the pre-OS graphics environment provided by libgfxinit.
+
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/mainboard/dell/e6400/Kconfig   | 3 +++
+ src/northbridge/intel/gm45/Kconfig | 4 ++++
+ 2 files changed, 7 insertions(+)
+
+diff --git a/src/mainboard/dell/e6400/Kconfig b/src/mainboard/dell/e6400/Kconfig
+index 034de4be2b..4cb16af697 100644
+--- a/src/mainboard/dell/e6400/Kconfig
++++ b/src/mainboard/dell/e6400/Kconfig
+@@ -17,6 +17,9 @@ config BOARD_SPECIFIC_OPTIONS
+ 	select INTEL_GMA_HAVE_VBT
+ 	select EC_DELL_MEC5035
+ 
++config INTEL_GMA_DPLL_REF_FREQ
++	default 100000000
++
+ config MAINBOARD_DIR
+ 	default "dell/e6400"
+ 
+diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
+index 2a266b9771..2432c9d78e 100644
+--- a/src/northbridge/intel/gm45/Kconfig
++++ b/src/northbridge/intel/gm45/Kconfig
+@@ -13,6 +13,10 @@ config NORTHBRIDGE_INTEL_GM45
+ 
+ if NORTHBRIDGE_INTEL_GM45
+ 
++config INTEL_GMA_DPLL_REF_FREQ
++	int
++	default 96000000
++
+ config VBOOT
+ 	select VBOOT_STARTS_IN_BOOTBLOCK
+ 
+-- 
+2.45.1
+

config/coreboot/dell/patches/0018-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch

@@ -1,28 +0,0 @@
-From a65797a9e7e610b1c916cb4d275b72848622c218 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Sat, 6 May 2023 15:53:41 -0600
-Subject: [PATCH 18/22] mb/dell/e6400: Enable 01.0 device in devicetree for
- dGPU models
-
-Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
----
- src/mainboard/dell/e6400/devicetree.cb | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/mainboard/dell/e6400/devicetree.cb b/src/mainboard/dell/e6400/devicetree.cb
-index bb954cbd7b..e9f3915d17 100644
---- a/src/mainboard/dell/e6400/devicetree.cb
-+++ b/src/mainboard/dell/e6400/devicetree.cb
-@@ -19,7 +19,7 @@ chip northbridge/intel/gm45
- 		ops gm45_pci_domain_ops
- 
- 		device pci 00.0 on end # host bridge
--		device pci 01.0 off end
-+		device pci 01.0 on end
- 		device pci 02.0 on end # VGA
- 		device pci 02.1 on end # Display
- 		device pci 03.0 on end # ME
--- 
-2.39.2
-

config/coreboot/dell/patches/0020-ec-dell-mec5035-Add-command-to-enable-disable-radios.patch

@@ -1,61 +0,0 @@
-From f0db13a15c76c2947eec8919fd121450048914ce Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Sun, 27 Aug 2023 17:36:36 -0600
-Subject: [PATCH 20/22] ec/dell/mec5035: Add command to enable/disable radios
-
-These were determined by sniffing the LPC bus while toggling the
-hardware wireless switch on the Latitude E6400. To differentiate devices
-options in the vendor BIOS to change which radios the switch controlled
-were used.
-
-Change-Id: I173dc197d63cda232dd7ede0cb798ab0a364482b
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
----
- src/ec/dell/mec5035/mec5035.c | 9 +++++++++
- src/ec/dell/mec5035/mec5035.h | 8 ++++++++
- 2 files changed, 17 insertions(+)
-
-diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
-index 8da11e5b1c..e0335a4635 100644
---- a/src/ec/dell/mec5035/mec5035.c
-+++ b/src/ec/dell/mec5035/mec5035.c
-@@ -84,6 +84,15 @@ u8 mec5035_mouse_touchpad(u8 setting)
- 	return buf[0];
- }
- 
-+void mec5035_radio_enable(enum mec5035_radio_dev dev, u8 on)
-+{
-+	/* From LPC traces and userspace testing with other values,
-+	   the second byte has to be 2 for an unknown reason. */
-+	u8 buf[3] = {dev, 2, on};
-+	write_mailbox_regs(buf, 2, 3);
-+	ec_command(CMD_RADIO_EN);
-+}
-+
- void mec5035_early_init(void)
- {
- 	/* If this isn't sent the EC shuts down the system after about 15
-diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h
-index e7a05b64d4..16512e2cc2 100644
---- a/src/ec/dell/mec5035/mec5035.h
-+++ b/src/ec/dell/mec5035/mec5035.h
-@@ -16,8 +16,16 @@
- 
- #define CMD_CPU_OK	0xc2
- 
-+#define CMD_RADIO_EN	0x2b
-+enum mec5035_radio_dev {
-+	RADIO_WLAN = 0,
-+	RADIO_WWAN = 1,
-+	RADIO_WPAN = 2,
-+};
-+
- u8 mec5035_mouse_touchpad(u8 setting);
- void mec5035_cpu_ok(void);
- void mec5035_early_init(void);
-+void mec5035_radio_enable(enum mec5035_radio_dev device, u8 on);
- 
- #endif /* _EC_DELL_MEC5035_H_ */
--- 
-2.39.2
-

config/coreboot/dell/patches/0021-ec-dell-mec5035-Hook-up-radio-enables-to-option-API.patch

@@ -1,37 +0,0 @@
-From 4537c365dae010645404fdb5d2d4e5f478dede67 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Sun, 27 Aug 2023 19:15:37 -0600
-Subject: [PATCH 21/22] ec/dell/mec5035: Hook up radio enables to option API
-
-Change-Id: I52de5ea3d24b400a93adee7a6207a4439eac61db
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
----
- src/ec/dell/mec5035/mec5035.c | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
-index e0335a4635..20a33cc0ad 100644
---- a/src/ec/dell/mec5035/mec5035.c
-+++ b/src/ec/dell/mec5035/mec5035.c
-@@ -4,6 +4,7 @@
- #include <console/console.h>
- #include <device/device.h>
- #include <device/pnp.h>
-+#include <option.h>
- #include <pc80/keyboard.h>
- #include <stdint.h>
- #include "mec5035.h"
-@@ -108,6 +109,10 @@ static void mec5035_init(struct device *dev)
- 	mec5035_mouse_touchpad(TP_PS2_MOUSE);
- 
- 	pc_keyboard_init(NO_AUX_DEVICE);
-+
-+	mec5035_radio_enable(RADIO_WLAN, get_uint_option("wlan", 1));
-+	mec5035_radio_enable(RADIO_WWAN, get_uint_option("wwan", 1));
-+	mec5035_radio_enable(RADIO_WPAN, get_uint_option("bluetooth", 1));
- }
- 
- static struct device_operations ops = {
--- 
-2.39.2
-

config/coreboot/dell/patches/0025-Revert-Kconfig-Bring-HEAP_SIZE-to-a-common-large-val.patch

@@ -1,341 +0,0 @@
-From f1b5b0051718139cf59ad047d42d1360b8452ec5 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Sun, 29 Oct 2023 01:18:50 +0000
-Subject: [PATCH 1/1] Revert "Kconfig: Bring HEAP_SIZE to a common, large
- value"
-
-This reverts commit 44a48ce7a46c36df69f7b2cf3552bf10fa5f61b6.
-
-NOTE:
-
-this is done instead of merging:
-https://review.coreboot.org/c/coreboot/+/78623
-
-which is still under review for now
-
-the patch i'm reverting is this one:
-https://review.coreboot.org/c/coreboot/+/78270
-
-this was actually only merged the day before i
-updated coreboot revs in lbmk to the 12 october rev,
-so there's no harm in quickly reverting this for now
-
-however, later on, we will rely on the other patch
----
- src/Kconfig                                   | 3 ++-
- src/cpu/qemu-x86/Kconfig                      | 3 +++
- src/mainboard/sifive/hifive-unleashed/Kconfig | 3 +++
- src/northbridge/amd/pi/Kconfig                | 4 ++++
- src/soc/amd/picasso/Kconfig                   | 4 ++++
- src/soc/amd/stoneyridge/Kconfig               | 4 ++++
- src/soc/cavium/cn81xx/Kconfig                 | 3 +++
- src/soc/intel/alderlake/Kconfig               | 5 +++++
- src/soc/intel/apollolake/Kconfig              | 4 ++++
- src/soc/intel/cannonlake/Kconfig              | 4 ++++
- src/soc/intel/elkhartlake/Kconfig             | 4 ++++
- src/soc/intel/jasperlake/Kconfig              | 4 ++++
- src/soc/intel/meteorlake/Kconfig              | 5 +++++
- src/soc/intel/skylake/Kconfig                 | 4 ++++
- src/soc/intel/tigerlake/Kconfig               | 4 ++++
- src/soc/intel/xeon_sp/Kconfig                 | 4 ++++
- src/soc/intel/xeon_sp/cpx/Kconfig             | 4 ++++
- src/soc/intel/xeon_sp/skx/Kconfig             | 4 ++++
- src/soc/intel/xeon_sp/spr/Kconfig             | 4 ++++
- src/soc/qualcomm/ipq40xx/Kconfig              | 4 ++++
- 20 files changed, 77 insertions(+), 1 deletion(-)
-
-diff --git a/src/Kconfig b/src/Kconfig
-index ae8024089e..1549719dd0 100644
---- a/src/Kconfig
-+++ b/src/Kconfig
-@@ -751,7 +751,8 @@ config RTC
- 
- config HEAP_SIZE
- 	hex
--	default 0x100000
-+	default 0x100000 if FLATTENED_DEVICE_TREE
-+	default 0x4000
- 
- config STACK_SIZE
- 	hex
-diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig
-index 0fa999e1ac..f3e2c4cea9 100644
---- a/src/cpu/qemu-x86/Kconfig
-+++ b/src/cpu/qemu-x86/Kconfig
-@@ -35,4 +35,7 @@ config MAX_CPUS
- 	default 32 if SMM_TSEG
- 	default 4
- 
-+config HEAP_SIZE
-+	default 0x8000
-+
- endif
-diff --git a/src/mainboard/sifive/hifive-unleashed/Kconfig b/src/mainboard/sifive/hifive-unleashed/Kconfig
-index 7bc3b0bcbb..7f9300f2a7 100644
---- a/src/mainboard/sifive/hifive-unleashed/Kconfig
-+++ b/src/mainboard/sifive/hifive-unleashed/Kconfig
-@@ -10,6 +10,9 @@ config BOARD_SPECIFIC_OPTIONS
- 	select FLATTENED_DEVICE_TREE
- 	select SPI_SDCARD
- 
-+config HEAP_SIZE
-+	default 0x10000
-+
- config MAINBOARD_DIR
- 	default "sifive/hifive-unleashed"
- 
-diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig
-index 4ffe82a15f..4518db149b 100644
---- a/src/northbridge/amd/pi/Kconfig
-+++ b/src/northbridge/amd/pi/Kconfig
-@@ -29,4 +29,8 @@ config HW_MEM_HOLE_SIZEK
- 	hex
- 	default 0x200000
- 
-+config HEAP_SIZE
-+	hex
-+	default 0xc0000
-+
- endif # NORTHBRIDGE_AMD_PI
-diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
-index c33f287067..796fe4eb13 100644
---- a/src/soc/amd/picasso/Kconfig
-+++ b/src/soc/amd/picasso/Kconfig
-@@ -264,6 +264,10 @@ config S3_VGA_ROM_RUN
- 	bool
- 	default n
- 
-+config HEAP_SIZE
-+	hex
-+	default 0xc0000
-+
- config SERIRQ_CONTINUOUS_MODE
- 	bool
- 	default n
-diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
-index 6ff135e6a8..9af7455bae 100644
---- a/src/soc/amd/stoneyridge/Kconfig
-+++ b/src/soc/amd/stoneyridge/Kconfig
-@@ -152,6 +152,10 @@ config S3_VGA_ROM_RUN
- 	bool
- 	default n
- 
-+config HEAP_SIZE
-+	hex
-+	default 0xc0000
-+
- config EHCI_BAR
- 	hex
- 	default 0xfef00000
-diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig
-index 77ca97202b..368581f8f1 100644
---- a/src/soc/cavium/cn81xx/Kconfig
-+++ b/src/soc/cavium/cn81xx/Kconfig
-@@ -30,6 +30,9 @@ config ARCH_ARMV8_EXTENSION
- 	int
- 	default 1
- 
-+config HEAP_SIZE
-+	default 0x10000
-+
- config STACK_SIZE
- 	default 0x2000
- 
-diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
-index 4b960c1d22..82ec8f263e 100644
---- a/src/soc/intel/alderlake/Kconfig
-+++ b/src/soc/intel/alderlake/Kconfig
-@@ -215,6 +215,11 @@ config IED_REGION_SIZE
- 	hex
- 	default 0x400000
- 
-+config HEAP_SIZE
-+	hex
-+	default 0x80000 if BMP_LOGO
-+	default 0x10000
-+
- config GFX_GMA_DEFAULT_MMIO
- 	default 0xaf000000 if MAINBOARD_HAS_EARLY_LIBGFXINIT
- 
-diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
-index 78ec2987ce..bce935d800 100644
---- a/src/soc/intel/apollolake/Kconfig
-+++ b/src/soc/intel/apollolake/Kconfig
-@@ -252,6 +252,10 @@ config IFWI_FILE_NAME
- 	help
- 	  Name of file to store in the IFWI region.
- 
-+config HEAP_SIZE
-+	hex
-+	default 0x8000
-+
- config MAX_ROOT_PORTS
- 	int
- 	default 6
-diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
-index a42a3c365b..80237f9810 100644
---- a/src/soc/intel/cannonlake/Kconfig
-+++ b/src/soc/intel/cannonlake/Kconfig
-@@ -160,6 +160,10 @@ config IED_REGION_SIZE
- 	hex
- 	default 0x400000
- 
-+config HEAP_SIZE
-+	hex
-+	default 0x8000
-+
- config NHLT_DMIC_1CH_16B
- 	bool
- 	depends on ACPI_NHLT
-diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig
-index 3361c0ddb9..7f1c767379 100644
---- a/src/soc/intel/elkhartlake/Kconfig
-+++ b/src/soc/intel/elkhartlake/Kconfig
-@@ -104,6 +104,10 @@ config IED_REGION_SIZE
- 	hex
- 	default 0x0
- 
-+config HEAP_SIZE
-+	hex
-+	default 0x8000
-+
- config MAX_ROOT_PORTS
- 	int
- 	default 7
-diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
-index 3d84991e09..ff5def3263 100644
---- a/src/soc/intel/jasperlake/Kconfig
-+++ b/src/soc/intel/jasperlake/Kconfig
-@@ -106,6 +106,10 @@ config IED_REGION_SIZE
- 	hex
- 	default 0x400000
- 
-+config HEAP_SIZE
-+	hex
-+	default 0x8000
-+
- config MAX_ROOT_PORTS
- 	int
- 	default 8
-diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
-index 590e8b80e1..48030a1911 100644
---- a/src/soc/intel/meteorlake/Kconfig
-+++ b/src/soc/intel/meteorlake/Kconfig
-@@ -197,6 +197,11 @@ config IED_REGION_SIZE
- 	hex
- 	default 0x400000
- 
-+config HEAP_SIZE
-+	hex
-+	default 0x80000 if BMP_LOGO
-+	default 0x10000
-+
- # Intel recommends reserving the PCIe TBT root port resources as below:
- # - 42 buses
- # - 194 MiB Non-prefetchable memory
-diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
-index e0df501460..d6a11363ee 100644
---- a/src/soc/intel/skylake/Kconfig
-+++ b/src/soc/intel/skylake/Kconfig
-@@ -151,6 +151,10 @@ config EXCLUDE_NATIVE_SD_INTERFACE
- 	help
- 	  If you set this option to n, will not use native SD controller.
- 
-+config HEAP_SIZE
-+	hex
-+	default 0x80000
-+
- config IED_REGION_SIZE
- 	hex
- 	default 0x400000
-diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
-index c07a0d8365..0a4b7bfdb8 100644
---- a/src/soc/intel/tigerlake/Kconfig
-+++ b/src/soc/intel/tigerlake/Kconfig
-@@ -152,6 +152,10 @@ config IED_REGION_SIZE
- config INTEL_TME
- 	default n
- 
-+config HEAP_SIZE
-+	hex
-+	default 0x10000
-+
- config MAX_ROOT_PORTS
- 	int
- 	default 24 if SOC_INTEL_TIGERLAKE_PCH_H
-diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
-index e63bee5451..63ced01067 100644
---- a/src/soc/intel/xeon_sp/Kconfig
-+++ b/src/soc/intel/xeon_sp/Kconfig
-@@ -91,6 +91,10 @@ config ECAM_MMCONF_BASE_ADDRESS
- config ECAM_MMCONF_BUS_NUMBER
- 	default 256
- 
-+config HEAP_SIZE
-+	hex
-+	default 0x80000
-+
- config HPET_MIN_TICKS
- 	hex
- 	default 0x80
-diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig
-index ac166c3038..f54f7716b6 100644
---- a/src/soc/intel/xeon_sp/cpx/Kconfig
-+++ b/src/soc/intel/xeon_sp/cpx/Kconfig
-@@ -71,6 +71,10 @@ config CPU_MICROCODE_CBFS_LEN
- 	hex
- 	default 0x7C00
- 
-+config HEAP_SIZE
-+	hex
-+	default 0x80000
-+
- config STACK_SIZE
- 	hex
- 	default 0x4000
-diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig
-index 5d843878e1..c2c3d4e2e8 100644
---- a/src/soc/intel/xeon_sp/skx/Kconfig
-+++ b/src/soc/intel/xeon_sp/skx/Kconfig
-@@ -55,6 +55,10 @@ config CPU_MICROCODE_CBFS_LEN
- 	hex
- 	default 0x7C00
- 
-+config HEAP_SIZE
-+	hex
-+	default 0x80000
-+
- config IED_REGION_SIZE
- 	hex
- 	default 0x400000
-diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
-index 43b87ade14..b1c4c783b7 100644
---- a/src/soc/intel/xeon_sp/spr/Kconfig
-+++ b/src/soc/intel/xeon_sp/spr/Kconfig
-@@ -79,6 +79,10 @@ config CPU_MICROCODE_CBFS_LEN
- 	hex
- 	default 0x8c00
- 
-+config HEAP_SIZE
-+	hex
-+	default 0x80000
-+
- config STACK_SIZE
- 	hex
- 	default 0x4000
-diff --git a/src/soc/qualcomm/ipq40xx/Kconfig b/src/soc/qualcomm/ipq40xx/Kconfig
-index 0ce92731c0..0eabb00752 100644
---- a/src/soc/qualcomm/ipq40xx/Kconfig
-+++ b/src/soc/qualcomm/ipq40xx/Kconfig
-@@ -57,4 +57,8 @@ config SBL_UTIL_PATH
- 	help
- 	  Path for utils to combine SBL_ELF and bootblock
- 
-+config HEAP_SIZE
-+	hex
-+	default 0x8000
-+
- endif
--- 
-2.39.2
-

config/coreboot/dell/target.cfg

@@ -1,3 +1,4 @@
 tree="dell"
-rev="d862695f5f432b5c78dada5f16c293a4c3f9fce6"
-xarch="i386-elf"
+tree_depend="default"
+xtree="default"
+rev="b6cbfa977f63d57d5d6b9e9f7c1cef30162f575a"

config/coreboot/e6400_4mb/config/libgfxinit_corebootfb

@@ -22,6 +22,7 @@ CONFIG_USE_OPTION_TABLE=y
 CONFIG_STATIC_OPTION_TABLE=y
 CONFIG_COMPRESS_RAMSTAGE_LZMA=y
 # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
+CONFIG_SEPARATE_ROMSTAGE=y
 CONFIG_INCLUDE_CONFIG_FILE=y
 CONFIG_COLLECT_TIMESTAMPS=y
 # CONFIG_TIMESTAMPS_ON_CONSOLE is not set
@@ -133,6 +134,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 CONFIG_BOARD_DELL_E6400=y
 # CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
 # CONFIG_BOARD_DELL_PRECISION_T1650 is not set
+CONFIG_INTEL_GMA_DPLL_REF_FREQ=100000000
 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
 CONFIG_ECAM_MMCONF_BUS_NUMBER=64
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
@@ -148,7 +150,6 @@ CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_IFD_BIN_PATH="../../../config/ifd/ich9m/4_ifd"
 CONFIG_GBE_BIN_PATH="../../../config/ifd/ich9m/gbe"
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_VBT_DATA_SIZE_KB=8
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -167,7 +168,6 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_4096=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -181,6 +181,7 @@ CONFIG_COREBOOT_ROMSIZE_KB_4096=y
 # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
 CONFIG_COREBOOT_ROMSIZE_KB=4096
@@ -209,6 +210,7 @@ CONFIG_VERSTAGE_ADDR=0x2000000
 CONFIG_SMM_RESERVED_SIZE=0x100000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
 # CONFIG_USE_EXP_X86_64_SUPPORT is not set
+CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
 CONFIG_EHCI_BAR=0xfef00000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -217,14 +219,15 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0x61256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
+CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
 # CONFIG_PCIEXP_COMMON_CLOCK is not set
+CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
 CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_CBFS_CACHE_ALIGN=8
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 
 #
 # CPU
@@ -323,6 +326,8 @@ CONFIG_HAVE_EXP_X86_64_SUPPORT=y
 CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
 CONFIG_AP_IN_SIPI_WAIT=y
 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
+CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
+CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
 CONFIG_PC80_SYSTEM=y
 CONFIG_HAVE_CMOS_DEFAULT=y
 CONFIG_POSTCAR_STAGE=y
@@ -358,7 +363,7 @@ CONFIG_LINEAR_FRAMEBUFFER=y
 CONFIG_PCI=y
 CONFIG_ECAM_MMCONF_SUPPORT=y
 CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_PLUGIN_SUPPORT=y
+CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
 CONFIG_PCIEXP_PLUGIN_SUPPORT=y
 CONFIG_ECAM_MMCONF_LENGTH=0x04000000
 CONFIG_PCI_ALLOW_BUS_MASTER=y
@@ -369,8 +374,6 @@ CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
 CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
 # CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
 CONFIG_PCIEXP_HOTPLUG_IO=0x2000
-CONFIG_FIRMWARE_CONNECTION_MANAGER=y
-# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
 # CONFIG_EARLY_PCI_BRIDGE is not set
 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
@@ -400,6 +403,7 @@ CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_ISSI=y
 # CONFIG_DRIVERS_UART_OXPCIE is not set
 CONFIG_HAVE_USBDEBUG=y
 CONFIG_HAVE_USBDEBUG_OPTIONS=y
@@ -415,6 +419,10 @@ CONFIG_INTEL_EDID=y
 CONFIG_INTEL_INT15=y
 CONFIG_INTEL_GMA_ACPI=y
 CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y
+CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
+# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
+# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
+CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
 CONFIG_GFX_GMA=y
 CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
 CONFIG_GFX_GMA_DYN_CPU=y
@@ -453,6 +461,7 @@ CONFIG_NO_TPM=y
 CONFIG_PCR_BOOT_MODE=1
 CONFIG_PCR_HWID=1
 CONFIG_PCR_SRTM=2
+CONFIG_PCR_FW_VER=10
 CONFIG_PCR_RUNTIME_DATA=3
 # end of Trusted Platform Module
 
@@ -480,6 +489,7 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
+CONFIG_HEAP_SIZE=0x100000
 
 #
 # Console
@@ -543,6 +553,10 @@ CONFIG_PAYLOAD_NONE=y
 #
 # CONFIG_DISPLAY_MTRRS is not set
 
+#
+# Vendorcode Debug Settings
+#
+
 #
 # BLOB Debug Settings
 #

config/coreboot/e6400_4mb/config/libgfxinit_txtmode

@@ -22,6 +22,7 @@ CONFIG_USE_OPTION_TABLE=y
 CONFIG_STATIC_OPTION_TABLE=y
 CONFIG_COMPRESS_RAMSTAGE_LZMA=y
 # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
+CONFIG_SEPARATE_ROMSTAGE=y
 CONFIG_INCLUDE_CONFIG_FILE=y
 CONFIG_COLLECT_TIMESTAMPS=y
 # CONFIG_TIMESTAMPS_ON_CONSOLE is not set
@@ -131,6 +132,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 CONFIG_BOARD_DELL_E6400=y
 # CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
 # CONFIG_BOARD_DELL_PRECISION_T1650 is not set
+CONFIG_INTEL_GMA_DPLL_REF_FREQ=100000000
 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
 CONFIG_ECAM_MMCONF_BUS_NUMBER=64
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
@@ -146,7 +148,6 @@ CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_IFD_BIN_PATH="../../../config/ifd/ich9m/4_ifd"
 CONFIG_GBE_BIN_PATH="../../../config/ifd/ich9m/gbe"
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_VBT_DATA_SIZE_KB=8
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -165,7 +166,6 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_4096=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -179,6 +179,7 @@ CONFIG_COREBOOT_ROMSIZE_KB_4096=y
 # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
 CONFIG_COREBOOT_ROMSIZE_KB=4096
@@ -207,6 +208,7 @@ CONFIG_VERSTAGE_ADDR=0x2000000
 CONFIG_SMM_RESERVED_SIZE=0x100000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
 # CONFIG_USE_EXP_X86_64_SUPPORT is not set
+CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
 CONFIG_EHCI_BAR=0xfef00000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -215,14 +217,15 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0x61256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
+CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
 # CONFIG_PCIEXP_COMMON_CLOCK is not set
+CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
 CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_CBFS_CACHE_ALIGN=8
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 
 #
 # CPU
@@ -321,6 +324,8 @@ CONFIG_HAVE_EXP_X86_64_SUPPORT=y
 CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
 CONFIG_AP_IN_SIPI_WAIT=y
 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
+CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
+CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
 CONFIG_PC80_SYSTEM=y
 CONFIG_HAVE_CMOS_DEFAULT=y
 CONFIG_POSTCAR_STAGE=y
@@ -354,7 +359,7 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y
 CONFIG_PCI=y
 CONFIG_ECAM_MMCONF_SUPPORT=y
 CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_PLUGIN_SUPPORT=y
+CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
 CONFIG_PCIEXP_PLUGIN_SUPPORT=y
 CONFIG_ECAM_MMCONF_LENGTH=0x04000000
 CONFIG_PCI_ALLOW_BUS_MASTER=y
@@ -365,8 +370,6 @@ CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
 CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
 # CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
 CONFIG_PCIEXP_HOTPLUG_IO=0x2000
-CONFIG_FIRMWARE_CONNECTION_MANAGER=y
-# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
 # CONFIG_EARLY_PCI_BRIDGE is not set
 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
@@ -396,6 +399,7 @@ CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_ISSI=y
 # CONFIG_DRIVERS_UART_OXPCIE is not set
 CONFIG_HAVE_USBDEBUG=y
 CONFIG_HAVE_USBDEBUG_OPTIONS=y
@@ -411,6 +415,10 @@ CONFIG_INTEL_EDID=y
 CONFIG_INTEL_INT15=y
 CONFIG_INTEL_GMA_ACPI=y
 CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y
+CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
+# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
+# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
+CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
 CONFIG_GFX_GMA=y
 CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
 CONFIG_GFX_GMA_DYN_CPU=y
@@ -449,6 +457,7 @@ CONFIG_NO_TPM=y
 CONFIG_PCR_BOOT_MODE=1
 CONFIG_PCR_HWID=1
 CONFIG_PCR_SRTM=2
+CONFIG_PCR_FW_VER=10
 CONFIG_PCR_RUNTIME_DATA=3
 # end of Trusted Platform Module
 
@@ -476,6 +485,7 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
+CONFIG_HEAP_SIZE=0x100000
 
 #
 # Console
@@ -539,6 +549,10 @@ CONFIG_PAYLOAD_NONE=y
 #
 # CONFIG_DISPLAY_MTRRS is not set
 
+#
+# Vendorcode Debug Settings
+#
+
 #
 # BLOB Debug Settings
 #

config/coreboot/e6400_4mb/target.cfg

@@ -1,9 +1,7 @@
 tree="dell"
 xarch="i386-elf"
-payload_grub="n"
-payload_grub_withseabios="n"
 payload_seabios="y"
+payload_grub="y"
 payload_memtest="y"
-payload_seabios_withgrub="y"
-payload_seabios_grubonly="y"
 grub_scan_disk="ahci"
+vcfg="e6400"

config/coreboot/fam15h_rdimm/patches/0001-Tweak-cmos-defaults-for-KCMA-D8-for-a-little-speed-b.patch

@@ -1,7 +1,7 @@
-From 7a00638cea41ad939a59fc0e5996959435fbdb7f Mon Sep 17 00:00:00 2001
+From dede42141890bee0065c46b86a8e23952651239d Mon Sep 17 00:00:00 2001
 From: "D.d.P.F. Lombard" <lombard@lombards.xyz>
 Date: Sun, 7 Feb 2021 16:40:05 +0100
-Subject: [PATCH 3/6] Tweak cmos defaults for KCMA-D8 (for a little speed
+Subject: [PATCH 1/9] Tweak cmos defaults for KCMA-D8 (for a little speed
  boost)
 
 63xx CPUs have the option to use a reduced latency value inside the crossbar.
@@ -34,5 +34,5 @@ index 306687157f..4e033d756f 100644
  power_on_after_fail=On
  boot_option=Fallback
 -- 
-2.25.1
+2.39.2
 

config/coreboot/fam15h_rdimm/patches/0002-asus-kgpe-d16-enable-lc_cache_partitioning-and-exper.patch

@@ -1,7 +1,7 @@
-From f0aac7261e16adc8e61eca7a506ff2de5112be47 Mon Sep 17 00:00:00 2001
+From b8520bb9440ff1c6145536c5519a86e6b4c64e69 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Fri, 7 May 2021 19:43:32 +0100
-Subject: [PATCH 6/6] asus/kgpe-d16: enable lc_cache_partitioning and
+Subject: [PATCH 2/9] asus/kgpe-d16: enable lc_cache_partitioning and
  experimental_memory_speed_boost
 
 This really only benefits 63xx opterons which are less reliable in libreboot due
@@ -28,5 +28,5 @@ index 7c496a50d7..8a25620e1d 100644
  power_on_after_fail=On
  boot_option=Fallback
 -- 
-2.25.1
+2.39.2
 

config/coreboot/fam15h_rdimm/patches/0003-util-cbfstool-Makefile-support-distclean.patch

@@ -1,7 +1,7 @@
-From d5dc3f23eb546cf328fdfe1e918afa028fb9cd8c Mon Sep 17 00:00:00 2001
+From b193eb189926be76a6e6979b158a3d4fe35c846a Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Sun, 9 Jul 2023 04:13:52 +0100
-Subject: [PATCH 1/1] util/cbfstool Makefile: support distclean
+Subject: [PATCH 3/9] util/cbfstool Makefile: support distclean
 
 it just does make-clean
 
@@ -37,5 +37,5 @@ index d5321f6959..b8424d7d87 100644
  .SILENT:
  endif
 -- 
-2.40.1
+2.39.2
 

config/coreboot/fam15h_rdimm/patches/0004-crossgcc-patch-binutils-2.32-for-newer-hostcc.patch

@@ -1,7 +1,7 @@
-From 4b4b2bdc2cedb3e219c6f90809e5684441b1dafa Mon Sep 17 00:00:00 2001
+From 0040629068d6e0e340a6ba76a568c27b699c6913 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Sun, 9 Jul 2023 04:54:19 +0100
-Subject: [PATCH 1/1] crossgcc: patch binutils 2.32 for newer hostcc
+Subject: [PATCH 4/9] crossgcc: patch binutils 2.32 for newer hostcc
 
 tested on debian sid as of 9 July 2023
 
@@ -33,5 +33,5 @@ index 0000000000..de27a2752a
 + #include "gold-threads.h"
 +
 -- 
-2.40.1
+2.39.2
 

config/coreboot/fam15h_rdimm/patches/0005-fix-crossgcc-acpica-build-on-newer-hostcc.patch

@@ -1,7 +1,7 @@
-From 373dd351e374f391c9e2048e5f3e535267a04719 Mon Sep 17 00:00:00 2001
+From 200c943bb5f39d5455d9a6836116349773c86578 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Sun, 9 Jul 2023 19:37:39 +0100
-Subject: [PATCH 1/1] fix crossgcc/acpica build on newer hostcc
+Subject: [PATCH 5/9] fix crossgcc/acpica build on newer hostcc
 
 Changes made to acpica/iasl:
 
@@ -104,5 +104,5 @@ index 0000000000..8de47245bd
 +2.40.1
 +
 -- 
-2.40.1
+2.39.2
 

config/coreboot/fam15h_rdimm/patches/0006-coreboot-fam15h-use-new-upstream-for-acpica.patch

@@ -1,7 +1,7 @@
-From ba94a3f27a26d181291b5908bdd627be375eb606 Mon Sep 17 00:00:00 2001
+From 1071d59eb4d2a5cb36f3c670119aadb838eb6a85 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Sun, 16 Jul 2023 00:44:22 +0100
-Subject: [PATCH 1/1] coreboot/fam15h: use new upstream for acpica
+Subject: [PATCH 6/9] coreboot/fam15h: use new upstream for acpica
 
 the original upstream died
 
@@ -21,7 +21,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org>
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
-index b75b90a877..e3efa722f1 100755
+index b75b90a877..4b838208bb 100755
 --- a/util/crossgcc/buildgcc
 +++ b/util/crossgcc/buildgcc
 @@ -73,7 +73,7 @@ MPC_ARCHIVE="https://ftpmirror.gnu.org/mpc/mpc-${MPC_VERSION}.tar.gz"
@@ -34,5 +34,5 @@ index b75b90a877..e3efa722f1 100755
  EXPAT_ARCHIVE="https://downloads.sourceforge.net/sourceforge/expat/expat-${EXPAT_VERSION}.tar.bz2"
  # CLANG toolchain archive locations
 -- 
-2.40.1
+2.39.2
 

config/coreboot/fam15h_rdimm/patches/0007-use-mirrorservire.org-for-gcc-downloads.patch

@@ -1,7 +1,7 @@
-From 5358f0adc28bb1300162aa6bcfaa45aea69970d0 Mon Sep 17 00:00:00 2001
+From 68434f686e36d7e245e3d49c2851fcc4e319a857 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Sun, 5 Nov 2023 23:08:43 +0000
-Subject: [PATCH 1/1] use mirrorservire.org for gcc downloads
+Subject: [PATCH 7/9] use mirrorservire.org for gcc downloads
 
 the gnu.org 302 redirect often fails
 

config/coreboot/fam15h_rdimm/patches/0008-buildgcc-don-t-treat-binutil-warnings-as-errors.patch

@@ -0,0 +1,35 @@
+From b11feca5893a2fdc3a0c0e6ccbd6084f60be6ab3 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Sat, 13 Jan 2024 14:57:46 +0000
+Subject: [PATCH 8/9] buildgcc: don't treat binutil warnings as errors
+
+binutils 2.32 has too many build warnings on modern toolchains,
+and newer gcc versions are much more pedantic about warnings,
+treating them as errors by default.
+
+instead of patching binutils like before, just let the warnings
+persist. the warnings are benign. a user on gnuboot irc had serious
+issues building binutils 2.32 specifically, on current gentoo as
+of 13 January 2024. this patch mitigates those warning messages.
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ util/crossgcc/buildgcc | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
+index 438fb5a59f..0ad1980104 100755
+--- a/util/crossgcc/buildgcc
++++ b/util/crossgcc/buildgcc
+@@ -719,7 +719,7 @@ build_BINUTILS() {
+ 		--disable-werror --disable-nls --enable-lto --enable-gold \
+ 		--enable-interwork --enable-multilib \
+ 		--enable-plugins --enable-multilibs \
+-		CFLAGS="$HOSTCFLAGS" \
++		CFLAGS="$HOSTCFLAGS -Wno-error -w" \
+ 		CXXFLAGS="$HOSTCFLAGS" \
+ 		|| touch .failed
+ 	# shellcheck disable=SC2086
+-- 
+2.39.2
+

config/coreboot/fam15h_rdimm/patches/0009-Do-not-use-microcode-updates-on-AMD-platforms.patch

@@ -1,7 +1,7 @@
-From 2b1d40b970d9cbbb4f8fe30679e9b6909aa3d99a Mon Sep 17 00:00:00 2001
+From 857b0f7beca46cc93b06d580f2b641a7742df597 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Thu, 6 May 2021 17:07:06 +0100
-Subject: [PATCH 4/6] Do not use microcode updates on AMD platforms
+Subject: [PATCH 9/9] Do not use microcode updates on AMD platforms
 
 Coreboot is hardcoding the use of microcode updates on some platforms.
 
@@ -14,10 +14,10 @@ not be used.
  3 files changed, 2 insertions(+), 61 deletions(-)
 
 diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
-index b80c30d72b..e7909d32ed 100644
+index 66ee2f9169..dcf02d5f67 100644
 --- a/src/cpu/Makefile.inc
 +++ b/src/cpu/Makefile.inc
-@@ -14,54 +14,4 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32))
+@@ -16,54 +16,4 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32))
  ## Rules for building the microcode blob in CBFS
  ################################################################################
  
@@ -104,5 +104,5 @@ index 7035323026..e0029f562d 100644
 -microcode_amd_fam15h.bin-type := microcode
 +# Microcode deleted in this version of coreboot.
 -- 
-2.25.1
+2.39.2
 

config/coreboot/fam15h_rdimm/patches/0010-Never-download-blobs-even-if-USE_BLOBS-y.patch

@@ -0,0 +1,43 @@
+From 31cb9eefd880bd8011d18fa070f31c498a0265e5 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <info@minifree.org>
+Date: Fri, 3 May 2024 06:29:41 +0100
+Subject: [PATCH 1/1] Never download blobs, even if USE_BLOBS=y
+
+Same idea as my never-microcode patch. With this and that
+other patch, I can now re-use lbmk coreboot configs reliably
+without modifying them; i currently set CONFIG_USE_BLOBS=n
+on the Canoeboot versions.
+
+Thus, this patch will reduce the maintenance burden for cbmk.
+
+Signed-off-by: Leah Rowe <info@minifree.org>
+---
+ Makefile.inc | 12 ------------
+ 1 file changed, 12 deletions(-)
+
+diff --git a/Makefile.inc b/Makefile.inc
+index be198d6580..2b3718b67c 100644
+--- a/Makefile.inc
++++ b/Makefile.inc
+@@ -196,18 +196,6 @@ endif
+ ifneq ($(UPDATED_SUBMODULES),1)
+ # try to fetch non-optional submodules if the source is under git
+ forgetthis:=$(if $(GIT),$(shell git submodule update --init))
+-ifeq ($(CONFIG_USE_BLOBS),y)
+-# These items are necessary because each has update=none in .gitmodules.  They are ignored
+-# until expressly requested and enabled with --checkout
+-forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/blobs))
+-forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/intel-microcode))
+-ifeq ($(CONFIG_PLATFORM_USES_FSP1_0)$(CONFIG_PLATFORM_USES_FSP1_1)$(CONFIG_PLATFORM_USES_FSP2_0),y)
+-forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/fsp))
+-endif
+-ifeq ($(CONFIG_USE_AMD_BLOBS),y)
+-forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/amd_blobs))
+-endif
+-endif
+ UPDATED_SUBMODULES:=1
+ COREBOOT_EXPORTS += UPDATED_SUBMODULES
+ endif
+-- 
+2.39.2
+

config/coreboot/fam15h_rdimm/target.cfg

@@ -1,8 +1,2 @@
 tree="fam15h_rdimm"
 rev="1c13f8d85c7306213cd525308ee8973e5663a3f8"
-xarch="i386-elf"
-payload_grub="n"
-payload_grub_withseabios="n"
-payload_seabios="n"
-payload_memtest="n"
-xlang="c"

config/coreboot/fam15h_udimm/patches/0001-Revert-Revert-nb-amd-mct_ddr3-Fix-RDIMM-training-fai.patch

@@ -1,7 +1,7 @@
-From 8f2988cba4fffef1bd4f65e123c76bf4b7a18672 Mon Sep 17 00:00:00 2001
+From 80db97601779457d5044acbd085e85f05c46575d Mon Sep 17 00:00:00 2001
 From: "D.d.P.F. Lombard" <lombard@lombards.xyz>
 Date: Sun, 7 Feb 2021 15:29:40 +0100
-Subject: [PATCH 1/6] Revert "Revert "nb/amd/mct_ddr3: Fix RDIMM training
+Subject: [PATCH 01/10] Revert "Revert "nb/amd/mct_ddr3: Fix RDIMM training
  failure on Fam15h" (fixes a bug that prevent certain RAM modules from
  booting)
 
@@ -27,5 +27,5 @@ index ddaaaab8d5..3b07786b91 100644
  		if (pDCTstat->Status & (1 << SB_Registered)) {
  			misc2 |= 1 << SubMemclkRegDly;
 -- 
-2.25.1
+2.39.2
 

config/coreboot/fam15h_udimm/patches/0002-Tweak-cmos-defaults-for-KCMA-D8-for-a-little-speed-b.patch

@@ -1,7 +1,7 @@
-From 7a00638cea41ad939a59fc0e5996959435fbdb7f Mon Sep 17 00:00:00 2001
+From 744c3c7f81c015a96f8d5feeece86f622ca85604 Mon Sep 17 00:00:00 2001
 From: "D.d.P.F. Lombard" <lombard@lombards.xyz>
 Date: Sun, 7 Feb 2021 16:40:05 +0100
-Subject: [PATCH 3/6] Tweak cmos defaults for KCMA-D8 (for a little speed
+Subject: [PATCH 02/10] Tweak cmos defaults for KCMA-D8 (for a little speed
  boost)
 
 63xx CPUs have the option to use a reduced latency value inside the crossbar.
@@ -34,5 +34,5 @@ index 306687157f..4e033d756f 100644
  power_on_after_fail=On
  boot_option=Fallback
 -- 
-2.25.1
+2.39.2
 

config/coreboot/fam15h_udimm/patches/0003-asus-kgpe-d16-enable-lc_cache_partitioning-and-exper.patch

@@ -1,7 +1,7 @@
-From f0aac7261e16adc8e61eca7a506ff2de5112be47 Mon Sep 17 00:00:00 2001
+From f8eb43796090965baef1c6f75aa438e2918bf2e1 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Fri, 7 May 2021 19:43:32 +0100
-Subject: [PATCH 6/6] asus/kgpe-d16: enable lc_cache_partitioning and
+Subject: [PATCH 03/10] asus/kgpe-d16: enable lc_cache_partitioning and
  experimental_memory_speed_boost
 
 This really only benefits 63xx opterons which are less reliable in libreboot due
@@ -28,5 +28,5 @@ index 7c496a50d7..8a25620e1d 100644
  power_on_after_fail=On
  boot_option=Fallback
 -- 
-2.25.1
+2.39.2
 

config/coreboot/fam15h_udimm/patches/0004-util-cbfstool-Makefile-support-distclean.patch

@@ -1,7 +1,7 @@
-From d5dc3f23eb546cf328fdfe1e918afa028fb9cd8c Mon Sep 17 00:00:00 2001
+From e56750af2637fe078d4b6c4a17f936f9cd8a8768 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Sun, 9 Jul 2023 04:13:52 +0100
-Subject: [PATCH 1/1] util/cbfstool Makefile: support distclean
+Subject: [PATCH 04/10] util/cbfstool Makefile: support distclean
 
 it just does make-clean
 
@@ -37,5 +37,5 @@ index d5321f6959..b8424d7d87 100644
  .SILENT:
  endif
 -- 
-2.40.1
+2.39.2
 

config/coreboot/fam15h_udimm/patches/0005-crossgcc-patch-binutils-2.32-for-newer-hostcc.patch

@@ -1,7 +1,7 @@
-From 4b4b2bdc2cedb3e219c6f90809e5684441b1dafa Mon Sep 17 00:00:00 2001
+From cc9d7de95387eb607ef78240ff0a7bf71127cb1e Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Sun, 9 Jul 2023 04:54:19 +0100
-Subject: [PATCH 1/1] crossgcc: patch binutils 2.32 for newer hostcc
+Subject: [PATCH 05/10] crossgcc: patch binutils 2.32 for newer hostcc
 
 tested on debian sid as of 9 July 2023
 
@@ -33,5 +33,5 @@ index 0000000000..de27a2752a
 + #include "gold-threads.h"
 +
 -- 
-2.40.1
+2.39.2
 

config/coreboot/fam15h_udimm/patches/0006-fix-crossgcc-acpica-build-on-newer-hostcc.patch

@@ -1,7 +1,7 @@
-From 373dd351e374f391c9e2048e5f3e535267a04719 Mon Sep 17 00:00:00 2001
+From 473918ced4ce1f1e1eac54335495a4bb865a93e1 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Sun, 9 Jul 2023 19:37:39 +0100
-Subject: [PATCH 1/1] fix crossgcc/acpica build on newer hostcc
+Subject: [PATCH 06/10] fix crossgcc/acpica build on newer hostcc
 
 Changes made to acpica/iasl:
 
@@ -104,5 +104,5 @@ index 0000000000..8de47245bd
 +2.40.1
 +
 -- 
-2.40.1
+2.39.2
 

config/coreboot/fam15h_udimm/patches/0007-coreboot-fam15h-use-new-upstream-for-acpica.patch

@@ -1,7 +1,7 @@
-From ba94a3f27a26d181291b5908bdd627be375eb606 Mon Sep 17 00:00:00 2001
+From 8be51d32c574e52cafed06c4e8772ad3eb4338ca Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Sun, 16 Jul 2023 00:44:22 +0100
-Subject: [PATCH 1/1] coreboot/fam15h: use new upstream for acpica
+Subject: [PATCH 07/10] coreboot/fam15h: use new upstream for acpica
 
 the original upstream died
 
@@ -21,7 +21,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org>
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
-index b75b90a877..e3efa722f1 100755
+index b75b90a877..4b838208bb 100755
 --- a/util/crossgcc/buildgcc
 +++ b/util/crossgcc/buildgcc
 @@ -73,7 +73,7 @@ MPC_ARCHIVE="https://ftpmirror.gnu.org/mpc/mpc-${MPC_VERSION}.tar.gz"
@@ -34,5 +34,5 @@ index b75b90a877..e3efa722f1 100755
  EXPAT_ARCHIVE="https://downloads.sourceforge.net/sourceforge/expat/expat-${EXPAT_VERSION}.tar.bz2"
  # CLANG toolchain archive locations
 -- 
-2.40.1
+2.39.2
 

config/coreboot/fam15h_udimm/patches/0008-use-mirrorservire.org-for-gcc-downloads.patch

@@ -1,7 +1,7 @@
-From 5358f0adc28bb1300162aa6bcfaa45aea69970d0 Mon Sep 17 00:00:00 2001
+From 2c19c93059bc8c8970f6c4ea1647396e032a60fa Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Sun, 5 Nov 2023 23:08:43 +0000
-Subject: [PATCH 1/1] use mirrorservire.org for gcc downloads
+Subject: [PATCH 08/10] use mirrorservire.org for gcc downloads
 
 the gnu.org 302 redirect often fails
 

config/coreboot/fam15h_udimm/patches/0009-buildgcc-don-t-treat-binutil-warnings-as-errors.patch

@@ -0,0 +1,35 @@
+From 32909c251a2e3bd771b8f0036b91402369c9724d Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Sat, 13 Jan 2024 14:57:46 +0000
+Subject: [PATCH 09/10] buildgcc: don't treat binutil warnings as errors
+
+binutils 2.32 has too many build warnings on modern toolchains,
+and newer gcc versions are much more pedantic about warnings,
+treating them as errors by default.
+
+instead of patching binutils like before, just let the warnings
+persist. the warnings are benign. a user on gnuboot irc had serious
+issues building binutils 2.32 specifically, on current gentoo as
+of 13 January 2024. this patch mitigates those warning messages.
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ util/crossgcc/buildgcc | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
+index 438fb5a59f..0ad1980104 100755
+--- a/util/crossgcc/buildgcc
++++ b/util/crossgcc/buildgcc
+@@ -719,7 +719,7 @@ build_BINUTILS() {
+ 		--disable-werror --disable-nls --enable-lto --enable-gold \
+ 		--enable-interwork --enable-multilib \
+ 		--enable-plugins --enable-multilibs \
+-		CFLAGS="$HOSTCFLAGS" \
++		CFLAGS="$HOSTCFLAGS -Wno-error -w" \
+ 		CXXFLAGS="$HOSTCFLAGS" \
+ 		|| touch .failed
+ 	# shellcheck disable=SC2086
+-- 
+2.39.2
+

config/coreboot/fam15h_udimm/patches/0010-Do-not-use-microcode-updates-on-AMD-platforms.patch

@@ -1,7 +1,7 @@
-From 2b1d40b970d9cbbb4f8fe30679e9b6909aa3d99a Mon Sep 17 00:00:00 2001
+From 9cd31ddc0614247bfe2ee5d51f304667b84306c7 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Thu, 6 May 2021 17:07:06 +0100
-Subject: [PATCH 4/6] Do not use microcode updates on AMD platforms
+Subject: [PATCH 10/10] Do not use microcode updates on AMD platforms
 
 Coreboot is hardcoding the use of microcode updates on some platforms.
 
@@ -14,10 +14,10 @@ not be used.
  3 files changed, 2 insertions(+), 61 deletions(-)
 
 diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
-index b80c30d72b..e7909d32ed 100644
+index 66ee2f9169..dcf02d5f67 100644
 --- a/src/cpu/Makefile.inc
 +++ b/src/cpu/Makefile.inc
-@@ -14,54 +14,4 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32))
+@@ -16,54 +16,4 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32))
  ## Rules for building the microcode blob in CBFS
  ################################################################################
  
@@ -104,5 +104,5 @@ index 7035323026..e0029f562d 100644
 -microcode_amd_fam15h.bin-type := microcode
 +# Microcode deleted in this version of coreboot.
 -- 
-2.25.1
+2.39.2
 

config/coreboot/fam15h_udimm/patches/0011-Never-download-blobs-even-if-USE_BLOBS-y.patch

@@ -0,0 +1,43 @@
+From 31cb9eefd880bd8011d18fa070f31c498a0265e5 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <info@minifree.org>
+Date: Fri, 3 May 2024 06:29:41 +0100
+Subject: [PATCH 1/1] Never download blobs, even if USE_BLOBS=y
+
+Same idea as my never-microcode patch. With this and that
+other patch, I can now re-use lbmk coreboot configs reliably
+without modifying them; i currently set CONFIG_USE_BLOBS=n
+on the Canoeboot versions.
+
+Thus, this patch will reduce the maintenance burden for cbmk.
+
+Signed-off-by: Leah Rowe <info@minifree.org>
+---
+ Makefile.inc | 12 ------------
+ 1 file changed, 12 deletions(-)
+
+diff --git a/Makefile.inc b/Makefile.inc
+index be198d6580..2b3718b67c 100644
+--- a/Makefile.inc
++++ b/Makefile.inc
+@@ -196,18 +196,6 @@ endif
+ ifneq ($(UPDATED_SUBMODULES),1)
+ # try to fetch non-optional submodules if the source is under git
+ forgetthis:=$(if $(GIT),$(shell git submodule update --init))
+-ifeq ($(CONFIG_USE_BLOBS),y)
+-# These items are necessary because each has update=none in .gitmodules.  They are ignored
+-# until expressly requested and enabled with --checkout
+-forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/blobs))
+-forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/intel-microcode))
+-ifeq ($(CONFIG_PLATFORM_USES_FSP1_0)$(CONFIG_PLATFORM_USES_FSP1_1)$(CONFIG_PLATFORM_USES_FSP2_0),y)
+-forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/fsp))
+-endif
+-ifeq ($(CONFIG_USE_AMD_BLOBS),y)
+-forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/amd_blobs))
+-endif
+-endif
+ UPDATED_SUBMODULES:=1
+ COREBOOT_EXPORTS += UPDATED_SUBMODULES
+ endif
+-- 
+2.39.2
+

config/coreboot/fam15h_udimm/target.cfg

@@ -1,8 +1,4 @@
 tree="fam15h_udimm"
+tree_depend="fam15h_rdimm"
+xtree="fam15h_rdimm"
 rev="1c13f8d85c7306213cd525308ee8973e5663a3f8"
-xarch="i386-elf"
-payload_grub="n"
-payload_grub_withseabios="n"
-payload_seabios="n"
-payload_memtest="n"
-xlang="c"

config/coreboot/g43t_am3/config/libgfxinit_txtmode

@@ -22,6 +22,7 @@ CONFIG_USE_OPTION_TABLE=y
 CONFIG_STATIC_OPTION_TABLE=y
 CONFIG_COMPRESS_RAMSTAGE_LZMA=y
 # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
+CONFIG_SEPARATE_ROMSTAGE=y
 CONFIG_INCLUDE_CONFIG_FILE=y
 CONFIG_COLLECT_TIMESTAMPS=y
 # CONFIG_TIMESTAMPS_ON_CONSOLE is not set
@@ -143,7 +144,6 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
 CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_DRIVERS_INTEL_WIFI is not set
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_VBT_DATA_SIZE_KB=8
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -163,7 +163,6 @@ CONFIG_PCIEXP_CLK_PM=y
 CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_2048=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -177,6 +176,7 @@ CONFIG_COREBOOT_ROMSIZE_KB_2048=y
 # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
 CONFIG_COREBOOT_ROMSIZE_KB=2048
@@ -203,6 +203,7 @@ CONFIG_VERSTAGE_ADDR=0x2000000
 CONFIG_SMM_RESERVED_SIZE=0x100000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
 # CONFIG_USE_EXP_X86_64_SUPPORT is not set
+CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
 CONFIG_EHCI_BAR=0xfef00000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -211,14 +212,15 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
+CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
 # CONFIG_PCIEXP_COMMON_CLOCK is not set
+CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
 CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_CBFS_CACHE_ALIGN=8
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 
 #
 # CPU
@@ -318,6 +320,8 @@ CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
 CONFIG_AP_IN_SIPI_WAIT=y
 CONFIG_SIPI_VECTOR_IN_ROM=y
 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
+CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
+CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
 CONFIG_PC80_SYSTEM=y
 CONFIG_HAVE_CMOS_DEFAULT=y
 CONFIG_POSTCAR_STAGE=y
@@ -351,7 +355,7 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y
 CONFIG_PCI=y
 CONFIG_ECAM_MMCONF_SUPPORT=y
 CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_PLUGIN_SUPPORT=y
+CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
 CONFIG_PCIEXP_PLUGIN_SUPPORT=y
 CONFIG_ECAM_MMCONF_LENGTH=0x10000000
 CONFIG_PCI_ALLOW_BUS_MASTER=y
@@ -362,8 +366,6 @@ CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
 CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
 # CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
 CONFIG_PCIEXP_HOTPLUG_IO=0x2000
-CONFIG_FIRMWARE_CONNECTION_MANAGER=y
-# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
 # CONFIG_EARLY_PCI_BRIDGE is not set
 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
@@ -396,6 +398,7 @@ CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_ISSI=y
 # CONFIG_DRIVERS_UART_OXPCIE is not set
 CONFIG_HAVE_USBDEBUG=y
 CONFIG_HAVE_USBDEBUG_OPTIONS=y
@@ -409,6 +412,10 @@ CONFIG_HAVE_USBDEBUG_OPTIONS=y
 CONFIG_DRIVERS_I2C_CK505=y
 # CONFIG_DRIVERS_I2C_MAX98396 is not set
 CONFIG_INTEL_GMA_ACPI=y
+CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
+# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
+# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
+CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
 CONFIG_GFX_GMA=y
 CONFIG_GFX_GMA_DYN_CPU=y
 CONFIG_GFX_GMA_GENERATION="G45"
@@ -446,6 +453,7 @@ CONFIG_NO_TPM=y
 CONFIG_PCR_BOOT_MODE=1
 CONFIG_PCR_HWID=1
 CONFIG_PCR_SRTM=2
+CONFIG_PCR_FW_VER=10
 CONFIG_PCR_RUNTIME_DATA=3
 # end of Trusted Platform Module
 
@@ -472,6 +480,7 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
+CONFIG_HEAP_SIZE=0x100000
 
 #
 # Console
@@ -535,6 +544,10 @@ CONFIG_PAYLOAD_NONE=y
 #
 # CONFIG_DISPLAY_MTRRS is not set
 
+#
+# Vendorcode Debug Settings
+#
+
 #
 # BLOB Debug Settings
 #

config/coreboot/g43t_am3/target.cfg

@@ -2,4 +2,4 @@ tree="default"
 xarch="i386-elf"
 payload_seabios="y"
 payload_memtest="y"
-grub_timeout=10
+grubtree="nvme"

config/coreboot/g43t_am3_16mb/config/libgfxinit_txtmode

@@ -22,6 +22,7 @@ CONFIG_USE_OPTION_TABLE=y
 CONFIG_STATIC_OPTION_TABLE=y
 CONFIG_COMPRESS_RAMSTAGE_LZMA=y
 # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
+CONFIG_SEPARATE_ROMSTAGE=y
 CONFIG_INCLUDE_CONFIG_FILE=y
 CONFIG_COLLECT_TIMESTAMPS=y
 # CONFIG_TIMESTAMPS_ON_CONSOLE is not set
@@ -143,7 +144,6 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
 CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_DRIVERS_INTEL_WIFI is not set
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_VBT_DATA_SIZE_KB=8
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -163,7 +163,6 @@ CONFIG_PCIEXP_CLK_PM=y
 CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_2048=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -177,6 +176,7 @@ CONFIG_BOARD_ROMSIZE_KB_2048=y
 # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
 CONFIG_COREBOOT_ROMSIZE_KB_16384=y
+# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
 CONFIG_COREBOOT_ROMSIZE_KB=16384
@@ -203,6 +203,7 @@ CONFIG_VERSTAGE_ADDR=0x2000000
 CONFIG_SMM_RESERVED_SIZE=0x100000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
 # CONFIG_USE_EXP_X86_64_SUPPORT is not set
+CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
 CONFIG_EHCI_BAR=0xfef00000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -211,14 +212,15 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
+CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
 # CONFIG_PCIEXP_COMMON_CLOCK is not set
+CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
 CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_CBFS_CACHE_ALIGN=8
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 
 #
 # CPU
@@ -318,6 +320,8 @@ CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
 CONFIG_AP_IN_SIPI_WAIT=y
 CONFIG_SIPI_VECTOR_IN_ROM=y
 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
+CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
+CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
 CONFIG_PC80_SYSTEM=y
 CONFIG_HAVE_CMOS_DEFAULT=y
 CONFIG_POSTCAR_STAGE=y
@@ -351,7 +355,7 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y
 CONFIG_PCI=y
 CONFIG_ECAM_MMCONF_SUPPORT=y
 CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_PLUGIN_SUPPORT=y
+CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
 CONFIG_PCIEXP_PLUGIN_SUPPORT=y
 CONFIG_ECAM_MMCONF_LENGTH=0x10000000
 CONFIG_PCI_ALLOW_BUS_MASTER=y
@@ -362,8 +366,6 @@ CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
 CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
 # CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
 CONFIG_PCIEXP_HOTPLUG_IO=0x2000
-CONFIG_FIRMWARE_CONNECTION_MANAGER=y
-# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
 # CONFIG_EARLY_PCI_BRIDGE is not set
 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
@@ -396,6 +398,7 @@ CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_ISSI=y
 # CONFIG_DRIVERS_UART_OXPCIE is not set
 CONFIG_HAVE_USBDEBUG=y
 CONFIG_HAVE_USBDEBUG_OPTIONS=y
@@ -409,6 +412,10 @@ CONFIG_HAVE_USBDEBUG_OPTIONS=y
 CONFIG_DRIVERS_I2C_CK505=y
 # CONFIG_DRIVERS_I2C_MAX98396 is not set
 CONFIG_INTEL_GMA_ACPI=y
+CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
+# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
+# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
+CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
 CONFIG_GFX_GMA=y
 CONFIG_GFX_GMA_DYN_CPU=y
 CONFIG_GFX_GMA_GENERATION="G45"
@@ -446,6 +453,7 @@ CONFIG_NO_TPM=y
 CONFIG_PCR_BOOT_MODE=1
 CONFIG_PCR_HWID=1
 CONFIG_PCR_SRTM=2
+CONFIG_PCR_FW_VER=10
 CONFIG_PCR_RUNTIME_DATA=3
 # end of Trusted Platform Module
 
@@ -472,6 +480,7 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
+CONFIG_HEAP_SIZE=0x100000
 
 #
 # Console
@@ -535,6 +544,10 @@ CONFIG_PAYLOAD_NONE=y
 #
 # CONFIG_DISPLAY_MTRRS is not set
 
+#
+# Vendorcode Debug Settings
+#
+
 #
 # BLOB Debug Settings
 #

config/coreboot/g43t_am3_16mb/target.cfg

@@ -2,5 +2,5 @@ tree="default"
 xarch="i386-elf"
 payload_seabios="y"
 payload_memtest="y"
-grub_scan_disk="ata"
-grub_timeout=10
+release="n"
+grubtree="nvme"

config/coreboot/ga_g41m_es2l/config/libgfxinit_txtmode

@@ -22,6 +22,7 @@ CONFIG_USE_OPTION_TABLE=y
 CONFIG_STATIC_OPTION_TABLE=y
 CONFIG_COMPRESS_RAMSTAGE_LZMA=y
 # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
+CONFIG_SEPARATE_ROMSTAGE=y
 CONFIG_INCLUDE_CONFIG_FILE=y
 CONFIG_COLLECT_TIMESTAMPS=y
 # CONFIG_TIMESTAMPS_ON_CONSOLE is not set
@@ -151,7 +152,6 @@ CONFIG_BOARD_GIGABYTE_GA_G41M_ES2L=y
 # CONFIG_BOARD_GIGABYTE_GA_H61M_DS2V is not set
 # CONFIG_BOARD_GIGABYTE_GA_H61MA_D3V is not set
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_VBT_DATA_SIZE_KB=8
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -170,7 +170,6 @@ CONFIG_PCIEXP_CLK_PM=y
 CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_1024=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -184,6 +183,7 @@ CONFIG_COREBOOT_ROMSIZE_KB_1024=y
 # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
 CONFIG_COREBOOT_ROMSIZE_KB=1024
@@ -210,6 +210,7 @@ CONFIG_VERSTAGE_ADDR=0x2000000
 CONFIG_SMM_RESERVED_SIZE=0x100000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
 # CONFIG_USE_EXP_X86_64_SUPPORT is not set
+CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
 CONFIG_EHCI_BAR=0xfef00000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -218,17 +219,18 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
+CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
 # CONFIG_PCIEXP_COMMON_CLOCK is not set
+CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
 CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_CBFS_CACHE_ALIGN=8
 CONFIG_INTEL_HAS_TOP_SWAP=y
 # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
 CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 
 #
 # CPU
@@ -324,6 +326,8 @@ CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
 CONFIG_AP_IN_SIPI_WAIT=y
 CONFIG_SIPI_VECTOR_IN_ROM=y
 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
+CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
+CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
 CONFIG_PC80_SYSTEM=y
 CONFIG_HAVE_CMOS_DEFAULT=y
 CONFIG_POSTCAR_STAGE=y
@@ -357,7 +361,7 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y
 CONFIG_PCI=y
 CONFIG_ECAM_MMCONF_SUPPORT=y
 CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_PLUGIN_SUPPORT=y
+CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
 CONFIG_PCIEXP_PLUGIN_SUPPORT=y
 CONFIG_ECAM_MMCONF_LENGTH=0x10000000
 CONFIG_PCI_ALLOW_BUS_MASTER=y
@@ -368,8 +372,6 @@ CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
 CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
 # CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
 CONFIG_PCIEXP_HOTPLUG_IO=0x2000
-CONFIG_FIRMWARE_CONNECTION_MANAGER=y
-# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
 # CONFIG_EARLY_PCI_BRIDGE is not set
 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
@@ -404,6 +406,7 @@ CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_ISSI=y
 # CONFIG_DRIVERS_UART_OXPCIE is not set
 CONFIG_HAVE_USBDEBUG=y
 # CONFIG_USBDEBUG is not set
@@ -415,6 +418,10 @@ CONFIG_HAVE_USBDEBUG=y
 # CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
 # CONFIG_DRIVERS_I2C_MAX98396 is not set
 CONFIG_INTEL_GMA_ACPI=y
+CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
+# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
+# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
+CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
 CONFIG_GFX_GMA=y
 CONFIG_GFX_GMA_DYN_CPU=y
 CONFIG_GFX_GMA_GENERATION="G45"
@@ -452,6 +459,7 @@ CONFIG_NO_TPM=y
 CONFIG_PCR_BOOT_MODE=1
 CONFIG_PCR_HWID=1
 CONFIG_PCR_SRTM=2
+CONFIG_PCR_FW_VER=10
 CONFIG_PCR_RUNTIME_DATA=3
 # end of Trusted Platform Module
 
@@ -479,6 +487,7 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
+CONFIG_HEAP_SIZE=0x100000
 
 #
 # Console
@@ -542,6 +551,10 @@ CONFIG_PAYLOAD_NONE=y
 #
 # CONFIG_DISPLAY_MTRRS is not set
 
+#
+# Vendorcode Debug Settings
+#
+
 #
 # BLOB Debug Settings
 #

config/coreboot/ga_g41m_es2l/target.cfg

@@ -2,4 +2,4 @@ tree="default"
 xarch="i386-elf"
 payload_seabios="y"
 payload_memtest="y"
-grub_timeout=10
+grubtree="nvme"

config/coreboot/gru_bob/config/libgfxinit_corebootfb

@@ -21,6 +21,7 @@ CONFIG_COMPRESS_RAMSTAGE_LZMA=y
 # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
 CONFIG_COMPRESS_PRERAM_STAGES=y
 CONFIG_COMPRESS_BOOTBLOCK=y
+CONFIG_SEPARATE_ROMSTAGE=y
 CONFIG_INCLUDE_CONFIG_FILE=y
 # CONFIG_COLLECT_TIMESTAMPS is not set
 # CONFIG_USE_BLOBS is not set
@@ -148,6 +149,11 @@ CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_BOARD_GOOGLE_TRICKY is not set
 # CONFIG_BOARD_GOOGLE_ZAKO is not set
 
+#
+# Brox
+#
+# CONFIG_BOARD_GOOGLE_BROX is not set
+
 #
 # Brya
 #
@@ -183,7 +189,6 @@ CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_BOARD_GOOGLE_OSIRIS is not set
 # CONFIG_BOARD_GOOGLE_PIRRHA is not set
 # CONFIG_BOARD_GOOGLE_PRIMUS is not set
-# CONFIG_BOARD_GOOGLE_PRIMUS4ES is not set
 # CONFIG_BOARD_GOOGLE_PUJJO is not set
 # CONFIG_BOARD_GOOGLE_QUANDISO is not set
 # CONFIG_BOARD_GOOGLE_REDRIX is not set
@@ -202,6 +207,8 @@ CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_BOARD_GOOGLE_ZYDRON is not set
 # CONFIG_BOARD_GOOGLE_NOKRIS is not set
 # CONFIG_BOARD_GOOGLE_DOCHI is not set
+# CONFIG_BOARD_GOOGLE_ANRAGGAR is not set
+# CONFIG_BOARD_GOOGLE_XOL is not set
 
 #
 # Butterfly
@@ -229,6 +236,7 @@ CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_BOARD_GOOGLE_KRABBY is not set
 # CONFIG_BOARD_GOOGLE_TENTACRUEL is not set
 # CONFIG_BOARD_GOOGLE_MAGIKARP is not set
+# CONFIG_BOARD_GOOGLE_CHINCHOU is not set
 
 #
 # Staryu
@@ -288,6 +296,7 @@ CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_BOARD_GOOGLE_TARANZA is not set
 # CONFIG_BOARD_GOOGLE_BOXY is not set
 # CONFIG_BOARD_GOOGLE_DEXI is not set
+# CONFIG_BOARD_GOOGLE_DITA is not set
 
 #
 # Drallion
@@ -320,6 +329,7 @@ CONFIG_SPI_FLASH_WINBOND=y
 # Geralt
 #
 # CONFIG_BOARD_GOOGLE_GERALT is not set
+# CONFIG_BOARD_GOOGLE_CIRI is not set
 
 #
 # Glados
@@ -345,9 +355,9 @@ CONFIG_BOARD_GOOGLE_BOB=y
 #
 # Guybrush
 #
+# CONFIG_BOARD_GOOGLE_DEWATT is not set
 # CONFIG_BOARD_GOOGLE_GUYBRUSH is not set
 # CONFIG_BOARD_GOOGLE_NIPPERKIN is not set
-# CONFIG_BOARD_GOOGLE_DEWATT is not set
 
 #
 # Hatch
@@ -367,10 +377,15 @@ CONFIG_BOARD_GOOGLE_BOB=y
 #
 # Herobrine
 #
-
-#
-# (Herobrine requires 'Allow QC blobs repository')
-#
+# CONFIG_BOARD_GOOGLE_HEROBRINE is not set
+# CONFIG_BOARD_GOOGLE_HEROBRINE_REV0 is not set
+# CONFIG_BOARD_GOOGLE_SENOR is not set
+# CONFIG_BOARD_GOOGLE_PIGLIN is not set
+# CONFIG_BOARD_GOOGLE_HOGLIN is not set
+# CONFIG_BOARD_GOOGLE_VILLAGER is not set
+# CONFIG_BOARD_GOOGLE_EVOKER is not set
+# CONFIG_BOARD_GOOGLE_ZOGLIN is not set
+# CONFIG_BOARD_GOOGLE_ZOMBIE is not set
 
 #
 # Jecht
@@ -551,6 +566,8 @@ CONFIG_BOARD_GOOGLE_BOB=y
 # CONFIG_BOARD_GOOGLE_REX_EC_ISH is not set
 # CONFIG_BOARD_GOOGLE_OVIS is not set
 # CONFIG_BOARD_GOOGLE_OVIS4ES is not set
+# CONFIG_BOARD_GOOGLE_DEKU is not set
+# CONFIG_BOARD_GOOGLE_DEKU4ES is not set
 # CONFIG_BOARD_GOOGLE_REX4ES is not set
 # CONFIG_BOARD_GOOGLE_REX4ES_EC_ISH is not set
 
@@ -563,11 +580,11 @@ CONFIG_BOARD_GOOGLE_BOB=y
 #
 # Skyrim
 #
+# CONFIG_BOARD_GOOGLE_CRYSTALDRIFT is not set
+# CONFIG_BOARD_GOOGLE_FROSTFLOW is not set
+# CONFIG_BOARD_GOOGLE_MARKARTH is not set
 # CONFIG_BOARD_GOOGLE_SKYRIM is not set
 # CONFIG_BOARD_GOOGLE_WINTERHOLD is not set
-# CONFIG_BOARD_GOOGLE_FROSTFLOW is not set
-# CONFIG_BOARD_GOOGLE_CRYSTALDRIFT is not set
-# CONFIG_BOARD_GOOGLE_MARKARTH is not set
 
 #
 # Slippy
@@ -595,10 +612,19 @@ CONFIG_BOARD_GOOGLE_BOB=y
 #
 # Trogdor
 #
-
-#
-# (Trogdor requires 'Allow QC blobs repository')
-#
+# CONFIG_BOARD_GOOGLE_BUBS is not set
+# CONFIG_BOARD_GOOGLE_COACHZ is not set
+# CONFIG_BOARD_GOOGLE_GELARSHIE is not set
+# CONFIG_BOARD_GOOGLE_HOMESTAR is not set
+# CONFIG_BOARD_GOOGLE_KINGOFTOWN is not set
+# CONFIG_BOARD_GOOGLE_LAZOR is not set
+# CONFIG_BOARD_GOOGLE_MARZIPAN is not set
+# CONFIG_BOARD_GOOGLE_MRBLAND is not set
+# CONFIG_BOARD_GOOGLE_PAZQUEL is not set
+# CONFIG_BOARD_GOOGLE_POMPOM is not set
+# CONFIG_BOARD_GOOGLE_QUACKINGSTICK is not set
+# CONFIG_BOARD_GOOGLE_WORMDINGLER is not set
+# CONFIG_BOARD_GOOGLE_TROGDOR is not set
 
 #
 # Veyron
@@ -645,22 +671,21 @@ CONFIG_BOARD_GOOGLE_BOB=y
 #
 # Zork
 #
-# CONFIG_BOARD_GOOGLE_DALBOZ is not set
-# CONFIG_BOARD_GOOGLE_VILBOZ is not set
-# CONFIG_BOARD_GOOGLE_EZKINIL is not set
-# CONFIG_BOARD_GOOGLE_MORPHIUS is not set
-# CONFIG_BOARD_GOOGLE_TREMBYLE is not set
 # CONFIG_BOARD_GOOGLE_BERKNIP is not set
-# CONFIG_BOARD_GOOGLE_WOOMAX is not set
+# CONFIG_BOARD_GOOGLE_DALBOZ is not set
 # CONFIG_BOARD_GOOGLE_DIRINBOZ is not set
-# CONFIG_BOARD_GOOGLE_SHUBOZ is not set
+# CONFIG_BOARD_GOOGLE_EZKINIL is not set
 # CONFIG_BOARD_GOOGLE_GUMBOZ is not set
+# CONFIG_BOARD_GOOGLE_MORPHIUS is not set
+# CONFIG_BOARD_GOOGLE_SHUBOZ is not set
+# CONFIG_BOARD_GOOGLE_TREMBYLE is not set
+# CONFIG_BOARD_GOOGLE_VILBOZ is not set
+# CONFIG_BOARD_GOOGLE_WOOMAX is not set
 CONFIG_DRIVER_TPM_SPI_BUS=0x0
 CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS=0x5
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
 CONFIG_DRIVER_TPM_I2C_BUS=0x0
 CONFIG_DRIVER_TPM_I2C_ADDR=0x20
-CONFIG_VBT_DATA_SIZE_KB=8
 CONFIG_PMIC_BUS=-1
 CONFIG_BOARD_GOOGLE_GRU_COMMON=y
 CONFIG_GRU_HAS_TPM2=y
@@ -675,7 +700,6 @@ CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_TTYS0_BAUD=115200
 CONFIG_D3COLD_SUPPORT=y
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_DRIVER_TPM_SPI_CHIP=0
 # CONFIG_TPM_MEASURED_BOOT is not set
@@ -691,6 +715,7 @@ CONFIG_COREBOOT_ROMSIZE_KB_8192=y
 # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
 CONFIG_COREBOOT_ROMSIZE_KB=8192
@@ -712,6 +737,7 @@ CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
 CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
+CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION=y
 CONFIG_GENERIC_UDELAY=y
 CONFIG_SOC_ROCKCHIP_RK3399=y
 CONFIG_RK3399_SPREAD_SPECTRUM_DDR=y
@@ -782,8 +808,6 @@ CONFIG_LINEAR_FRAMEBUFFER=y
 # CONFIG_BOOTSPLASH is not set
 # end of Display
 
-CONFIG_FIRMWARE_CONNECTION_MANAGER=y
-# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
 # CONFIG_SOFTWARE_I2C is not set
 CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
 CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
@@ -845,6 +869,7 @@ CONFIG_MAINBOARD_HAS_TPM2=y
 CONFIG_PCR_BOOT_MODE=1
 CONFIG_PCR_HWID=1
 CONFIG_PCR_SRTM=2
+CONFIG_PCR_FW_VER=10
 CONFIG_PCR_RUNTIME_DATA=3
 # end of Trusted Platform Module
 
@@ -865,6 +890,7 @@ CONFIG_ACPI_CUSTOM_MADT=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
+CONFIG_HEAP_SIZE=0x100000
 
 #
 # Console
@@ -923,6 +949,10 @@ CONFIG_PAYLOAD_NONE=y
 # CPU Debug Settings
 #
 
+#
+# Vendorcode Debug Settings
+#
+
 #
 # BLOB Debug Settings
 #

config/coreboot/gru_kevin/config/libgfxinit_corebootfb

@@ -21,6 +21,7 @@ CONFIG_COMPRESS_RAMSTAGE_LZMA=y
 # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
 CONFIG_COMPRESS_PRERAM_STAGES=y
 CONFIG_COMPRESS_BOOTBLOCK=y
+CONFIG_SEPARATE_ROMSTAGE=y
 CONFIG_INCLUDE_CONFIG_FILE=y
 # CONFIG_COLLECT_TIMESTAMPS is not set
 # CONFIG_USE_BLOBS is not set
@@ -148,6 +149,11 @@ CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_BOARD_GOOGLE_TRICKY is not set
 # CONFIG_BOARD_GOOGLE_ZAKO is not set
 
+#
+# Brox
+#
+# CONFIG_BOARD_GOOGLE_BROX is not set
+
 #
 # Brya
 #
@@ -183,7 +189,6 @@ CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_BOARD_GOOGLE_OSIRIS is not set
 # CONFIG_BOARD_GOOGLE_PIRRHA is not set
 # CONFIG_BOARD_GOOGLE_PRIMUS is not set
-# CONFIG_BOARD_GOOGLE_PRIMUS4ES is not set
 # CONFIG_BOARD_GOOGLE_PUJJO is not set
 # CONFIG_BOARD_GOOGLE_QUANDISO is not set
 # CONFIG_BOARD_GOOGLE_REDRIX is not set
@@ -202,6 +207,8 @@ CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_BOARD_GOOGLE_ZYDRON is not set
 # CONFIG_BOARD_GOOGLE_NOKRIS is not set
 # CONFIG_BOARD_GOOGLE_DOCHI is not set
+# CONFIG_BOARD_GOOGLE_ANRAGGAR is not set
+# CONFIG_BOARD_GOOGLE_XOL is not set
 
 #
 # Butterfly
@@ -229,6 +236,7 @@ CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_BOARD_GOOGLE_KRABBY is not set
 # CONFIG_BOARD_GOOGLE_TENTACRUEL is not set
 # CONFIG_BOARD_GOOGLE_MAGIKARP is not set
+# CONFIG_BOARD_GOOGLE_CHINCHOU is not set
 
 #
 # Staryu
@@ -288,6 +296,7 @@ CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_BOARD_GOOGLE_TARANZA is not set
 # CONFIG_BOARD_GOOGLE_BOXY is not set
 # CONFIG_BOARD_GOOGLE_DEXI is not set
+# CONFIG_BOARD_GOOGLE_DITA is not set
 
 #
 # Drallion
@@ -320,6 +329,7 @@ CONFIG_SPI_FLASH_WINBOND=y
 # Geralt
 #
 # CONFIG_BOARD_GOOGLE_GERALT is not set
+# CONFIG_BOARD_GOOGLE_CIRI is not set
 
 #
 # Glados
@@ -345,9 +355,9 @@ CONFIG_BOARD_GOOGLE_KEVIN=y
 #
 # Guybrush
 #
+# CONFIG_BOARD_GOOGLE_DEWATT is not set
 # CONFIG_BOARD_GOOGLE_GUYBRUSH is not set
 # CONFIG_BOARD_GOOGLE_NIPPERKIN is not set
-# CONFIG_BOARD_GOOGLE_DEWATT is not set
 
 #
 # Hatch
@@ -367,10 +377,15 @@ CONFIG_BOARD_GOOGLE_KEVIN=y
 #
 # Herobrine
 #
-
-#
-# (Herobrine requires 'Allow QC blobs repository')
-#
+# CONFIG_BOARD_GOOGLE_HEROBRINE is not set
+# CONFIG_BOARD_GOOGLE_HEROBRINE_REV0 is not set
+# CONFIG_BOARD_GOOGLE_SENOR is not set
+# CONFIG_BOARD_GOOGLE_PIGLIN is not set
+# CONFIG_BOARD_GOOGLE_HOGLIN is not set
+# CONFIG_BOARD_GOOGLE_VILLAGER is not set
+# CONFIG_BOARD_GOOGLE_EVOKER is not set
+# CONFIG_BOARD_GOOGLE_ZOGLIN is not set
+# CONFIG_BOARD_GOOGLE_ZOMBIE is not set
 
 #
 # Jecht
@@ -551,6 +566,8 @@ CONFIG_BOARD_GOOGLE_KEVIN=y
 # CONFIG_BOARD_GOOGLE_REX_EC_ISH is not set
 # CONFIG_BOARD_GOOGLE_OVIS is not set
 # CONFIG_BOARD_GOOGLE_OVIS4ES is not set
+# CONFIG_BOARD_GOOGLE_DEKU is not set
+# CONFIG_BOARD_GOOGLE_DEKU4ES is not set
 # CONFIG_BOARD_GOOGLE_REX4ES is not set
 # CONFIG_BOARD_GOOGLE_REX4ES_EC_ISH is not set
 
@@ -563,11 +580,11 @@ CONFIG_BOARD_GOOGLE_KEVIN=y
 #
 # Skyrim
 #
+# CONFIG_BOARD_GOOGLE_CRYSTALDRIFT is not set
+# CONFIG_BOARD_GOOGLE_FROSTFLOW is not set
+# CONFIG_BOARD_GOOGLE_MARKARTH is not set
 # CONFIG_BOARD_GOOGLE_SKYRIM is not set
 # CONFIG_BOARD_GOOGLE_WINTERHOLD is not set
-# CONFIG_BOARD_GOOGLE_FROSTFLOW is not set
-# CONFIG_BOARD_GOOGLE_CRYSTALDRIFT is not set
-# CONFIG_BOARD_GOOGLE_MARKARTH is not set
 
 #
 # Slippy
@@ -595,10 +612,19 @@ CONFIG_BOARD_GOOGLE_KEVIN=y
 #
 # Trogdor
 #
-
-#
-# (Trogdor requires 'Allow QC blobs repository')
-#
+# CONFIG_BOARD_GOOGLE_BUBS is not set
+# CONFIG_BOARD_GOOGLE_COACHZ is not set
+# CONFIG_BOARD_GOOGLE_GELARSHIE is not set
+# CONFIG_BOARD_GOOGLE_HOMESTAR is not set
+# CONFIG_BOARD_GOOGLE_KINGOFTOWN is not set
+# CONFIG_BOARD_GOOGLE_LAZOR is not set
+# CONFIG_BOARD_GOOGLE_MARZIPAN is not set
+# CONFIG_BOARD_GOOGLE_MRBLAND is not set
+# CONFIG_BOARD_GOOGLE_PAZQUEL is not set
+# CONFIG_BOARD_GOOGLE_POMPOM is not set
+# CONFIG_BOARD_GOOGLE_QUACKINGSTICK is not set
+# CONFIG_BOARD_GOOGLE_WORMDINGLER is not set
+# CONFIG_BOARD_GOOGLE_TROGDOR is not set
 
 #
 # Veyron
@@ -645,22 +671,21 @@ CONFIG_BOARD_GOOGLE_KEVIN=y
 #
 # Zork
 #
-# CONFIG_BOARD_GOOGLE_DALBOZ is not set
-# CONFIG_BOARD_GOOGLE_VILBOZ is not set
-# CONFIG_BOARD_GOOGLE_EZKINIL is not set
-# CONFIG_BOARD_GOOGLE_MORPHIUS is not set
-# CONFIG_BOARD_GOOGLE_TREMBYLE is not set
 # CONFIG_BOARD_GOOGLE_BERKNIP is not set
-# CONFIG_BOARD_GOOGLE_WOOMAX is not set
+# CONFIG_BOARD_GOOGLE_DALBOZ is not set
 # CONFIG_BOARD_GOOGLE_DIRINBOZ is not set
-# CONFIG_BOARD_GOOGLE_SHUBOZ is not set
+# CONFIG_BOARD_GOOGLE_EZKINIL is not set
 # CONFIG_BOARD_GOOGLE_GUMBOZ is not set
+# CONFIG_BOARD_GOOGLE_MORPHIUS is not set
+# CONFIG_BOARD_GOOGLE_SHUBOZ is not set
+# CONFIG_BOARD_GOOGLE_TREMBYLE is not set
+# CONFIG_BOARD_GOOGLE_VILBOZ is not set
+# CONFIG_BOARD_GOOGLE_WOOMAX is not set
 CONFIG_DRIVER_TPM_SPI_BUS=0x0
 CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS=0x5
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
 CONFIG_DRIVER_TPM_I2C_BUS=0x0
 CONFIG_DRIVER_TPM_I2C_ADDR=0x20
-CONFIG_VBT_DATA_SIZE_KB=8
 CONFIG_PMIC_BUS=-1
 CONFIG_BOARD_GOOGLE_GRU_COMMON=y
 # CONFIG_GRU_HAS_TPM2 is not set
@@ -675,7 +700,6 @@ CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_TTYS0_BAUD=115200
 CONFIG_D3COLD_SUPPORT=y
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_8192=y
@@ -690,6 +714,7 @@ CONFIG_COREBOOT_ROMSIZE_KB_8192=y
 # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
 CONFIG_COREBOOT_ROMSIZE_KB=8192
@@ -711,6 +736,7 @@ CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
 CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
+CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION=y
 CONFIG_GENERIC_UDELAY=y
 CONFIG_SOC_ROCKCHIP_RK3399=y
 # CONFIG_RK3399_SPREAD_SPECTRUM_DDR is not set
@@ -781,8 +807,6 @@ CONFIG_LINEAR_FRAMEBUFFER=y
 # CONFIG_BOOTSPLASH is not set
 # end of Display
 
-CONFIG_FIRMWARE_CONNECTION_MANAGER=y
-# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
 # CONFIG_SOFTWARE_I2C is not set
 CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
 CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
@@ -842,6 +866,7 @@ CONFIG_MAINBOARD_HAS_TPM1=y
 CONFIG_PCR_BOOT_MODE=1
 CONFIG_PCR_HWID=1
 CONFIG_PCR_SRTM=2
+CONFIG_PCR_FW_VER=10
 CONFIG_PCR_RUNTIME_DATA=3
 # end of Trusted Platform Module
 
@@ -862,6 +887,7 @@ CONFIG_ACPI_CUSTOM_MADT=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
+CONFIG_HEAP_SIZE=0x100000
 
 #
 # Console
@@ -920,6 +946,10 @@ CONFIG_PAYLOAD_NONE=y
 # CPU Debug Settings
 #
 
+#
+# Vendorcode Debug Settings
+#
+
 #
 # BLOB Debug Settings
 #

config/coreboot/i945/nuke.list

@@ -0,0 +1,47 @@
+3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_hotplug.c
+3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_mcdi.c
+3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_suspend.c
+3rdparty/arm-trusted-firmware/plat/rockchip/rk3368/drivers/ddr/rk3368_ddr_reg_resume_V1.05.bin
+3rdparty/chromeec/test/legacy_nvmem_dump.h
+3rdparty/chromeec/third_party/bmi260/accelgyro_bmi260_config_tbin.h
+3rdparty/vboot/tests/futility/data/bios_link_mp.bin
+3rdparty/vboot/tests/futility/data/bios_peppy_dev.bin
+3rdparty/vboot/tests/futility/data/bios_peppy_mp.bin
+src/coreboot/default/3rdparty/stm/Test/FrmPkg/Core/Init/Dmar.h
+src/coreboot/fam15h_rdimm/src/vendorcode/intel/fsp1_0/baytrail/absf/minnowmax_1gb.absf
+src/coreboot/fam15h_rdimm/src/vendorcode/intel/fsp1_0/baytrail/absf/minnowmax_2gb.absf
+src/coreboot/fam15h_udimm/src/vendorcode/intel/fsp1_0/baytrail/absf/minnowmax_1gb.absf
+src/coreboot/fam15h_udimm/src/vendorcode/intel/fsp1_0/baytrail/absf/minnowmax_2gb.absf
+src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_err.h
+src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gap.h
+src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gattc.h
+src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gatt.h
+src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gatts.h
+src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble.h
+src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_hci.h
+src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_l2cap.h
+src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_ranges.h
+src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_types.h
+src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf52/nrf_mbr.h
+src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_error.h
+src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_error_sdm.h
+src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_error_soc.h
+src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_nvic.h
+src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_sdm.h
+src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_soc.h
+src/pico-sdk/lib/tinyusb/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/nrf_svc.h
+src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbSmuFirmware.h
+src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c
+src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c
+src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000029.c
+src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000119.c
+src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h
+src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h
+src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600111F_Enc.c
+src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h
+src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFM2.h
+src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFS1.h
+src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c
+src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h
+src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSamuPatchKB.h
+src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSmuFirmwareKB.h

config/coreboot/i945/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch

@@ -0,0 +1,23 @@
+From 4d85316e931a83ccf4929551c1d200d80d1d3c3d Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@retroboot.org>
+Date: Fri, 19 Mar 2021 05:54:58 +0000
+Subject: [PATCH 01/10] apple/macbook21: Set default VRAM to 64MiB instead of
+ 8MiB
+
+---
+ src/mainboard/apple/macbook21/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default
+index cf1bc4566e..dc0df3b6d6 100644
+--- a/src/mainboard/apple/macbook21/cmos.default
++++ b/src/mainboard/apple/macbook21/cmos.default
+@@ -5,4 +5,4 @@ boot_devices=''
+ boot_default=0x40
+ cmos_defaults_loaded=Yes
+ lpt=Enable
+-gfx_uma_size=8M
++gfx_uma_size=64M
+-- 
+2.39.2
+

config/coreboot/i945/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch

@@ -0,0 +1,68 @@
+From 6663cf5197c5eb8034e7bc6048fda6183674816e Mon Sep 17 00:00:00 2001
+From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com>
+Date: Wed, 27 Oct 2021 13:36:01 +0200
+Subject: [PATCH 02/10] add c3 and clockgen to apple/macbook21
+
+---
+ src/mainboard/apple/macbook21/Kconfig       |  1 +
+ src/mainboard/apple/macbook21/cstates.c     | 13 +++++++++++++
+ src/mainboard/apple/macbook21/devicetree.cb |  6 ++++++
+ 3 files changed, 20 insertions(+)
+
+diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig
+index 5f5ffde588..27377b737c 100644
+--- a/src/mainboard/apple/macbook21/Kconfig
++++ b/src/mainboard/apple/macbook21/Kconfig
+@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS
+ 	select HAVE_ACPI_TABLES
+ 	select HAVE_ACPI_RESUME
+ 	select I945_LVDS
++	select DRIVERS_I2C_CK505
+ 
+ config MAINBOARD_DIR
+ 	default "apple/macbook21"
+diff --git a/src/mainboard/apple/macbook21/cstates.c b/src/mainboard/apple/macbook21/cstates.c
+index 13d06f0839..88b8669c61 100644
+--- a/src/mainboard/apple/macbook21/cstates.c
++++ b/src/mainboard/apple/macbook21/cstates.c
+@@ -29,6 +29,19 @@ static const acpi_cstate_t cst_entries[] = {
+ 			.addrh = 0,
+ 		}
+ 	},
++	{
++		.ctype = 3,
++		.latency = 17,
++		.power = 250,
++		.resource = {
++			.space_id = ACPI_ADDRESS_SPACE_FIXED,
++			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
++			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
++			.access_size = ACPI_ACCESS_SIZE_UNDEFINED,
++			.addrl = 0x20,
++			.addrh = 0,
++		}
++	},
+ };
+ 
+ int get_cst_entries(const acpi_cstate_t **entries)
+diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb
+index dd701da7ed..5587c48d1f 100644
+--- a/src/mainboard/apple/macbook21/devicetree.cb
++++ b/src/mainboard/apple/macbook21/devicetree.cb
+@@ -100,7 +100,13 @@ chip northbridge/intel/i945
+ 			end
+ 			device pci 1f.3 on # SMBUS
+ 				subsystemid 0x8086 0x7270
++				chip drivers/i2c/ck505
++					register "mask" = "{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }"
++					register "regs" = "{ 0x77, 0x77, 0x2d, 0x00, 0x21, 0x10, 0x3b, 0x06, 0x07, 0x0f, 0xf0, 0x01, 0x1e, 0x7f, 0x80, 0x80, 0x10, 0x08, 0x04, 0x01 }"
++					device i2c 69 on end
++				end
+ 			end
++
+ 		end
+ 	end
+ end
+-- 
+2.39.2
+

config/coreboot/i945/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch

@@ -0,0 +1,23 @@
+From d3c5a8dfd1965b241fe07fb505e63692512c147d Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@osboot.org>
+Date: Sun, 3 Jan 2021 03:34:01 +0000
+Subject: [PATCH 03/10] lenovo/x60: 64MiB Video RAM changed to default
+ (previously it was 8MiB)
+
+---
+ src/mainboard/lenovo/x60/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default
+index 5c3576d1f3..88170a1aab 100644
+--- a/src/mainboard/lenovo/x60/cmos.default
++++ b/src/mainboard/lenovo/x60/cmos.default
+@@ -15,4 +15,4 @@ trackpoint=Enable
+ sticky_fn=Disable
+ power_management_beeps=Enable
+ low_battery_beep=Enable
+-gfx_uma_size=8M
++gfx_uma_size=64M
+-- 
+2.39.2
+

config/coreboot/i945/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch

@@ -0,0 +1,22 @@
+From db5eb56166860265dd2f7ecb4af89a5ca95d02c8 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@osboot.org>
+Date: Mon, 22 Feb 2021 22:16:59 +0000
+Subject: [PATCH 04/10] lenovo/t60: make 64MiB VRAM the default in cmos.default
+
+---
+ src/mainboard/lenovo/t60/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/lenovo/t60/cmos.default b/src/mainboard/lenovo/t60/cmos.default
+index af865f16da..7f03157df7 100644
+--- a/src/mainboard/lenovo/t60/cmos.default
++++ b/src/mainboard/lenovo/t60/cmos.default
+@@ -15,4 +15,4 @@ trackpoint=Enable
+ sticky_fn=Disable
+ power_management_beeps=Enable
+ low_battery_beep=Enable
+-gfx_uma_size=8M
++gfx_uma_size=64M
+-- 
+2.39.2
+

config/coreboot/i945/patches/0005-buildgcc-use-mirrorservice-for-gnu-toolchains.patch

@@ -0,0 +1,34 @@
+From 42db605ad6a12153c7659c204ca77a741dced59c Mon Sep 17 00:00:00 2001
+From: Leah Rowe <info@minifree.org>
+Date: Fri, 26 Apr 2024 09:16:57 +0100
+Subject: [PATCH 05/10] buildgcc: use mirrorservice for gnu toolchains
+
+Signed-off-by: Leah Rowe <info@minifree.org>
+---
+ util/crossgcc/buildgcc | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
+index 0de27ed6e8..0faea86894 100755
+--- a/util/crossgcc/buildgcc
++++ b/util/crossgcc/buildgcc
+@@ -66,11 +66,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2"
+ # to the jenkins build as well, or the builder won't download it.
+ 
+ # GCC toolchain archive locations
+-GMP_BASE_URL="https://ftpmirror.gnu.org/gmp"
+-MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
+-MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
+-GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
+-BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
++GMP_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp"
++MPFR_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr"
++MPC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc"
++GCC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}"
++BINUTILS_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils"
+ IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags"
+ # CLANG toolchain archive locations
+ LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
+-- 
+2.39.2
+

config/coreboot/i945/patches/0006-drivers-pc80-rtc-option.c-Stop-resetting-CMOS-during.patch

@@ -0,0 +1,56 @@
+From 539ea838d5aa0a51dcc518ec8b0ad1ad2b51c2ea Mon Sep 17 00:00:00 2001
+From: Bill XIE <persmule@hardenedlinux.org>
+Date: Sat, 7 Oct 2023 01:32:51 +0800
+Subject: [PATCH 06/10] drivers/pc80/rtc/option.c: Stop resetting CMOS during
+ s3 resume
+
+After commit e12b313844da ("drivers/pc80/rtc/option.c: Allow CMOS
+defaults to extend to bank 1"), Thinkpad X200 with
+CONFIG(STATIC_OPTION_TABLE) can no longer resume from s3 (detected via
+bisect).
+
+Further inspection shows that DRAM training result of GM45 is stored
+in CMOS above 128 bytes in raminit_read_write_training.c, for s3 resume
+to restore, but it will be erased by sanitize_cmos(), which now clears
+both bank 0 and bank 1, leaving only "untrained" result restored, so s3
+resume will fail.
+
+However, resetting CMOS seems unnecessary during s3 resume. Now,
+cmos_need_reset will be negated when acpi_is_wakeup_s3() returns true.
+
+Tested: Thinkpad X200 with CONFIG(STATIC_OPTION_TABLE) can resume from
+	s3 again with these changes.
+
+Change-Id: I533e83f3b95f327b0e24f4d750f8812325b7770b
+Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
+Reviewed-on: https://review.coreboot.org/c/coreboot/+/78288
+Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
+Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
+---
+ src/drivers/pc80/rtc/option.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c
+index e8e2345133..e6cfa175ad 100644
+--- a/src/drivers/pc80/rtc/option.c
++++ b/src/drivers/pc80/rtc/option.c
+@@ -1,5 +1,6 @@
+ /* SPDX-License-Identifier: GPL-2.0-only */
+ 
++#include <acpi/acpi.h>
+ #include <console/console.h>
+ #include <string.h>
+ #include <cbfs.h>
+@@ -200,7 +201,8 @@ void sanitize_cmos(void)
+ {
+ 	const unsigned char *cmos_default;
+ 	const bool cmos_need_reset =
+-		CONFIG(STATIC_OPTION_TABLE) || cmos_error() || !cmos_lb_cks_valid();
++		(CONFIG(STATIC_OPTION_TABLE) || cmos_error() || !cmos_lb_cks_valid())
++		&& !acpi_is_wakeup_s3();
+ 	size_t length = 128;
+ 	size_t i;
+ 
+-- 
+2.39.2
+

config/coreboot/i945/patches/0007-drivers-pc80-rtc-option.c-Reset-only-CMOS-range-cove.patch

@@ -0,0 +1,51 @@
+From 8d00bf577d12c9d64595ca2cd1ceec6f49bd57a4 Mon Sep 17 00:00:00 2001
+From: Bill XIE <persmule@hardenedlinux.org>
+Date: Fri, 3 Nov 2023 12:34:01 +0800
+Subject: [PATCH 07/10] drivers/pc80/rtc/option.c: Reset only CMOS range
+ covered by checksum
+
+Proposed in the comment of commit 29030d0f3dad
+("drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume"),
+during sanitize_cmos(), only reset CMOS range covered by checksum and
+the checksum itself from the file cmos.default in CBFS, in order to
+prevent other runtime data in CMOS (e.g. the DRAM training data on
+GM45 platforms for s3 resume) being erased.
+
+Tested: cherry-pick this commit before commit 44a48ce7a46c ("Kconfig:
+	Bring HEAP_SIZE to a common, large value"), which is already
+	before my commit 29030d0f3dad , Thinkpad X200 with
+	CONFIG(STATIC_OPTION_TABLE) can resume from s3 again,
+	indicating that DRAM training data are no longer erased.
+
+Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
+Co-authored-by: Jonathon Hall <jonathon.hall@puri.sm>
+Change-Id: I872bf5f41422bc3424cd8631e932aaae2ae82f7a
+Reviewed-on: https://review.coreboot.org/c/coreboot/+/78906
+Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
+Reviewed-by: Nico Huber <nico.h@gmx.de>
+Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
+---
+ src/drivers/pc80/rtc/option.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c
+index e6cfa175ad..cb18e14ae9 100644
+--- a/src/drivers/pc80/rtc/option.c
++++ b/src/drivers/pc80/rtc/option.c
+@@ -213,8 +213,12 @@ void sanitize_cmos(void)
+ 			return;
+ 
+ 		u8 control_state = cmos_disable_rtc();
+-		for (i = 14; i < MIN(128, length); i++)
++		/* Copy checked range and the checksum from the default */
++		for (i = LB_CKS_RANGE_START; i < MIN(LB_CKS_RANGE_END + 1, length); i++)
+ 			cmos_write_inner(cmos_default[i], i);
++		/* CMOS checksum takes 2 bytes */
++		cmos_write_inner(cmos_default[LB_CKS_LOC], LB_CKS_LOC);
++		cmos_write_inner(cmos_default[LB_CKS_LOC + 1], LB_CKS_LOC + 1);
+ 		cmos_restore_rtc(control_state);
+ 	}
+ }
+-- 
+2.39.2
+

config/coreboot/i945/patches/0008-Remove-warning-for-coreboot-images-built-without-a-p.patch

@@ -1,7 +1,7 @@
-From 7d5452bc3358cf82eea48fde312494bcb4ca8101 Mon Sep 17 00:00:00 2001
+From 7686b9576cb5b1464c74c0a4ce4fb9044caea932 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Fri, 12 May 2023 19:55:15 -0600
-Subject: [PATCH 19/22] Remove warning for coreboot images built without a
+Subject: [PATCH 08/10] Remove warning for coreboot images built without a
  payload
 
 I added this in upstream to prevent people from accidentally flashing

config/coreboot/i945/patches/0009-use-mirrorservice.org-for-iasl-downloads.patch

@@ -0,0 +1,28 @@
+From f4d1d81877bc1720a9af76b0b03bc80d077f7ede Mon Sep 17 00:00:00 2001
+From: Leah Rowe <info@minifree.org>
+Date: Sun, 28 Apr 2024 01:59:30 +0100
+Subject: [PATCH 09/10] use mirrorservice.org for iasl downloads
+
+github is unreliable. i mirror these files myself.
+
+Signed-off-by: Leah Rowe <info@minifree.org>
+---
+ util/crossgcc/buildgcc | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
+index 0faea86894..6779a20425 100755
+--- a/util/crossgcc/buildgcc
++++ b/util/crossgcc/buildgcc
+@@ -71,7 +71,7 @@ MPFR_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr"
+ MPC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc"
+ GCC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}"
+ BINUTILS_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils"
+-IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags"
++IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
+ # CLANG toolchain archive locations
+ LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
+ CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
+-- 
+2.39.2
+

config/coreboot/i945/patches/0010-never-add-microcode-updates-even-if-told-to.patch

@@ -1,9 +1,11 @@
-From eaec1bbb21283fa409a2d1610688c05a62c7b1bc Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Thu, 12 Oct 2023 01:20:23 +0100
-Subject: [PATCH 1/1] never enable cpu microcode, even if told to
+From fd7e1a29eb14d4387adfaac63034ed144eb103d7 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <info@minifree.org>
+Date: Fri, 3 May 2024 05:33:41 +0100
+Subject: [PATCH 10/10] never add microcode updates, even if told to
 
-Signed-off-by: Leah Rowe <leah@libreboot.org>
+because gnu free system distribution guidelines
+
+Signed-off-by: Leah Rowe <info@minifree.org>
 ---
  src/cpu/Makefile.inc           | 55 ----------------------------------
  src/cpu/intel/fit/Makefile.inc | 31 -------------------
@@ -76,7 +78,7 @@ index 12c682d43d..e5fb13b33d 100644
  cpu_microcode_blob.bin-COREBOOT-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC)
  endif
 diff --git a/src/cpu/intel/fit/Makefile.inc b/src/cpu/intel/fit/Makefile.inc
-index da4549e5d1..c31102872e 100644
+index d3f12e43e6..c31102872e 100644
 --- a/src/cpu/intel/fit/Makefile.inc
 +++ b/src/cpu/intel/fit/Makefile.inc
 @@ -17,35 +17,4 @@ $(call add_intermediate, set_fit_ptr, $(IFITTOOL))
@@ -85,7 +87,7 @@ index da4549e5d1..c31102872e 100644
  
 -ifneq ($(CONFIG_UPDATE_IMAGE),y) # never update the bootblock
 -
--ifneq ($(CONFIG_CPU_MICROCODE_CBFS_NONE)$(CONFIG_CPU_INTEL_MICROCODE_CBFS_SPLIT_BINS),y)
+-ifneq ($(CONFIG_CPU_MICROCODE_CBFS_NONE),y)
 -
 -$(call add_intermediate, add_mcu_fit, set_fit_ptr $(IFITTOOL))
 -	@printf "    UPDATE-FIT Microcode\n"

config/coreboot/i945/patches/0011-never-download-blobs-even-if-USE_BLOBS-y.patch

@@ -0,0 +1,54 @@
+From 72a2762b7b7cadac1dfd628a908af17fb907df9c Mon Sep 17 00:00:00 2001
+From: Leah Rowe <info@minifree.org>
+Date: Fri, 3 May 2024 06:33:05 +0100
+Subject: [PATCH 1/1] never download blobs even if USE_BLOBS=y
+
+With this and the existing never-add-microcode patch,
+I can re-use lbmk coreboot configs without modifying them.
+
+I already don't disable microcode in those configs when
+porting them to canoeboot, because Canoeboot modifies
+coreboot to never download/handle microcode, even when
+microcode is enabled in a coreboot config.
+
+This patch does the same thing, but for disabling the download
+of 3rdparty blob repositories.
+
+Therefore, I can now keep canoeboot's coreboot configs more
+closely in sync with those of Libreboot, reducing the
+maintenance burden for each Canoeboot release.
+
+Signed-off-by: Leah Rowe <info@minifree.org>
+---
+ Makefile.inc | 15 ---------------
+ 1 file changed, 15 deletions(-)
+
+diff --git a/Makefile.inc b/Makefile.inc
+index 96121d4019..6e8f7ec581 100644
+--- a/Makefile.inc
++++ b/Makefile.inc
+@@ -199,21 +199,6 @@ $(info Updating git submodules.)
+ forgetthis:=$(shell git submodule update --init $(quiet_errors))
+ # Checkout Cmocka repository
+ forgetthis:=$(shell git submodule update --init --checkout 3rdparty/cmocka $(quiet_errors))
+-ifeq ($(CONFIG_USE_BLOBS),y)
+-# These items are necessary because each has update=none in .gitmodules.  They are ignored
+-# until expressly requested and enabled with --checkout
+-forgetthis:=$(shell git submodule update --init --checkout 3rdparty/blobs $(quiet_errors))
+-forgetthis:=$(shell git submodule update --init --checkout 3rdparty/intel-microcode $(quiet_errors))
+-ifeq ($(CONFIG_FSP_USE_REPO),y)
+-forgetthis:=$(shell git submodule update --init --checkout 3rdparty/fsp $(quiet_errors))
+-endif
+-ifeq ($(CONFIG_USE_AMD_BLOBS),y)
+-forgetthis:=$(shell git submodule update --init --checkout 3rdparty/amd_blobs $(quiet_errors))
+-endif
+-ifeq ($(CONFIG_USE_QC_BLOBS),y)
+-forgetthis:=$(shell git submodule update --init --checkout 3rdparty/qc_blobs $(quiet_errors))
+-endif
+-endif
+ UPDATED_SUBMODULES:=1
+ COREBOOT_EXPORTS += UPDATED_SUBMODULES
+ 
+-- 
+2.39.2
+