174 lines
5.7 KiB
Diff
174 lines
5.7 KiB
Diff
From fdde15b69bd5c8bf54339adf3581a32fa992a503 Mon Sep 17 00:00:00 2001
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From: Leah Rowe <leah@libreboot.org>
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Date: Mon, 17 Apr 2023 15:49:57 +0100
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Subject: [PATCH 17/22] GM45-type CPUs: don't enable alternative SMRR
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This reverts the changes in coreboot revision:
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df7aecd92643d207feaf7fd840f8835097346644
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While this fix is *technically correct*, the one in
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coreboot, it breaks rebooting as tested on several
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GM45 ThinkPads e.g. X200, T400, when microcode
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updates are not applied.
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Since November 2022, Libreboot includes microcode
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updates by default, but it tells users how to remove
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it from the ROM (with cbfstool) if they wish.
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Well, with Libreboot 20221214, 20230319 and 20230413,
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mitigations present in Libreboot 20220710 (which did
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not have microcode updates) do not exist.
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This patch, along with the other patch to remove PECI
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support (which breaks speedstep when microcode updates
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are not applied) have now been re-added to Libreboot.
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It is still best to use microcode updates by default.
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These patches in coreboot are not critically urgent,
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and you can use the machines with or without them,
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regardless of ucode.
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I'll probably re-write this and the other patch at
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some point, applying the change conditionally upon
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whether or not microcode is applied.
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Pragmatism is a good thing. I recommend it.
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---
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src/cpu/intel/model_1067x/model_1067x_init.c | 4 +++
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src/cpu/intel/model_1067x/mp_init.c | 26 --------------------
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src/cpu/intel/model_106cx/model_106cx_init.c | 4 +++
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src/cpu/intel/model_6ex/model_6ex_init.c | 4 +++
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src/cpu/intel/model_6fx/model_6fx_init.c | 4 +++
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5 files changed, 16 insertions(+), 26 deletions(-)
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diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
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index 1423fd72bc..d1f98ca43a 100644
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--- a/src/cpu/intel/model_1067x/model_1067x_init.c
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+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
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@@ -8,6 +8,7 @@
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#include <cpu/x86/cache.h>
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#include <cpu/x86/name.h>
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#include <cpu/intel/smm_reloc.h>
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+#include <cpu/intel/common/common.h>
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#define MSR_BBL_CR_CTL3 0x11e
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@@ -234,6 +235,9 @@ static void model_1067x_init(struct device *cpu)
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fill_processor_name(processor_name);
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printk(BIOS_INFO, "CPU: %s.\n", processor_name);
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+ /* Set virtualization based on Kconfig option */
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+ set_vmx_and_lock();
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+
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/* Configure C States */
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configure_c_states(quad);
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diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
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index bc53214310..72f40f6762 100644
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--- a/src/cpu/intel/model_1067x/mp_init.c
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+++ b/src/cpu/intel/model_1067x/mp_init.c
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@@ -43,34 +43,8 @@ static void pre_mp_smm_init(void)
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smm_initialize();
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}
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-#define SMRR_SUPPORTED (1 << 11)
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-
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static void per_cpu_smm_trigger(void)
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{
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- msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
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- if (cpu_has_alternative_smrr() && mtrr_cap.lo & SMRR_SUPPORTED) {
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- set_feature_ctrl_vmx();
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- msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL);
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- /* We don't care if the lock is already setting
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- as our smm relocation handler is able to handle
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- setups where SMRR is not enabled here. */
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- if (ia32_ft_ctrl.lo & (1 << 0)) {
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- /* IA32_FEATURE_CONTROL locked. If we set it again we
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- get an illegal instruction. */
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- printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n");
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- printk(BIOS_DEBUG, "SMRR status: %senabled\n",
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- ia32_ft_ctrl.lo & (1 << 3) ? "" : "not ");
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- } else {
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- if (!CONFIG(SET_IA32_FC_LOCK_BIT))
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- printk(BIOS_INFO,
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- "Overriding CONFIG(SET_IA32_FC_LOCK_BIT) to enable SMRR\n");
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- ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0);
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- wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl);
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- }
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- } else {
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- set_vmx_and_lock();
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- }
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-
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/* Relocate the SMM handler. */
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smm_relocate();
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}
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diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
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index 05f5f327cc..0450c2ad83 100644
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--- a/src/cpu/intel/model_106cx/model_106cx_init.c
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+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
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@@ -7,6 +7,7 @@
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#include <cpu/intel/speedstep.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/name.h>
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+#include <cpu/intel/common/common.h>
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#define HIGHEST_CLEVEL 3
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static void configure_c_states(void)
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@@ -66,6 +67,9 @@ static void model_106cx_init(struct device *cpu)
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fill_processor_name(processor_name);
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printk(BIOS_INFO, "CPU: %s.\n", processor_name);
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+ /* Set virtualization based on Kconfig option */
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+ set_vmx_and_lock();
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+
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/* Configure C States */
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configure_c_states();
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diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
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index 5bd1c32815..f3bb08cde3 100644
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--- a/src/cpu/intel/model_6ex/model_6ex_init.c
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+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
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@@ -7,6 +7,7 @@
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#include <cpu/intel/speedstep.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/name.h>
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+#include <cpu/intel/common/common.h>
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#define HIGHEST_CLEVEL 3
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static void configure_c_states(void)
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@@ -105,6 +106,9 @@ static void model_6ex_init(struct device *cpu)
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/* Setup Page Attribute Tables (PAT) */
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// TODO set up PAT
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+ /* Set virtualization based on Kconfig option */
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+ set_vmx_and_lock();
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+
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/* Configure C States */
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configure_c_states();
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diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
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index 535fb8fae7..f7b05facd2 100644
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--- a/src/cpu/intel/model_6fx/model_6fx_init.c
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+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
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@@ -7,6 +7,7 @@
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#include <cpu/intel/speedstep.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/name.h>
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+#include <cpu/intel/common/common.h>
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#define HIGHEST_CLEVEL 3
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static void configure_c_states(void)
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@@ -118,6 +119,9 @@ static void model_6fx_init(struct device *cpu)
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/* Setup Page Attribute Tables (PAT) */
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// TODO set up PAT
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+ /* Set virtualization based on Kconfig option */
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+ set_vmx_and_lock();
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+
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/* Configure C States */
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configure_c_states();
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--
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2.39.2
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