32 lines
1.3 KiB
Diff
32 lines
1.3 KiB
Diff
From 8f2988cba4fffef1bd4f65e123c76bf4b7a18672 Mon Sep 17 00:00:00 2001
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From: "D.d.P.F. Lombard" <lombard@lombards.xyz>
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Date: Sun, 7 Feb 2021 15:29:40 +0100
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Subject: [PATCH 1/6] Revert "Revert "nb/amd/mct_ddr3: Fix RDIMM training
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failure on Fam15h" (fixes a bug that prevent certain RAM modules from
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booting)
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This reverts commit 610d1c67b2298a9840681c2b4492b6d3fdf44a46.
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After 610d1c67b2298a9840681c2b4492b6d3fdf44a46 many RAM modules wouldn't work and you couldn't even see any output on the screen.
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---
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src/northbridge/amd/amdmct/mct_ddr3/mctproc.c | 3 +++
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1 file changed, 3 insertions(+)
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diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
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index ddaaaab8d5..3b07786b91 100644
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--- a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
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+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
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@@ -71,6 +71,9 @@ u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat,
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misc2 |= ((cs_mux_67 & 0x1) << 27);
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misc2 &= ~(0x1 << 26); /* CsMux45 = cs_mux_45 */
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misc2 |= ((cs_mux_45 & 0x1) << 26);
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+
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+ if (pDCTstat->Status & (1 << SB_Registered))
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+ misc2 |= 1 << SubMemclkRegDly;
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} else if (pDCTstat->LogicalCPUID & (AMD_DR_Dx | AMD_DR_Cx)) {
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if (pDCTstat->Status & (1 << SB_Registered)) {
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misc2 |= 1 << SubMemclkRegDly;
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--
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2.25.1
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