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gnu: yosys: Add xdot functionality.

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* gnu/packages/fpga.scm (yosys)[inputs]: Add xdot, graphviz and psmisc.
[arguments]: Add 'fix-paths' phase.

Signed-off-by: Leo Famulari <leo@famulari.name>
This commit is contained in:
Theodoros Foradis 2016-11-26 16:27:57 +02:00 committed by Leo Famulari
parent abdd28e8c1
commit f90f6b683e
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1 changed files with 13 additions and 1 deletions
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14
gnu/packages/fpga.scm
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@ -1,5 +1,6 @@
;;; GNU Guix --- Functional package management for GNU
;;; Copyright © 2016 Danny Milosavljevic <dannym@scratchpost.org>
;;; Copyright © 2016 Theodoros Foradis <theodoros.for@openmailbox.org>
;;;
;;; This file is part of GNU Guix.
;;;
@ -31,7 +32,9 @@
#:use-module (gnu packages bison)
#:use-module (gnu packages flex)
#:use-module (gnu packages gtk)
#:use-module (gnu packages graphviz)
#:use-module (gnu packages libffi)
#:use-module (gnu packages linux)
#:use-module (gnu packages zip)
#:use-module (gnu packages perl)
#:use-module (gnu packages ghostscript)
@ -136,6 +139,13 @@ For synthesis, the compiler generates netlists in the desired format.")
(string-append "PREFIX=" %output))
#:phases
(modify-phases %standard-phases
(add-before 'configure 'fix-paths
(lambda _
(substitute* "./passes/cmds/show.cc"
(("exec xdot") (string-append "exec " (which "xdot")))
(("dot -") (string-append (which "dot") " -"))
(("fuser") (which "fuser")))
#t))
(replace 'configure
(lambda* (#:key inputs (make-flags '()) #:allow-other-keys)
(zero? (apply system* "make" "config-gcc" make-flags))))
@ -172,7 +182,6 @@ For synthesis, the compiler generates netlists in the desired format.")
(("iverilog_bin=\".*\"") (string-append "iverilog_bin=\""
iverilog "\"")))
#t))))))
;; TODO add xdot [patch the path to it here] as soon as I find out where it is.
(native-inputs
`(("pkg-config" ,pkg-config)
("python" ,python)
@ -185,6 +194,9 @@ For synthesis, the compiler generates netlists in the desired format.")
`(("tcl" ,tcl)
("readline" ,readline)
("libffi" ,libffi)
("graphviz" ,graphviz)
("psmisc" ,psmisc)
("xdot" ,xdot)
("abc" ,abc)))
(home-page "http://www.clifford.at/yosys/")
(synopsis "FPGA Verilog RTL synthesizer")