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* gnu/packages/patches/qemu-CVE-2015-4037.patch, gnu/packages/patches/qemu-CVE-2015-4103.patch, gnu/packages/patches/qemu-CVE-2015-4104.patch, gnu/packages/patches/qemu-CVE-2015-4105.patch, gnu/packages/patches/qemu-CVE-2015-4106-pt1.patch, gnu/packages/patches/qemu-CVE-2015-4106-pt2.patch, gnu/packages/patches/qemu-CVE-2015-4106-pt3.patch, gnu/packages/patches/qemu-CVE-2015-4106-pt4.patch, gnu/packages/patches/qemu-CVE-2015-4106-pt5.patch, gnu/packages/patches/qemu-CVE-2015-4106-pt6.patch, gnu/packages/patches/qemu-CVE-2015-4106-pt7.patch, gnu/packages/patches/qemu-CVE-2015-4106-pt8.patch: New files. * gnu-system.am (dist_patch_DATA): Add them. * gnu/packages/qemu.scm (qemu-headless)[source]: Add patches.
189 lines
6.9 KiB
Diff
189 lines
6.9 KiB
Diff
From 7611dae8a69f0f1775ba1a9a942961c2aa10d88e Mon Sep 17 00:00:00 2001
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From: Jan Beulich <jbeulich@suse.com>
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Date: Tue, 2 Jun 2015 15:07:00 +0000
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Subject: [PATCH] xen: don't allow guest to control MSI mask register
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It's being used by the hypervisor. For now simply mimic a device not
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capable of masking, and fully emulate any accesses a guest may issue
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nevertheless as simple reads/writes without side effects.
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This is XSA-129.
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Signed-off-by: Jan Beulich <jbeulich@suse.com>
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Reviewed-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
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---
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hw/pci/msi.c | 4 --
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hw/xen/xen_pt_config_init.c | 98 ++++++++++++++++++++++++++++++++++++++++-----
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include/hw/pci/pci_regs.h | 2 +
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3 files changed, 90 insertions(+), 14 deletions(-)
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diff --git a/hw/pci/msi.c b/hw/pci/msi.c
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index c111dba..f9c0484 100644
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--- a/hw/pci/msi.c
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+++ b/hw/pci/msi.c
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@@ -21,10 +21,6 @@
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#include "hw/pci/msi.h"
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#include "qemu/range.h"
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-/* Eventually those constants should go to Linux pci_regs.h */
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-#define PCI_MSI_PENDING_32 0x10
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-#define PCI_MSI_PENDING_64 0x14
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-
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/* PCI_MSI_ADDRESS_LO */
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#define PCI_MSI_ADDRESS_LO_MASK (~0x3)
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diff --git a/hw/xen/xen_pt_config_init.c b/hw/xen/xen_pt_config_init.c
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index dae0519..68b8f22 100644
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--- a/hw/xen/xen_pt_config_init.c
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+++ b/hw/xen/xen_pt_config_init.c
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@@ -1016,13 +1016,9 @@ static XenPTRegInfo xen_pt_emu_reg_pm[] = {
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*/
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/* Helper */
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-static bool xen_pt_msgdata_check_type(uint32_t offset, uint16_t flags)
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-{
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- /* check the offset whether matches the type or not */
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- bool is_32 = (offset == PCI_MSI_DATA_32) && !(flags & PCI_MSI_FLAGS_64BIT);
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- bool is_64 = (offset == PCI_MSI_DATA_64) && (flags & PCI_MSI_FLAGS_64BIT);
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- return is_32 || is_64;
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-}
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+#define xen_pt_msi_check_type(offset, flags, what) \
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+ ((offset) == ((flags) & PCI_MSI_FLAGS_64BIT ? \
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+ PCI_MSI_##what##_64 : PCI_MSI_##what##_32))
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/* Message Control register */
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static int xen_pt_msgctrl_reg_init(XenPCIPassthroughState *s,
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@@ -1134,7 +1130,45 @@ static int xen_pt_msgdata_reg_init(XenPCIPassthroughState *s,
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uint32_t offset = reg->offset;
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/* check the offset whether matches the type or not */
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- if (xen_pt_msgdata_check_type(offset, flags)) {
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+ if (xen_pt_msi_check_type(offset, flags, DATA)) {
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+ *data = reg->init_val;
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+ } else {
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+ *data = XEN_PT_INVALID_REG;
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+ }
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+ return 0;
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+}
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+
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+/* this function will be called twice (for 32 bit and 64 bit type) */
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+/* initialize Mask register */
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+static int xen_pt_mask_reg_init(XenPCIPassthroughState *s,
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+ XenPTRegInfo *reg, uint32_t real_offset,
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+ uint32_t *data)
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+{
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+ uint32_t flags = s->msi->flags;
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+
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+ /* check the offset whether matches the type or not */
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+ if (!(flags & PCI_MSI_FLAGS_MASKBIT)) {
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+ *data = XEN_PT_INVALID_REG;
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+ } else if (xen_pt_msi_check_type(reg->offset, flags, MASK)) {
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+ *data = reg->init_val;
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+ } else {
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+ *data = XEN_PT_INVALID_REG;
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+ }
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+ return 0;
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+}
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+
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+/* this function will be called twice (for 32 bit and 64 bit type) */
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+/* initialize Pending register */
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+static int xen_pt_pending_reg_init(XenPCIPassthroughState *s,
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+ XenPTRegInfo *reg, uint32_t real_offset,
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+ uint32_t *data)
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+{
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+ uint32_t flags = s->msi->flags;
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+
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+ /* check the offset whether matches the type or not */
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+ if (!(flags & PCI_MSI_FLAGS_MASKBIT)) {
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+ *data = XEN_PT_INVALID_REG;
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+ } else if (xen_pt_msi_check_type(reg->offset, flags, PENDING)) {
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*data = reg->init_val;
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} else {
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*data = XEN_PT_INVALID_REG;
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@@ -1222,7 +1256,7 @@ static int xen_pt_msgdata_reg_write(XenPCIPassthroughState *s,
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uint32_t offset = reg->offset;
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/* check the offset whether matches the type or not */
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- if (!xen_pt_msgdata_check_type(offset, msi->flags)) {
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+ if (!xen_pt_msi_check_type(offset, msi->flags, DATA)) {
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/* exit I/O emulator */
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XEN_PT_ERR(&s->dev, "the offset does not match the 32/64 bit type!\n");
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return -1;
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@@ -1267,7 +1301,7 @@ static XenPTRegInfo xen_pt_emu_reg_msi[] = {
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.size = 2,
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.init_val = 0x0000,
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.ro_mask = 0xFF8E,
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- .emu_mask = 0x007F,
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+ .emu_mask = 0x017F,
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.init = xen_pt_msgctrl_reg_init,
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.u.w.read = xen_pt_word_reg_read,
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.u.w.write = xen_pt_msgctrl_reg_write,
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@@ -1316,6 +1350,50 @@ static XenPTRegInfo xen_pt_emu_reg_msi[] = {
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.u.w.read = xen_pt_word_reg_read,
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.u.w.write = xen_pt_msgdata_reg_write,
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},
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+ /* Mask reg (if PCI_MSI_FLAGS_MASKBIT set, for 32-bit devices) */
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+ {
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+ .offset = PCI_MSI_MASK_32,
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+ .size = 4,
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+ .init_val = 0x00000000,
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+ .ro_mask = 0xFFFFFFFF,
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+ .emu_mask = 0xFFFFFFFF,
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+ .init = xen_pt_mask_reg_init,
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+ .u.dw.read = xen_pt_long_reg_read,
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+ .u.dw.write = xen_pt_long_reg_write,
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+ },
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+ /* Mask reg (if PCI_MSI_FLAGS_MASKBIT set, for 64-bit devices) */
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+ {
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+ .offset = PCI_MSI_MASK_64,
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+ .size = 4,
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+ .init_val = 0x00000000,
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+ .ro_mask = 0xFFFFFFFF,
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+ .emu_mask = 0xFFFFFFFF,
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+ .init = xen_pt_mask_reg_init,
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+ .u.dw.read = xen_pt_long_reg_read,
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+ .u.dw.write = xen_pt_long_reg_write,
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+ },
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+ /* Pending reg (if PCI_MSI_FLAGS_MASKBIT set, for 32-bit devices) */
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+ {
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+ .offset = PCI_MSI_MASK_32 + 4,
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+ .size = 4,
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+ .init_val = 0x00000000,
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+ .ro_mask = 0xFFFFFFFF,
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+ .emu_mask = 0x00000000,
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+ .init = xen_pt_pending_reg_init,
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+ .u.dw.read = xen_pt_long_reg_read,
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+ .u.dw.write = xen_pt_long_reg_write,
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+ },
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+ /* Pending reg (if PCI_MSI_FLAGS_MASKBIT set, for 64-bit devices) */
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+ {
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+ .offset = PCI_MSI_MASK_64 + 4,
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+ .size = 4,
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+ .init_val = 0x00000000,
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+ .ro_mask = 0xFFFFFFFF,
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+ .emu_mask = 0x00000000,
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+ .init = xen_pt_pending_reg_init,
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+ .u.dw.read = xen_pt_long_reg_read,
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+ .u.dw.write = xen_pt_long_reg_write,
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+ },
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{
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.size = 0,
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},
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diff --git a/include/hw/pci/pci_regs.h b/include/hw/pci/pci_regs.h
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index 56a404b..57e8c80 100644
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--- a/include/hw/pci/pci_regs.h
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+++ b/include/hw/pci/pci_regs.h
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@@ -298,8 +298,10 @@
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#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
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#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
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#define PCI_MSI_MASK_32 12 /* Mask bits register for 32-bit devices */
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+#define PCI_MSI_PENDING_32 16 /* Pending bits register for 32-bit devices */
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#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
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#define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */
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+#define PCI_MSI_PENDING_64 20 /* Pending bits register for 32-bit devices */
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/* MSI-X registers */
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#define PCI_MSIX_FLAGS 2
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--
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2.2.1
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