Added VHDL-mode snippets

snippets/vhdl-mode/architecture

@@ -0,0 +1,8 @@
+# -*- mode: snippet -*-
+# name: architecture
+# key: arch
+# --
+architecture ${1:Type} of ${2:Name} is
+begin
+  $0
+end $1;

snippets/vhdl-mode/asignation

@@ -0,0 +1,5 @@
+# -*- mode: snippet -*-
+# name: asignation
+# key: asig
+# --
+${1:variable} <= ${2:value};

snippets/vhdl-mode/case

@@ -0,0 +1,9 @@
+# -*- mode: snippet -*-
+# name: case
+# key: case
+# --
+case ${1:cond} is
+    when ${2:Value} =>
+        $0
+
+end case;

snippets/vhdl-mode/component

@@ -0,0 +1,7 @@
+# -*- mode: snippet -*-
+# name: component
+# key: comp
+# --
+component ${1:Name}
+  $0
+end component;

snippets/vhdl-mode/constant

@@ -0,0 +1,5 @@
+# -*- mode: snippet -*-
+# name: constant
+# key: const
+# --
+constant ${1:Name}: ${2:Type} := ${3:Value};

snippets/vhdl-mode/downto

@@ -0,0 +1,5 @@
+# -*- mode: snippet -*-
+# name: downto
+# key: dto
+# --
+${1:name}(${2:start} downto ${3:end})$0

snippets/vhdl-mode/entity

@@ -0,0 +1,7 @@
+# -*- mode: snippet -*-
+# name: entity
+# key: ent
+# --
+entity ${1:Name} is
+    $0
+end $1;

snippets/vhdl-mode/if

@@ -0,0 +1,7 @@
+# -*- mode: snippet -*-
+# name: if
+# key: if
+# --
+if ${1:cond} then
+   $0
+end if;

snippets/vhdl-mode/ifelif

@@ -0,0 +1,9 @@
+# -*- mode: snippet -*-
+# name: ifelif
+# key: ifelif
+# --
+if ${1:cond1} then
+   $0
+elsif ${2:cond2} then
+      
+end if;

snippets/vhdl-mode/ifelse

@@ -0,0 +1,9 @@
+# -*- mode: snippet -*-
+# name: ifelse
+# key: ifel
+# --
+if ${1:cond1} then
+   $0
+else
+   
+end if;

snippets/vhdl-mode/lib

@@ -0,0 +1,6 @@
+# -*- mode: snippet -*-
+# name: library
+# key: lib
+# --
+library IEEE;
+use IEEE.std_logic_1164.all;

snippets/vhdl-mode/port

@@ -0,0 +1,5 @@
+# -*- mode: snippet -*-
+# name: port
+# key: port
+# --
+port(${1:name}: ${2:IO} ${3:type});

snippets/vhdl-mode/process

@@ -0,0 +1,8 @@
+# -*- mode: snippet -*-
+# name: process
+# key: process
+# --
+${1:Name}: process(${2:Sensitivity List})
+begin
+  $0
+end process $1;

snippets/vhdl-mode/signal

@@ -0,0 +1,5 @@
+# -*- mode: snippet -*-
+# name: signal
+# key: signal
+# --
+signal ${1:Names}: ${2:Type};

snippets/vhdl-mode/to

@@ -0,0 +1,5 @@
+# -*- mode: snippet -*-
+# name: to
+# key: to
+# --
+${1:name}(${2:start} to ${3:end})$0

snippets/vhdl-mode/type

@@ -0,0 +1,5 @@
+# -*- mode: snippet -*-
+# name: type
+# key: type
+# --
+type ${1:Name} is (${2:Value list});

snippets/vhdl-mode/when

@@ -0,0 +1,6 @@
+# -*- mode: snippet -*-
+# name: when
+# key: when
+# --
+when ${1:Value} =>
+    $0