9 lines
485 B
Text
9 lines
485 B
Text
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Verilator is the fastest free Verilog HDL simulator, and beats most commercial
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simulators. It compiles synthesizable Verilog (not test-bench code!), plus some
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PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is
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designed for large projects where fast simulation performance is of primary
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concern, and is especially well suited to generate executable models of CPUs
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for embedded software design teams.
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WWW: https://www.veripool.org/projects/verilator/wiki/Intro
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