freebsd-ports/cad/gplcver/distinfo

MD5 (gplcver-2.11a.src.tar.bz2) = 4967e78c299bdfdb0c9f2dcd4803e734
SHA256 (gplcver-2.11a.src.tar.bz2) = b64eea22f354bee2de09532309c6a1e3f3658c427fe2d063ef3921c1042fa380
SIZE (gplcver-2.11a.src.tar.bz2) = 1189439
[NEW PORT] cad/gplcver: A Verilog HDL simulator GPL Cver is a full 1995 P1364 Verilog standard HDL simulator. It also implements some of the 2001 P1364 standard features including all three PLI interfaces (tf_, acc_ and vpi_) as defined in the 2001 Language Reference Manual (LRM). Verilog is the name for both a language for describing electronic hardware called a hardware description language (HDL) and the name of the program that simulates HDL circuit descriptions to verify that described circuits will function correctly when the are constructed. Verilog is used only for describing digital logic circuits. Other HDLs such as Spice are used for describing analog circuits. There is an IEEE standard named P1364 that standardizes the Verilog HDL and the behavior of Verilog simulators. Verilog is officially defined in the IEEE P1364 Language Reference Manual (LRM) that can be purchased from IEEE. There are many good books for learning that teach the Verilog HDL and/or that teach digital circuit design using Verilog. WWW: http://www.pragmatic-c.com/gpl-cver/ PR: ports/80968 Submitted by: Ying-Chieh Liao <ijliao@csie.nctu.edu.tw> 2005-12-29 04:48:58 +01:00			`MD5 (gplcver-2.11a.src.tar.bz2) = 4967e78c299bdfdb0c9f2dcd4803e734`
			`SHA256 (gplcver-2.11a.src.tar.bz2) = b64eea22f354bee2de09532309c6a1e3f3658c427fe2d063ef3921c1042fa380`
			`SIZE (gplcver-2.11a.src.tar.bz2) = 1189439`