12 lines
694 B
Text
12 lines
694 B
Text
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A digital synthesis flow is a set of tools and methods used to turn a circuit
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design written in a high-level behavioral language like verilog or VHDL into a
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physical circuit, which can either be configuration code for an FPGA target like
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a Xilinx or Altera chip, or a layout in a specific fabrication process
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technology, that would become part of a fabricated circuit chip. Several digital
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synthesis flows targeting FPGAs are available, usually from the FPGA
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manufacturers, and while they are typically not open source, they are generally
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distributed for free (presumably on the sensible assumption that more people
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will be buying more FPGA hardware).
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WWW: http://opencircuitdesign.com/qflow/
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