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freebsd-ports/cad/p5-Verilog-Perl/Makefile

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cad/p5-Verilog-Perl: 3.404 -> 3.418 Changes: http://cpansearch.perl.org/src/WSNYDER/Verilog-Perl-3.418/Changes Removed dependency of gcc. Now, p5-Verilog-Perl compiles with clang. PR: 207050 Submitted by: otacilio.neto@ee.ufcg.edu.br (maintainer)
2016-02-10 20:34:24 +01:00
# Created by: Otacilio de Araujo Ramos Neto <otacilio.neto@bsd.com.br>
The Verilog-Perl library is a building point for Verilog support in the Perl language. It includes: * Verilog::Getopt which parses command line options similar to C++ and VCS. * Verilog::Language which knows the language keywords and parses numbers. * Verilog::Netlist which builds netlists out of Verilog files. This allows easy scripts to determine things such as the hierarchy of modules. * Verilog::Parser invokes callbacks for language tokens. * Verilog::Preproc preprocesses the language, and allows reading post-processed files right from Perl without temporary files. * vpassert inserts PLIish warnings and assertions for any simulator. * vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language. * vrename renames and cross-references Verilog symbols. Vrename creates Verilog cross references and makes it easy to rename signal and module names across multiple files. Vrename uses a simple and efficient three step process. First, you run vrename to create a list of signals in the design. You then edit this list, changing as many symbols as you wish. Vrename is then run a second time to apply the changes. WWW: http://www.veripool.org/wiki/verilog-perl PR: ports/134124 Submitted by: Otacílio de Araújo Ramos Neto <otacilio.neto at ee.ufcg.edu.br>
2009-05-26 13:01:39 +02:00
PORTNAME= Verilog-Perl
cad/p5-Verilog-Perl: 3.404 -> 3.418 Changes: http://cpansearch.perl.org/src/WSNYDER/Verilog-Perl-3.418/Changes Removed dependency of gcc. Now, p5-Verilog-Perl compiles with clang. PR: 207050 Submitted by: otacilio.neto@ee.ufcg.edu.br (maintainer)
2016-02-10 20:34:24 +01:00
PORTVERSION= 3.418
The Verilog-Perl library is a building point for Verilog support in the Perl language. It includes: * Verilog::Getopt which parses command line options similar to C++ and VCS. * Verilog::Language which knows the language keywords and parses numbers. * Verilog::Netlist which builds netlists out of Verilog files. This allows easy scripts to determine things such as the hierarchy of modules. * Verilog::Parser invokes callbacks for language tokens. * Verilog::Preproc preprocesses the language, and allows reading post-processed files right from Perl without temporary files. * vpassert inserts PLIish warnings and assertions for any simulator. * vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language. * vrename renames and cross-references Verilog symbols. Vrename creates Verilog cross references and makes it easy to rename signal and module names across multiple files. Vrename uses a simple and efficient three step process. First, you run vrename to create a list of signals in the design. You then edit this list, changing as many symbols as you wish. Vrename is then run a second time to apply the changes. WWW: http://www.veripool.org/wiki/verilog-perl PR: ports/134124 Submitted by: Otacílio de Araújo Ramos Neto <otacilio.neto at ee.ufcg.edu.br>
2009-05-26 13:01:39 +02:00
CATEGORIES= cad perl5
MASTER_SITES= CPAN
PKGNAMEPREFIX= p5-
- Change maintainer email [1] - Add LICENSE info [1] - Strip more binaries [1] - No need to include bsd.port.pre.mk PR: 210844 [1] Submitted by: otacilio.neto@bsd.com.br (maintainer)
2016-07-27 19:04:44 +02:00
MAINTAINER= otacilio.neto@bsd.com.br
The Verilog-Perl library is a building point for Verilog support in the Perl language. It includes: * Verilog::Getopt which parses command line options similar to C++ and VCS. * Verilog::Language which knows the language keywords and parses numbers. * Verilog::Netlist which builds netlists out of Verilog files. This allows easy scripts to determine things such as the hierarchy of modules. * Verilog::Parser invokes callbacks for language tokens. * Verilog::Preproc preprocesses the language, and allows reading post-processed files right from Perl without temporary files. * vpassert inserts PLIish warnings and assertions for any simulator. * vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language. * vrename renames and cross-references Verilog symbols. Vrename creates Verilog cross references and makes it easy to rename signal and module names across multiple files. Vrename uses a simple and efficient three step process. First, you run vrename to create a list of signals in the design. You then edit this list, changing as many symbols as you wish. Vrename is then run a second time to apply the changes. WWW: http://www.veripool.org/wiki/verilog-perl PR: ports/134124 Submitted by: Otacílio de Araújo Ramos Neto <otacilio.neto at ee.ufcg.edu.br>
2009-05-26 13:01:39 +02:00
COMMENT= Building point for Verilog support in the Perl language
- Fix LICENSE - Add LICENSE_FILE - Silence stripping - Update WWW Approved by: portmgr blanket
2020-02-16 10:31:26 +01:00
LICENSE= ART20 LGPL3
LICENSE_COMB= dual
LICENSE_FILE_ART20= ${WRKSRC}/COPYING
- Change maintainer email [1] - Add LICENSE info [1] - Strip more binaries [1] - No need to include bsd.port.pre.mk PR: 210844 [1] Submitted by: otacilio.neto@bsd.com.br (maintainer)
2016-07-27 19:04:44 +02:00
Use byacc instead of bison (via the new bison wrapper)
2020-03-10 15:24:19 +01:00
USES= bison:wrapper gmake perl5
Convert to new perl framework Submitted by: az
2013-09-17 08:12:35 +02:00
USE_PERL5= configure
- Update to 3.404 - Fix build, it needs gcc PR: 191368 Submitted by: otaciliodearaujo@gmail.com (maintainer)
2014-06-27 20:59:28 +02:00
CONFIGURE_ENV= CXX=${CXX}\
CPP=${CPP}\
CC=${CC}
The Verilog-Perl library is a building point for Verilog support in the Perl language. It includes: * Verilog::Getopt which parses command line options similar to C++ and VCS. * Verilog::Language which knows the language keywords and parses numbers. * Verilog::Netlist which builds netlists out of Verilog files. This allows easy scripts to determine things such as the hierarchy of modules. * Verilog::Parser invokes callbacks for language tokens. * Verilog::Preproc preprocesses the language, and allows reading post-processed files right from Perl without temporary files. * vpassert inserts PLIish warnings and assertions for any simulator. * vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language. * vrename renames and cross-references Verilog symbols. Vrename creates Verilog cross references and makes it easy to rename signal and module names across multiple files. Vrename uses a simple and efficient three step process. First, you run vrename to create a list of signals in the design. You then edit this list, changing as many symbols as you wish. Vrename is then run a second time to apply the changes. WWW: http://www.veripool.org/wiki/verilog-perl PR: ports/134124 Submitted by: Otacílio de Araújo Ramos Neto <otacilio.neto at ee.ufcg.edu.br>
2009-05-26 13:01:39 +02:00
- add stage support - unbreak
2014-06-01 16:19:13 +02:00
post-install:
- Fix LICENSE - Add LICENSE_FILE - Silence stripping - Update WWW Approved by: portmgr blanket
2020-02-16 10:31:26 +01:00
@${STRIP_CMD} ${STAGEDIR}${PREFIX}/${SITE_ARCH_REL}/auto/Verilog/Parser/*.so
@${STRIP_CMD} ${STAGEDIR}${PREFIX}/${SITE_ARCH_REL}/auto/Verilog/Preproc/*.so
The Verilog-Perl library is a building point for Verilog support in the Perl language. It includes: * Verilog::Getopt which parses command line options similar to C++ and VCS. * Verilog::Language which knows the language keywords and parses numbers. * Verilog::Netlist which builds netlists out of Verilog files. This allows easy scripts to determine things such as the hierarchy of modules. * Verilog::Parser invokes callbacks for language tokens. * Verilog::Preproc preprocesses the language, and allows reading post-processed files right from Perl without temporary files. * vpassert inserts PLIish warnings and assertions for any simulator. * vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language. * vrename renames and cross-references Verilog symbols. Vrename creates Verilog cross references and makes it easy to rename signal and module names across multiple files. Vrename uses a simple and efficient three step process. First, you run vrename to create a list of signals in the design. You then edit this list, changing as many symbols as you wish. Vrename is then run a second time to apply the changes. WWW: http://www.veripool.org/wiki/verilog-perl PR: ports/134124 Submitted by: Otacílio de Araújo Ramos Neto <otacilio.neto at ee.ufcg.edu.br>
2009-05-26 13:01:39 +02:00
- Change maintainer email [1] - Add LICENSE info [1] - Strip more binaries [1] - No need to include bsd.port.pre.mk PR: 210844 [1] Submitted by: otacilio.neto@bsd.com.br (maintainer)
2016-07-27 19:04:44 +02:00
.include <bsd.port.mk>
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