freebsd-ports/cad/iverilog/pkg-plist

bin/iverilog
bin/iverilog-vpi
bin/vvp
include/iverilog/_pli_types.h
include/iverilog/acc_user.h
include/iverilog/ivl_target.h
include/iverilog/sv_vpi_user.h
include/iverilog/veriuser.h
include/iverilog/vpi_user.h
lib/ivl/blif-s.conf
lib/ivl/blif.conf
lib/ivl/blif.tgt
lib/ivl/cadpli.vpl
lib/ivl/include/constants.vams
lib/ivl/include/disciplines.vams
lib/ivl/ivl
lib/ivl/ivlpp
lib/ivl/null-s.conf
lib/ivl/null.conf
lib/ivl/null.tgt
lib/ivl/pcb-s.conf
lib/ivl/pcb.conf
lib/ivl/pcb.tgt
lib/ivl/sizer-s.conf
lib/ivl/sizer.conf
lib/ivl/sizer.tgt
lib/ivl/stub-s.conf
lib/ivl/stub.conf
lib/ivl/stub.tgt
lib/ivl/system.sft
lib/ivl/system.vpi
lib/ivl/vlog95-s.conf
lib/ivl/vlog95.conf
lib/ivl/vlog95.tgt
lib/ivl/vpi_debug.vpi
lib/ivl/v2005_math.sft
lib/ivl/v2005_math.vpi
lib/ivl/v2009.sft
lib/ivl/v2009.vpi
lib/ivl/va_math.sft
lib/ivl/va_math.vpi
lib/ivl/vhdl-s.conf
lib/ivl/vhdl_sys.sft
lib/ivl/vhdl_sys.vpi
lib/ivl/vhdl.conf
lib/ivl/vhdl.tgt
lib/ivl/vhdlpp
lib/ivl/vvp-s.conf
lib/ivl/vvp.conf
lib/ivl/vvp.tgt
lib/libveriuser.a
lib/libvpi.a
man/man1/iverilog.1.gz
man/man1/iverilog-vpi.1.gz
man/man1/vvp.1.gz
add iverilog, a Verilog simulation and synthesis tool 2001-02-13 12:02:15 +01:00			`bin/iverilog`
Update to iverilog 0.7 Submitted by: Joachim Str?mbergson <watchman@ludd.luth.se> 2003-01-31 18:49:45 +01:00			`bin/iverilog-vpi`
Fix this port and remove BROKEN. 2003-05-16 20:18:38 +02:00			`bin/vvp`
- Update to 0.8.7. 2009-01-23 23:04:50 +01:00			`include/iverilog/_pli_types.h`
			`include/iverilog/acc_user.h`
			`include/iverilog/ivl_target.h`
Update to 10.0 Committed from: EuroBSDCon 2015 2015-10-04 14:17:59 +02:00			`include/iverilog/sv_vpi_user.h`
- Update to 0.8.7. 2009-01-23 23:04:50 +01:00			`include/iverilog/veriuser.h`
			`include/iverilog/vpi_user.h`
Update to 10.0 Committed from: EuroBSDCon 2015 2015-10-04 14:17:59 +02:00			`lib/ivl/blif-s.conf`
			`lib/ivl/blif.conf`
			`lib/ivl/blif.tgt`
Maintainer Update to latest snapshot. Changes: add AMD64 support (experimental); time 0 race resolution; identation cleanup; manpage update. PR: ports/58320 2003-10-27 11:02:34 +01:00			`lib/ivl/cadpli.vpl`
- Update to 0.9.1. 2009-06-09 14:58:04 +02:00			`lib/ivl/include/constants.vams`
			`lib/ivl/include/disciplines.vams`
Fix this port and remove BROKEN. 2003-05-16 20:18:38 +02:00			`lib/ivl/ivl`
add iverilog, a Verilog simulation and synthesis tool 2001-02-13 12:02:15 +01:00			`lib/ivl/ivlpp`
Update to 20031202 snapshot. Summary of changes listed on ftp://icarus.com/pub/eda/verilog/snapshots/verilog-20031202.txt: Combination 64bit/32bit runtime support now works fully on AMD64 systems; wait on lists of named events now works; there is no longer a common iverilog.conf, instead there are target specific foo.conf files with a new and cleaner format; 64bit values are more portably handled; several synthesis bugs related to the control inputs of flip-flops have been fixed. Committer is marking this BROKEN on 4.x while we investigate install problems. It works on 5.x only for now. PR: ports/60162 Submitted by: Joachim Strombergson <watchman@ludd.luth.se> (maintainer) 2003-12-17 17:02:50 +01:00			`lib/ivl/null-s.conf`
			`lib/ivl/null.conf`
add iverilog, a Verilog simulation and synthesis tool 2001-02-13 12:02:15 +01:00			`lib/ivl/null.tgt`
Update to 10.0 Committed from: EuroBSDCon 2015 2015-10-04 14:17:59 +02:00			`lib/ivl/pcb-s.conf`
			`lib/ivl/pcb.conf`
			`lib/ivl/pcb.tgt`
			`lib/ivl/sizer-s.conf`
			`lib/ivl/sizer.conf`
			`lib/ivl/sizer.tgt`
- Update to 0.9.1. 2009-06-09 14:58:04 +02:00			`lib/ivl/stub-s.conf`
			`lib/ivl/stub.conf`
			`lib/ivl/stub.tgt`
Update to 0.8 PR: 72949 Submitted by: Joachim Strombergson <watchman@ludd.ltu.se> 2004-11-05 14:16:52 +01:00			`lib/ivl/system.sft`
Fix this port and remove BROKEN. 2003-05-16 20:18:38 +02:00			`lib/ivl/system.vpi`
Update to 10.0 Committed from: EuroBSDCon 2015 2015-10-04 14:17:59 +02:00			`lib/ivl/vlog95-s.conf`
			`lib/ivl/vlog95.conf`
			`lib/ivl/vlog95.tgt`
			`lib/ivl/vpi_debug.vpi`
- Update to 0.9.1. 2009-06-09 14:58:04 +02:00			`lib/ivl/v2005_math.sft`
			`lib/ivl/v2005_math.vpi`
Update to 10.0 Committed from: EuroBSDCon 2015 2015-10-04 14:17:59 +02:00			`lib/ivl/v2009.sft`
			`lib/ivl/v2009.vpi`
- Update to 0.9.1. 2009-06-09 14:58:04 +02:00			`lib/ivl/va_math.sft`
			`lib/ivl/va_math.vpi`
			`lib/ivl/vhdl-s.conf`
Update to 10.0 Committed from: EuroBSDCon 2015 2015-10-04 14:17:59 +02:00			`lib/ivl/vhdl_sys.sft`
			`lib/ivl/vhdl_sys.vpi`
- Update to 0.9.1. 2009-06-09 14:58:04 +02:00			`lib/ivl/vhdl.conf`
			`lib/ivl/vhdl.tgt`
Update to 10.0 Committed from: EuroBSDCon 2015 2015-10-04 14:17:59 +02:00			`lib/ivl/vhdlpp`
Update to 20031202 snapshot. Summary of changes listed on ftp://icarus.com/pub/eda/verilog/snapshots/verilog-20031202.txt: Combination 64bit/32bit runtime support now works fully on AMD64 systems; wait on lists of named events now works; there is no longer a common iverilog.conf, instead there are target specific foo.conf files with a new and cleaner format; 64bit values are more portably handled; several synthesis bugs related to the control inputs of flip-flops have been fixed. Committer is marking this BROKEN on 4.x while we investigate install problems. It works on 5.x only for now. PR: ports/60162 Submitted by: Joachim Strombergson <watchman@ludd.luth.se> (maintainer) 2003-12-17 17:02:50 +01:00			`lib/ivl/vvp-s.conf`
			`lib/ivl/vvp.conf`
Add missing files 2002-09-19 05:04:23 +02:00			`lib/ivl/vvp.tgt`
Update to iverilog 0.7 Submitted by: Joachim Str?mbergson <watchman@ludd.luth.se> 2003-01-31 18:49:45 +01:00			`lib/libveriuser.a`
Add missing files 2002-09-19 05:04:23 +02:00			`lib/libvpi.a`
Update to 0.9.7. Stagify. 2013-12-10 17:08:47 +01:00			`man/man1/iverilog.1.gz`
			`man/man1/iverilog-vpi.1.gz`
			`man/man1/vvp.1.gz`