cad/yosys-systemverilog: New port: SystemVerilog support for Yosys
This commit is contained in:
Yuri Victorovich
parent
fcffbcbce7
commit
2fde22d5d0
7 changed files with 208 additions and 0 deletions
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@ -151,6 +151,7 @@
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SUBDIR += xcircuit
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SUBDIR += xyce
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SUBDIR += yosys
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SUBDIR += yosys-systemverilog
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SUBDIR += z88
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SUBDIR += zcad
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93
cad/yosys-systemverilog/Makefile
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93
cad/yosys-systemverilog/Makefile
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@ -0,0 +1,93 @@
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PORTNAME= yosys-systemverilog
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DISTVERSION= 2023-06-05
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CATEGORIES= cad
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PKGNAMEPREFIX=
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MAINTAINER= yuri@FreeBSD.org
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COMMENT= SystemVerilog support for Yosys
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WWW= https://github.com/antmicro/yosys-systemverilog
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LICENSE= APACHE20
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LICENSE_FILE= ${WRKSRC}/LICENSE
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BUILD_DEPENDS= bash:shells/bash \
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yosys>0:cad/yosys
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LIB_DEPENDS= libcapnp.so:devel/capnproto \
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libffi.so:devel/libffi \
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libsurelog.so:cad/surelog \
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libuhdm.so:cad/uhdm
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RUN_DEPENDS= yosys>0:cad/yosys
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USES= cabal gmake pkgconfig python:build readline tcl
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USE_CABAL= alex-3.3.0.0 \
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cmdargs-0.10.22 \
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githash-0.1.6.3 \
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happy-1.20.1.1 \
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hashable-1.4.2.0_1 \
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primitive-0.8.0.0 \
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th-compat-0.1.4_2 \
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vector-0.13.0.0_3 \
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vector-stream-0.1.0.0_2
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SKIP_CABAL_PLIST= yes
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# in order to update USE_CABAL run 'make local-cabal-configure local-make-use-cabal'
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USE_GITHUB= yes
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GH_ACCOUNT= antmicro
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GH_TAGNAME= 00c9bce-${DISTVERSION}
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GH_TUPLE= chipsalliance:yosys-f4pga-plugins:56f957c:yosys_f4pga_plugins/yosys-f4pga-plugins \
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zachjs:sv2v:6c4ee8f:sv2v/sv2v \
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YosysHQ:yosys:c5e4eec:yosys/yosys
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MAKE_ENV= DESTDIR=${DESTDIR} \
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HOME=${WRKSRC}
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MAKE_ARGS= YOSYS_PATH=${LOCALBASE} -j${MAKE_JOBS_NUMBER}
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BINARY_ALIAS= python3=${PYTHON_CMD} \
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install=${FILESDIR}/install.sh
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OPTIONS_DEFINE= TCMALLOC
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OPTIONS_DEFAULT= TCMALLOC # should be the same TCMALLOC default as in cad/yosys, cad/surelog, cad/uhdm because surelog's lib is used in the yosys plugin cad/yosys-systemverilog
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TCMALLOC_LDFLAGS= `pkg-config --libs libtcmalloc`
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TCMALLOC_LIB_DEPENDS= libtcmalloc.so:devel/google-perftools
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post-extract:
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@${CP} ${WRKSRC_yosys}/passes/pmgen/pmgen.py ${WRKSRC}/yosys-f4pga-plugins
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local-cabal-configure: check-cabal
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@cd ${WRKSRC}/sv2v && \
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${SETENV} ${MAKE_ENV} ${CABAL_HOME_ENV} ${CABAL_CMD} build --dry-run --disable-benchmarks --disable-tests --flags="${CABAL_FLAGS}" ${CABAL_WITH_ARGS} ${CABAL_LTO_ARGS} ${BUILD_ARGS} exe:sv2v
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local-make-use-cabal: check-cabal2tuple
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@${_CABAL2TUPLE_CMD} ${CABAL2TUPLE_ARGS} ${WRKSRC}/sv2v || (${ECHO_CMD} "Did you forget to make do-cabal-configure ?" ; exit 1)
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do-build:
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# UHDM plugin
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${ECHO} "==> Building the C part (yosys-f4pga-plugins)"
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@cd ${WRKSRC}/yosys-f4pga-plugins && ${SETENV} ${MAKE_ENV} ${GMAKE} ${MAKE_ARGS} ${ALL_TARGET}
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# sv2v
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${ECHO} "==> Building the Haskell part (sv2v)"
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cd ${WRKSRC}/sv2v && \
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${LN} -fs ${CABAL_DEPSDIR} && \
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${LN} -fs ../cabal.project.local && \
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${SETENV} ${MAKE_ENV} ${CABAL_HOME_ENV} ${CABAL_CMD} build --offline --disable-benchmarks --disable-tests ${CABAL_WITH_ARGS} ${CABAL_LTO_ARGS} --flags "${CABAL_FLAGS}" ${BUILD_ARGS} exe:sv2v
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do-install:
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# create directories
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@${MKDIR} \
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${STAGEDIR}${PREFIX}/share/yosys/plugins/fasm_extra_modules \
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${STAGEDIR}${PREFIX}/share/yosys/quicklogic/pp3 \
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${STAGEDIR}${PREFIX}/share/yosys/quicklogic/qlf_k6n10 \
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${STAGEDIR}${PREFIX}/share/yosys/quicklogic/qlf_k6n10f \
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${STAGEDIR}${PREFIX}/share/yosys/nexus
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# UHDM plugin
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cd ${WRKSRC}/yosys-f4pga-plugins && ${SETENV} ${MAKE_ENV} ${GMAKE} ${MAKE_ARGS} ${INSTALL_TARGET}
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# sv2v
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${INSTALL_PROGRAM} \
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${WRKSRC}/sv2v/dist-newstyle/build/*-freebsd/ghc-*/sv2v-*/x/sv2v/build/sv2v/sv2v \
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${STAGEDIR}${PREFIX}/bin
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# strip binaries
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${STRIP_CMD} ${STAGEDIR}${PREFIX}/share/yosys/plugins/*.so
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.include <bsd.port.mk>
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35
cad/yosys-systemverilog/distinfo
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35
cad/yosys-systemverilog/distinfo
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@ -0,0 +1,35 @@
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TIMESTAMP = 1686074483
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SHA256 (cabal/alex-3.3.0.0/alex-3.3.0.0.tar.gz) = 810f8e85ea6b87c37cba10f7660d7f1aa0ba251c1275e3a18c312964bb329a63
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SIZE (cabal/alex-3.3.0.0/alex-3.3.0.0.tar.gz) = 86004
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SHA256 (cabal/cmdargs-0.10.22/cmdargs-0.10.22.tar.gz) = b8b12e7f8795cf13037bb062d453b86c788eae62558586f59e9419aabe6e9bef
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SIZE (cabal/cmdargs-0.10.22/cmdargs-0.10.22.tar.gz) = 65154
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SHA256 (cabal/githash-0.1.6.3/githash-0.1.6.3.tar.gz) = fcba79b60ef87bdd4976332e998589a62e1be012b932b543b49de5e0620eef1b
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SIZE (cabal/githash-0.1.6.3/githash-0.1.6.3.tar.gz) = 7617
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SHA256 (cabal/happy-1.20.1.1/happy-1.20.1.1.tar.gz) = 8b4e7dc5a6c5fd666f8f7163232931ab28746d0d17da8fa1cbd68be9e878881b
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SIZE (cabal/happy-1.20.1.1/happy-1.20.1.1.tar.gz) = 183409
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SHA256 (cabal/hashable-1.4.2.0/hashable-1.4.2.0.tar.gz) = 1b4000ea82b81f69d46d0af4152c10c6303873510738e24cfc4767760d30e3f8
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SIZE (cabal/hashable-1.4.2.0/hashable-1.4.2.0.tar.gz) = 25094
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SHA256 (cabal/hashable-1.4.2.0/revision/1.cabal) = 585792335d5541dba78fa8dfcb291a89cd5812a281825ff7a44afa296ab5d58a
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SIZE (cabal/hashable-1.4.2.0/revision/1.cabal) = 4520
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SHA256 (cabal/primitive-0.8.0.0/primitive-0.8.0.0.tar.gz) = 5553c21b4a789f9b591eed69e598cc58484c274af29250e517b5a8bcc62b995f
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SIZE (cabal/primitive-0.8.0.0/primitive-0.8.0.0.tar.gz) = 57222
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SHA256 (cabal/th-compat-0.1.4/th-compat-0.1.4.tar.gz) = d8f97ac14ab47b6b8a7b0fdb4ff95426322ec56badd01652ac15da4a44d4bab8
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SIZE (cabal/th-compat-0.1.4/th-compat-0.1.4.tar.gz) = 14838
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SHA256 (cabal/th-compat-0.1.4/revision/2.cabal) = e5ae7c083ef3a22248558f8451669bb1c55ea8090f5908b86b9033743c161730
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SIZE (cabal/th-compat-0.1.4/revision/2.cabal) = 3224
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SHA256 (cabal/vector-0.13.0.0/vector-0.13.0.0.tar.gz) = c5d3167d15e12f52e00879ddf304a591672a74e369cc47bc5c7fa1d5a8d15b4f
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SIZE (cabal/vector-0.13.0.0/vector-0.13.0.0.tar.gz) = 154509
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SHA256 (cabal/vector-0.13.0.0/revision/3.cabal) = fa5cac81a17a5af388716792e8b99c24b3b66770086756d0d8b23f8272a0244c
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SIZE (cabal/vector-0.13.0.0/revision/3.cabal) = 9112
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SHA256 (cabal/vector-stream-0.1.0.0/vector-stream-0.1.0.0.tar.gz) = a888210f6467f155090653734be5cc920406a07227e0d3adb59096716fdb806c
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SIZE (cabal/vector-stream-0.1.0.0/vector-stream-0.1.0.0.tar.gz) = 12377
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SHA256 (cabal/vector-stream-0.1.0.0/revision/2.cabal) = f5d6d5291cd1b5f2f063403593f1f5c8127d692c888eedeb3e1eb40497a88dca
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SIZE (cabal/vector-stream-0.1.0.0/revision/2.cabal) = 1404
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SHA256 (cabal/antmicro-yosys-systemverilog-2023-06-05-00c9bce-2023-06-05_GH0.tar.gz) = 7dbc3b1607a39478f77fd35689483b574cf7c0111dd262bc7ed7ea936e31a75f
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SIZE (cabal/antmicro-yosys-systemverilog-2023-06-05-00c9bce-2023-06-05_GH0.tar.gz) = 158127
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SHA256 (cabal/chipsalliance-yosys-f4pga-plugins-56f957c_GH0.tar.gz) = e2bf0adae00912e07524f2ecf5f6de3d395d283890652d38568175ad56d7bada
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SIZE (cabal/chipsalliance-yosys-f4pga-plugins-56f957c_GH0.tar.gz) = 2690136
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SHA256 (cabal/zachjs-sv2v-6c4ee8f_GH0.tar.gz) = b03955f19128d05c2a2c9d162b2b946fd23a220146abbc5b7847c83c3f937e90
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SIZE (cabal/zachjs-sv2v-6c4ee8f_GH0.tar.gz) = 279380
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SHA256 (cabal/YosysHQ-yosys-c5e4eec_GH0.tar.gz) = ad4b43d55d98d2cc6f4892c1af6b0770af994a51f0cf8d450029f2a404738b8a
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SIZE (cabal/YosysHQ-yosys-c5e4eec_GH0.tar.gz) = 2542646
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14
cad/yosys-systemverilog/files/install.sh
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14
cad/yosys-systemverilog/files/install.sh
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@ -0,0 +1,14 @@
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#!/bin/sh
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##
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## workaround for
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## * https://github.com/chipsalliance/yosys-f4pga-plugins/issues/527
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##
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##
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if [ "$1" != "-D" ]; then
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exit 1
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fi
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#/usr/bin/install -m 0644 $2 ${DESTDIR}$3
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/usr/bin/install $2 $3
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11
cad/yosys-systemverilog/files/patch-sv2v_Makefile
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11
cad/yosys-systemverilog/files/patch-sv2v_Makefile
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@ -0,0 +1,11 @@
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--- sv2v/Makefile.orig 2023-05-10 12:48:15 UTC
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+++ sv2v/Makefile
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@@ -4,7 +4,7 @@ all: sv2v
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sv2v:
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mkdir -p bin
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- stack install --install-ghc --local-bin-path bin
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+ stack config set system-ghc --global true && stack build --system-ghc --no-install-ghc
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clean:
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stack clean
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2
cad/yosys-systemverilog/pkg-descr
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2
cad/yosys-systemverilog/pkg-descr
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yosys-systemverilog is a YoSys add-on that contains all moving parts needed to
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get SystemVerilog support enabled in Yosys.
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52
cad/yosys-systemverilog/pkg-plist
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52
cad/yosys-systemverilog/pkg-plist
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@ -0,0 +1,52 @@
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bin/sv2v
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share/yosys/nexus/dsp_rules.txt
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share/yosys/plugins/design_introspection.so
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share/yosys/plugins/dsp-ff.so
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share/yosys/plugins/fasm.so
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share/yosys/plugins/fasm_extra_modules/BANK.v
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share/yosys/plugins/integrateinv.so
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share/yosys/plugins/params.so
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share/yosys/plugins/ql-iob.so
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share/yosys/plugins/ql-qlf.so
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share/yosys/plugins/sdc.so
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share/yosys/plugins/systemverilog.so
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share/yosys/plugins/uhdm.so
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share/yosys/plugins/xdc.so
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share/yosys/quicklogic/pp3/abc9_map.v
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share/yosys/quicklogic/pp3/abc9_model.v
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share/yosys/quicklogic/pp3/abc9_unmap.v
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share/yosys/quicklogic/pp3/bram_init_32.vh
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share/yosys/quicklogic/pp3/bram_init_8_16.vh
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share/yosys/quicklogic/pp3/brams.txt
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share/yosys/quicklogic/pp3/brams_map.v
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share/yosys/quicklogic/pp3/brams_sim.v
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share/yosys/quicklogic/pp3/cells_map.v
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share/yosys/quicklogic/pp3/cells_sim.v
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share/yosys/quicklogic/pp3/ffs_map.v
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share/yosys/quicklogic/pp3/latches_map.v
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share/yosys/quicklogic/pp3/lut_map.v
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share/yosys/quicklogic/pp3/lutdefs.txt
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share/yosys/quicklogic/pp3/mult_sim.v
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share/yosys/quicklogic/pp3/qlal3_sim.v
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share/yosys/quicklogic/pp3/qlal4s3b_sim.v
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share/yosys/quicklogic/qlf_k6n10/arith_map.v
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share/yosys/quicklogic/qlf_k6n10/brams.txt
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share/yosys/quicklogic/qlf_k6n10/brams_map.v
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share/yosys/quicklogic/qlf_k6n10/cells_sim.v
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share/yosys/quicklogic/qlf_k6n10/dsp_map.v
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share/yosys/quicklogic/qlf_k6n10/ffs_map.v
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share/yosys/quicklogic/qlf_k6n10/lut_map.v
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share/yosys/quicklogic/qlf_k6n10f/TDP18K_FIFO.v
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share/yosys/quicklogic/qlf_k6n10f/arith_map.v
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share/yosys/quicklogic/qlf_k6n10f/brams.txt
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share/yosys/quicklogic/qlf_k6n10f/brams_final_map.v
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share/yosys/quicklogic/qlf_k6n10f/brams_map.v
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share/yosys/quicklogic/qlf_k6n10f/brams_sim.v
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share/yosys/quicklogic/qlf_k6n10f/cells_sim.v
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share/yosys/quicklogic/qlf_k6n10f/dsp_final_map.v
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share/yosys/quicklogic/qlf_k6n10f/dsp_map.v
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share/yosys/quicklogic/qlf_k6n10f/dsp_sim.v
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share/yosys/quicklogic/qlf_k6n10f/ffs_map.v
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share/yosys/quicklogic/qlf_k6n10f/primitives_sim.v
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share/yosys/quicklogic/qlf_k6n10f/sram1024x18.v
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share/yosys/quicklogic/qlf_k6n10f/ufifo_ctl.v
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