diff --git a/devel/Makefile b/devel/Makefile index 35e85ae621af..5047d8d866d9 100644 --- a/devel/Makefile +++ b/devel/Makefile @@ -255,6 +255,7 @@ SUBDIR += mips-rtems-gcc SUBDIR += mips-rtems-gcj SUBDIR += mips-rtems-objc + SUBDIR += mipsel-linux-kernel-headers SUBDIR += mkcmd SUBDIR += mkmf SUBDIR += mm diff --git a/devel/mipsel-linux-kernel-headers/Makefile b/devel/mipsel-linux-kernel-headers/Makefile new file mode 100644 index 000000000000..5d3bc6e9c65b --- /dev/null +++ b/devel/mipsel-linux-kernel-headers/Makefile @@ -0,0 +1,27 @@ +# New ports collection makefile for: mipsel-linxu-kernel-headers +# Date created: 14 June 2001 +# Whom: Lev Serebryakov +# +# $FreeBSD$ +# + +PORTNAME= kernel-headers +PORTVERSION= 2.4.0.t9 +CATEGORIES= devel +MASTER_SITES= http://lev.serebryakov.spb.ru/download/agenda/ +PKGNAMEPREFIX= mipsel-linux- +DISTNAME= kernel-headers-2.4.0-test9 + +MAINTAINER= lev@serebryakov.spb.ru + +PATCH_STRIP= -p1 +USE_BZIP2= yes +NO_BUILD= yes + +do-install: + (cd ${WRKSRC} && tar --exclude '*.orig' -cf - *) \ + | (cd ${PREFIX}/${PKGNAMEPREFIX:S/-$//} && tar xf -) + ${LN} -sf ${PREFIX}/${PKGNAMEPREFIX:S/-$//}/include/asm-mips \ + ${PREFIX}/${PKGNAMEPREFIX:S/-$//}/include/asm + +.include diff --git a/devel/mipsel-linux-kernel-headers/distinfo b/devel/mipsel-linux-kernel-headers/distinfo new file mode 100644 index 000000000000..b20be7c3770a --- /dev/null +++ b/devel/mipsel-linux-kernel-headers/distinfo @@ -0,0 +1 @@ +MD5 (kernel-headers-2.4.0-test9.tar.bz2) = a42c6a5003624cf850f375525050738b diff --git a/devel/mipsel-linux-kernel-headers/files/patch-aa-mips-2000-11-08 b/devel/mipsel-linux-kernel-headers/files/patch-aa-mips-2000-11-08 new file mode 100644 index 000000000000..24b967361775 --- /dev/null +++ b/devel/mipsel-linux-kernel-headers/files/patch-aa-mips-2000-11-08 @@ -0,0 +1,6335 @@ +diff -ruN linux/include/asm-mips/addrspace.h linux-mips/include/asm-mips/addrspace.h +--- linux/include/asm-mips/addrspace.h Thu Jun 26 12:33:39 1997 ++++ linux-mips/include/asm-mips/addrspace.h Mon Sep 11 23:53:12 2000 +@@ -4,6 +4,7 @@ + * for more details. + * + * Copyright (C) 1996 by Ralf Baechle ++ * Copyright (C) 2000 by Maciej W. Rozycki + * + * Defitions for the address spaces of the MIPS CPUs. + */ +@@ -22,20 +23,35 @@ + /* + * Returns the kernel segment base of a given address + */ ++#ifndef __ASSEMBLY__ + #define KSEGX(a) (((unsigned long)(a)) & 0xe0000000) ++#else ++#define KSEGX(a) ((a) & 0xe0000000) ++#endif + + /* + * Returns the physical address of a KSEG0/KSEG1 address + */ ++#ifndef __ASSEMBLY__ + #define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff) ++#else ++#define PHYSADDR(a) ((a) & 0x1fffffff) ++#endif + + /* + * Map an address to a certain kernel segment + */ ++#ifndef __ASSEMBLY__ + #define KSEG0ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG0)) + #define KSEG1ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG1)) + #define KSEG2ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG2)) + #define KSEG3ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG3)) ++#else ++#define KSEG0ADDR(a) (((a) & 0x1fffffff) | KSEG0) ++#define KSEG1ADDR(a) (((a) & 0x1fffffff) | KSEG1) ++#define KSEG2ADDR(a) (((a) & 0x1fffffff) | KSEG2) ++#define KSEG3ADDR(a) (((a) & 0x1fffffff) | KSEG3) ++#endif + + /* + * Memory segments (64bit kernel mode addresses) +diff -ruN linux/include/asm-mips/atomic.h linux-mips/include/asm-mips/atomic.h +--- linux/include/asm-mips/atomic.h Sat May 13 08:31:25 2000 ++++ linux-mips/include/asm-mips/atomic.h Fri Nov 10 00:11:39 2000 +@@ -9,20 +9,14 @@ + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * +- * Copyright (C) 1996, 1997 by Ralf Baechle +- * +- * $Id: atomic.h,v 1.6 1999/07/26 19:42:42 harald Exp $ ++ * Copyright (C) 1996, 1997, 2000 by Ralf Baechle + */ + #ifndef __ASM_ATOMIC_H + #define __ASM_ATOMIC_H + + #include + +-#ifdef CONFIG_SMP + typedef struct { volatile int counter; } atomic_t; +-#else +-typedef struct { int counter; } atomic_t; +-#endif + + #ifdef __KERNEL__ + #define ATOMIC_INIT(i) { (i) } +@@ -38,7 +32,7 @@ + * The MIPS I implementation is only atomic with respect to + * interrupts. R3000 based multiprocessor machines are rare anyway ... + */ +-extern __inline__ void atomic_add(int i, volatile atomic_t * v) ++extern __inline__ void atomic_add(int i, atomic_t * v) + { + int flags; + +@@ -48,7 +42,7 @@ + restore_flags(flags); + } + +-extern __inline__ void atomic_sub(int i, volatile atomic_t * v) ++extern __inline__ void atomic_sub(int i, atomic_t * v) + { + int flags; + +@@ -86,21 +80,6 @@ + return temp; + } + +-extern __inline__ void atomic_clear_mask(unsigned long mask, unsigned long * v) +-{ +- unsigned long temp; +- int flags; +- +- save_flags(flags); +- cli(); +- temp = *v; +- temp &= ~mask; +- *v = temp; +- restore_flags(flags); +- +- return; +-} +- + #else + + /* +@@ -108,41 +87,30 @@ + * implementation is SMP safe ... + */ + +-/* +- * Make sure gcc doesn't try to be clever and move things around +- * on us. We need to use _exactly_ the address the user gave us, +- * not some alias that contains the same information. +- */ +-#define __atomic_fool_gcc(x) (*(volatile struct { int a[100]; } *)x) +- +-extern __inline__ void atomic_add(int i, volatile atomic_t * v) ++extern __inline__ void atomic_add(int i, atomic_t * v) + { + unsigned long temp; + + __asm__ __volatile__( +- "1:\tll\t%0,%1\n\t" +- "addu\t%0,%2\n\t" +- "sc\t%0,%1\n\t" +- "beqz\t%0,1b" +- :"=&r" (temp), +- "=m" (__atomic_fool_gcc(v)) +- :"Ir" (i), +- "m" (__atomic_fool_gcc(v))); ++ "1:\tll\t%0, %1\t\t\t# atomic_add\n\t" ++ "addu\t%0, %2\n\t" ++ "sc\t%0, %1\n\t" ++ "beqz\t%0, 1b" ++ : "=&r" (temp), "=m" (v->counter) ++ : "Ir" (i), "m" (v->counter)); + } + +-extern __inline__ void atomic_sub(int i, volatile atomic_t * v) ++extern __inline__ void atomic_sub(int i, atomic_t * v) + { + unsigned long temp; + + __asm__ __volatile__( +- "1:\tll\t%0,%1\n\t" +- "subu\t%0,%2\n\t" +- "sc\t%0,%1\n\t" +- "beqz\t%0,1b" +- :"=&r" (temp), +- "=m" (__atomic_fool_gcc(v)) +- :"Ir" (i), +- "m" (__atomic_fool_gcc(v))); ++ "1:\tll\t%0, %1\t\t\t# atomic_sub\n\t" ++ "subu\t%0, %2\n\t" ++ "sc\t%0, %1\n\t" ++ "beqz\t%0, 1b" ++ : "=&r" (temp), "=m" (v->counter) ++ : "Ir" (i), "m" (v->counter)); + } + + /* +@@ -153,18 +121,16 @@ + unsigned long temp, result; + + __asm__ __volatile__( +- ".set\tnoreorder\n" ++ ".set\tnoreorder\t\t\t# atomic_add_return\n" + "1:\tll\t%1,%2\n\t" + "addu\t%0,%1,%3\n\t" + "sc\t%0,%2\n\t" + "beqz\t%0,1b\n\t" + "addu\t%0,%1,%3\n\t" + ".set\treorder" +- :"=&r" (result), +- "=&r" (temp), +- "=m" (__atomic_fool_gcc(v)) +- :"Ir" (i), +- "m" (__atomic_fool_gcc(v))); ++ : "=&r" (result), "=&r" (temp), "=m" (v->counter) ++ : "Ir" (i), "m" (v->counter) ++ : "memory"); + + return result; + } +@@ -174,18 +140,16 @@ + unsigned long temp, result; + + __asm__ __volatile__( +- ".set\tnoreorder\n" ++ ".set\tnoreorder\t\t\t# atomic_sub_return\n" + "1:\tll\t%1,%2\n\t" + "subu\t%0,%1,%3\n\t" + "sc\t%0,%2\n\t" + "beqz\t%0,1b\n\t" + "subu\t%0,%1,%3\n\t" + ".set\treorder" +- :"=&r" (result), +- "=&r" (temp), +- "=m" (__atomic_fool_gcc(v)) +- :"Ir" (i), +- "m" (__atomic_fool_gcc(v))); ++ : "=&r" (result), "=&r" (temp), "=m" (v->counter) ++ : "Ir" (i), "m" (v->counter) ++ : "memory"); + + return result; + } +@@ -201,4 +165,4 @@ + #define atomic_dec(v) atomic_sub(1,(v)) + #endif /* defined(__KERNEL__) */ + +-#endif /* __ASM_MIPS_ATOMIC_H */ ++#endif /* __ASM_ATOMIC_H */ +diff -ruN linux/include/asm-mips/bcache.h linux-mips/include/asm-mips/bcache.h +--- linux/include/asm-mips/bcache.h Sat May 13 08:31:25 2000 ++++ linux-mips/include/asm-mips/bcache.h Fri Nov 10 00:11:39 2000 +@@ -1,14 +1,19 @@ +-/* $Id$ +- * ++/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * +- * Copyright (c) 1997, 1999 by Ralf Baechle ++ * Copyright (c) 1997, 1999, 2000 by Ralf Baechle ++ * Copyright (c) 2000 by Silicon Graphics, Inc. + */ + #ifndef _ASM_BCACHE_H + #define _ASM_BCACHE_H + ++#include ++ ++/* Some R4000 / R4400 / R4600 / R5000 machines may have a non-dma-coherent, ++ chipset implemented caches. On machines with other CPUs the CPU does the ++ cache thing itself. */ + struct bcache_ops { + void (*bc_enable)(void); + void (*bc_disable)(void); +@@ -19,6 +24,39 @@ + extern void indy_sc_init(void); + extern void sni_pcimt_sc_init(void); + ++#ifdef CONFIG_BOARD_SCACHE ++ + extern struct bcache_ops *bcops; ++ ++extern inline void bc_enable(void) ++{ ++ bcops->bc_enable(); ++} ++ ++extern inline void bc_disable(void) ++{ ++ bcops->bc_disable(); ++} ++ ++extern inline void bc_wback_inv(unsigned long page, unsigned long size) ++{ ++ bcops->bc_wback_inv(page, size); ++} ++ ++extern inline void bc_inv(unsigned long page, unsigned long size) ++{ ++ bcops->bc_inv(page, size); ++} ++ ++#else /* !defined(CONFIG_BOARD_SCACHE) */ ++ ++/* Not R4000 / R4400 / R4600 / R5000. */ ++ ++#define bc_enable() do { } while (0) ++#define bc_disable() do { } while (0) ++#define bc_wback_inv(page, size) do { } while (0) ++#define bc_inv(page, size) do { } while (0) ++ ++#endif /* !defined(CONFIG_BOARD_SCACHE) */ + + #endif /* _ASM_BCACHE_H */ +diff -ruN linux/include/asm-mips/bitops.h linux-mips/include/asm-mips/bitops.h +--- linux/include/asm-mips/bitops.h Wed Jul 5 22:15:26 2000 ++++ linux-mips/include/asm-mips/bitops.h Fri Nov 10 00:11:41 2000 +@@ -1,10 +1,10 @@ +-/* $Id: bitops.h,v 1.7 1999/08/19 22:56:33 ralf Exp $ +- * ++/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * +- * Copyright (c) 1994 - 1997, 1999 Ralf Baechle (ralf@gnu.org) ++ * Copyright (c) 1994 - 1997, 1999, 2000 Ralf Baechle (ralf@gnu.org) ++ * Copyright (c) 2000 Silicon Graphics, Inc. + */ + #ifndef _ASM_BITOPS_H + #define _ASM_BITOPS_H +@@ -19,6 +19,12 @@ + #include + + /* ++ * clear_bit() doesn't provide any barrier for the compiler. ++ */ ++#define smp_mb__before_clear_bit() barrier() ++#define smp_mb__after_clear_bit() barrier() ++ ++/* + * Only disable interrupt for kernel mode stuff to keep usermode stuff + * that dares to use kernel include files alive. + */ +@@ -35,25 +41,6 @@ + #define __bi_restore_flags(x) + #endif /* __KERNEL__ */ + +-/* +- * Note that the bit operations are defined on arrays of 32 bit sized +- * elements. With respect to a future 64 bit implementation it is +- * wrong to use long *. Use u32 * or int *. +- */ +-extern __inline__ void set_bit(int nr, void *addr); +-extern __inline__ void clear_bit(int nr, void *addr); +-extern __inline__ void change_bit(int nr, void *addr); +-extern __inline__ int test_and_set_bit(int nr, void *addr); +-extern __inline__ int test_and_clear_bit(int nr, void *addr); +-extern __inline__ int test_and_change_bit(int nr, void *addr); +- +-extern __inline__ int test_bit(int nr, const void *addr); +-#ifndef __MIPSEB__ +-extern __inline__ int find_first_zero_bit (void *addr, unsigned size); +-#endif +-extern __inline__ int find_next_zero_bit (void * addr, int size, int offset); +-extern __inline__ unsigned long ffz(unsigned long word); +- + #if defined(CONFIG_CPU_HAS_LLSC) + + #include +@@ -63,93 +50,162 @@ + * interrupt friendly + */ + +-/* +- * The following functions will only work for the R4000! +- */ ++extern __inline__ void ++set_bit(int nr, volatile void *addr) ++{ ++ unsigned long *m = ((unsigned long *) addr) + (nr >> 5); ++ unsigned long temp; + +-extern __inline__ void set_bit(int nr, void *addr) ++ __asm__ __volatile__( ++ "1:\tll\t%0, %1\t\t# set_bit\n\t" ++ "or\t%0, %2\n\t" ++ "sc\t%0, %1\n\t" ++ "beqz\t%0, 1b" ++ : "=&r" (temp), "=m" (*m) ++ : "ir" (1UL << (nr & 0x1f)), "m" (*m)); ++} ++ ++/* WARNING: non atomic and it can be reordered! */ ++extern __inline__ void __set_bit(int nr, volatile void * addr) + { +- int mask, mw; ++ unsigned long * m = ((unsigned long *) addr) + (nr >> 5); + +- addr += ((nr >> 3) & ~3); +- mask = 1 << (nr & 0x1f); +- do { +- mw = load_linked(addr); +- } while (!store_conditional(addr, mw|mask)); ++ *m |= 1UL << (nr & 31); + } + +-extern __inline__ void clear_bit(int nr, void *addr) ++extern __inline__ void ++clear_bit(int nr, volatile void *addr) + { +- int mask, mw; ++ unsigned long *m = ((unsigned long *) addr) + (nr >> 5); ++ unsigned long temp; + +- addr += ((nr >> 3) & ~3); +- mask = 1 << (nr & 0x1f); +- do { +- mw = load_linked(addr); +- } +- while (!store_conditional(addr, mw & ~mask)); ++ __asm__ __volatile__( ++ "1:\tll\t%0, %1\t\t# clear_bit\n\t" ++ "and\t%0, %2\n\t" ++ "sc\t%0, %1\n\t" ++ "beqz\t%0, 1b\n\t" ++ : "=&r" (temp), "=m" (*m) ++ : "ir" (~(1UL << (nr & 0x1f))), "m" (*m)); + } + +-extern __inline__ void change_bit(int nr, void *addr) ++extern __inline__ void ++change_bit(int nr, volatile void *addr) + { +- int mask, mw; ++ unsigned long *m = ((unsigned long *) addr) + (nr >> 5); ++ unsigned long temp; + +- addr += ((nr >> 3) & ~3); +- mask = 1 << (nr & 0x1f); +- do { +- mw = load_linked(addr); +- } while (!store_conditional(addr, mw ^ mask)); ++ __asm__ __volatile__( ++ "1:\tll\t%0, %1\t\t# change_bit\n\t" ++ "xor\t%0, %2\n\t" ++ "sc\t%0, %1\n\t" ++ "beqz\t%0, 1b" ++ : "=&r" (temp), "=m" (*m) ++ : "ir" (1UL << (nr & 0x1f)), "m" (*m)); + } + +-extern __inline__ int test_and_set_bit(int nr, void *addr) ++/* ++ * It will also imply a memory barrier, thus it must clobber memory ++ * to make sure to reload anything that was cached into registers ++ * outside _this_ critical section. ++ */ ++extern __inline__ int ++test_and_set_bit(int nr, volatile void *addr) + { +- int mask, retval, mw; ++ unsigned long *m = ((unsigned long *) addr) + (nr >> 5); ++ unsigned long temp, res; + +- addr += ((nr >> 3) & ~3); +- mask = 1 << (nr & 0x1f); +- do { +- mw = load_linked(addr); +- retval = (mask & mw) != 0; +- } while (!store_conditional(addr, mw|mask)); ++ __asm__ __volatile__( ++ ".set\tnoreorder\t\t# test_and_set_bit\n" ++ "1:\tll\t%0, %1\n\t" ++ "or\t%2, %0, %3\n\t" ++ "sc\t%2, %1\n\t" ++ "beqz\t%2, 1b\n\t" ++ " and\t%2, %0, %3\n\t" ++ ".set\treorder" ++ : "=&r" (temp), "=m" (*m), "=&r" (res) ++ : "r" (1UL << (nr & 0x1f)), "m" (*m) ++ : "memory"); + +- return retval; ++ return res != 0; + } + +-extern __inline__ int test_and_clear_bit(int nr, void *addr) ++/* WARNING: non atomic and it can be reordered! */ ++extern __inline__ int __test_and_set_bit(int nr, volatile void * addr) + { +- int mask, retval, mw; ++ int mask, retval; ++ volatile int *a = addr; + +- addr += ((nr >> 3) & ~3); ++ a += nr >> 5; + mask = 1 << (nr & 0x1f); +- do { +- mw = load_linked(addr); +- retval = (mask & mw) != 0; +- } +- while (!store_conditional(addr, mw & ~mask)); ++ retval = (mask & *a) != 0; ++ *a |= mask; + + return retval; + } + +-extern __inline__ int test_and_change_bit(int nr, void *addr) ++extern __inline__ int ++test_and_clear_bit(int nr, volatile void *addr) + { +- int mask, retval, mw; ++ unsigned long *m = ((unsigned long *) addr) + (nr >> 5); ++ unsigned long temp, res; ++ ++ __asm__ __volatile__( ++ ".set\tnoreorder\t\t# test_and_clear_bit\n" ++ "1:\tll\t%0, %1\n\t" ++ "or\t%2, %0, %3\n\t" ++ "xor\t%2, %3\n\t" ++ "sc\t%2, %1\n\t" ++ "beqz\t%2, 1b\n\t" ++ " and\t%2, %0, %3\n\t" ++ ".set\treorder" ++ : "=&r" (temp), "=m" (*m), "=&r" (res) ++ : "r" (1UL << (nr & 0x1f)), "m" (*m) ++ : "memory"); + +- addr += ((nr >> 3) & ~3); ++ return res != 0; ++} ++ ++/* WARNING: non atomic and it can be reordered! */ ++extern __inline__ int __test_and_clear_bit(int nr, volatile void * addr) ++{ ++ int mask, retval; ++ volatile int *a = addr; ++ ++ a += nr >> 5; + mask = 1 << (nr & 0x1f); +- do { +- mw = load_linked(addr); +- retval = (mask & mw) != 0; +- } while (!store_conditional(addr, mw ^ mask)); ++ retval = (mask & *a) != 0; ++ *a &= ~mask; + + return retval; + } + ++extern __inline__ int ++test_and_change_bit(int nr, volatile void *addr) ++{ ++ unsigned long *m = ((unsigned long *) addr) + (nr >> 5); ++ unsigned long temp, res; ++ ++ __asm__ __volatile__( ++ ".set\tnoreorder\t\t# test_and_change_bit\n" ++ "1:\tll\t%0, %1\n\t" ++ "xor\t%2, %0, %3\n\t" ++ "sc\t%2, %1\n\t" ++ "beqz\t%2, 1b\n\t" ++ " and\t%2, %0, %3\n\t" ++ ".set\treorder" ++ : "=&r" (temp), "=m" (*m), "=&r" (res) ++ : "r" (1UL << (nr & 0x1f)), "m" (*m) ++ : "memory"); ++ ++ return res != 0; ++} ++ + #else /* MIPS I */ + +-extern __inline__ void set_bit(int nr, void * addr) ++extern __inline__ void set_bit(int nr, volatile void * addr) + { + int mask; +- int *a = addr; ++ volatile int *a = addr; + __bi_flags; + + a += nr >> 5; +@@ -159,10 +215,22 @@ + __bi_restore_flags(flags); + } + +-extern __inline__ void clear_bit(int nr, void * addr) ++/* WARNING: non atomic and it can be reordered! */ ++extern __inline__ void __set_bit(int nr, volatile void * addr) ++{ ++ int mask; ++ volatile int *a = addr; ++ ++ a += nr >> 5; ++ mask = 1 << (nr & 0x1f); ++ *a |= mask; ++} ++ ++/* WARNING: non atomic and it can be reordered! */ ++extern __inline__ void clear_bit(int nr, volatile void * addr) + { + int mask; +- int *a = addr; ++ volatile int *a = addr; + __bi_flags; + + a += nr >> 5; +@@ -172,10 +240,10 @@ + __bi_restore_flags(flags); + } + +-extern __inline__ void change_bit(int nr, void * addr) ++extern __inline__ void change_bit(int nr, volatile void * addr) + { + int mask; +- int *a = addr; ++ volatile int *a = addr; + __bi_flags; + + a += nr >> 5; +@@ -185,10 +253,10 @@ + __bi_restore_flags(flags); + } + +-extern __inline__ int test_and_set_bit(int nr, void * addr) ++extern __inline__ int test_and_set_bit(int nr, volatile void * addr) + { + int mask, retval; +- int *a = addr; ++ volatile int *a = addr; + __bi_flags; + + a += nr >> 5; +@@ -201,10 +269,24 @@ + return retval; + } + +-extern __inline__ int test_and_clear_bit(int nr, void * addr) ++/* WARNING: non atomic and it can be reordered! */ ++extern __inline__ int __test_and_set_bit(int nr, volatile void * addr) + { + int mask, retval; +- int *a = addr; ++ volatile int *a = addr; ++ ++ a += nr >> 5; ++ mask = 1 << (nr & 0x1f); ++ retval = (mask & *a) != 0; ++ *a |= mask; ++ ++ return retval; ++} ++ ++extern __inline__ int test_and_clear_bit(int nr, volatile void * addr) ++{ ++ int mask, retval; ++ volatile int *a = addr; + __bi_flags; + + a += nr >> 5; +@@ -217,10 +299,24 @@ + return retval; + } + +-extern __inline__ int test_and_change_bit(int nr, void * addr) ++/* WARNING: non atomic and it can be reordered! */ ++extern __inline__ int __test_and_clear_bit(int nr, volatile void * addr) ++{ ++ int mask, retval; ++ volatile int *a = addr; ++ ++ a += nr >> 5; ++ mask = 1 << (nr & 0x1f); ++ retval = (mask & *a) != 0; ++ *a &= ~mask; ++ ++ return retval; ++} ++ ++extern __inline__ int test_and_change_bit(int nr, volatile void * addr) + { + int mask, retval; +- int *a = addr; ++ volatile int *a = addr; + __bi_flags; + + a += nr >> 5; +@@ -234,13 +330,13 @@ + } + + #undef __bi_flags +-#undef __bi_cli() +-#undef __bi_save_flags(x) +-#undef __bi_restore_flags(x) ++#undef __bi_cli ++#undef __bi_save_flags ++#undef __bi_restore_flags + + #endif /* MIPS I */ + +-extern __inline__ int test_bit(int nr, const void *addr) ++extern __inline__ int test_bit(int nr, volatile void *addr) + { + return ((1UL << (nr & 31)) & (((const unsigned int *) addr)[nr >> 5])) != 0; + } +@@ -285,13 +381,9 @@ + ".set\tat\n\t" + ".set\treorder\n" + "2:" +- : "=r" (res), +- "=r" (dummy), +- "=r" (addr) +- : "0" ((signed int) 0), +- "1" ((unsigned int) 0xffffffff), +- "2" (addr), +- "r" (size) ++ : "=r" (res), "=r" (dummy), "=r" (addr) ++ : "0" ((signed int) 0), "1" ((unsigned int) 0xffffffff), ++ "2" (addr), "r" (size) + : "$1"); + + return res; +@@ -320,11 +412,8 @@ + ".set\tat\n\t" + ".set\treorder\n" + "1:" +- : "=r" (set), +- "=r" (dummy) +- : "0" (0), +- "1" (1 << bit), +- "r" (*p) ++ : "=r" (set), "=r" (dummy) ++ : "0" (0), "1" (1 << bit), "r" (*p) + : "$1"); + if (set < (32 - bit)) + return set + offset; +diff -ruN linux/include/asm-mips/bootinfo.h linux-mips/include/asm-mips/bootinfo.h +--- linux/include/asm-mips/bootinfo.h Tue Jul 11 11:15:02 2000 ++++ linux-mips/include/asm-mips/bootinfo.h Fri Nov 10 00:11:41 2000 +@@ -1,16 +1,13 @@ +-/* $Id: bootinfo.h,v 1.11 2000/03/06 11:14:32 raiko Exp $ +- * +- * bootinfo.h -- Definition of the Linux/MIPS boot information structure +- * +- * Copyright (C) 1995, 1996 by Ralf Baechle, Andreas Busse, +- * Stoned Elipot and Paul M. Antoine. +- * ++/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. ++ * ++ * Copyright (C) 1995, 1996 by Ralf Baechle, Andreas Busse, ++ * Stoned Elipot and Paul M. Antoine. + */ +-#ifndef __ASM_MIPS_BOOTINFO_H +-#define __ASM_MIPS_BOOTINFO_H ++#ifndef _ASM_BOOTINFO_H ++#define _ASM_BOOTINFO_H + + /* + * Values for machgroup +@@ -26,9 +23,10 @@ + #define MACH_GROUP_NEC_DDB 8 /* NEC DDB */ + #define MACH_GROUP_BAGET 9 /* Baget */ + #define MACH_GROUP_ORION 10 /* CoSine Orion */ ++#define MACH_GROUP_GALILEO 11 /* Galileo Eval Boards*/ + + #define GROUP_NAMES { "unknown", "Jazz", "Digital", "ARC", \ +- "SNI", "ACN", "SGI", "Cobalt", "NEC DDB", "Baget", "Orion" } ++ "SNI", "ACN", "SGI", "Cobalt", "NEC DDB", "Baget", "Orion", "Galileo" } + + /* + * Valid machtype values for group unknown (low order halfword of mips_machtype) +@@ -105,8 +103,9 @@ + * Valid machtype for group NEC DDB + */ + #define MACH_NEC_DDB5074 0 /* NEC DDB Vrc-5074 */ ++#define MACH_NEC_DDB5476 1 /* NEC DDB Vrc-5476 */ + +-#define GROUP_NEC_DDB_NAMES { "Vrc-5074" } ++#define GROUP_NEC_DDB_NAMES { "Vrc-5074", "Vrc-5476"} + + /* + * Valid machtype for group BAGET +@@ -117,6 +116,13 @@ + #define GROUP_BAGET_NAMES { "BT23-201", "BT23-202" } + + /* ++ * Valid machtype for group GALILEO ++ */ ++#define MACH_EV96100 0 /* EV96100 */ ++ ++#define GROUP_GALILEO_NAMES { "EV96100" } ++ ++/* + * Valid cputype values + */ + #define CPU_UNKNOWN 0 +@@ -147,13 +153,15 @@ + #define CPU_R5000A 25 + #define CPU_R4640 26 + #define CPU_NEVADA 27 /* RM5230, RM5260 */ +-#define CPU_LAST 27 ++#define CPU_RM7000 28 ++#define CPU_R5432 29 ++#define CPU_LAST 29 + + #define CPU_NAMES { "unknown", "R2000", "R3000", "R3000A", "R3041", "R3051", \ + "R3052", "R3081", "R3081E", "R4000PC", "R4000SC", "R4000MC", \ + "R4200", "R4400PC", "R4400SC", "R4400MC", "R4600", "R6000", \ + "R6000A", "R8000", "R10000", "R4300", "R4650", "R4700", "R5000", \ +- "R5000A", "R4640", "Nevada" } ++ "R5000A", "R4640", "Nevada", "RM7000", "R5432" } + + #define CL_SIZE (80) + +@@ -193,4 +201,4 @@ + + #endif /* _LANGUAGE_ASSEMBLY */ + +-#endif /* __ASM_MIPS_BOOTINFO_H */ ++#endif /* _ASM_BOOTINFO_H */ +diff -ruN linux/include/asm-mips/bugs.h linux-mips/include/asm-mips/bugs.h +--- linux/include/asm-mips/bugs.h Sat May 13 08:31:25 2000 ++++ linux-mips/include/asm-mips/bugs.h Mon Sep 11 23:53:13 2000 +@@ -30,6 +30,7 @@ + case CPU_R4700: + case CPU_R5000: + case CPU_NEVADA: ++ case CPU_RM7000: + cpu_wait = r4k_wait; + printk(" available.\n"); + break; +diff -ruN linux/include/asm-mips/cpu.h linux-mips/include/asm-mips/cpu.h +--- linux/include/asm-mips/cpu.h Sat May 13 08:31:25 2000 ++++ linux-mips/include/asm-mips/cpu.h Fri Nov 10 00:11:41 2000 +@@ -25,6 +25,7 @@ + #define PRID_IMP_R4640 0x2200 + #define PRID_IMP_R4650 0x2200 /* Same as R4640 */ + #define PRID_IMP_R5000 0x2300 ++#define PRID_IMP_R5432 0x5400 + #define PRID_IMP_SONIC 0x2400 + #define PRID_IMP_MAGIC 0x2500 + #define PRID_IMP_RM7000 0x2700 +diff -ruN linux/include/asm-mips/dec/interrupts.h linux-mips/include/asm-mips/dec/interrupts.h +--- linux/include/asm-mips/dec/interrupts.h Fri Jun 25 17:37:53 1999 ++++ linux-mips/include/asm-mips/dec/interrupts.h Mon Sep 11 23:53:17 2000 +@@ -36,7 +36,7 @@ + + #define NR_INTS 11 + +-#ifndef _LANGUAGE_ASSEMBLY ++#ifndef __ASSEMBLY__ + /* + * Data structure to hide the differences between the DECstation Interrupts + * +@@ -50,6 +50,12 @@ + unsigned int iemask; /* enabling interrupts in IRQ Controller */ + } decint_t; + ++extern volatile unsigned int *isr; ++ /* address of the interrupt status register */ ++extern volatile unsigned int *imr; ++ /* address of the interrupt mask register */ ++extern decint_t dec_interrupt[NR_INTS]; ++ + /* + * Interrupt table structure to hide differences between different + * systems such. +@@ -68,7 +74,7 @@ + extern void dec_intr_rtc(void); + + extern void kn02_io_int(void); +-extern void kn02ba_io_int(void); ++extern void kn02xa_io_int(void); + extern void kn03_io_int(void); + + extern void intr_halt(void); +diff -ruN linux/include/asm-mips/dec/ioasic.h linux-mips/include/asm-mips/dec/ioasic.h +--- linux/include/asm-mips/dec/ioasic.h Wed Dec 31 16:00:00 1969 ++++ linux-mips/include/asm-mips/dec/ioasic.h Mon Sep 11 23:53:17 2000 +@@ -0,0 +1,24 @@ ++/* ++ * linux/asm-mips/dec/ioasic.h ++ * ++ * Copyright (C) 2000 Maciej W. Rozycki ++ * ++ * DEC I/O ASIC access operations. ++ */ ++ ++#ifndef __ASM_DEC_IOASIC_H ++#define __ASM_DEC_IOASIC_H ++ ++extern volatile unsigned int *ioasic_base; ++ ++extern inline void ioasic_write(unsigned int reg, unsigned int v) ++{ ++ ioasic_base[reg / 4] = v; ++} ++ ++extern inline unsigned int ioasic_read(unsigned int reg) ++{ ++ return ioasic_base[reg / 4]; ++} ++ ++#endif /* __ASM_DEC_IOASIC_H */ +diff -ruN linux/include/asm-mips/dec/ioasic_addrs.h linux-mips/include/asm-mips/dec/ioasic_addrs.h +--- linux/include/asm-mips/dec/ioasic_addrs.h Fri Jun 25 17:37:53 1999 ++++ linux-mips/include/asm-mips/dec/ioasic_addrs.h Mon Sep 11 23:53:17 2000 +@@ -17,25 +17,25 @@ + + #define CHUNK_SIZE 0x00040000 + +-#define SYSTEM_ROM 00*CHUNK_SIZE /* ??? */ +-#define IOCTL 01*CHUNK_SIZE +-#define ESAR 02*CHUNK_SIZE +-#define LANCE 03*CHUNK_SIZE +-#define SCC0 04*CHUNK_SIZE +-#define VDAC_HI 05*CHUNK_SIZE /* maxine only */ +-#define SCC1 06*CHUNK_SIZE +-#define VDAC_LO 07*CHUNK_SIZE /* maxine only */ +-#define TOY 08*CHUNK_SIZE +-#define ISDN 09*CHUNK_SIZE /* maxine only */ +-#define ERRADDR 09*CHUNK_SIZE /* 3maxplus only */ +-#define CHKSYN 10*CHUNK_SIZE /* 3maxplus only */ +-#define ACCESS_BUS 10*CHUNK_SIZE /* maxine only */ +-#define MCR 11*CHUNK_SIZE /* 3maxplus only */ +-#define FLOPPY 11*CHUNK_SIZE /* maxine only */ +-#define SCSI 12*CHUNK_SIZE +-#define FLOPPY_DMA 13*CHUNK_SIZE /* maxine only */ +-#define SCSI_DMA 14*CHUNK_SIZE +-#define RESERVED_4 15*CHUNK_SIZE ++#define SYSTEM_ROM (00*CHUNK_SIZE) /* ??? */ ++#define IOCTL (01*CHUNK_SIZE) ++#define ESAR (02*CHUNK_SIZE) ++#define LANCE (03*CHUNK_SIZE) ++#define SCC0 (04*CHUNK_SIZE) ++#define VDAC_HI (05*CHUNK_SIZE) /* maxine only */ ++#define SCC1 (06*CHUNK_SIZE) ++#define VDAC_LO (07*CHUNK_SIZE) /* maxine only */ ++#define TOY (08*CHUNK_SIZE) ++#define ISDN (09*CHUNK_SIZE) /* maxine only */ ++#define ERRADDR (09*CHUNK_SIZE) /* 3maxplus only */ ++#define CHKSYN (10*CHUNK_SIZE) /* 3maxplus only */ ++#define ACCESS_BUS (10*CHUNK_SIZE) /* maxine only */ ++#define MCR (11*CHUNK_SIZE) /* 3maxplus only */ ++#define FLOPPY (11*CHUNK_SIZE) /* maxine only */ ++#define SCSI (12*CHUNK_SIZE) ++#define FLOPPY_DMA (13*CHUNK_SIZE) /* maxine only */ ++#define SCSI_DMA (14*CHUNK_SIZE) ++#define RESERVED_4 (15*CHUNK_SIZE) + + /* + * Offsets for IOCTL registers (relative to (system_base + IOCTL)) +@@ -56,6 +56,7 @@ + #define SSR 0x100 /* System Support Register */ + #define SIR 0x110 /* System Interrupt Register */ + #define SIMR 0x120 /* System Interrupt Mask Register */ ++#define FCTR 0x1e0 /* Free-Running Counter */ + + /* + * Handle partial word SCSI DMA transfers +diff -ruN linux/include/asm-mips/dec/kn02xa.h linux-mips/include/asm-mips/dec/kn02xa.h +--- linux/include/asm-mips/dec/kn02xa.h Fri Jun 25 17:37:53 1999 ++++ linux-mips/include/asm-mips/dec/kn02xa.h Fri Nov 10 00:12:14 2000 +@@ -9,6 +9,7 @@ + * + * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions + * are by curteousy of Chris Fraser. ++ * Copyright (C) 2000 Maciej W. Rozycki + * + * These are addresses which have to be known early in the boot process. + * For other addresses refer to tc.h ioasic_addrs.h and friends. +@@ -19,16 +20,12 @@ + #include + + /* +- * Motherboard regs (kseg1 addresses) +- */ +-#define KN02XA_SSR_ADDR KSEG1ADDR(0x1c040100) /* system control & status reg */ +-#define KN02XA_SIR_ADDR KSEG1ADDR(0x1c040110) /* system interrupt reg */ +-#define KN02XA_SIRM_ADDR KSEG1ADDR(0x1c040120) /* system interrupt mask reg */ +- +-/* + * Some port addresses... + * FIXME: these addresses are incomplete and need tidying up! + */ +-#define KN02XA_RTC_BASE (KSEG1ADDR(0x1c000000 + 0x200000)) /* ASIC + SL8 */ ++#define KN02XA_IOASIC_BASE KSEG1ADDR(0x1c040000) /* I/O ASIC */ ++#define KN02XA_RTC_BASE KSEG1ADDR(0x1c200000) /* RTC */ ++ ++#define KN02XA_IOASIC_REG(r) (KN02XA_IOASIC_BASE+(r)) + + #endif /* __ASM_MIPS_DEC_KN02XA_H */ +diff -ruN linux/include/asm-mips/dec/kn03.h linux-mips/include/asm-mips/dec/kn03.h +--- linux/include/asm-mips/dec/kn03.h Fri Jun 25 17:37:53 1999 ++++ linux-mips/include/asm-mips/dec/kn03.h Mon Sep 11 23:53:17 2000 +@@ -8,6 +8,7 @@ + * + * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions + * are by curteousy of Chris Fraser. ++ * Copyright (C) 2000 Maciej W. Rozycki + * + * These are addresses which have to be known early in the boot process. + * For other addresses refer to tc.h ioasic_addrs.h and friends. +@@ -18,16 +19,12 @@ + #include + + /* +- * Motherboard regs (kseg1 addresses) +- */ +-#define KN03_SSR_ADDR KSEG1ADDR(0x1f840100) /* system control & status reg */ +-#define KN03_SIR_ADDR KSEG1ADDR(0x1f840110) /* system interrupt reg */ +-#define KN03_SIRM_ADDR KSEG1ADDR(0x1f840120) /* system interrupt mask reg */ +- +-/* + * Some port addresses... + * FIXME: these addresses are incomplete and need tidying up! + */ +-#define KN03_RTC_BASE (KSEG1ADDR(0x1f800000 + 0x200000)) /* ASIC + SL8 */ ++#define KN03_IOASIC_BASE KSEG1ADDR(0x1f840000) /* I/O ASIC */ ++#define KN03_RTC_BASE KSEG1ADDR(0x1fa00000) /* RTC */ ++ ++#define KN03_IOASIC_REG(r) (KN03_IOASIC_BASE+(r)) + + #endif /* __ASM_MIPS_DEC_KN03_H */ +diff -ruN linux/include/asm-mips/div64.h linux-mips/include/asm-mips/div64.h +--- linux/include/asm-mips/div64.h Sat May 13 08:31:25 2000 ++++ linux-mips/include/asm-mips/div64.h Mon Sep 11 23:53:13 2000 +@@ -1,4 +1,7 @@ +-/* $Id: div64.h,v 1.1 2000/01/28 23:18:43 ralf Exp $ ++/* ++ * include/asm-mips/div64.h ++ * ++ * Copyright (C) 2000 Maciej W. Rozycki + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive +@@ -7,14 +10,104 @@ + #ifndef _ASM_DIV64_H + #define _ASM_DIV64_H + ++#include ++ + /* +- * Hey, we're already 64-bit, no +- * need to play games.. ++ * No traps on overflows for any of these... + */ +-#define do_div(n,base) ({ \ +- int __res; \ +- __res = ((unsigned long) n) % (unsigned) base; \ +- n = ((unsigned long) n) / (unsigned) base; \ +- __res; }) ++ ++#if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) ++ ++#define do_div64_32(res, high, low, base) ({ \ ++ unsigned long __quot, __mod; \ ++ unsigned long __cf, __tmp, __i; \ ++ \ ++ __asm__(".set push\n\t" \ ++ ".set noat\n\t" \ ++ ".set noreorder\n\t" \ ++ "b 1f\n\t" \ ++ " li %4,0x21\n" \ ++ "0:\n\t" \ ++ "sll $1,%0,0x1\n\t" \ ++ "srl %3,%0,0x1f\n\t" \ ++ "or %0,$1,$2\n\t" \ ++ "sll %1,%1,0x1\n\t" \ ++ "sll %2,%2,0x1\n" \ ++ "1:\n\t" \ ++ "bnez %3,2f\n\t" \ ++ "sltu $2,%0,%z5\n\t" \ ++ "bnez $2,3f\n\t" \ ++ "2:\n\t" \ ++ " addiu %4,%4,-1\n\t" \ ++ "subu %0,%0,%z5\n\t" \ ++ "addiu %2,%2,1\n" \ ++ "3:\n\t" \ ++ "bnez %4,0b\n\t" \ ++ " srl $2,%1,0x1f\n\t" \ ++ ".set pop" \ ++ : "=&r" (__mod), "=&r" (__tmp), "=&r" (__quot), "=&r" (__cf), \ ++ "=&r" (__i) \ ++ : "Jr" (base), "0" (high), "1" (low), "2" (0), "3" (0) \ ++ /* Aarrgh! Ran out of gcc's limit on constraints... */ \ ++ : "$1", "$2"); \ ++ \ ++ (res) = __quot; \ ++ __mod; }) ++ ++#define do_div(n, base) ({ \ ++ unsigned long long __quot; \ ++ unsigned long __upper, __low, __high, __mod; \ ++ \ ++ __quot = (n); \ ++ __high = __quot >> 32; \ ++ __low = __quot; \ ++ __upper = __high; \ ++ \ ++ if (__high) \ ++ __asm__("divu $0,%z2,%z3" \ ++ : "=h" (__upper), "=l" (__high) \ ++ : "Jr" (__high), "Jr" (base)); \ ++ \ ++ __mod = do_div64_32(__low, __upper, __low, base); \ ++ \ ++ __quot = __high; \ ++ __quot = __quot << 32 | __low; \ ++ (n) = __quot; \ ++ __mod; }) ++ ++#else ++ ++#define do_div64_32(res, high, low, base) ({ \ ++ unsigned long __quot, __mod, __r0; \ ++ \ ++ __asm__("dsll32 %2,%z3,0\n\t" \ ++ "or %2,%2,%z4\n\t" \ ++ "ddivu $0,%2,%z5" \ ++ : "=h" (__mod), "=l" (__quot), "=&r" (__r0) \ ++ : "Jr" (high), "Jr" (low), "Jr" (base)); \ ++ \ ++ (res) = __quot; \ ++ __mod; }) ++ ++#define do_div(n, base) ({ \ ++ unsigned long long __quot; \ ++ unsigned long __mod, __r0; \ ++ \ ++ __quot = (n); \ ++ \ ++ __asm__("dsll32 %2,%M3,0\n\t" \ ++ "or %2,%2,%L3\n\t" \ ++ "ddivu $0,%2,%z4\n\t" \ ++ "mflo %L1\n\t" \ ++ "dsra32 %M1,%L1,0\n\t" \ ++ "dsll32 %L1,%L1,0\n\t" \ ++ "dsra32 %L1,%L1,0" \ ++ : "=h" (__mod), "=r" (__quot), "=&r" (__r0) \ ++ : "r" (n), "Jr" (base)); \ ++ \ ++ (n) = __quot; \ ++ __mod; }) ++ ++#endif + + #endif /* _ASM_DIV64_H */ +diff -ruN linux/include/asm-mips/fcntl.h linux-mips/include/asm-mips/fcntl.h +--- linux/include/asm-mips/fcntl.h Thu Nov 23 15:51:49 2000 ++++ linux-mips/include/asm-mips/fcntl.h Fri Nov 10 00:11:44 2000 +@@ -1,13 +1,12 @@ +-/* $Id: fcntl.h,v 1.4 1998/09/19 19:19:36 ralf Exp $ +- * ++/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995, 1996, 1997, 1998 by Ralf Baechle + */ +-#ifndef __ASM_MIPS_FCNTL_H +-#define __ASM_MIPS_FCNTL_H ++#ifndef __ASM_FCNTL_H ++#define __ASM_FCNTL_H + + /* open/fcntl - O_SYNC is only implemented on blocks devices and on files + located on an ext2 file system */ +@@ -44,6 +43,10 @@ + #define F_SETSIG 10 /* for sockets. */ + #define F_GETSIG 11 /* for sockets. */ + ++#define F_GETLK64 33 /* using 'struct flock64' */ ++#define F_SETLK64 34 ++#define F_SETLKW64 35 ++ + /* for F_[GET|SET]FL */ + #define FD_CLOEXEC 1 /* actually anything with low bit set goes */ + +@@ -76,10 +79,19 @@ + short l_whence; + __kernel_off_t l_start; + __kernel_off_t l_len; +- long l_sysid; /* XXXXXXXXXXXXXXXXXXXXXXXXX */ ++ long l_sysid; /* ABI junk, unused on Linux */ + __kernel_pid_t l_pid; +- long pad[4]; /* ZZZZZZZZZZZZZZZZZZZZZZZZZZ */ ++ long pad[4]; /* ABI junk, unused on Linux */ + } flock_t; + ++typedef struct flock64 { ++ short l_type; ++ short l_whence; ++ loff_t l_start; ++ loff_t l_len; ++ pid_t l_pid; ++} flock64_t; ++ + #define F_LINUX_SPECIFIC_BASE 1024 +-#endif /* __ASM_MIPS_FCNTL_H */ ++ ++#endif /* __ASM_FCNTL_H */ +diff -ruN linux/include/asm-mips/galileo-boards/ev96100.h linux-mips/include/asm-mips/galileo-boards/ev96100.h +--- linux/include/asm-mips/galileo-boards/ev96100.h Wed Dec 31 16:00:00 1969 ++++ linux-mips/include/asm-mips/galileo-boards/ev96100.h Fri Nov 10 00:12:16 2000 +@@ -0,0 +1,55 @@ ++/* ++ * ++ */ ++#ifndef _MIPS_EV96100_H ++#define _MIPS_EV96100_H ++ ++#include ++ ++/* ++ * GT64120 config space base address ++ */ ++#define GT64120_BASE (KSEG1ADDR(0x14000000)) ++#define MIPS_GT_BASE GT64120_BASE ++ ++/* ++ * PCI Bus allocation ++ */ ++#define GT_PCI_MEM_BASE 0x12000000 ++#define GT_PCI_MEM_SIZE 0x02000000 ++#define GT_PCI_IO_BASE 0x10000000 ++#define GT_PCI_IO_SIZE 0x02000000 ++#define GT_ISA_IO_BASE PCI_IO_BASE ++ ++/* ++ * Duart I/O ports. ++ */ ++#define EV96100_COM1_BASE_ADDR (0x1d000000 + 0x20) ++#define EV96100_COM2_BASE_ADDR (0x1d000000 + 0x00) ++ ++ ++/* ++ * EV96100 interrupt controller register base. ++ */ ++#define EV96100_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000)) ++ ++/* ++ * EV96100 UART register base. ++ */ ++#define EV96100_UART0_REGS_BASE (KSEG1ADDR(EV96100_COM1_BASE_ADDR)) ++#define EV96100_UART1_REGS_BASE (KSEG1ADDR(EV96100_COM2_BASE_ADDR)) ++#define EV96100_BASE_BAUD ( 3686400 / 16 ) ++ ++ ++/* ++ * Because of an error/peculiarity in the Galileo chip, we need to swap the ++ * bytes when running bigendian. ++ */ ++ ++#define GT_WRITE(ofs, data) \ ++ *(volatile u32 *)(MIPS_GT_BASE+ofs) = cpu_to_le32(data) ++#define GT_READ(ofs, data) \ ++ data = le32_to_cpu(*(volatile u32 *)(MIPS_GT_BASE+ofs)) ++ ++ ++#endif /* !(_MIPS_EV96100_H) */ +diff -ruN linux/include/asm-mips/galileo-boards/ev96100int.h linux-mips/include/asm-mips/galileo-boards/ev96100int.h +--- linux/include/asm-mips/galileo-boards/ev96100int.h Wed Dec 31 16:00:00 1969 ++++ linux-mips/include/asm-mips/galileo-boards/ev96100int.h Fri Nov 10 00:12:16 2000 +@@ -0,0 +1,12 @@ ++/* ++ * ++ */ ++#ifndef _MIPS_EV96100INT_H ++#define _MIPS_EV96100INT_H ++ ++#define EV96100INT_UART_0 6 /* IP 6 */ ++#define EV96100INT_TIMER 7 /* IP 7 */ ++ ++extern void ev96100int_init(void); ++ ++#endif /* !(_MIPS_EV96100_H) */ +diff -ruN linux/include/asm-mips/galileo-boards/gt64120.h linux-mips/include/asm-mips/galileo-boards/gt64120.h +--- linux/include/asm-mips/galileo-boards/gt64120.h Wed Dec 31 16:00:00 1969 ++++ linux-mips/include/asm-mips/galileo-boards/gt64120.h Fri Nov 10 00:12:17 2000 +@@ -0,0 +1,320 @@ ++/* ++ * Carsten Langgaard, carstenl@mips.com ++ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. ++ * ++ * ######################################################################## ++ * ++ * This program is free software; you can distribute it and/or modify it ++ * under the terms of the GNU General Public License (Version 2) as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. ++ * ++ * ######################################################################## ++ * ++ * Register definitions for Galileo 64120 system controller. ++ * ++ */ ++#ifndef GT64120_H ++#define GT64120_H ++ ++#define MSK(n) ((1 << (n)) - 1) ++ ++/************************************************************************ ++ * Register offset addresses ++ ************************************************************************/ ++ ++#define GT_CPU_OFS 0x000 ++ ++#define GT_INTRCAUSE_OFS 0xc18 ++#define GT_PCI0_CFGADDR_OFS 0xcf8 ++#define GT_PCI0_CFGDATA_OFS 0xcfc ++#define GT_SDRAM_BM_OFS 0x478 ++#define GT_SDRAM_ADDRDECODE_OFS 0x47c ++#define GT_SDRAM_B0_OFS 0x44c ++#define GT_SDRAM_B2_OFS 0x454 ++#define GT_SDRAM_CFG_OFS 0x448 ++#define GT_SDRAM_OPMODE_OFS 0x474 ++ ++#define GT_ISD_OFS 0x068 ++ ++#define GT_SCS10LD_OFS 0x008 ++#define GT_SCS10HD_OFS 0x010 ++#define GT_SCS32LD_OFS 0x018 ++#define GT_SCS32HD_OFS 0x020 ++#define GT_CS20LD_OFS 0x028 ++#define GT_CS20HD_OFS 0x030 ++#define GT_CS3BOOTLD_OFS 0x038 ++#define GT_CS3BOOTHD_OFS 0x040 ++#define GT_PCI0IOLD_OFS 0x048 ++#define GT_PCI0IOHD_OFS 0x050 ++#define GT_PCI0M0LD_OFS 0x058 ++#define GT_PCI0M0HD_OFS 0x060 ++#define GT_PCI0M1LD_OFS 0x080 ++#define GT_PCI0M1HD_OFS 0x088 ++#define GT_PCI1IOLD_OFS 0x090 ++#define GT_PCI1IOHD_OFS 0x098 ++#define GT_PCI1M0LD_OFS 0x0a0 ++#define GT_PCI1M0HD_OFS 0x0a8 ++#define GT_PCI1M1LD_OFS 0x0b0 ++#define GT_PCI1M1HD_OFS 0x0b8 ++ ++#define GT_SCS0LD_OFS 0x400 ++#define GT_SCS0HD_OFS 0x404 ++#define GT_SCS1LD_OFS 0x408 ++#define GT_SCS1HD_OFS 0x40c ++#define GT_SCS2LD_OFS 0x410 ++#define GT_SCS2HD_OFS 0x414 ++#define GT_SCS3LD_OFS 0x418 ++#define GT_SCS3HD_OFS 0x41c ++#define GT_CS0LD_OFS 0x420 ++#define GT_CS0HD_OFS 0x424 ++#define GT_CS1LD_OFS 0x428 ++#define GT_CS1HD_OFS 0x42c ++#define GT_CS2LD_OFS 0x430 ++#define GT_CS2HD_OFS 0x434 ++#define GT_CS3LD_OFS 0x438 ++#define GT_CS3HD_OFS 0x43c ++#define GT_BOOTLD_OFS 0x440 ++#define GT_BOOTHD_OFS 0x444 ++ ++#define GT_PCI0_BS_SCS10_OFS 0Xc08 ++#define GT_PCI0_BS_SCS32_OFS 0xc0c ++#define GT_PCI0_BARE_OFS 0Xc3c ++ ++#define GT_PCI0_TOR_OFS 0xc04 ++ ++#define GT_PCI0_IACK_OFS 0xc34 ++ ++ ++/************************************************************************ ++ * Register encodings ++ ************************************************************************/ ++ ++#define GT_CPU_WR_SHF 16 ++#define GT_CPU_WR_MSK (MSK(1) << GT_CPU_WR_SHF) ++#define GT_CPU_WR_BIT GT_CPU_WR_MSK ++#define GT_CPU_WR_DXDXDXDX 0 ++#define GT_CPU_WR_DDDD 1 ++ ++ ++#define GT_CFGADDR_CFGEN_SHF 31 ++#define GT_CFGADDR_CFGEN_MSK (MSK(1) << GT_CFGADDR_CFGEN_SHF) ++#define GT_CFGADDR_CFGEN_BIT GT_CFGADDR_CFGEN_MSK ++ ++#define GT_CFGADDR_BUSNUM_SHF 16 ++#define GT_CFGADDR_BUSNUM_MSK (MSK(8) << GT_CFGADDR_BUSNUM_SHF) ++ ++#define GT_CFGADDR_DEVNUM_SHF 11 ++#define GT_CFGADDR_DEVNUM_MSK (MSK(5) << GT_CFGADDR_DEVNUM_SHF) ++ ++#define GT_CFGADDR_FUNCNUM_SHF 8 ++#define GT_CFGADDR_FUNCNUM_MSK (MSK(3) << GT_CFGADDR_FUNCNUM_SHF) ++ ++#define GT_CFGADDR_REGNUM_SHF 2 ++#define GT_CFGADDR_REGNUM_MSK (MSK(6) << GT_CFGADDR_REGNUM_SHF) ++ ++ ++#define GT_SDRAM_BM_ORDER_SHF 2 ++#define GT_SDRAM_BM_ORDER_MSK (MSK(1) << GT_SDRAM_BM_ORDER_SHF) ++#define GT_SDRAM_BM_ORDER_BIT GT_SDRAM_BM_ORDER_MSK ++#define GT_SDRAM_BM_ORDER_SUB 1 ++#define GT_SDRAM_BM_ORDER_LIN 0 ++ ++#define GT_SDRAM_BM_RSVD_ALL1 0xFFB ++ ++ ++#define GT_SDRAM_ADDRDECODE_ADDR_SHF 0 ++#define GT_SDRAM_ADDRDECODE_ADDR_MSK (MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF) ++#define GT_SDRAM_ADDRDECODE_ADDR_0 0 ++#define GT_SDRAM_ADDRDECODE_ADDR_1 1 ++#define GT_SDRAM_ADDRDECODE_ADDR_2 2 ++#define GT_SDRAM_ADDRDECODE_ADDR_3 3 ++#define GT_SDRAM_ADDRDECODE_ADDR_4 4 ++#define GT_SDRAM_ADDRDECODE_ADDR_5 5 ++#define GT_SDRAM_ADDRDECODE_ADDR_6 6 ++#define GT_SDRAM_ADDRDECODE_ADDR_7 7 ++ ++ ++#define GT_SDRAM_B0_CASLAT_SHF 0 ++#define GT_SDRAM_B0_CASLAT_MSK (MSK(2) << GT_SDRAM_B0__SHF) ++#define GT_SDRAM_B0_CASLAT_2 1 ++#define GT_SDRAM_B0_CASLAT_3 2 ++ ++#define GT_SDRAM_B0_FTDIS_SHF 2 ++#define GT_SDRAM_B0_FTDIS_MSK (MSK(1) << GT_SDRAM_B0_FTDIS_SHF) ++#define GT_SDRAM_B0_FTDIS_BIT GT_SDRAM_B0_FTDIS_MSK ++ ++#define GT_SDRAM_B0_SRASPRCHG_SHF 3 ++#define GT_SDRAM_B0_SRASPRCHG_MSK (MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF) ++#define GT_SDRAM_B0_SRASPRCHG_BIT GT_SDRAM_B0_SRASPRCHG_MSK ++#define GT_SDRAM_B0_SRASPRCHG_2 0 ++#define GT_SDRAM_B0_SRASPRCHG_3 1 ++ ++#define GT_SDRAM_B0_B0COMPAB_SHF 4 ++#define GT_SDRAM_B0_B0COMPAB_MSK (MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF) ++#define GT_SDRAM_B0_B0COMPAB_BIT GT_SDRAM_B0_B0COMPAB_MSK ++ ++#define GT_SDRAM_B0_64BITINT_SHF 5 ++#define GT_SDRAM_B0_64BITINT_MSK (MSK(1) << GT_SDRAM_B0_64BITINT_SHF) ++#define GT_SDRAM_B0_64BITINT_BIT GT_SDRAM_B0_64BITINT_MSK ++#define GT_SDRAM_B0_64BITINT_2 0 ++#define GT_SDRAM_B0_64BITINT_4 1 ++ ++#define GT_SDRAM_B0_BW_SHF 6 ++#define GT_SDRAM_B0_BW_MSK (MSK(1) << GT_SDRAM_B0_BW_SHF) ++#define GT_SDRAM_B0_BW_BIT GT_SDRAM_B0_BW_MSK ++#define GT_SDRAM_B0_BW_32 0 ++#define GT_SDRAM_B0_BW_64 1 ++ ++#define GT_SDRAM_B0_BLODD_SHF 7 ++#define GT_SDRAM_B0_BLODD_MSK (MSK(1) << GT_SDRAM_B0_BLODD_SHF) ++#define GT_SDRAM_B0_BLODD_BIT GT_SDRAM_B0_BLODD_MSK ++ ++#define GT_SDRAM_B0_PAR_SHF 8 ++#define GT_SDRAM_B0_PAR_MSK (MSK(1) << GT_SDRAM_B0_PAR_SHF) ++#define GT_SDRAM_B0_PAR_BIT GT_SDRAM_B0_PAR_MSK ++ ++#define GT_SDRAM_B0_BYPASS_SHF 9 ++#define GT_SDRAM_B0_BYPASS_MSK (MSK(1) << GT_SDRAM_B0_BYPASS_SHF) ++#define GT_SDRAM_B0_BYPASS_BIT GT_SDRAM_B0_BYPASS_MSK ++ ++#define GT_SDRAM_B0_SRAS2SCAS_SHF 10 ++#define GT_SDRAM_B0_SRAS2SCAS_MSK (MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF) ++#define GT_SDRAM_B0_SRAS2SCAS_BIT GT_SDRAM_B0_SRAS2SCAS_MSK ++#define GT_SDRAM_B0_SRAS2SCAS_2 0 ++#define GT_SDRAM_B0_SRAS2SCAS_3 1 ++ ++#define GT_SDRAM_B0_SIZE_SHF 11 ++#define GT_SDRAM_B0_SIZE_MSK (MSK(1) << GT_SDRAM_B0_SIZE_SHF) ++#define GT_SDRAM_B0_SIZE_BIT GT_SDRAM_B0_SIZE_MSK ++#define GT_SDRAM_B0_SIZE_16M 0 ++#define GT_SDRAM_B0_SIZE_64M 1 ++ ++#define GT_SDRAM_B0_EXTPAR_SHF 12 ++#define GT_SDRAM_B0_EXTPAR_MSK (MSK(1) << GT_SDRAM_B0_EXTPAR_SHF) ++#define GT_SDRAM_B0_EXTPAR_BIT GT_SDRAM_B0_EXTPAR_MSK ++ ++#define GT_SDRAM_B0_BLEN_SHF 13 ++#define GT_SDRAM_B0_BLEN_MSK (MSK(1) << GT_SDRAM_B0_BLEN_SHF) ++#define GT_SDRAM_B0_BLEN_BIT GT_SDRAM_B0_BLEN_MSK ++#define GT_SDRAM_B0_BLEN_8 0 ++#define GT_SDRAM_B0_BLEN_4 1 ++ ++ ++#define GT_SDRAM_CFG_REFINT_SHF 0 ++#define GT_SDRAM_CFG_REFINT_MSK (MSK(14) << GT_SDRAM_CFG_REFINT_SHF) ++ ++#define GT_SDRAM_CFG_NINTERLEAVE_SHF 14 ++#define GT_SDRAM_CFG_NINTERLEAVE_MSK (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF) ++#define GT_SDRAM_CFG_NINTERLEAVE_BIT GT_SDRAM_CFG_NINTERLEAVE_MSK ++ ++#define GT_SDRAM_CFG_RMW_SHF 15 ++#define GT_SDRAM_CFG_RMW_MSK (MSK(1) << GT_SDRAM_CFG_RMW_SHF) ++#define GT_SDRAM_CFG_RMW_BIT GT_SDRAM_CFG_RMW_MSK ++ ++#define GT_SDRAM_CFG_NONSTAGREF_SHF 16 ++#define GT_SDRAM_CFG_NONSTAGREF_MSK (MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF) ++#define GT_SDRAM_CFG_NONSTAGREF_BIT GT_SDRAM_CFG_NONSTAGREF_MSK ++ ++#define GT_SDRAM_CFG_DUPCNTL_SHF 19 ++#define GT_SDRAM_CFG_DUPCNTL_MSK (MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF) ++#define GT_SDRAM_CFG_DUPCNTL_BIT GT_SDRAM_CFG_DUPCNTL_MSK ++ ++#define GT_SDRAM_CFG_DUPBA_SHF 20 ++#define GT_SDRAM_CFG_DUPBA_MSK (MSK(1) << GT_SDRAM_CFG_DUPBA_SHF) ++#define GT_SDRAM_CFG_DUPBA_BIT GT_SDRAM_CFG_DUPBA_MSK ++ ++#define GT_SDRAM_CFG_DUPEOT0_SHF 21 ++#define GT_SDRAM_CFG_DUPEOT0_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF) ++#define GT_SDRAM_CFG_DUPEOT0_BIT GT_SDRAM_CFG_DUPEOT0_MSK ++ ++#define GT_SDRAM_CFG_DUPEOT1_SHF 22 ++#define GT_SDRAM_CFG_DUPEOT1_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF) ++#define GT_SDRAM_CFG_DUPEOT1_BIT GT_SDRAM_CFG_DUPEOT1_MSK ++ ++#define GT_SDRAM_OPMODE_OP_SHF 0 ++#define GT_SDRAM_OPMODE_OP_MSK (MSK(3) << GT_SDRAM_OPMODE_OP_SHF) ++#define GT_SDRAM_OPMODE_OP_NORMAL 0 ++#define GT_SDRAM_OPMODE_OP_NOP 1 ++#define GT_SDRAM_OPMODE_OP_PRCHG 2 ++#define GT_SDRAM_OPMODE_OP_MODE 3 ++#define GT_SDRAM_OPMODE_OP_CBR 4 ++ ++ ++#define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0 ++#define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF) ++#define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT GT_PCI0_BARE_SWSCS3BOOTDIS_MSK ++ ++#define GT_PCI0_BARE_SWSCS32DIS_SHF 1 ++#define GT_PCI0_BARE_SWSCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF) ++#define GT_PCI0_BARE_SWSCS32DIS_BIT GT_PCI0_BARE_SWSCS32DIS_MSK ++ ++#define GT_PCI0_BARE_SWSCS10DIS_SHF 2 ++#define GT_PCI0_BARE_SWSCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF) ++#define GT_PCI0_BARE_SWSCS10DIS_BIT GT_PCI0_BARE_SWSCS10DIS_MSK ++ ++#define GT_PCI0_BARE_INTIODIS_SHF 3 ++#define GT_PCI0_BARE_INTIODIS_MSK (MSK(1) << GT_PCI0_BARE_INTIODIS_SHF) ++#define GT_PCI0_BARE_INTIODIS_BIT GT_PCI0_BARE_INTIODIS_MSK ++ ++#define GT_PCI0_BARE_INTMEMDIS_SHF 4 ++#define GT_PCI0_BARE_INTMEMDIS_MSK (MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF) ++#define GT_PCI0_BARE_INTMEMDIS_BIT GT_PCI0_BARE_INTMEMDIS_MSK ++ ++#define GT_PCI0_BARE_CS3BOOTDIS_SHF 5 ++#define GT_PCI0_BARE_CS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF) ++#define GT_PCI0_BARE_CS3BOOTDIS_BIT GT_PCI0_BARE_CS3BOOTDIS_MSK ++ ++#define GT_PCI0_BARE_CS20DIS_SHF 6 ++#define GT_PCI0_BARE_CS20DIS_MSK (MSK(1) << GT_PCI0_BARE_CS20DIS_SHF) ++#define GT_PCI0_BARE_CS20DIS_BIT GT_PCI0_BARE_CS20DIS_MSK ++ ++#define GT_PCI0_BARE_SCS32DIS_SHF 7 ++#define GT_PCI0_BARE_SCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF) ++#define GT_PCI0_BARE_SCS32DIS_BIT GT_PCI0_BARE_SCS32DIS_MSK ++ ++#define GT_PCI0_BARE_SCS10DIS_SHF 8 ++#define GT_PCI0_BARE_SCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF) ++#define GT_PCI0_BARE_SCS10DIS_BIT GT_PCI0_BARE_SCS10DIS_MSK ++ ++ ++#define GT_INTRCAUSE_MASABORT0_SHF 18 ++#define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF) ++#define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK ++ ++#define GT_INTRCAUSE_TARABORT0_SHF 19 ++#define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF) ++#define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK ++ ++ ++#define GT_PCI0_CFGADDR_REGNUM_SHF 2 ++#define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF) ++#define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8 ++#define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF) ++#define GT_PCI0_CFGADDR_DEVNUM_SHF 11 ++#define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF) ++#define GT_PCI0_CFGADDR_BUSNUM_SHF 16 ++#define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF) ++#define GT_PCI0_CFGADDR_CONFIGEN_SHF 31 ++#define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF) ++#define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK ++ ++ ++/************************************************************************ ++ * Misc ++ ************************************************************************/ ++ ++#define GT_DEF_BASE 0x14000000 ++#define GT_DEF_PCI0_MEM0_BASE 0x12000000 ++#define GT_MAX_BANKSIZE (256 * 1024 * 1024) /* Max 256MB bank */ ++#define GT_LATTIM_MIN 6 /* Minimum lat */ ++ ++#endif /* #ifndef GT64120_H */ +diff -ruN linux/include/asm-mips/galileo-boards/gt96100.h linux-mips/include/asm-mips/galileo-boards/gt96100.h +--- linux/include/asm-mips/galileo-boards/gt96100.h Wed Dec 31 16:00:00 1969 ++++ linux-mips/include/asm-mips/galileo-boards/gt96100.h Fri Nov 10 00:12:18 2000 +@@ -0,0 +1,432 @@ ++/* ++ * Copyright 2000 MontaVista Software Inc. ++ * Author: MontaVista Software, Inc. ++ * stevel@mvista.com or support@mvista.com ++ * ++ * ######################################################################## ++ * ++ * This program is free software; you can distribute it and/or modify it ++ * under the terms of the GNU General Public License (Version 2) as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. ++ * ++ * ######################################################################## ++ * ++ * Register offsets of the MIPS GT96100 Advanced Communication Controller. ++ * ++ */ ++#ifndef _GT96100_H ++#define _GT96100_H ++ ++/* ++ * Galileo GT96100 internal register base. ++ */ ++#define MIPS_GT96100_BASE (KSEG1ADDR(0x14000000)) ++ ++#define GT96100_WRITE(ofs, data) \ ++ *(volatile u32 *)(MIPS_GT96100_BASE+ofs) = cpu_to_le32(data) ++#define GT96100_READ(ofs) \ ++ le32_to_cpu(*(volatile u32 *)(MIPS_GT96100_BASE+ofs)) ++ ++#define GT96100_ETH_IO_SIZE 0x4000 ++ ++/************************************************************************ ++ * Register offset addresses follow ++ ************************************************************************/ ++ ++/* CPU Interface Control Registers */ ++#define GT96100_CPU_INTERF_CONFIG 0x000000 ++ ++/* Ethernet Ports */ ++#define GT96100_ETH_PHY_ADDR_REG 0x080800 ++#define GT96100_ETH_SMI_REG 0x080810 ++/* ++ These are offsets to port 0 registers. Add GT96100_ETH_IO_SIZE to ++ get offsets to port 1 registers. ++*/ ++#define GT96100_ETH_PORT_CONFIG 0x084800 ++#define GT96100_ETH_PORT_CONFIG_EXT 0x084808 ++#define GT96100_ETH_PORT_COMM 0x084810 ++#define GT96100_ETH_PORT_STATUS 0x084818 ++#define GT96100_ETH_SER_PARAM 0x084820 ++#define GT96100_ETH_HASH_TBL_PTR 0x084828 ++#define GT96100_ETH_FLOW_CNTRL_SRC_ADDR_L 0x084830 ++#define GT96100_ETH_FLOW_CNTRL_SRC_ADDR_H 0x084838 ++#define GT96100_ETH_SDMA_CONFIG 0x084840 ++#define GT96100_ETH_SDMA_COMM 0x084848 ++#define GT96100_ETH_INT_CAUSE 0x084850 ++#define GT96100_ETH_INT_MASK 0x084858 ++#define GT96100_ETH_1ST_RX_DESC_PTR0 0x084880 ++#define GT96100_ETH_1ST_RX_DESC_PTR1 0x084884 ++#define GT96100_ETH_1ST_RX_DESC_PTR2 0x084888 ++#define GT96100_ETH_1ST_RX_DESC_PTR3 0x08488C ++#define GT96100_ETH_CURR_RX_DESC_PTR0 0x0848A0 ++#define GT96100_ETH_CURR_RX_DESC_PTR1 0x0848A4 ++#define GT96100_ETH_CURR_RX_DESC_PTR2 0x0848A8 ++#define GT96100_ETH_CURR_RX_DESC_PTR3 0x0848AC ++#define GT96100_ETH_CURR_TX_DESC_PTR0 0x0848E0 ++#define GT96100_ETH_CURR_TX_DESC_PTR1 0x0848E4 ++#define GT96100_ETH_MIB_COUNT_BASE 0x085800 ++ ++/* SDMAs */ ++#define GT96100_SDMA_GROUP_CONFIG 0x101AF0 ++/* SDMA Group 0 */ ++#define GT96100_SDMA_G0_CHAN0_CONFIG 0x000900 ++#define GT96100_SDMA_G0_CHAN0_COMM 0x000908 ++#define GT96100_SDMA_G0_CHAN0_RX_DESC_BASE 0x008900 ++#define GT96100_SDMA_G0_CHAN0_CURR_RX_DESC_PTR 0x008910 ++#define GT96100_SDMA_G0_CHAN0_TX_DESC_BASE 0x00C900 ++#define GT96100_SDMA_G0_CHAN0_CURR_TX_DESC_PTR 0x00C910 ++#define GT96100_SDMA_G0_CHAN0_1ST_TX_DESC_PTR 0x00C914 ++#define GT96100_SDMA_G0_CHAN1_CONFIG 0x010900 ++#define GT96100_SDMA_G0_CHAN1_COMM 0x010908 ++#define GT96100_SDMA_G0_CHAN1_RX_DESC_BASE 0x018900 ++#define GT96100_SDMA_G0_CHAN1_CURR_RX_DESC_PTR 0x018910 ++#define GT96100_SDMA_G0_CHAN1_TX_DESC_BASE 0x01C900 ++#define GT96100_SDMA_G0_CHAN1_CURR_TX_DESC_PTR 0x01C910 ++#define GT96100_SDMA_G0_CHAN1_1ST_TX_DESC_PTR 0x01C914 ++#define GT96100_SDMA_G0_CHAN2_CONFIG 0x020900 ++#define GT96100_SDMA_G0_CHAN2_COMM 0x020908 ++#define GT96100_SDMA_G0_CHAN2_RX_DESC_BASE 0x028900 ++#define GT96100_SDMA_G0_CHAN2_CURR_RX_DESC_PTR 0x028910 ++#define GT96100_SDMA_G0_CHAN2_TX_DESC_BASE 0x02C900 ++#define GT96100_SDMA_G0_CHAN2_CURR_TX_DESC_PTR 0x02C910 ++#define GT96100_SDMA_G0_CHAN2_1ST_TX_DESC_PTR 0x02C914 ++#define GT96100_SDMA_G0_CHAN3_CONFIG 0x030900 ++#define GT96100_SDMA_G0_CHAN3_COMM 0x030908 ++#define GT96100_SDMA_G0_CHAN3_RX_DESC_BASE 0x038900 ++#define GT96100_SDMA_G0_CHAN3_CURR_RX_DESC_PTR 0x038910 ++#define GT96100_SDMA_G0_CHAN3_TX_DESC_BASE 0x03C900 ++#define GT96100_SDMA_G0_CHAN3_CURR_TX_DESC_PTR 0x03C910 ++#define GT96100_SDMA_G0_CHAN3_1ST_TX_DESC_PTR 0x03C914 ++#define GT96100_SDMA_G0_CHAN4_CONFIG 0x040900 ++#define GT96100_SDMA_G0_CHAN4_COMM 0x040908 ++#define GT96100_SDMA_G0_CHAN4_RX_DESC_BASE 0x048900 ++#define GT96100_SDMA_G0_CHAN4_CURR_RX_DESC_PTR 0x048910 ++#define GT96100_SDMA_G0_CHAN4_TX_DESC_BASE 0x04C900 ++#define GT96100_SDMA_G0_CHAN4_CURR_TX_DESC_PTR 0x04C910 ++#define GT96100_SDMA_G0_CHAN4_1ST_TX_DESC_PTR 0x04C914 ++#define GT96100_SDMA_G0_CHAN5_CONFIG 0x050900 ++#define GT96100_SDMA_G0_CHAN5_COMM 0x050908 ++#define GT96100_SDMA_G0_CHAN5_RX_DESC_BASE 0x058900 ++#define GT96100_SDMA_G0_CHAN5_CURR_RX_DESC_PTR 0x058910 ++#define GT96100_SDMA_G0_CHAN5_TX_DESC_BASE 0x05C900 ++#define GT96100_SDMA_G0_CHAN5_CURR_TX_DESC_PTR 0x05C910 ++#define GT96100_SDMA_G0_CHAN5_1ST_TX_DESC_PTR 0x05C914 ++#define GT96100_SDMA_G0_CHAN6_CONFIG 0x060900 ++#define GT96100_SDMA_G0_CHAN6_COMM 0x060908 ++#define GT96100_SDMA_G0_CHAN6_RX_DESC_BASE 0x068900 ++#define GT96100_SDMA_G0_CHAN6_CURR_RX_DESC_PTR 0x068910 ++#define GT96100_SDMA_G0_CHAN6_TX_DESC_BASE 0x06C900 ++#define GT96100_SDMA_G0_CHAN6_CURR_TX_DESC_PTR 0x06C910 ++#define GT96100_SDMA_G0_CHAN6_1ST_TX_DESC_PTR 0x06C914 ++#define GT96100_SDMA_G0_CHAN7_CONFIG 0x070900 ++#define GT96100_SDMA_G0_CHAN7_COMM 0x070908 ++#define GT96100_SDMA_G0_CHAN7_RX_DESC_BASE 0x078900 ++#define GT96100_SDMA_G0_CHAN7_CURR_RX_DESC_PTR 0x078910 ++#define GT96100_SDMA_G0_CHAN7_TX_DESC_BASE 0x07C900 ++#define GT96100_SDMA_G0_CHAN7_CURR_TX_DESC_PTR 0x07C910 ++#define GT96100_SDMA_G0_CHAN7_1ST_TX_DESC_PTR 0x07C914 ++/* SDMA Group 1 */ ++#define GT96100_SDMA_G1_CHAN0_CONFIG 0x100900 ++#define GT96100_SDMA_G1_CHAN0_COMM 0x100908 ++#define GT96100_SDMA_G1_CHAN0_RX_DESC_BASE 0x108900 ++#define GT96100_SDMA_G1_CHAN0_CURR_RX_DESC_PTR 0x108910 ++#define GT96100_SDMA_G1_CHAN0_TX_DESC_BASE 0x10C900 ++#define GT96100_SDMA_G1_CHAN0_CURR_TX_DESC_PTR 0x10C910 ++#define GT96100_SDMA_G1_CHAN0_1ST_TX_DESC_PTR 0x10C914 ++#define GT96100_SDMA_G1_CHAN1_CONFIG 0x110900 ++#define GT96100_SDMA_G1_CHAN1_COMM 0x110908 ++#define GT96100_SDMA_G1_CHAN1_RX_DESC_BASE 0x118900 ++#define GT96100_SDMA_G1_CHAN1_CURR_RX_DESC_PTR 0x118910 ++#define GT96100_SDMA_G1_CHAN1_TX_DESC_BASE 0x11C900 ++#define GT96100_SDMA_G1_CHAN1_CURR_TX_DESC_PTR 0x11C910 ++#define GT96100_SDMA_G1_CHAN1_1ST_TX_DESC_PTR 0x11C914 ++#define GT96100_SDMA_G1_CHAN2_CONFIG 0x120900 ++#define GT96100_SDMA_G1_CHAN2_COMM 0x120908 ++#define GT96100_SDMA_G1_CHAN2_RX_DESC_BASE 0x128900 ++#define GT96100_SDMA_G1_CHAN2_CURR_RX_DESC_PTR 0x128910 ++#define GT96100_SDMA_G1_CHAN2_TX_DESC_BASE 0x12C900 ++#define GT96100_SDMA_G1_CHAN2_CURR_TX_DESC_PTR 0x12C910 ++#define GT96100_SDMA_G1_CHAN2_1ST_TX_DESC_PTR 0x12C914 ++#define GT96100_SDMA_G1_CHAN3_CONFIG 0x130900 ++#define GT96100_SDMA_G1_CHAN3_COMM 0x130908 ++#define GT96100_SDMA_G1_CHAN3_RX_DESC_BASE 0x138900 ++#define GT96100_SDMA_G1_CHAN3_CURR_RX_DESC_PTR 0x138910 ++#define GT96100_SDMA_G1_CHAN3_TX_DESC_BASE 0x13C900 ++#define GT96100_SDMA_G1_CHAN3_CURR_TX_DESC_PTR 0x13C910 ++#define GT96100_SDMA_G1_CHAN3_1ST_TX_DESC_PTR 0x13C914 ++#define GT96100_SDMA_G1_CHAN4_CONFIG 0x140900 ++#define GT96100_SDMA_G1_CHAN4_COMM 0x140908 ++#define GT96100_SDMA_G1_CHAN4_RX_DESC_BASE 0x148900 ++#define GT96100_SDMA_G1_CHAN4_CURR_RX_DESC_PTR 0x148910 ++#define GT96100_SDMA_G1_CHAN4_TX_DESC_BASE 0x14C900 ++#define GT96100_SDMA_G1_CHAN4_CURR_TX_DESC_PTR 0x14C910 ++#define GT96100_SDMA_G1_CHAN4_1ST_TX_DESC_PTR 0x14C914 ++#define GT96100_SDMA_G1_CHAN5_CONFIG 0x150900 ++#define GT96100_SDMA_G1_CHAN5_COMM 0x150908 ++#define GT96100_SDMA_G1_CHAN5_RX_DESC_BASE 0x158900 ++#define GT96100_SDMA_G1_CHAN5_CURR_RX_DESC_PTR 0x158910 ++#define GT96100_SDMA_G1_CHAN5_TX_DESC_BASE 0x15C900 ++#define GT96100_SDMA_G1_CHAN5_CURR_TX_DESC_PTR 0x15C910 ++#define GT96100_SDMA_G1_CHAN5_1ST_TX_DESC_PTR 0x15C914 ++#define GT96100_SDMA_G1_CHAN6_CONFIG 0x160900 ++#define GT96100_SDMA_G1_CHAN6_COMM 0x160908 ++#define GT96100_SDMA_G1_CHAN6_RX_DESC_BASE 0x168900 ++#define GT96100_SDMA_G1_CHAN6_CURR_RX_DESC_PTR 0x168910 ++#define GT96100_SDMA_G1_CHAN6_TX_DESC_BASE 0x16C900 ++#define GT96100_SDMA_G1_CHAN6_CURR_TX_DESC_PTR 0x16C910 ++#define GT96100_SDMA_G1_CHAN6_1ST_TX_DESC_PTR 0x16C914 ++#define GT96100_SDMA_G1_CHAN7_CONFIG 0x170900 ++#define GT96100_SDMA_G1_CHAN7_COMM 0x170908 ++#define GT96100_SDMA_G1_CHAN7_RX_DESC_BASE 0x178900 ++#define GT96100_SDMA_G1_CHAN7_CURR_RX_DESC_PTR 0x178910 ++#define GT96100_SDMA_G1_CHAN7_TX_DESC_BASE 0x17C900 ++#define GT96100_SDMA_G1_CHAN7_CURR_TX_DESC_PTR 0x17C910 ++#define GT96100_SDMA_G1_CHAN7_1ST_TX_DESC_PTR 0x17C914 ++/* MPSCs */ ++#define GT96100_MPSC0_MAIN_CONFIG_LOW 0x000A00 ++#define GT96100_MPSC0_MAIN_CONFIG_HIGH 0x000A04 ++#define GT96100_MPSC0_PROTOCOL_CONFIG 0x000A08 ++#define GT96100_MPSC_CHAN0_REG1 0x000A0C ++#define GT96100_MPSC_CHAN0_REG2 0x000A10 ++#define GT96100_MPSC_CHAN0_REG3 0x000A14 ++#define GT96100_MPSC_CHAN0_REG4 0x000A18 ++#define GT96100_MPSC_CHAN0_REG5 0x000A1C ++#define GT96100_MPSC_CHAN0_REG6 0x000A20 ++#define GT96100_MPSC_CHAN0_REG7 0x000A24 ++#define GT96100_MPSC_CHAN0_REG8 0x000A28 ++#define GT96100_MPSC_CHAN0_REG9 0x000A2C ++#define GT96100_MPSC_CHAN0_REG10 0x000A30 ++#define GT96100_MPSC_CHAN0_REG11 0x000A34 ++#define GT96100_MPSC1_MAIN_CONFIG_LOW 0x008A00 ++#define GT96100_MPSC1_MAIN_CONFIG_HIGH 0x008A04 ++#define GT96100_MPSC1_PROTOCOL_CONFIG 0x008A08 ++#define GT96100_MPSC_CHAN1_REG1 0x008A0C ++#define GT96100_MPSC_CHAN1_REG2 0x008A10 ++#define GT96100_MPSC_CHAN1_REG3 0x008A14 ++#define GT96100_MPSC_CHAN1_REG4 0x008A18 ++#define GT96100_MPSC_CHAN1_REG5 0x008A1C ++#define GT96100_MPSC_CHAN1_REG6 0x008A20 ++#define GT96100_MPSC_CHAN1_REG7 0x008A24 ++#define GT96100_MPSC_CHAN1_REG8 0x008A28 ++#define GT96100_MPSC_CHAN1_REG9 0x008A2C ++#define GT96100_MPSC_CHAN1_REG10 0x008A30 ++#define GT96100_MPSC_CHAN1_REG11 0x008A34 ++#define GT96100_MPSC2_MAIN_CONFIG_LOW 0x010A00 ++#define GT96100_MPSC2_MAIN_CONFIG_HIGH 0x010A04 ++#define GT96100_MPSC2_PROTOCOL_CONFIG 0x010A08 ++#define GT96100_MPSC_CHAN2_REG1 0x010A0C ++#define GT96100_MPSC_CHAN2_REG2 0x010A10 ++#define GT96100_MPSC_CHAN2_REG3 0x010A14 ++#define GT96100_MPSC_CHAN2_REG4 0x010A18 ++#define GT96100_MPSC_CHAN2_REG5 0x010A1C ++#define GT96100_MPSC_CHAN2_REG6 0x010A20 ++#define GT96100_MPSC_CHAN2_REG7 0x010A24 ++#define GT96100_MPSC_CHAN2_REG8 0x010A28 ++#define GT96100_MPSC_CHAN2_REG9 0x010A2C ++#define GT96100_MPSC_CHAN2_REG10 0x010A30 ++#define GT96100_MPSC_CHAN2_REG11 0x010A34 ++#define GT96100_MPSC3_MAIN_CONFIG_LOW 0x018A00 ++#define GT96100_MPSC3_MAIN_CONFIG_HIGH 0x018A04 ++#define GT96100_MPSC3_PROTOCOL_CONFIG 0x018A08 ++#define GT96100_MPSC_CHAN3_REG1 0x018A0C ++#define GT96100_MPSC_CHAN3_REG2 0x018A10 ++#define GT96100_MPSC_CHAN3_REG3 0x018A14 ++#define GT96100_MPSC_CHAN3_REG4 0x018A18 ++#define GT96100_MPSC_CHAN3_REG5 0x018A1C ++#define GT96100_MPSC_CHAN3_REG6 0x018A20 ++#define GT96100_MPSC_CHAN3_REG7 0x018A24 ++#define GT96100_MPSC_CHAN3_REG8 0x018A28 ++#define GT96100_MPSC_CHAN3_REG9 0x018A2C ++#define GT96100_MPSC_CHAN3_REG10 0x018A30 ++#define GT96100_MPSC_CHAN3_REG11 0x018A34 ++#define GT96100_MPSC4_MAIN_CONFIG_LOW 0x020A00 ++#define GT96100_MPSC4_MAIN_CONFIG_HIGH 0x020A04 ++#define GT96100_MPSC4_PROTOCOL_CONFIG 0x020A08 ++#define GT96100_MPSC_CHAN4_REG1 0x020A0C ++#define GT96100_MPSC_CHAN4_REG2 0x020A10 ++#define GT96100_MPSC_CHAN4_REG3 0x020A14 ++#define GT96100_MPSC_CHAN4_REG4 0x020A18 ++#define GT96100_MPSC_CHAN4_REG5 0x020A1C ++#define GT96100_MPSC_CHAN4_REG6 0x020A20 ++#define GT96100_MPSC_CHAN4_REG7 0x020A24 ++#define GT96100_MPSC_CHAN4_REG8 0x020A28 ++#define GT96100_MPSC_CHAN4_REG9 0x020A2C ++#define GT96100_MPSC_CHAN4_REG10 0x020A30 ++#define GT96100_MPSC_CHAN4_REG11 0x020A34 ++#define GT96100_MPSC5_MAIN_CONFIG_LOW 0x028A00 ++#define GT96100_MPSC5_MAIN_CONFIG_HIGH 0x028A04 ++#define GT96100_MPSC5_PROTOCOL_CONFIG 0x028A08 ++#define GT96100_MPSC_CHAN5_REG1 0x028A0C ++#define GT96100_MPSC_CHAN5_REG2 0x028A10 ++#define GT96100_MPSC_CHAN5_REG3 0x028A14 ++#define GT96100_MPSC_CHAN5_REG4 0x028A18 ++#define GT96100_MPSC_CHAN5_REG5 0x028A1C ++#define GT96100_MPSC_CHAN5_REG6 0x028A20 ++#define GT96100_MPSC_CHAN5_REG7 0x028A24 ++#define GT96100_MPSC_CHAN5_REG8 0x028A28 ++#define GT96100_MPSC_CHAN5_REG9 0x028A2C ++#define GT96100_MPSC_CHAN5_REG10 0x028A30 ++#define GT96100_MPSC_CHAN5_REG11 0x028A34 ++#define GT96100_MPSC6_MAIN_CONFIG_LOW 0x030A00 ++#define GT96100_MPSC6_MAIN_CONFIG_HIGH 0x030A04 ++#define GT96100_MPSC6_PROTOCOL_CONFIG 0x030A08 ++#define GT96100_MPSC_CHAN6_REG1 0x030A0C ++#define GT96100_MPSC_CHAN6_REG2 0x030A10 ++#define GT96100_MPSC_CHAN6_REG3 0x030A14 ++#define GT96100_MPSC_CHAN6_REG4 0x030A18 ++#define GT96100_MPSC_CHAN6_REG5 0x030A1C ++#define GT96100_MPSC_CHAN6_REG6 0x030A20 ++#define GT96100_MPSC_CHAN6_REG7 0x030A24 ++#define GT96100_MPSC_CHAN6_REG8 0x030A28 ++#define GT96100_MPSC_CHAN6_REG9 0x030A2C ++#define GT96100_MPSC_CHAN6_REG10 0x030A30 ++#define GT96100_MPSC_CHAN6_REG11 0x030A34 ++#define GT96100_MPSC7_MAIN_CONFIG_LOW 0x038A00 ++#define GT96100_MPSC7_MAIN_CONFIG_HIGH 0x038A04 ++#define GT96100_MPSC7_PROTOCOL_CONFIG 0x038A08 ++#define GT96100_MPSC_CHAN7_REG1 0x038A0C ++#define GT96100_MPSC_CHAN7_REG2 0x038A10 ++#define GT96100_MPSC_CHAN7_REG3 0x038A14 ++#define GT96100_MPSC_CHAN7_REG4 0x038A18 ++#define GT96100_MPSC_CHAN7_REG5 0x038A1C ++#define GT96100_MPSC_CHAN7_REG6 0x038A20 ++#define GT96100_MPSC_CHAN7_REG7 0x038A24 ++#define GT96100_MPSC_CHAN7_REG8 0x038A28 ++#define GT96100_MPSC_CHAN7_REG9 0x038A2C ++#define GT96100_MPSC_CHAN7_REG10 0x038A30 ++#define GT96100_MPSC_CHAN7_REG11 0x038A34 ++/* FlexTDMs */ ++/* TDPR0 - Transmit Dual Port RAM. block size 0xff */ ++#define GT96100_FXTDM0_TDPR0_BLK0_BASE 0x000B00 ++#define GT96100_FXTDM0_TDPR0_BLK1_BASE 0x001B00 ++#define GT96100_FXTDM0_TDPR0_BLK2_BASE 0x002B00 ++#define GT96100_FXTDM0_TDPR0_BLK3_BASE 0x003B00 ++/* RDPR0 - Receive Dual Port RAM. block size 0xff */ ++#define GT96100_FXTDM0_RDPR0_BLK0_BASE 0x004B00 ++#define GT96100_FXTDM0_RDPR0_BLK1_BASE 0x005B00 ++#define GT96100_FXTDM0_RDPR0_BLK2_BASE 0x006B00 ++#define GT96100_FXTDM0_RDPR0_BLK3_BASE 0x007B00 ++#define GT96100_FXTDM0_TX_READ_PTR 0x008B00 ++#define GT96100_FXTDM0_RX_READ_PTR 0x008B04 ++#define GT96100_FXTDM0_CONFIG 0x008B08 ++#define GT96100_FXTDM0_AUX_CHANA_TX 0x008B0C ++#define GT96100_FXTDM0_AUX_CHANA_RX 0x008B10 ++#define GT96100_FXTDM0_AUX_CHANB_TX 0x008B14 ++#define GT96100_FXTDM0_AUX_CHANB_RX 0x008B18 ++#define GT96100_FXTDM1_TDPR1_BLK0_BASE 0x010B00 ++#define GT96100_FXTDM1_TDPR1_BLK1_BASE 0x011B00 ++#define GT96100_FXTDM1_TDPR1_BLK2_BASE 0x012B00 ++#define GT96100_FXTDM1_TDPR1_BLK3_BASE 0x013B00 ++#define GT96100_FXTDM1_RDPR1_BLK0_BASE 0x014B00 ++#define GT96100_FXTDM1_RDPR1_BLK1_BASE 0x015B00 ++#define GT96100_FXTDM1_RDPR1_BLK2_BASE 0x016B00 ++#define GT96100_FXTDM1_RDPR1_BLK3_BASE 0x017B00 ++#define GT96100_FXTDM1_TX_READ_PTR 0x018B00 ++#define GT96100_FXTDM1_RX_READ_PTR 0x018B04 ++#define GT96100_FXTDM1_CONFIG 0x018B08 ++#define GT96100_FXTDM1_AUX_CHANA_TX 0x018B0C ++#define GT96100_FXTDM1_AUX_CHANA_RX 0x018B10 ++#define GT96100_FLTDM1_AUX_CHANB_TX 0x018B14 ++#define GT96100_FLTDM1_AUX_CHANB_RX 0x018B18 ++#define GT96100_FLTDM2_TDPR2_BLK0_BASE 0x020B00 ++#define GT96100_FLTDM2_TDPR2_BLK1_BASE 0x021B00 ++#define GT96100_FLTDM2_TDPR2_BLK2_BASE 0x022B00 ++#define GT96100_FLTDM2_TDPR2_BLK3_BASE 0x023B00 ++#define GT96100_FLTDM2_RDPR2_BLK0_BASE 0x024B00 ++#define GT96100_FLTDM2_RDPR2_BLK1_BASE 0x025B00 ++#define GT96100_FLTDM2_RDPR2_BLK2_BASE 0x026B00 ++#define GT96100_FLTDM2_RDPR2_BLK3_BASE 0x027B00 ++#define GT96100_FLTDM2_TX_READ_PTR 0x028B00 ++#define GT96100_FLTDM2_RX_READ_PTR 0x028B04 ++#define GT96100_FLTDM2_CONFIG 0x028B08 ++#define GT96100_FLTDM2_AUX_CHANA_TX 0x028B0C ++#define GT96100_FLTDM2_AUX_CHANA_RX 0x028B10 ++#define GT96100_FLTDM2_AUX_CHANB_TX 0x028B14 ++#define GT96100_FLTDM2_AUX_CHANB_RX 0x028B18 ++#define GT96100_FLTDM3_TDPR3_BLK0_BASE 0x030B00 ++#define GT96100_FLTDM3_TDPR3_BLK1_BASE 0x031B00 ++#define GT96100_FLTDM3_TDPR3_BLK2_BASE 0x032B00 ++#define GT96100_FLTDM3_TDPR3_BLK3_BASE 0x033B00 ++#define GT96100_FXTDM3_RDPR3_BLK0_BASE 0x034B00 ++#define GT96100_FXTDM3_RDPR3_BLK1_BASE 0x035B00 ++#define GT96100_FXTDM3_RDPR3_BLK2_BASE 0x036B00 ++#define GT96100_FXTDM3_RDPR3_BLK3_BASE 0x037B00 ++#define GT96100_FXTDM3_TX_READ_PTR 0x038B00 ++#define GT96100_FXTDM3_RX_READ_PTR 0x038B04 ++#define GT96100_FXTDM3_CONFIG 0x038B08 ++#define GT96100_FXTDM3_AUX_CHANA_TX 0x038B0C ++#define GT96100_FXTDM3_AUX_CHANA_RX 0x038B10 ++#define GT96100_FXTDM3_AUX_CHANB_TX 0x038B14 ++#define GT96100_FXTDM3_AUX_CHANB_RX 0x038B18 ++/* Baud Rate Generators */ ++#define GT96100_BRG0_CONFIG 0x102A00 ++#define GT96100_BRG0_BAUD_TUNE 0x102A04 ++#define GT96100_BRG1_CONFIG 0x102A08 ++#define GT96100_BRG1_BAUD_TUNE 0x102A0C ++#define GT96100_BRG2_CONFIG 0x102A10 ++#define GT96100_BRG2_BAUD_TUNE 0x102A14 ++#define GT96100_BRG3_CONFIG 0x102A18 ++#define GT96100_BRG3_BAUD_TUNE 0x102A1C ++#define GT96100_BRG4_CONFIG 0x102A20 ++#define GT96100_BRG4_BAUD_TUNE 0x102A24 ++#define GT96100_BRG5_CONFIG 0x102A28 ++#define GT96100_BRG5_BAUD_TUNE 0x102A2C ++#define GT96100_BRG6_CONFIG 0x102A30 ++#define GT96100_BRG6_BAUD_TUNE 0x102A34 ++#define GT96100_BRG7_CONFIG 0x102A38 ++#define GT96100_BRG7_BAUD_TUNE 0x102A3C ++/* Routing Registers */ ++#define GT96100_ROUTE_MAIN 0x101A00 ++#define GT96100_ROUTE_RX_CLOCK 0x101A10 ++#define GT96100_ROUTE_TX_CLOCK 0x101A20 ++/* General Purpose Ports */ ++#define GT96100_GPP_CONFIG0 0x100A00 ++#define GT96100_GPP_CONFIG1 0x100A04 ++#define GT96100_GPP_CONFIG2 0x100A08 ++#define GT96100_GPP_CONFIG3 0x100A0C ++#define GT96100_GPP_IO0 0x100A20 ++#define GT96100_GPP_IO1 0x100A24 ++#define GT96100_GPP_IO2 0x100A28 ++#define GT96100_GPP_IO3 0x100A2C ++#define GT96100_GPP_DATA0 0x100A40 ++#define GT96100_GPP_DATA1 0x100A44 ++#define GT96100_GPP_DATA2 0x100A48 ++#define GT96100_GPP_DATA3 0x100A4C ++#define GT96100_GPP_LEVEL0 0x100A60 ++#define GT96100_GPP_LEVEL1 0x100A64 ++#define GT96100_GPP_LEVEL2 0x100A68 ++#define GT96100_GPP_LEVEL3 0x100A6C ++/* Watchdog */ ++#define GT96100_WD_CONFIG 0x101A80 ++#define GT96100_WD_VALUE 0x101A84 ++/* Communication Unit Arbiter */ ++#define GT96100_COMM_UNIT_ARBTR_CONFIG 0x101AC0 ++/* PCI Arbiters */ ++#define GT96100_PCI0_ARBTR_CONFIG 0x101AE0 ++#define GT96100_PCI1_ARBTR_CONFIG 0x101AE4 ++/* CIU Arbiter */ ++#define GT96100_CIU_ARBITER_CONFIG 0x101AC0 ++/* Interrupt Controller */ ++#define GT96100_MAIN_CAUSE 0x000C18 ++#define GT96100_INT0_MAIN_MASK 0x000C1C ++#define GT96100_INT1_MAIN_MASK 0x000C24 ++#define GT96100_HIGH_CAUSE 0x000C98 ++#define GT96100_INT0_HIGH_MASK 0x000C9C ++#define GT96100_INT1_HIGH_MASK 0x000CA4 ++#define GT96100_INT0_SELECT 0x000C70 ++#define GT96100_INT1_SELECT 0x000C74 ++#define GT96100_SERIAL_CAUSE 0x103A00 ++#define GT96100_SERINT0_MASK 0x103A80 ++#define GT96100_SERINT1_MASK 0x103A88 ++ ++#endif /* _GT96100_H */ +diff -ruN linux/include/asm-mips/io.h linux-mips/include/asm-mips/io.h +--- linux/include/asm-mips/io.h Mon Feb 28 07:18:20 2000 ++++ linux-mips/include/asm-mips/io.h Fri Nov 10 00:11:47 2000 +@@ -317,6 +317,57 @@ + __OUTS(h,w,2) + __OUTS(w,l,4) + ++ ++#ifdef CONFIG_MIPS_EV96100 ++ ++#include ++ ++#define inb(port) in_8((u8 *)((port)+mips_io_port_base)) ++#define outb(val, port) out_8((u8 *)((port)+mips_io_port_base), (val)) ++#define inw(port) in_16((u16 *)((port)+mips_io_port_base)) ++#define outw(val, port) out_16((u16 *)((port)+mips_io_port_base), (val)) ++#define inl(port) in_32((u32 *)((port)+mips_io_port_base)) ++#define outl(val, port) out_32((u32 *)((port)+mips_io_port_base), (val)) ++ ++#define inb_p(port) inb((port)) ++#define outb_p(val, port) outb((val), (port)) ++#define inw_p(port) inw((port)) ++#define outw_p(val, port) outw((val), (port)) ++#define inl_p(port) inl((port)) ++#define outl_p(val, port) outl((val), (port)) ++ ++extern inline unsigned char in_8(const unsigned char *addr) ++{ ++ return *KSEG1ADDR(addr); ++} ++ ++extern inline void out_8(unsigned char *addr, unsigned int val) ++{ ++ *KSEG1ADDR(addr) = (unsigned char)val; ++} ++ ++extern inline unsigned short in_16(const unsigned short *addr) ++{ ++ return (le16_to_cpu(*KSEG1ADDR(addr))); ++} ++ ++extern inline void out_16(unsigned short *addr, unsigned int val) ++{ ++ *KSEG1ADDR(addr) = cpu_to_le16((unsigned short)val); ++} ++ ++extern inline unsigned int in_32(const unsigned int *addr) ++{ ++ return (le32_to_cpu(*KSEG1ADDR(addr))); ++} ++ ++extern inline void out_32(unsigned int *addr, unsigned int val) ++{ ++ *KSEG1ADDR(addr) = cpu_to_le32((unsigned int)val); ++} ++ ++#else ++ + /* + * Note that due to the way __builtin_constant_p() works, you + * - can't use it inside an inline function (it will never be true) +@@ -412,6 +463,7 @@ + ((__builtin_constant_p((port)) && (port) < 32768) ? \ + __inslc((port),(addr),(count)) : \ + __insl((port),(addr),(count))) ++#endif + + #define IO_SPACE_LIMIT 0xffff + +diff -ruN linux/include/asm-mips/irq.h linux-mips/include/asm-mips/irq.h +--- linux/include/asm-mips/irq.h Sat May 13 08:31:25 2000 ++++ linux-mips/include/asm-mips/irq.h Fri Nov 10 00:11:47 2000 +@@ -1,20 +1,28 @@ +-/* $Id: irq.h,v 1.6 2000/01/26 00:07:45 ralf Exp $ +- * ++/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle +- * Copyright (C) 1995, 1996, 1997, 1998 by Ralf Baechle ++ * Copyright (C) 1995, 96, 97, 98, 99, 2000 by Ralf Baechle + */ + #ifndef _ASM_IRQ_H + #define _ASM_IRQ_H + ++#include ++ + #define NR_IRQS 64 + + #define TIMER_IRQ 0 + +-extern int (*irq_cannonicalize)(int irq); ++#ifdef CONFIG_I8259 ++static inline int irq_cannonicalize(int irq) ++{ ++ return ((irq == 2) ? 9 : irq); ++} ++#else ++#define irq_cannonicalize(irq) (irq) /* Sane hardware, sane code ... */ ++#endif + + struct irqaction; + extern int i8259_setup_irq(int irq, struct irqaction * new); +diff -ruN linux/include/asm-mips/mc146818rtc.h linux-mips/include/asm-mips/mc146818rtc.h +--- linux/include/asm-mips/mc146818rtc.h Fri Aug 4 18:31:19 2000 ++++ linux-mips/include/asm-mips/mc146818rtc.h Fri Nov 10 00:11:51 2000 +@@ -49,4 +49,6 @@ + #define RTC_IRQ 8 + #endif + ++#define RTC_DEC_YEAR 0x3f /* Where we store the real year on DECs. */ ++ + #endif /* _ASM_MC146818RTC_H */ +diff -ruN linux/include/asm-mips/mips-boards/atlas.h linux-mips/include/asm-mips/mips-boards/atlas.h +--- linux/include/asm-mips/mips-boards/atlas.h Wed Dec 31 16:00:00 1969 ++++ linux-mips/include/asm-mips/mips-boards/atlas.h Fri Nov 10 00:12:18 2000 +@@ -0,0 +1,55 @@ ++/* ++ * Carsten Langgaard, carstenl@mips.com ++ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. ++ * ++ * ######################################################################## ++ * ++ * This program is free software; you can distribute it and/or modify it ++ * under the terms of the GNU General Public License (Version 2) as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. ++ * ++ * ######################################################################## ++ * ++ * Defines of the Atlas board specific address-MAP, registers, etc. ++ * ++ */ ++#ifndef _MIPS_ATLAS_H ++#define _MIPS_ATLAS_H ++ ++#include ++ ++/* ++ * Atlas RTC-device indirect register access. ++ */ ++#define ATLAS_RTC_ADR_REG (KSEG1ADDR(0x1f000800)) ++#define ATLAS_RTC_DAT_REG (KSEG1ADDR(0x1f000808)) ++ ++ ++/* ++ * Atlas interrupt controller register base. ++ */ ++#define ATLAS_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000)) ++ ++/* ++ * Atlas UART register base. ++ */ ++#define ATLAS_UART_REGS_BASE (KSEG1ADDR(0x1f000900)) ++#define ATLAS_BASE_BAUD ( 3686400 / 16 ) ++ ++/* ++ * Atlas PSU standby register. ++ */ ++#define ATLAS_PSUSTBY_REG (KSEG1ADDR(0x1f000600)) ++#define ATLAS_GOSTBY 0x4d ++ ++ ++#endif /* !(_MIPS_ATLAS_H) */ +diff -ruN linux/include/asm-mips/mips-boards/atlasint.h linux-mips/include/asm-mips/mips-boards/atlasint.h +--- linux/include/asm-mips/mips-boards/atlasint.h Wed Dec 31 16:00:00 1969 ++++ linux-mips/include/asm-mips/mips-boards/atlasint.h Fri Nov 10 00:12:18 2000 +@@ -0,0 +1,51 @@ ++/* ++ * Carsten Langgaard, carstenl@mips.com ++ * Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved. ++ * ++ * ######################################################################## ++ * ++ * This program is free software; you can distribute it and/or modify it ++ * under the terms of the GNU General Public License (Version 2) as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. ++ * ++ * ######################################################################## ++ * ++ * Defines for the Atlas interrupt controller. ++ * ++ */ ++#ifndef _MIPS_ATLASINT_H ++#define _MIPS_ATLASINT_H ++ ++/* Number of IRQ supported on hw interrupt 0. */ ++#define ATLASINT_UART 0 ++#define ATLASINT_END 32 ++ ++/* ++ * Atlas registers are memory mapped on 64-bit aligned boundaries and ++ * only word access are allowed. ++ */ ++struct atlas_ictrl_regs { ++ volatile unsigned long intraw; ++ long dummy1; ++ volatile unsigned long intseten; ++ long dummy2; ++ volatile unsigned long intrsten; ++ long dummy3; ++ volatile unsigned long intenable; ++ long dummy4; ++ volatile unsigned long intstatus; ++ long dummy5; ++}; ++ ++extern void atlasint_init(void); ++ ++#endif /* !(_MIPS_ATLASINT_H) */ +diff -ruN linux/include/asm-mips/mips-boards/generic.h linux-mips/include/asm-mips/mips-boards/generic.h +--- linux/include/asm-mips/mips-boards/generic.h Wed Dec 31 16:00:00 1969 ++++ linux-mips/include/asm-mips/mips-boards/generic.h Fri Nov 10 00:12:19 2000 +@@ -0,0 +1,65 @@ ++/* ++ * Carsten Langgaard, carstenl@mips.com ++ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. ++ * ++ * ######################################################################## ++ * ++ * This program is free software; you can distribute it and/or modify it ++ * under the terms of the GNU General Public License (Version 2) as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. ++ * ++ * ######################################################################## ++ * ++ * Defines of the MIPS boards specific address-MAP, registers, etc. ++ * ++ */ ++#ifndef _MIPS_GENERIC_H ++#define _MIPS_GENERIC_H ++ ++#include ++#include ++ ++/* ++ * Display register base. ++ */ ++#define ASCII_DISPLAY_WORD_BASE (KSEG1ADDR(0x1f000410)) ++#define ASCII_DISPLAY_POS_BASE (KSEG1ADDR(0x1f000418)) ++ ++ ++/* ++ * Yamon Prom print address. ++ */ ++#define YAMON_PROM_PRINT_ADDR (KSEG1ADDR(0x1fc00504)) ++ ++ ++/* ++ * Reset register. ++ */ ++#define SOFTRES_REG (KSEG1ADDR(0x1f000500)) ++#define GORESET 0x42 ++ ++ ++/* ++ * Galileo GT64120 system controller register base. ++ */ ++#define MIPS_GT_BASE (KSEG1ADDR(0x1be00000)) ++ ++/* ++ * Because of an error/peculiarity in the Galileo chip, we need to swap the ++ * bytes when running bigendian. ++ */ ++#define GT_WRITE(ofs, data) \ ++ *(volatile u32 *)(MIPS_GT_BASE+ofs) = cpu_to_le32(data) ++#define GT_READ(ofs, data) \ ++ data = le32_to_cpu(*(volatile u32 *)(MIPS_GT_BASE+ofs)) ++ ++#endif /* !(_MIPS_GENERIC_H) */ +diff -ruN linux/include/asm-mips/mips-boards/gt64120.h linux-mips/include/asm-mips/mips-boards/gt64120.h +--- linux/include/asm-mips/mips-boards/gt64120.h Wed Dec 31 16:00:00 1969 ++++ linux-mips/include/asm-mips/mips-boards/gt64120.h Fri Nov 10 00:12:19 2000 +@@ -0,0 +1,320 @@ ++/* ++ * Carsten Langgaard, carstenl@mips.com ++ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. ++ * ++ * ######################################################################## ++ * ++ * This program is free software; you can distribute it and/or modify it ++ * under the terms of the GNU General Public License (Version 2) as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. ++ * ++ * ######################################################################## ++ * ++ * Register definitions for Galileo 64120 system controller. ++ * ++ */ ++#ifndef GT64120_H ++#define GT64120_H ++ ++#define MSK(n) ((1 << (n)) - 1) ++ ++/************************************************************************ ++ * Register offset addresses ++ ************************************************************************/ ++ ++#define GT_CPU_OFS 0x000 ++ ++#define GT_INTRCAUSE_OFS 0xc18 ++#define GT_PCI0_CFGADDR_OFS 0xcf8 ++#define GT_PCI0_CFGDATA_OFS 0xcfc ++#define GT_SDRAM_BM_OFS 0x478 ++#define GT_SDRAM_ADDRDECODE_OFS 0x47c ++#define GT_SDRAM_B0_OFS 0x44c ++#define GT_SDRAM_B2_OFS 0x454 ++#define GT_SDRAM_CFG_OFS 0x448 ++#define GT_SDRAM_OPMODE_OFS 0x474 ++ ++#define GT_ISD_OFS 0x068 ++ ++#define GT_SCS10LD_OFS 0x008 ++#define GT_SCS10HD_OFS 0x010 ++#define GT_SCS32LD_OFS 0x018 ++#define GT_SCS32HD_OFS 0x020 ++#define GT_CS20LD_OFS 0x028 ++#define GT_CS20HD_OFS 0x030 ++#define GT_CS3BOOTLD_OFS 0x038 ++#define GT_CS3BOOTHD_OFS 0x040 ++#define GT_PCI0IOLD_OFS 0x048 ++#define GT_PCI0IOHD_OFS 0x050 ++#define GT_PCI0M0LD_OFS 0x058 ++#define GT_PCI0M0HD_OFS 0x060 ++#define GT_PCI0M1LD_OFS 0x080 ++#define GT_PCI0M1HD_OFS 0x088 ++#define GT_PCI1IOLD_OFS 0x090 ++#define GT_PCI1IOHD_OFS 0x098 ++#define GT_PCI1M0LD_OFS 0x0a0 ++#define GT_PCI1M0HD_OFS 0x0a8 ++#define GT_PCI1M1LD_OFS 0x0b0 ++#define GT_PCI1M1HD_OFS 0x0b8 ++ ++#define GT_SCS0LD_OFS 0x400 ++#define GT_SCS0HD_OFS 0x404 ++#define GT_SCS1LD_OFS 0x408 ++#define GT_SCS1HD_OFS 0x40c ++#define GT_SCS2LD_OFS 0x410 ++#define GT_SCS2HD_OFS 0x414 ++#define GT_SCS3LD_OFS 0x418 ++#define GT_SCS3HD_OFS 0x41c ++#define GT_CS0LD_OFS 0x420 ++#define GT_CS0HD_OFS 0x424 ++#define GT_CS1LD_OFS 0x428 ++#define GT_CS1HD_OFS 0x42c ++#define GT_CS2LD_OFS 0x430 ++#define GT_CS2HD_OFS 0x434 ++#define GT_CS3LD_OFS 0x438 ++#define GT_CS3HD_OFS 0x43c ++#define GT_BOOTLD_OFS 0x440 ++#define GT_BOOTHD_OFS 0x444 ++ ++#define GT_PCI0_BS_SCS10_OFS 0Xc08 ++#define GT_PCI0_BS_SCS32_OFS 0xc0c ++#define GT_PCI0_BARE_OFS 0Xc3c ++ ++#define GT_PCI0_TOR_OFS 0xc04 ++ ++#define GT_PCI0_IACK_OFS 0xc34 ++ ++ ++/************************************************************************ ++ * Register encodings ++ ************************************************************************/ ++ ++#define GT_CPU_WR_SHF 16 ++#define GT_CPU_WR_MSK (MSK(1) << GT_CPU_WR_SHF) ++#define GT_CPU_WR_BIT GT_CPU_WR_MSK ++#define GT_CPU_WR_DXDXDXDX 0 ++#define GT_CPU_WR_DDDD 1 ++ ++ ++#define GT_CFGADDR_CFGEN_SHF 31 ++#define GT_CFGADDR_CFGEN_MSK (MSK(1) << GT_CFGADDR_CFGEN_SHF) ++#define GT_CFGADDR_CFGEN_BIT GT_CFGADDR_CFGEN_MSK ++ ++#define GT_CFGADDR_BUSNUM_SHF 16 ++#define GT_CFGADDR_BUSNUM_MSK (MSK(8) << GT_CFGADDR_BUSNUM_SHF) ++ ++#define GT_CFGADDR_DEVNUM_SHF 11 ++#define GT_CFGADDR_DEVNUM_MSK (MSK(5) << GT_CFGADDR_DEVNUM_SHF) ++ ++#define GT_CFGADDR_FUNCNUM_SHF 8 ++#define GT_CFGADDR_FUNCNUM_MSK (MSK(3) << GT_CFGADDR_FUNCNUM_SHF) ++ ++#define GT_CFGADDR_REGNUM_SHF 2 ++#define GT_CFGADDR_REGNUM_MSK (MSK(6) << GT_CFGADDR_REGNUM_SHF) ++ ++ ++#define GT_SDRAM_BM_ORDER_SHF 2 ++#define GT_SDRAM_BM_ORDER_MSK (MSK(1) << GT_SDRAM_BM_ORDER_SHF) ++#define GT_SDRAM_BM_ORDER_BIT GT_SDRAM_BM_ORDER_MSK ++#define GT_SDRAM_BM_ORDER_SUB 1 ++#define GT_SDRAM_BM_ORDER_LIN 0 ++ ++#define GT_SDRAM_BM_RSVD_ALL1 0xFFB ++ ++ ++#define GT_SDRAM_ADDRDECODE_ADDR_SHF 0 ++#define GT_SDRAM_ADDRDECODE_ADDR_MSK (MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF) ++#define GT_SDRAM_ADDRDECODE_ADDR_0 0 ++#define GT_SDRAM_ADDRDECODE_ADDR_1 1 ++#define GT_SDRAM_ADDRDECODE_ADDR_2 2 ++#define GT_SDRAM_ADDRDECODE_ADDR_3 3 ++#define GT_SDRAM_ADDRDECODE_ADDR_4 4 ++#define GT_SDRAM_ADDRDECODE_ADDR_5 5 ++#define GT_SDRAM_ADDRDECODE_ADDR_6 6 ++#define GT_SDRAM_ADDRDECODE_ADDR_7 7 ++ ++ ++#define GT_SDRAM_B0_CASLAT_SHF 0 ++#define GT_SDRAM_B0_CASLAT_MSK (MSK(2) << GT_SDRAM_B0__SHF) ++#define GT_SDRAM_B0_CASLAT_2 1 ++#define GT_SDRAM_B0_CASLAT_3 2 ++ ++#define GT_SDRAM_B0_FTDIS_SHF 2 ++#define GT_SDRAM_B0_FTDIS_MSK (MSK(1) << GT_SDRAM_B0_FTDIS_SHF) ++#define GT_SDRAM_B0_FTDIS_BIT GT_SDRAM_B0_FTDIS_MSK ++ ++#define GT_SDRAM_B0_SRASPRCHG_SHF 3 ++#define GT_SDRAM_B0_SRASPRCHG_MSK (MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF) ++#define GT_SDRAM_B0_SRASPRCHG_BIT GT_SDRAM_B0_SRASPRCHG_MSK ++#define GT_SDRAM_B0_SRASPRCHG_2 0 ++#define GT_SDRAM_B0_SRASPRCHG_3 1 ++ ++#define GT_SDRAM_B0_B0COMPAB_SHF 4 ++#define GT_SDRAM_B0_B0COMPAB_MSK (MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF) ++#define GT_SDRAM_B0_B0COMPAB_BIT GT_SDRAM_B0_B0COMPAB_MSK ++ ++#define GT_SDRAM_B0_64BITINT_SHF 5 ++#define GT_SDRAM_B0_64BITINT_MSK (MSK(1) << GT_SDRAM_B0_64BITINT_SHF) ++#define GT_SDRAM_B0_64BITINT_BIT GT_SDRAM_B0_64BITINT_MSK ++#define GT_SDRAM_B0_64BITINT_2 0 ++#define GT_SDRAM_B0_64BITINT_4 1 ++ ++#define GT_SDRAM_B0_BW_SHF 6 ++#define GT_SDRAM_B0_BW_MSK (MSK(1) << GT_SDRAM_B0_BW_SHF) ++#define GT_SDRAM_B0_BW_BIT GT_SDRAM_B0_BW_MSK ++#define GT_SDRAM_B0_BW_32 0 ++#define GT_SDRAM_B0_BW_64 1 ++ ++#define GT_SDRAM_B0_BLODD_SHF 7 ++#define GT_SDRAM_B0_BLODD_MSK (MSK(1) << GT_SDRAM_B0_BLODD_SHF) ++#define GT_SDRAM_B0_BLODD_BIT GT_SDRAM_B0_BLODD_MSK ++ ++#define GT_SDRAM_B0_PAR_SHF 8 ++#define GT_SDRAM_B0_PAR_MSK (MSK(1) << GT_SDRAM_B0_PAR_SHF) ++#define GT_SDRAM_B0_PAR_BIT GT_SDRAM_B0_PAR_MSK ++ ++#define GT_SDRAM_B0_BYPASS_SHF 9 ++#define GT_SDRAM_B0_BYPASS_MSK (MSK(1) << GT_SDRAM_B0_BYPASS_SHF) ++#define GT_SDRAM_B0_BYPASS_BIT GT_SDRAM_B0_BYPASS_MSK ++ ++#define GT_SDRAM_B0_SRAS2SCAS_SHF 10 ++#define GT_SDRAM_B0_SRAS2SCAS_MSK (MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF) ++#define GT_SDRAM_B0_SRAS2SCAS_BIT GT_SDRAM_B0_SRAS2SCAS_MSK ++#define GT_SDRAM_B0_SRAS2SCAS_2 0 ++#define GT_SDRAM_B0_SRAS2SCAS_3 1 ++ ++#define GT_SDRAM_B0_SIZE_SHF 11 ++#define GT_SDRAM_B0_SIZE_MSK (MSK(1) << GT_SDRAM_B0_SIZE_SHF) ++#define GT_SDRAM_B0_SIZE_BIT GT_SDRAM_B0_SIZE_MSK ++#define GT_SDRAM_B0_SIZE_16M 0 ++#define GT_SDRAM_B0_SIZE_64M 1 ++ ++#define GT_SDRAM_B0_EXTPAR_SHF 12 ++#define GT_SDRAM_B0_EXTPAR_MSK (MSK(1) << GT_SDRAM_B0_EXTPAR_SHF) ++#define GT_SDRAM_B0_EXTPAR_BIT GT_SDRAM_B0_EXTPAR_MSK ++ ++#define GT_SDRAM_B0_BLEN_SHF 13 ++#define GT_SDRAM_B0_BLEN_MSK (MSK(1) << GT_SDRAM_B0_BLEN_SHF) ++#define GT_SDRAM_B0_BLEN_BIT GT_SDRAM_B0_BLEN_MSK ++#define GT_SDRAM_B0_BLEN_8 0 ++#define GT_SDRAM_B0_BLEN_4 1 ++ ++ ++#define GT_SDRAM_CFG_REFINT_SHF 0 ++#define GT_SDRAM_CFG_REFINT_MSK (MSK(14) << GT_SDRAM_CFG_REFINT_SHF) ++ ++#define GT_SDRAM_CFG_NINTERLEAVE_SHF 14 ++#define GT_SDRAM_CFG_NINTERLEAVE_MSK (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF) ++#define GT_SDRAM_CFG_NINTERLEAVE_BIT GT_SDRAM_CFG_NINTERLEAVE_MSK ++ ++#define GT_SDRAM_CFG_RMW_SHF 15 ++#define GT_SDRAM_CFG_RMW_MSK (MSK(1) << GT_SDRAM_CFG_RMW_SHF) ++#define GT_SDRAM_CFG_RMW_BIT GT_SDRAM_CFG_RMW_MSK ++ ++#define GT_SDRAM_CFG_NONSTAGREF_SHF 16 ++#define GT_SDRAM_CFG_NONSTAGREF_MSK (MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF) ++#define GT_SDRAM_CFG_NONSTAGREF_BIT GT_SDRAM_CFG_NONSTAGREF_MSK ++ ++#define GT_SDRAM_CFG_DUPCNTL_SHF 19 ++#define GT_SDRAM_CFG_DUPCNTL_MSK (MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF) ++#define GT_SDRAM_CFG_DUPCNTL_BIT GT_SDRAM_CFG_DUPCNTL_MSK ++ ++#define GT_SDRAM_CFG_DUPBA_SHF 20 ++#define GT_SDRAM_CFG_DUPBA_MSK (MSK(1) << GT_SDRAM_CFG_DUPBA_SHF) ++#define GT_SDRAM_CFG_DUPBA_BIT GT_SDRAM_CFG_DUPBA_MSK ++ ++#define GT_SDRAM_CFG_DUPEOT0_SHF 21 ++#define GT_SDRAM_CFG_DUPEOT0_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF) ++#define GT_SDRAM_CFG_DUPEOT0_BIT GT_SDRAM_CFG_DUPEOT0_MSK ++ ++#define GT_SDRAM_CFG_DUPEOT1_SHF 22 ++#define GT_SDRAM_CFG_DUPEOT1_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF) ++#define GT_SDRAM_CFG_DUPEOT1_BIT GT_SDRAM_CFG_DUPEOT1_MSK ++ ++#define GT_SDRAM_OPMODE_OP_SHF 0 ++#define GT_SDRAM_OPMODE_OP_MSK (MSK(3) << GT_SDRAM_OPMODE_OP_SHF) ++#define GT_SDRAM_OPMODE_OP_NORMAL 0 ++#define GT_SDRAM_OPMODE_OP_NOP 1 ++#define GT_SDRAM_OPMODE_OP_PRCHG 2 ++#define GT_SDRAM_OPMODE_OP_MODE 3 ++#define GT_SDRAM_OPMODE_OP_CBR 4 ++ ++ ++#define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0 ++#define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF) ++#define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT GT_PCI0_BARE_SWSCS3BOOTDIS_MSK ++ ++#define GT_PCI0_BARE_SWSCS32DIS_SHF 1 ++#define GT_PCI0_BARE_SWSCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF) ++#define GT_PCI0_BARE_SWSCS32DIS_BIT GT_PCI0_BARE_SWSCS32DIS_MSK ++ ++#define GT_PCI0_BARE_SWSCS10DIS_SHF 2 ++#define GT_PCI0_BARE_SWSCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF) ++#define GT_PCI0_BARE_SWSCS10DIS_BIT GT_PCI0_BARE_SWSCS10DIS_MSK ++ ++#define GT_PCI0_BARE_INTIODIS_SHF 3 ++#define GT_PCI0_BARE_INTIODIS_MSK (MSK(1) << GT_PCI0_BARE_INTIODIS_SHF) ++#define GT_PCI0_BARE_INTIODIS_BIT GT_PCI0_BARE_INTIODIS_MSK ++ ++#define GT_PCI0_BARE_INTMEMDIS_SHF 4 ++#define GT_PCI0_BARE_INTMEMDIS_MSK (MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF) ++#define GT_PCI0_BARE_INTMEMDIS_BIT GT_PCI0_BARE_INTMEMDIS_MSK ++ ++#define GT_PCI0_BARE_CS3BOOTDIS_SHF 5 ++#define GT_PCI0_BARE_CS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF) ++#define GT_PCI0_BARE_CS3BOOTDIS_BIT GT_PCI0_BARE_CS3BOOTDIS_MSK ++ ++#define GT_PCI0_BARE_CS20DIS_SHF 6 ++#define GT_PCI0_BARE_CS20DIS_MSK (MSK(1) << GT_PCI0_BARE_CS20DIS_SHF) ++#define GT_PCI0_BARE_CS20DIS_BIT GT_PCI0_BARE_CS20DIS_MSK ++ ++#define GT_PCI0_BARE_SCS32DIS_SHF 7 ++#define GT_PCI0_BARE_SCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF) ++#define GT_PCI0_BARE_SCS32DIS_BIT GT_PCI0_BARE_SCS32DIS_MSK ++ ++#define GT_PCI0_BARE_SCS10DIS_SHF 8 ++#define GT_PCI0_BARE_SCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF) ++#define GT_PCI0_BARE_SCS10DIS_BIT GT_PCI0_BARE_SCS10DIS_MSK ++ ++ ++#define GT_INTRCAUSE_MASABORT0_SHF 18 ++#define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF) ++#define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK ++ ++#define GT_INTRCAUSE_TARABORT0_SHF 19 ++#define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF) ++#define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK ++ ++ ++#define GT_PCI0_CFGADDR_REGNUM_SHF 2 ++#define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF) ++#define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8 ++#define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF) ++#define GT_PCI0_CFGADDR_DEVNUM_SHF 11 ++#define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF) ++#define GT_PCI0_CFGADDR_BUSNUM_SHF 16 ++#define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF) ++#define GT_PCI0_CFGADDR_CONFIGEN_SHF 31 ++#define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF) ++#define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK ++ ++ ++/************************************************************************ ++ * Misc ++ ************************************************************************/ ++ ++#define GT_DEF_BASE 0x14000000 ++#define GT_DEF_PCI0_MEM0_BASE 0x12000000 ++#define GT_MAX_BANKSIZE (256 * 1024 * 1024) /* Max 256MB bank */ ++#define GT_LATTIM_MIN 6 /* Minimum lat */ ++ ++#endif /* #ifndef GT64120_H */ +diff -ruN linux/include/asm-mips/mips-boards/malta.h linux-mips/include/asm-mips/mips-boards/malta.h +--- linux/include/asm-mips/mips-boards/malta.h Wed Dec 31 16:00:00 1969 ++++ linux-mips/include/asm-mips/mips-boards/malta.h Fri Nov 10 00:12:19 2000 +@@ -0,0 +1,59 @@ ++/* ++ * Carsten Langgaard, carstenl@mips.com ++ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. ++ * ++ * ######################################################################## ++ * ++ * This program is free software; you can distribute it and/or modify it ++ * under the terms of the GNU General Public License (Version 2) as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. ++ * ++ * ######################################################################## ++ * ++ * Defines of the Malta board specific address-MAP, registers, etc. ++ * ++ */ ++#ifndef _MIPS_MALTA_H ++#define _MIPS_MALTA_H ++ ++#include ++#include ++ ++/* ++ * Malta I/O ports base address. ++*/ ++#define MALTA_PORT_BASE (KSEG1ADDR(0x18000000)) ++ ++/* ++ * Malta RTC-device indirect register access. ++ */ ++#define MALTA_RTC_ADR_REG 0x70 ++#define MALTA_RTC_DAT_REG 0x71 ++ ++/* ++ * Malta SMSC FDC37M817 Super I/O Controller register. ++ */ ++#define SMSC_CONFIG_REG 0x3f0 ++#define SMSC_DATA_REG 0x3f1 ++ ++#define SMSC_CONFIG_DEVNUM 0x7 ++#define SMSC_CONFIG_ACTIVATE 0x30 ++#define SMSC_CONFIG_ENTER 0x55 ++#define SMSC_CONFIG_EXIT 0xaa ++ ++#define SMSC_CONFIG_DEVNUM_FLOPPY 0 ++ ++#define SMSC_CONFIG_ACTIVATE_ENABLE 1 ++ ++#define SMSC_WRITE(x,a) outb(x,a) ++ ++#endif /* !(_MIPS_MALTA_H) */ +diff -ruN linux/include/asm-mips/mips-boards/maltaint.h linux-mips/include/asm-mips/mips-boards/maltaint.h +--- linux/include/asm-mips/mips-boards/maltaint.h Wed Dec 31 16:00:00 1969 ++++ linux-mips/include/asm-mips/mips-boards/maltaint.h Fri Nov 10 00:12:19 2000 +@@ -0,0 +1,33 @@ ++/* ++ * Carsten Langgaard, carstenl@mips.com ++ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. ++ * ++ * ######################################################################## ++ * ++ * This program is free software; you can distribute it and/or modify it ++ * under the terms of the GNU General Public License (Version 2) as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. ++ * ++ * ######################################################################## ++ * ++ * Defines for the Malta interrupt controller. ++ * ++ */ ++#ifndef _MIPS_MALTAINT_H ++#define _MIPS_MALTAINT_H ++ ++/* Number of IRQ supported on hw interrupt 0. */ ++#define MALTAINT_END 16 ++ ++extern void maltaint_init(void); ++ ++#endif /* !(_MIPS_MALTAINT_H) */ +diff -ruN linux/include/asm-mips/mips-boards/piix4.h linux-mips/include/asm-mips/mips-boards/piix4.h +--- linux/include/asm-mips/mips-boards/piix4.h Wed Dec 31 16:00:00 1969 ++++ linux-mips/include/asm-mips/mips-boards/piix4.h Fri Nov 10 00:12:20 2000 +@@ -0,0 +1,86 @@ ++/* ++ * Carsten Langgaard, carstenl@mips.com ++ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. ++ * ++ * ######################################################################## ++ * ++ * This program is free software; you can distribute it and/or modify it ++ * under the terms of the GNU General Public License (Version 2) as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. ++ * ++ * ######################################################################## ++ * ++ * Register definitions for Intel PIIX4 South Bridge Device. ++ * ++ */ ++ ++#ifndef PIIX4_H ++#define PIIX4_H ++ ++/************************************************************************ ++ * IO register offsets ++ ************************************************************************/ ++#define PIIX4_ICTLR1_ICW1 0x20 ++#define PIIX4_ICTLR1_ICW2 0x21 ++#define PIIX4_ICTLR1_ICW3 0x21 ++#define PIIX4_ICTLR1_ICW4 0x21 ++#define PIIX4_ICTLR2_ICW1 0xa0 ++#define PIIX4_ICTLR2_ICW2 0xa1 ++#define PIIX4_ICTLR2_ICW3 0xa1 ++#define PIIX4_ICTLR2_ICW4 0xa1 ++#define PIIX4_ICTLR1_OCW1 0x21 ++#define PIIX4_ICTLR1_OCW2 0x20 ++#define PIIX4_ICTLR1_OCW3 0x20 ++#define PIIX4_ICTLR1_OCW4 0x20 ++#define PIIX4_ICTLR2_OCW1 0xa1 ++#define PIIX4_ICTLR2_OCW2 0xa0 ++#define PIIX4_ICTLR2_OCW3 0xa0 ++#define PIIX4_ICTLR2_OCW4 0xa0 ++ ++ ++/************************************************************************ ++ * Register encodings. ++ ************************************************************************/ ++#define PIIX4_OCW2_NSEOI (0x1 << 5) ++#define PIIX4_OCW2_SEOI (0x3 << 5) ++#define PIIX4_OCW2_RNSEOI (0x5 << 5) ++#define PIIX4_OCW2_RAEOIS (0x4 << 5) ++#define PIIX4_OCW2_RAEOIC (0x0 << 5) ++#define PIIX4_OCW2_RSEOI (0x7 << 5) ++#define PIIX4_OCW2_SP (0x6 << 5) ++#define PIIX4_OCW2_NOP (0x2 << 5) ++ ++#define PIIX4_OCW2_SEL (0x0 << 3) ++ ++#define PIIX4_OCW2_ILS_0 0 ++#define PIIX4_OCW2_ILS_1 1 ++#define PIIX4_OCW2_ILS_2 2 ++#define PIIX4_OCW2_ILS_3 3 ++#define PIIX4_OCW2_ILS_4 4 ++#define PIIX4_OCW2_ILS_5 5 ++#define PIIX4_OCW2_ILS_6 6 ++#define PIIX4_OCW2_ILS_7 7 ++#define PIIX4_OCW2_ILS_8 0 ++#define PIIX4_OCW2_ILS_9 1 ++#define PIIX4_OCW2_ILS_10 2 ++#define PIIX4_OCW2_ILS_11 3 ++#define PIIX4_OCW2_ILS_12 4 ++#define PIIX4_OCW2_ILS_13 5 ++#define PIIX4_OCW2_ILS_14 6 ++#define PIIX4_OCW2_ILS_15 7 ++ ++#define PIIX4_OCW3_SEL (0x1 << 3) ++ ++#define PIIX4_OCW3_IRR 0x2 ++#define PIIX4_OCW3_ISR 0x3 ++ ++#endif /* !(PIIX4_H) */ +diff -ruN linux/include/asm-mips/mips-boards/prom.h linux-mips/include/asm-mips/mips-boards/prom.h +--- linux/include/asm-mips/mips-boards/prom.h Wed Dec 31 16:00:00 1969 ++++ linux-mips/include/asm-mips/mips-boards/prom.h Fri Nov 10 00:12:20 2000 +@@ -0,0 +1,49 @@ ++/* ++ * Carsten Langgaard, carstenl@mips.com ++ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. ++ * ++ * ######################################################################## ++ * ++ * This program is free software; you can distribute it and/or modify it ++ * under the terms of the GNU General Public License (Version 2) as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. ++ * ++ * ######################################################################## ++ * ++ * MIPS boards bootprom interface for the Linux kernel. ++ * ++ */ ++ ++#ifndef _MIPS_PROM_H ++#define _MIPS_PROM_H ++ ++extern char *prom_getcmdline(void); ++extern char *prom_getenv(char *name); ++extern void setup_prom_printf(void); ++extern void prom_printf(char *fmt, ...); ++extern void prom_init_cmdline(void); ++extern void prom_meminit(void); ++extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem); ++extern void prom_free_prom_memory (void); ++extern void mips_display_message(const char *str); ++extern void mips_display_word(unsigned int num); ++extern int get_ethernet_addr(char *ethernet_addr); ++ ++/* Memory descriptor management. */ ++#define PROM_MAX_PMEMBLOCKS 32 ++struct prom_pmemblock { ++ unsigned long base; /* Within KSEG0. */ ++ unsigned int size; /* In bytes. */ ++ unsigned int type; /* free or prom memory */ ++}; ++ ++#endif /* !(_MIPS_PROM_H) */ +diff -ruN linux/include/asm-mips/mipsregs.h linux-mips/include/asm-mips/mipsregs.h +--- linux/include/asm-mips/mipsregs.h Sun Jul 9 22:18:15 2000 ++++ linux-mips/include/asm-mips/mipsregs.h Fri Nov 10 00:11:53 2000 +@@ -1,10 +1,10 @@ +-/* $Id: mipsregs.h,v 1.6 1999/07/26 19:42:43 harald Exp $ +- * ++/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * +- * Copyright (C) 1994, 1995, 1996, 1997 by Ralf Baechle ++ * Copyright (C) 1994, 1995, 1996, 1997, 2000 by Ralf Baechle ++ * Copyright (C) 2000 Silicon Graphics, Inc. + * Modified for further R[236]000 support by Paul M. Antoine, 1996. + */ + #ifndef __ASM_MIPS_MIPSREGS_H +@@ -184,42 +184,6 @@ + __BUILD_SET_CP0(config,CP0_CONFIG) + + #endif /* defined (_LANGUAGE_ASSEMBLY) */ +- +-/* +- * Inline code for use of the ll and sc instructions +- * +- * FIXME: This instruction is only available on MIPS ISA >=2. +- * Since these operations are only being used for atomic operations +- * the easiest workaround for the R[23]00 is to disable interrupts. +- * This fails for R3000 SMP machines which use that many different +- * technologies as replacement that it is difficult to create even +- * just a hook for for all machines to hook into. The only good +- * thing is that there is currently no R3000 SMP machine on the +- * Linux/MIPS target list ... +- */ +-#define load_linked(addr) \ +-({ \ +- unsigned int __res; \ +- \ +- __asm__ __volatile__( \ +- "ll\t%0,(%1)" \ +- : "=r" (__res) \ +- : "r" ((unsigned long) (addr))); \ +- \ +- __res; \ +-}) +- +-#define store_conditional(addr,value) \ +-({ \ +- int __res; \ +- \ +- __asm__ __volatile__( \ +- "sc\t%0,(%2)" \ +- : "=r" (__res) \ +- : "0" (value), "r" (addr)); \ +- \ +- __res; \ +-}) + + /* + * Bitfields in the R4xx0 cp0 status register +diff -ruN linux/include/asm-mips/pci.h linux-mips/include/asm-mips/pci.h +--- linux/include/asm-mips/pci.h Thu Jun 22 07:17:16 2000 ++++ linux-mips/include/asm-mips/pci.h Fri Nov 10 00:11:55 2000 +@@ -40,7 +40,7 @@ + #include + #include + +-#ifdef CONFIG_DDB5074 ++#if (defined(CONFIG_DDB5074) || defined(CONFIG_DDB5476)) + #undef PCIBIOS_MIN_IO + #undef PCIBIOS_MIN_MEM + #define PCIBIOS_MIN_IO 0x0100000 +diff -ruN linux/include/asm-mips/pgtable.h linux-mips/include/asm-mips/pgtable.h +--- linux/include/asm-mips/pgtable.h Mon Aug 7 21:02:27 2000 ++++ linux-mips/include/asm-mips/pgtable.h Fri Nov 10 00:11:57 2000 +@@ -3,7 +3,7 @@ + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * +- * Copyright (C) 1994 - 1999 by Ralf Baechle at alii ++ * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 by Ralf Baechle at alii + * Copyright (C) 1999 Silicon Graphics, Inc. + */ + #ifndef _ASM_PGTABLE_H +@@ -25,6 +25,7 @@ + * - flush_cache_page(mm, vmaddr) flushes a single page + * - flush_cache_range(mm, start, end) flushes a range of pages + * - flush_page_to_ram(page) write back kernel page to ram ++ * - flush_icache_range(start, end) flush a range of instructions + */ + extern void (*_flush_cache_all)(void); + extern void (*_flush_cache_mm)(struct mm_struct *mm); +@@ -33,6 +34,9 @@ + extern void (*_flush_cache_page)(struct vm_area_struct *vma, unsigned long page); + extern void (*_flush_cache_sigtramp)(unsigned long addr); + extern void (*_flush_page_to_ram)(struct page * page); ++extern void (*_flush_icache_range)(unsigned long start, unsigned long end); ++extern void (*_flush_icache_page)(struct vm_area_struct *vma, ++ struct page *page, unsigned long addr); + + #define flush_dcache_page(page) do { } while (0) + +@@ -43,14 +47,8 @@ + #define flush_cache_sigtramp(addr) _flush_cache_sigtramp(addr) + #define flush_page_to_ram(page) _flush_page_to_ram(page) + +-#define flush_icache_range(start, end) flush_cache_all() +- +-#define flush_icache_page(vma, page) \ +-do { \ +- unsigned long addr; \ +- addr = (unsigned long) page_address(page); \ +- _flush_cache_page(vma, addr); \ +-} while (0) ++#define flush_icache_range(start, end) _flush_icache_range(start,end) ++#define flush_icache_page(vma, page, addr) _flush_icache_page(vma, page, addr) + + + /* +@@ -303,7 +301,7 @@ + extern inline void pgd_clear(pgd_t *pgdp) { } + + /* +- * Permanent address of a page. On MIPS64 we never have highmem, so this ++ * Permanent address of a page. On MIPS we never have highmem, so this + * is simple. + */ + #define page_address(page) ((page)->virtual) +@@ -390,7 +388,7 @@ + + extern inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) + { +- return __pte(((physpage & PAGE_MASK) - PAGE_OFFSET) | pgprot_val(pgprot)); ++ return __pte(physpage | pgprot_val(pgprot)); + } + + extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot) +@@ -640,6 +638,19 @@ + "mtc0 %0, $6\n\t" + ".set pop" + : : "r" (val)); ++} ++ ++extern inline unsigned long get_info(void) ++{ ++ unsigned long val; ++ ++ __asm__( ++ ".set push\n\t" ++ ".set reorder\n\t" ++ "mfc0 %0, $7\n\t" ++ ".set pop" ++ : "=r" (val)); ++ return val; + } + + /* CP0_TAGLO and CP0_TAGHI registers */ +diff -ruN linux/include/asm-mips/resource.h linux-mips/include/asm-mips/resource.h +--- linux/include/asm-mips/resource.h Thu Nov 23 15:51:49 2000 ++++ linux-mips/include/asm-mips/resource.h Fri Nov 10 00:11:59 2000 +@@ -26,13 +26,13 @@ + + #define RLIM_NLIMITS 11 /* Number of limit flavors. */ + ++#ifdef __KERNEL__ ++ + /* + * SuS says limits have to be unsigned. + * Which makes a ton more sense anyway. + */ + #define RLIM_INFINITY 0x7fffffffUL +- +-#ifdef __KERNEL__ + + #define INIT_RLIMITS \ + { \ +diff -ruN linux/include/asm-mips/riscos-syscall.h linux-mips/include/asm-mips/riscos-syscall.h +--- linux/include/asm-mips/riscos-syscall.h Wed Dec 31 16:00:00 1969 ++++ linux-mips/include/asm-mips/riscos-syscall.h Fri Nov 10 00:12:02 2000 +@@ -0,0 +1,979 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 1995, 96, 97, 98, 99, 2000 by Ralf Baechle ++ */ ++#ifndef _ASM_RISCOS_SYSCALL_H ++#define _ASM_RISCOS_SYSCALL_H ++ ++/* ++ * The syscalls 0 - 3999 are reserved for a down to the root syscall ++ * compatibility with RISC/os and IRIX. We'll see how to deal with the ++ * various "real" BSD variants like Ultrix, NetBSD ... ++ */ ++ ++/* ++ * SVR4 syscalls are in the range from 1 to 999 ++ */ ++#define __NR_SVR4 0 ++#define __NR_SVR4_syscall (__NR_SVR4 + 0) ++#define __NR_SVR4_exit (__NR_SVR4 + 1) ++#define __NR_SVR4_fork (__NR_SVR4 + 2) ++#define __NR_SVR4_read (__NR_SVR4 + 3) ++#define __NR_SVR4_write (__NR_SVR4 + 4) ++#define __NR_SVR4_open (__NR_SVR4 + 5) ++#define __NR_SVR4_close (__NR_SVR4 + 6) ++#define __NR_SVR4_wait (__NR_SVR4 + 7) ++#define __NR_SVR4_creat (__NR_SVR4 + 8) ++#define __NR_SVR4_link (__NR_SVR4 + 9) ++#define __NR_SVR4_unlink (__NR_SVR4 + 10) ++#define __NR_SVR4_exec (__NR_SVR4 + 11) ++#define __NR_SVR4_chdir (__NR_SVR4 + 12) ++#define __NR_SVR4_gtime (__NR_SVR4 + 13) ++#define __NR_SVR4_mknod (__NR_SVR4 + 14) ++#define __NR_SVR4_chmod (__NR_SVR4 + 15) ++#define __NR_SVR4_chown (__NR_SVR4 + 16) ++#define __NR_SVR4_sbreak (__NR_SVR4 + 17) ++#define __NR_SVR4_stat (__NR_SVR4 + 18) ++#define __NR_SVR4_lseek (__NR_SVR4 + 19) ++#define __NR_SVR4_getpid (__NR_SVR4 + 20) ++#define __NR_SVR4_mount (__NR_SVR4 + 21) ++#define __NR_SVR4_umount (__NR_SVR4 + 22) ++#define __NR_SVR4_setuid (__NR_SVR4 + 23) ++#define __NR_SVR4_getuid (__NR_SVR4 + 24) ++#define __NR_SVR4_stime (__NR_SVR4 + 25) ++#define __NR_SVR4_ptrace (__NR_SVR4 + 26) ++#define __NR_SVR4_alarm (__NR_SVR4 + 27) ++#define __NR_SVR4_fstat (__NR_SVR4 + 28) ++#define __NR_SVR4_pause (__NR_SVR4 + 29) ++#define __NR_SVR4_utime (__NR_SVR4 + 30) ++#define __NR_SVR4_stty (__NR_SVR4 + 31) ++#define __NR_SVR4_gtty (__NR_SVR4 + 32) ++#define __NR_SVR4_access (__NR_SVR4 + 33) ++#define __NR_SVR4_nice (__NR_SVR4 + 34) ++#define __NR_SVR4_statfs (__NR_SVR4 + 35) ++#define __NR_SVR4_sync (__NR_SVR4 + 36) ++#define __NR_SVR4_kill (__NR_SVR4 + 37) ++#define __NR_SVR4_fstatfs (__NR_SVR4 + 38) ++#define __NR_SVR4_setpgrp (__NR_SVR4 + 39) ++#define __NR_SVR4_cxenix (__NR_SVR4 + 40) ++#define __NR_SVR4_dup (__NR_SVR4 + 41) ++#define __NR_SVR4_pipe (__NR_SVR4 + 42) ++#define __NR_SVR4_times (__NR_SVR4 + 43) ++#define __NR_SVR4_profil (__NR_SVR4 + 44) ++#define __NR_SVR4_plock (__NR_SVR4 + 45) ++#define __NR_SVR4_setgid (__NR_SVR4 + 46) ++#define __NR_SVR4_getgid (__NR_SVR4 + 47) ++#define __NR_SVR4_sig (__NR_SVR4 + 48) ++#define __NR_SVR4_msgsys (__NR_SVR4 + 49) ++#define __NR_SVR4_sysmips (__NR_SVR4 + 50) ++#define __NR_SVR4_sysacct (__NR_SVR4 + 51) ++#define __NR_SVR4_shmsys (__NR_SVR4 + 52) ++#define __NR_SVR4_semsys (__NR_SVR4 + 53) ++#define __NR_SVR4_ioctl (__NR_SVR4 + 54) ++#define __NR_SVR4_uadmin (__NR_SVR4 + 55) ++#define __NR_SVR4_exch (__NR_SVR4 + 56) ++#define __NR_SVR4_utssys (__NR_SVR4 + 57) ++#define __NR_SVR4_fsync (__NR_SVR4 + 58) ++#define __NR_SVR4_exece (__NR_SVR4 + 59) ++#define __NR_SVR4_umask (__NR_SVR4 + 60) ++#define __NR_SVR4_chroot (__NR_SVR4 + 61) ++#define __NR_SVR4_fcntl (__NR_SVR4 + 62) ++#define __NR_SVR4_ulimit (__NR_SVR4 + 63) ++#define __NR_SVR4_reserved1 (__NR_SVR4 + 64) ++#define __NR_SVR4_reserved2 (__NR_SVR4 + 65) ++#define __NR_SVR4_reserved3 (__NR_SVR4 + 66) ++#define __NR_SVR4_reserved4 (__NR_SVR4 + 67) ++#define __NR_SVR4_reserved5 (__NR_SVR4 + 68) ++#define __NR_SVR4_reserved6 (__NR_SVR4 + 69) ++#define __NR_SVR4_advfs (__NR_SVR4 + 70) ++#define __NR_SVR4_unadvfs (__NR_SVR4 + 71) ++#define __NR_SVR4_unused1 (__NR_SVR4 + 72) ++#define __NR_SVR4_unused2 (__NR_SVR4 + 73) ++#define __NR_SVR4_rfstart (__NR_SVR4 + 74) ++#define __NR_SVR4_unused3 (__NR_SVR4 + 75) ++#define __NR_SVR4_rdebug (__NR_SVR4 + 76) ++#define __NR_SVR4_rfstop (__NR_SVR4 + 77) ++#define __NR_SVR4_rfsys (__NR_SVR4 + 78) ++#define __NR_SVR4_rmdir (__NR_SVR4 + 79) ++#define __NR_SVR4_mkdir (__NR_SVR4 + 80) ++#define __NR_SVR4_getdents (__NR_SVR4 + 81) ++#define __NR_SVR4_libattach (__NR_SVR4 + 82) ++#define __NR_SVR4_libdetach (__NR_SVR4 + 83) ++#define __NR_SVR4_sysfs (__NR_SVR4 + 84) ++#define __NR_SVR4_getmsg (__NR_SVR4 + 85) ++#define __NR_SVR4_putmsg (__NR_SVR4 + 86) ++#define __NR_SVR4_poll (__NR_SVR4 + 87) ++#define __NR_SVR4_lstat (__NR_SVR4 + 88) ++#define __NR_SVR4_symlink (__NR_SVR4 + 89) ++#define __NR_SVR4_readlink (__NR_SVR4 + 90) ++#define __NR_SVR4_setgroups (__NR_SVR4 + 91) ++#define __NR_SVR4_getgroups (__NR_SVR4 + 92) ++#define __NR_SVR4_fchmod (__NR_SVR4 + 93) ++#define __NR_SVR4_fchown (__NR_SVR4 + 94) ++#define __NR_SVR4_sigprocmask (__NR_SVR4 + 95) ++#define __NR_SVR4_sigsuspend (__NR_SVR4 + 96) ++#define __NR_SVR4_sigaltstack (__NR_SVR4 + 97) ++#define __NR_SVR4_sigaction (__NR_SVR4 + 98) ++#define __NR_SVR4_sigpending (__NR_SVR4 + 99) ++#define __NR_SVR4_setcontext (__NR_SVR4 + 100) ++#define __NR_SVR4_evsys (__NR_SVR4 + 101) ++#define __NR_SVR4_evtrapret (__NR_SVR4 + 102) ++#define __NR_SVR4_statvfs (__NR_SVR4 + 103) ++#define __NR_SVR4_fstatvfs (__NR_SVR4 + 104) ++#define __NR_SVR4_reserved7 (__NR_SVR4 + 105) ++#define __NR_SVR4_nfssys (__NR_SVR4 + 106) ++#define __NR_SVR4_waitid (__NR_SVR4 + 107) ++#define __NR_SVR4_sigsendset (__NR_SVR4 + 108) ++#define __NR_SVR4_hrtsys (__NR_SVR4 + 109) ++#define __NR_SVR4_acancel (__NR_SVR4 + 110) ++#define __NR_SVR4_async (__NR_SVR4 + 111) ++#define __NR_SVR4_priocntlset (__NR_SVR4 + 112) ++#define __NR_SVR4_pathconf (__NR_SVR4 + 113) ++#define __NR_SVR4_mincore (__NR_SVR4 + 114) ++#define __NR_SVR4_mmap (__NR_SVR4 + 115) ++#define __NR_SVR4_mprotect (__NR_SVR4 + 116) ++#define __NR_SVR4_munmap (__NR_SVR4 + 117) ++#define __NR_SVR4_fpathconf (__NR_SVR4 + 118) ++#define __NR_SVR4_vfork (__NR_SVR4 + 119) ++#define __NR_SVR4_fchdir (__NR_SVR4 + 120) ++#define __NR_SVR4_readv (__NR_SVR4 + 121) ++#define __NR_SVR4_writev (__NR_SVR4 + 122) ++#define __NR_SVR4_xstat (__NR_SVR4 + 123) ++#define __NR_SVR4_lxstat (__NR_SVR4 + 124) ++#define __NR_SVR4_fxstat (__NR_SVR4 + 125) ++#define __NR_SVR4_xmknod (__NR_SVR4 + 126) ++#define __NR_SVR4_clocal (__NR_SVR4 + 127) ++#define __NR_SVR4_setrlimit (__NR_SVR4 + 128) ++#define __NR_SVR4_getrlimit (__NR_SVR4 + 129) ++#define __NR_SVR4_lchown (__NR_SVR4 + 130) ++#define __NR_SVR4_memcntl (__NR_SVR4 + 131) ++#define __NR_SVR4_getpmsg (__NR_SVR4 + 132) ++#define __NR_SVR4_putpmsg (__NR_SVR4 + 133) ++#define __NR_SVR4_rename (__NR_SVR4 + 134) ++#define __NR_SVR4_nuname (__NR_SVR4 + 135) ++#define __NR_SVR4_setegid (__NR_SVR4 + 136) ++#define __NR_SVR4_sysconf (__NR_SVR4 + 137) ++#define __NR_SVR4_adjtime (__NR_SVR4 + 138) ++#define __NR_SVR4_sysinfo (__NR_SVR4 + 139) ++#define __NR_SVR4_reserved8 (__NR_SVR4 + 140) ++#define __NR_SVR4_seteuid (__NR_SVR4 + 141) ++#define __NR_SVR4_PYRAMID_statis (__NR_SVR4 + 142) ++#define __NR_SVR4_PYRAMID_tuning (__NR_SVR4 + 143) ++#define __NR_SVR4_PYRAMID_forcerr (__NR_SVR4 + 144) ++#define __NR_SVR4_PYRAMID_mpcntl (__NR_SVR4 + 145) ++#define __NR_SVR4_reserved9 (__NR_SVR4 + 146) ++#define __NR_SVR4_reserved10 (__NR_SVR4 + 147) ++#define __NR_SVR4_reserved11 (__NR_SVR4 + 148) ++#define __NR_SVR4_reserved12 (__NR_SVR4 + 149) ++#define __NR_SVR4_reserved13 (__NR_SVR4 + 150) ++#define __NR_SVR4_reserved14 (__NR_SVR4 + 151) ++#define __NR_SVR4_reserved15 (__NR_SVR4 + 152) ++#define __NR_SVR4_reserved16 (__NR_SVR4 + 153) ++#define __NR_SVR4_reserved17 (__NR_SVR4 + 154) ++#define __NR_SVR4_reserved18 (__NR_SVR4 + 155) ++#define __NR_SVR4_reserved19 (__NR_SVR4 + 156) ++#define __NR_SVR4_reserved20 (__NR_SVR4 + 157) ++#define __NR_SVR4_reserved21 (__NR_SVR4 + 158) ++#define __NR_SVR4_reserved22 (__NR_SVR4 + 159) ++#define __NR_SVR4_reserved23 (__NR_SVR4 + 160) ++#define __NR_SVR4_reserved24 (__NR_SVR4 + 161) ++#define __NR_SVR4_reserved25 (__NR_SVR4 + 162) ++#define __NR_SVR4_reserved26 (__NR_SVR4 + 163) ++#define __NR_SVR4_reserved27 (__NR_SVR4 + 164) ++#define __NR_SVR4_reserved28 (__NR_SVR4 + 165) ++#define __NR_SVR4_reserved29 (__NR_SVR4 + 166) ++#define __NR_SVR4_reserved30 (__NR_SVR4 + 167) ++#define __NR_SVR4_reserved31 (__NR_SVR4 + 168) ++#define __NR_SVR4_reserved32 (__NR_SVR4 + 169) ++#define __NR_SVR4_reserved33 (__NR_SVR4 + 170) ++#define __NR_SVR4_reserved34 (__NR_SVR4 + 171) ++#define __NR_SVR4_reserved35 (__NR_SVR4 + 172) ++#define __NR_SVR4_reserved36 (__NR_SVR4 + 173) ++#define __NR_SVR4_reserved37 (__NR_SVR4 + 174) ++#define __NR_SVR4_reserved38 (__NR_SVR4 + 175) ++#define __NR_SVR4_reserved39 (__NR_SVR4 + 176) ++#define __NR_SVR4_reserved40 (__NR_SVR4 + 177) ++#define __NR_SVR4_reserved41 (__NR_SVR4 + 178) ++#define __NR_SVR4_reserved42 (__NR_SVR4 + 179) ++#define __NR_SVR4_reserved43 (__NR_SVR4 + 180) ++#define __NR_SVR4_reserved44 (__NR_SVR4 + 181) ++#define __NR_SVR4_reserved45 (__NR_SVR4 + 182) ++#define __NR_SVR4_reserved46 (__NR_SVR4 + 183) ++#define __NR_SVR4_reserved47 (__NR_SVR4 + 184) ++#define __NR_SVR4_reserved48 (__NR_SVR4 + 185) ++#define __NR_SVR4_reserved49 (__NR_SVR4 + 186) ++#define __NR_SVR4_reserved50 (__NR_SVR4 + 187) ++#define __NR_SVR4_reserved51 (__NR_SVR4 + 188) ++#define __NR_SVR4_reserved52 (__NR_SVR4 + 189) ++#define __NR_SVR4_reserved53 (__NR_SVR4 + 190) ++#define __NR_SVR4_reserved54 (__NR_SVR4 + 191) ++#define __NR_SVR4_reserved55 (__NR_SVR4 + 192) ++#define __NR_SVR4_reserved56 (__NR_SVR4 + 193) ++#define __NR_SVR4_reserved57 (__NR_SVR4 + 194) ++#define __NR_SVR4_reserved58 (__NR_SVR4 + 195) ++#define __NR_SVR4_reserved59 (__NR_SVR4 + 196) ++#define __NR_SVR4_reserved60 (__NR_SVR4 + 197) ++#define __NR_SVR4_reserved61 (__NR_SVR4 + 198) ++#define __NR_SVR4_reserved62 (__NR_SVR4 + 199) ++#define __NR_SVR4_reserved63 (__NR_SVR4 + 200) ++#define __NR_SVR4_aread (__NR_SVR4 + 201) ++#define __NR_SVR4_awrite (__NR_SVR4 + 202) ++#define __NR_SVR4_listio (__NR_SVR4 + 203) ++#define __NR_SVR4_mips_acancel (__NR_SVR4 + 204) ++#define __NR_SVR4_astatus (__NR_SVR4 + 205) ++#define __NR_SVR4_await (__NR_SVR4 + 206) ++#define __NR_SVR4_areadv (__NR_SVR4 + 207) ++#define __NR_SVR4_awritev (__NR_SVR4 + 208) ++#define __NR_SVR4_MIPS_reserved1 (__NR_SVR4 + 209) ++#define __NR_SVR4_MIPS_reserved2 (__NR_SVR4 + 210) ++#define __NR_SVR4_MIPS_reserved3 (__NR_SVR4 + 211) ++#define __NR_SVR4_MIPS_reserved4 (__NR_SVR4 + 212) ++#define __NR_SVR4_MIPS_reserved5 (__NR_SVR4 + 213) ++#define __NR_SVR4_MIPS_reserved6 (__NR_SVR4 + 214) ++#define __NR_SVR4_MIPS_reserved7 (__NR_SVR4 + 215) ++#define __NR_SVR4_MIPS_reserved8 (__NR_SVR4 + 216) ++#define __NR_SVR4_MIPS_reserved9 (__NR_SVR4 + 217) ++#define __NR_SVR4_MIPS_reserved10 (__NR_SVR4 + 218) ++#define __NR_SVR4_MIPS_reserved11 (__NR_SVR4 + 219) ++#define __NR_SVR4_MIPS_reserved12 (__NR_SVR4 + 220) ++#define __NR_SVR4_CDC_reserved1 (__NR_SVR4 + 221) ++#define __NR_SVR4_CDC_reserved2 (__NR_SVR4 + 222) ++#define __NR_SVR4_CDC_reserved3 (__NR_SVR4 + 223) ++#define __NR_SVR4_CDC_reserved4 (__NR_SVR4 + 224) ++#define __NR_SVR4_CDC_reserved5 (__NR_SVR4 + 225) ++#define __NR_SVR4_CDC_reserved6 (__NR_SVR4 + 226) ++#define __NR_SVR4_CDC_reserved7 (__NR_SVR4 + 227) ++#define __NR_SVR4_CDC_reserved8 (__NR_SVR4 + 228) ++#define __NR_SVR4_CDC_reserved9 (__NR_SVR4 + 229) ++#define __NR_SVR4_CDC_reserved10 (__NR_SVR4 + 230) ++#define __NR_SVR4_CDC_reserved11 (__NR_SVR4 + 231) ++#define __NR_SVR4_CDC_reserved12 (__NR_SVR4 + 232) ++#define __NR_SVR4_CDC_reserved13 (__NR_SVR4 + 233) ++#define __NR_SVR4_CDC_reserved14 (__NR_SVR4 + 234) ++#define __NR_SVR4_CDC_reserved15 (__NR_SVR4 + 235) ++#define __NR_SVR4_CDC_reserved16 (__NR_SVR4 + 236) ++#define __NR_SVR4_CDC_reserved17 (__NR_SVR4 + 237) ++#define __NR_SVR4_CDC_reserved18 (__NR_SVR4 + 238) ++#define __NR_SVR4_CDC_reserved19 (__NR_SVR4 + 239) ++#define __NR_SVR4_CDC_reserved20 (__NR_SVR4 + 240) ++ ++/* ++ * SYS V syscalls are in the range from 1000 to 1999 ++ */ ++#define __NR_SYSV 1000 ++#define __NR_SYSV_syscall (__NR_SYSV + 0) ++#define __NR_SYSV_exit (__NR_SYSV + 1) ++#define __NR_SYSV_fork (__NR_SYSV + 2) ++#define __NR_SYSV_read (__NR_SYSV + 3) ++#define __NR_SYSV_write (__NR_SYSV + 4) ++#define __NR_SYSV_open (__NR_SYSV + 5) ++#define __NR_SYSV_close (__NR_SYSV + 6) ++#define __NR_SYSV_wait (__NR_SYSV + 7) ++#define __NR_SYSV_creat (__NR_SYSV + 8) ++#define __NR_SYSV_link (__NR_SYSV + 9) ++#define __NR_SYSV_unlink (__NR_SYSV + 10) ++#define __NR_SYSV_execv (__NR_SYSV + 11) ++#define __NR_SYSV_chdir (__NR_SYSV + 12) ++#define __NR_SYSV_time (__NR_SYSV + 13) ++#define __NR_SYSV_mknod (__NR_SYSV + 14) ++#define __NR_SYSV_chmod (__NR_SYSV + 15) ++#define __NR_SYSV_chown (__NR_SYSV + 16) ++#define __NR_SYSV_brk (__NR_SYSV + 17) ++#define __NR_SYSV_stat (__NR_SYSV + 18) ++#define __NR_SYSV_lseek (__NR_SYSV + 19) ++#define __NR_SYSV_getpid (__NR_SYSV + 20) ++#define __NR_SYSV_mount (__NR_SYSV + 21) ++#define __NR_SYSV_umount (__NR_SYSV + 22) ++#define __NR_SYSV_setuid (__NR_SYSV + 23) ++#define __NR_SYSV_getuid (__NR_SYSV + 24) ++#define __NR_SYSV_stime (__NR_SYSV + 25) ++#define __NR_SYSV_ptrace (__NR_SYSV + 26) ++#define __NR_SYSV_alarm (__NR_SYSV + 27) ++#define __NR_SYSV_fstat (__NR_SYSV + 28) ++#define __NR_SYSV_pause (__NR_SYSV + 29) ++#define __NR_SYSV_utime (__NR_SYSV + 30) ++#define __NR_SYSV_stty (__NR_SYSV + 31) ++#define __NR_SYSV_gtty (__NR_SYSV + 32) ++#define __NR_SYSV_access (__NR_SYSV + 33) ++#define __NR_SYSV_nice (__NR_SYSV + 34) ++#define __NR_SYSV_statfs (__NR_SYSV + 35) ++#define __NR_SYSV_sync (__NR_SYSV + 36) ++#define __NR_SYSV_kill (__NR_SYSV + 37) ++#define __NR_SYSV_fstatfs (__NR_SYSV + 38) ++#define __NR_SYSV_setpgrp (__NR_SYSV + 39) ++#define __NR_SYSV_syssgi (__NR_SYSV + 40) ++#define __NR_SYSV_dup (__NR_SYSV + 41) ++#define __NR_SYSV_pipe (__NR_SYSV + 42) ++#define __NR_SYSV_times (__NR_SYSV + 43) ++#define __NR_SYSV_profil (__NR_SYSV + 44) ++#define __NR_SYSV_plock (__NR_SYSV + 45) ++#define __NR_SYSV_setgid (__NR_SYSV + 46) ++#define __NR_SYSV_getgid (__NR_SYSV + 47) ++#define __NR_SYSV_sig (__NR_SYSV + 48) ++#define __NR_SYSV_msgsys (__NR_SYSV + 49) ++#define __NR_SYSV_sysmips (__NR_SYSV + 50) ++#define __NR_SYSV_acct (__NR_SYSV + 51) ++#define __NR_SYSV_shmsys (__NR_SYSV + 52) ++#define __NR_SYSV_semsys (__NR_SYSV + 53) ++#define __NR_SYSV_ioctl (__NR_SYSV + 54) ++#define __NR_SYSV_uadmin (__NR_SYSV + 55) ++#define __NR_SYSV_sysmp (__NR_SYSV + 56) ++#define __NR_SYSV_utssys (__NR_SYSV + 57) ++#define __NR_SYSV_USG_reserved1 (__NR_SYSV + 58) ++#define __NR_SYSV_execve (__NR_SYSV + 59) ++#define __NR_SYSV_umask (__NR_SYSV + 60) ++#define __NR_SYSV_chroot (__NR_SYSV + 61) ++#define __NR_SYSV_fcntl (__NR_SYSV + 62) ++#define __NR_SYSV_ulimit (__NR_SYSV + 63) ++#define __NR_SYSV_SAFARI4_reserved1 (__NR_SYSV + 64) ++#define __NR_SYSV_SAFARI4_reserved2 (__NR_SYSV + 65) ++#define __NR_SYSV_SAFARI4_reserved3 (__NR_SYSV + 66) ++#define __NR_SYSV_SAFARI4_reserved4 (__NR_SYSV + 67) ++#define __NR_SYSV_SAFARI4_reserved5 (__NR_SYSV + 68) ++#define __NR_SYSV_SAFARI4_reserved6 (__NR_SYSV + 69) ++#define __NR_SYSV_advfs (__NR_SYSV + 70) ++#define __NR_SYSV_unadvfs (__NR_SYSV + 71) ++#define __NR_SYSV_rmount (__NR_SYSV + 72) ++#define __NR_SYSV_rumount (__NR_SYSV + 73) ++#define __NR_SYSV_rfstart (__NR_SYSV + 74) ++#define __NR_SYSV_getrlimit64 (__NR_SYSV + 75) ++#define __NR_SYSV_setrlimit64 (__NR_SYSV + 76) ++#define __NR_SYSV_nanosleep (__NR_SYSV + 77) ++#define __NR_SYSV_lseek64 (__NR_SYSV + 78) ++#define __NR_SYSV_rmdir (__NR_SYSV + 79) ++#define __NR_SYSV_mkdir (__NR_SYSV + 80) ++#define __NR_SYSV_getdents (__NR_SYSV + 81) ++#define __NR_SYSV_sginap (__NR_SYSV + 82) ++#define __NR_SYSV_sgikopt (__NR_SYSV + 83) ++#define __NR_SYSV_sysfs (__NR_SYSV + 84) ++#define __NR_SYSV_getmsg (__NR_SYSV + 85) ++#define __NR_SYSV_putmsg (__NR_SYSV + 86) ++#define __NR_SYSV_poll (__NR_SYSV + 87) ++#define __NR_SYSV_sigreturn (__NR_SYSV + 88) ++#define __NR_SYSV_accept (__NR_SYSV + 89) ++#define __NR_SYSV_bind (__NR_SYSV + 90) ++#define __NR_SYSV_connect (__NR_SYSV + 91) ++#define __NR_SYSV_gethostid (__NR_SYSV + 92) ++#define __NR_SYSV_getpeername (__NR_SYSV + 93) ++#define __NR_SYSV_getsockname (__NR_SYSV + 94) ++#define __NR_SYSV_getsockopt (__NR_SYSV + 95) ++#define __NR_SYSV_listen (__NR_SYSV + 96) ++#define __NR_SYSV_recv (__NR_SYSV + 97) ++#define __NR_SYSV_recvfrom (__NR_SYSV + 98) ++#define __NR_SYSV_recvmsg (__NR_SYSV + 99) ++#define __NR_SYSV_select (__NR_SYSV + 100) ++#define __NR_SYSV_send (__NR_SYSV + 101) ++#define __NR_SYSV_sendmsg (__NR_SYSV + 102) ++#define __NR_SYSV_sendto (__NR_SYSV + 103) ++#define __NR_SYSV_sethostid (__NR_SYSV + 104) ++#define __NR_SYSV_setsockopt (__NR_SYSV + 105) ++#define __NR_SYSV_shutdown (__NR_SYSV + 106) ++#define __NR_SYSV_socket (__NR_SYSV + 107) ++#define __NR_SYSV_gethostname (__NR_SYSV + 108) ++#define __NR_SYSV_sethostname (__NR_SYSV + 109) ++#define __NR_SYSV_getdomainname (__NR_SYSV + 110) ++#define __NR_SYSV_setdomainname (__NR_SYSV + 111) ++#define __NR_SYSV_truncate (__NR_SYSV + 112) ++#define __NR_SYSV_ftruncate (__NR_SYSV + 113) ++#define __NR_SYSV_rename (__NR_SYSV + 114) ++#define __NR_SYSV_symlink (__NR_SYSV + 115) ++#define __NR_SYSV_readlink (__NR_SYSV + 116) ++#define __NR_SYSV_lstat (__NR_SYSV + 117) ++#define __NR_SYSV_nfsmount (__NR_SYSV + 118) ++#define __NR_SYSV_nfssvc (__NR_SYSV + 119) ++#define __NR_SYSV_getfh (__NR_SYSV + 120) ++#define __NR_SYSV_async_daemon (__NR_SYSV + 121) ++#define __NR_SYSV_exportfs (__NR_SYSV + 122) ++#define __NR_SYSV_setregid (__NR_SYSV + 123) ++#define __NR_SYSV_setreuid (__NR_SYSV + 124) ++#define __NR_SYSV_getitimer (__NR_SYSV + 125) ++#define __NR_SYSV_setitimer (__NR_SYSV + 126) ++#define __NR_SYSV_adjtime (__NR_SYSV + 127) ++#define __NR_SYSV_BSD_getime (__NR_SYSV + 128) ++#define __NR_SYSV_sproc (__NR_SYSV + 129) ++#define __NR_SYSV_prctl (__NR_SYSV + 130) ++#define __NR_SYSV_procblk (__NR_SYSV + 131) ++#define __NR_SYSV_sprocsp (__NR_SYSV + 132) ++#define __NR_SYSV_sgigsc (__NR_SYSV + 133) ++#define __NR_SYSV_mmap (__NR_SYSV + 134) ++#define __NR_SYSV_munmap (__NR_SYSV + 135) ++#define __NR_SYSV_mprotect (__NR_SYSV + 136) ++#define __NR_SYSV_msync (__NR_SYSV + 137) ++#define __NR_SYSV_madvise (__NR_SYSV + 138) ++#define __NR_SYSV_pagelock (__NR_SYSV + 139) ++#define __NR_SYSV_getpagesize (__NR_SYSV + 140) ++#define __NR_SYSV_quotactl (__NR_SYSV + 141) ++#define __NR_SYSV_libdetach (__NR_SYSV + 142) ++#define __NR_SYSV_BSDgetpgrp (__NR_SYSV + 143) ++#define __NR_SYSV_BSDsetpgrp (__NR_SYSV + 144) ++#define __NR_SYSV_vhangup (__NR_SYSV + 145) ++#define __NR_SYSV_fsync (__NR_SYSV + 146) ++#define __NR_SYSV_fchdir (__NR_SYSV + 147) ++#define __NR_SYSV_getrlimit (__NR_SYSV + 148) ++#define __NR_SYSV_setrlimit (__NR_SYSV + 149) ++#define __NR_SYSV_cacheflush (__NR_SYSV + 150) ++#define __NR_SYSV_cachectl (__NR_SYSV + 151) ++#define __NR_SYSV_fchown (__NR_SYSV + 152) ++#define __NR_SYSV_fchmod (__NR_SYSV + 153) ++#define __NR_SYSV_wait3 (__NR_SYSV + 154) ++#define __NR_SYSV_socketpair (__NR_SYSV + 155) ++#define __NR_SYSV_sysinfo (__NR_SYSV + 156) ++#define __NR_SYSV_nuname (__NR_SYSV + 157) ++#define __NR_SYSV_xstat (__NR_SYSV + 158) ++#define __NR_SYSV_lxstat (__NR_SYSV + 159) ++#define __NR_SYSV_fxstat (__NR_SYSV + 160) ++#define __NR_SYSV_xmknod (__NR_SYSV + 161) ++#define __NR_SYSV_ksigaction (__NR_SYSV + 162) ++#define __NR_SYSV_sigpending (__NR_SYSV + 163) ++#define __NR_SYSV_sigprocmask (__NR_SYSV + 164) ++#define __NR_SYSV_sigsuspend (__NR_SYSV + 165) ++#define __NR_SYSV_sigpoll (__NR_SYSV + 166) ++#define __NR_SYSV_swapctl (__NR_SYSV + 167) ++#define __NR_SYSV_getcontext (__NR_SYSV + 168) ++#define __NR_SYSV_setcontext (__NR_SYSV + 169) ++#define __NR_SYSV_waitsys (__NR_SYSV + 170) ++#define __NR_SYSV_sigstack (__NR_SYSV + 171) ++#define __NR_SYSV_sigaltstack (__NR_SYSV + 172) ++#define __NR_SYSV_sigsendset (__NR_SYSV + 173) ++#define __NR_SYSV_statvfs (__NR_SYSV + 174) ++#define __NR_SYSV_fstatvfs (__NR_SYSV + 175) ++#define __NR_SYSV_getpmsg (__NR_SYSV + 176) ++#define __NR_SYSV_putpmsg (__NR_SYSV + 177) ++#define __NR_SYSV_lchown (__NR_SYSV + 178) ++#define __NR_SYSV_priocntl (__NR_SYSV + 179) ++#define __NR_SYSV_ksigqueue (__NR_SYSV + 180) ++#define __NR_SYSV_readv (__NR_SYSV + 181) ++#define __NR_SYSV_writev (__NR_SYSV + 182) ++#define __NR_SYSV_truncate64 (__NR_SYSV + 183) ++#define __NR_SYSV_ftruncate64 (__NR_SYSV + 184) ++#define __NR_SYSV_mmap64 (__NR_SYSV + 185) ++#define __NR_SYSV_dmi (__NR_SYSV + 186) ++#define __NR_SYSV_pread (__NR_SYSV + 187) ++#define __NR_SYSV_pwrite (__NR_SYSV + 188) ++ ++/* ++ * BSD 4.3 syscalls are in the range from 2000 to 2999 ++ */ ++#define __NR_BSD43 2000 ++#define __NR_BSD43_syscall (__NR_BSD43 + 0) ++#define __NR_BSD43_exit (__NR_BSD43 + 1) ++#define __NR_BSD43_fork (__NR_BSD43 + 2) ++#define __NR_BSD43_read (__NR_BSD43 + 3) ++#define __NR_BSD43_write (__NR_BSD43 + 4) ++#define __NR_BSD43_open (__NR_BSD43 + 5) ++#define __NR_BSD43_close (__NR_BSD43 + 6) ++#define __NR_BSD43_wait (__NR_BSD43 + 7) ++#define __NR_BSD43_creat (__NR_BSD43 + 8) ++#define __NR_BSD43_link (__NR_BSD43 + 9) ++#define __NR_BSD43_unlink (__NR_BSD43 + 10) ++#define __NR_BSD43_exec (__NR_BSD43 + 11) ++#define __NR_BSD43_chdir (__NR_BSD43 + 12) ++#define __NR_BSD43_time (__NR_BSD43 + 13) ++#define __NR_BSD43_mknod (__NR_BSD43 + 14) ++#define __NR_BSD43_chmod (__NR_BSD43 + 15) ++#define __NR_BSD43_chown (__NR_BSD43 + 16) ++#define __NR_BSD43_sbreak (__NR_BSD43 + 17) ++#define __NR_BSD43_oldstat (__NR_BSD43 + 18) ++#define __NR_BSD43_lseek (__NR_BSD43 + 19) ++#define __NR_BSD43_getpid (__NR_BSD43 + 20) ++#define __NR_BSD43_oldmount (__NR_BSD43 + 21) ++#define __NR_BSD43_umount (__NR_BSD43 + 22) ++#define __NR_BSD43_setuid (__NR_BSD43 + 23) ++#define __NR_BSD43_getuid (__NR_BSD43 + 24) ++#define __NR_BSD43_stime (__NR_BSD43 + 25) ++#define __NR_BSD43_ptrace (__NR_BSD43 + 26) ++#define __NR_BSD43_alarm (__NR_BSD43 + 27) ++#define __NR_BSD43_oldfstat (__NR_BSD43 + 28) ++#define __NR_BSD43_pause (__NR_BSD43 + 29) ++#define __NR_BSD43_utime (__NR_BSD43 + 30) ++#define __NR_BSD43_stty (__NR_BSD43 + 31) ++#define __NR_BSD43_gtty (__NR_BSD43 + 32) ++#define __NR_BSD43_access (__NR_BSD43 + 33) ++#define __NR_BSD43_nice (__NR_BSD43 + 34) ++#define __NR_BSD43_ftime (__NR_BSD43 + 35) ++#define __NR_BSD43_sync (__NR_BSD43 + 36) ++#define __NR_BSD43_kill (__NR_BSD43 + 37) ++#define __NR_BSD43_stat (__NR_BSD43 + 38) ++#define __NR_BSD43_oldsetpgrp (__NR_BSD43 + 39) ++#define __NR_BSD43_lstat (__NR_BSD43 + 40) ++#define __NR_BSD43_dup (__NR_BSD43 + 41) ++#define __NR_BSD43_pipe (__NR_BSD43 + 42) ++#define __NR_BSD43_times (__NR_BSD43 + 43) ++#define __NR_BSD43_profil (__NR_BSD43 + 44) ++#define __NR_BSD43_msgsys (__NR_BSD43 + 45) ++#define __NR_BSD43_setgid (__NR_BSD43 + 46) ++#define __NR_BSD43_getgid (__NR_BSD43 + 47) ++#define __NR_BSD43_ssig (__NR_BSD43 + 48) ++#define __NR_BSD43_reserved1 (__NR_BSD43 + 49) ++#define __NR_BSD43_reserved2 (__NR_BSD43 + 50) ++#define __NR_BSD43_sysacct (__NR_BSD43 + 51) ++#define __NR_BSD43_phys (__NR_BSD43 + 52) ++#define __NR_BSD43_lock (__NR_BSD43 + 53) ++#define __NR_BSD43_ioctl (__NR_BSD43 + 54) ++#define __NR_BSD43_reboot (__NR_BSD43 + 55) ++#define __NR_BSD43_mpxchan (__NR_BSD43 + 56) ++#define __NR_BSD43_symlink (__NR_BSD43 + 57) ++#define __NR_BSD43_readlink (__NR_BSD43 + 58) ++#define __NR_BSD43_execve (__NR_BSD43 + 59) ++#define __NR_BSD43_umask (__NR_BSD43 + 60) ++#define __NR_BSD43_chroot (__NR_BSD43 + 61) ++#define __NR_BSD43_fstat (__NR_BSD43 + 62) ++#define __NR_BSD43_reserved3 (__NR_BSD43 + 63) ++#define __NR_BSD43_getpagesize (__NR_BSD43 + 64) ++#define __NR_BSD43_mremap (__NR_BSD43 + 65) ++#define __NR_BSD43_vfork (__NR_BSD43 + 66) ++#define __NR_BSD43_vread (__NR_BSD43 + 67) ++#define __NR_BSD43_vwrite (__NR_BSD43 + 68) ++#define __NR_BSD43_sbrk (__NR_BSD43 + 69) ++#define __NR_BSD43_sstk (__NR_BSD43 + 70) ++#define __NR_BSD43_mmap (__NR_BSD43 + 71) ++#define __NR_BSD43_vadvise (__NR_BSD43 + 72) ++#define __NR_BSD43_munmap (__NR_BSD43 + 73) ++#define __NR_BSD43_mprotect (__NR_BSD43 + 74) ++#define __NR_BSD43_madvise (__NR_BSD43 + 75) ++#define __NR_BSD43_vhangup (__NR_BSD43 + 76) ++#define __NR_BSD43_vlimit (__NR_BSD43 + 77) ++#define __NR_BSD43_mincore (__NR_BSD43 + 78) ++#define __NR_BSD43_getgroups (__NR_BSD43 + 79) ++#define __NR_BSD43_setgroups (__NR_BSD43 + 80) ++#define __NR_BSD43_getpgrp (__NR_BSD43 + 81) ++#define __NR_BSD43_setpgrp (__NR_BSD43 + 82) ++#define __NR_BSD43_setitimer (__NR_BSD43 + 83) ++#define __NR_BSD43_wait3 (__NR_BSD43 + 84) ++#define __NR_BSD43_swapon (__NR_BSD43 + 85) ++#define __NR_BSD43_getitimer (__NR_BSD43 + 86) ++#define __NR_BSD43_gethostname (__NR_BSD43 + 87) ++#define __NR_BSD43_sethostname (__NR_BSD43 + 88) ++#define __NR_BSD43_getdtablesize (__NR_BSD43 + 89) ++#define __NR_BSD43_dup2 (__NR_BSD43 + 90) ++#define __NR_BSD43_getdopt (__NR_BSD43 + 91) ++#define __NR_BSD43_fcntl (__NR_BSD43 + 92) ++#define __NR_BSD43_select (__NR_BSD43 + 93) ++#define __NR_BSD43_setdopt (__NR_BSD43 + 94) ++#define __NR_BSD43_fsync (__NR_BSD43 + 95) ++#define __NR_BSD43_setpriority (__NR_BSD43 + 96) ++#define __NR_BSD43_socket (__NR_BSD43 + 97) ++#define __NR_BSD43_connect (__NR_BSD43 + 98) ++#define __NR_BSD43_oldaccept (__NR_BSD43 + 99) ++#define __NR_BSD43_getpriority (__NR_BSD43 + 100) ++#define __NR_BSD43_send (__NR_BSD43 + 101) ++#define __NR_BSD43_recv (__NR_BSD43 + 102) ++#define __NR_BSD43_sigreturn (__NR_BSD43 + 103) ++#define __NR_BSD43_bind (__NR_BSD43 + 104) ++#define __NR_BSD43_setsockopt (__NR_BSD43 + 105) ++#define __NR_BSD43_listen (__NR_BSD43 + 106) ++#define __NR_BSD43_vtimes (__NR_BSD43 + 107) ++#define __NR_BSD43_sigvec (__NR_BSD43 + 108) ++#define __NR_BSD43_sigblock (__NR_BSD43 + 109) ++#define __NR_BSD43_sigsetmask (__NR_BSD43 + 110) ++#define __NR_BSD43_sigpause (__NR_BSD43 + 111) ++#define __NR_BSD43_sigstack (__NR_BSD43 + 112) ++#define __NR_BSD43_oldrecvmsg (__NR_BSD43 + 113) ++#define __NR_BSD43_oldsendmsg (__NR_BSD43 + 114) ++#define __NR_BSD43_vtrace (__NR_BSD43 + 115) ++#define __NR_BSD43_gettimeofday (__NR_BSD43 + 116) ++#define __NR_BSD43_getrusage (__NR_BSD43 + 117) ++#define __NR_BSD43_getsockopt (__NR_BSD43 + 118) ++#define __NR_BSD43_reserved4 (__NR_BSD43 + 119) ++#define __NR_BSD43_readv (__NR_BSD43 + 120) ++#define __NR_BSD43_writev (__NR_BSD43 + 121) ++#define __NR_BSD43_settimeofday (__NR_BSD43 + 122) ++#define __NR_BSD43_fchown (__NR_BSD43 + 123) ++#define __NR_BSD43_fchmod (__NR_BSD43 + 124) ++#define __NR_BSD43_oldrecvfrom (__NR_BSD43 + 125) ++#define __NR_BSD43_setreuid (__NR_BSD43 + 126) ++#define __NR_BSD43_setregid (__NR_BSD43 + 127) ++#define __NR_BSD43_rename (__NR_BSD43 + 128) ++#define __NR_BSD43_truncate (__NR_BSD43 + 129) ++#define __NR_BSD43_ftruncate (__NR_BSD43 + 130) ++#define __NR_BSD43_flock (__NR_BSD43 + 131) ++#define __NR_BSD43_semsys (__NR_BSD43 + 132) ++#define __NR_BSD43_sendto (__NR_BSD43 + 133) ++#define __NR_BSD43_shutdown (__NR_BSD43 + 134) ++#define __NR_BSD43_socketpair (__NR_BSD43 + 135) ++#define __NR_BSD43_mkdir (__NR_BSD43 + 136) ++#define __NR_BSD43_rmdir (__NR_BSD43 + 137) ++#define __NR_BSD43_utimes (__NR_BSD43 + 138) ++#define __NR_BSD43_sigcleanup (__NR_BSD43 + 139) ++#define __NR_BSD43_adjtime (__NR_BSD43 + 140) ++#define __NR_BSD43_oldgetpeername (__NR_BSD43 + 141) ++#define __NR_BSD43_gethostid (__NR_BSD43 + 142) ++#define __NR_BSD43_sethostid (__NR_BSD43 + 143) ++#define __NR_BSD43_getrlimit (__NR_BSD43 + 144) ++#define __NR_BSD43_setrlimit (__NR_BSD43 + 145) ++#define __NR_BSD43_killpg (__NR_BSD43 + 146) ++#define __NR_BSD43_shmsys (__NR_BSD43 + 147) ++#define __NR_BSD43_quota (__NR_BSD43 + 148) ++#define __NR_BSD43_qquota (__NR_BSD43 + 149) ++#define __NR_BSD43_oldgetsockname (__NR_BSD43 + 150) ++#define __NR_BSD43_sysmips (__NR_BSD43 + 151) ++#define __NR_BSD43_cacheflush (__NR_BSD43 + 152) ++#define __NR_BSD43_cachectl (__NR_BSD43 + 153) ++#define __NR_BSD43_debug (__NR_BSD43 + 154) ++#define __NR_BSD43_reserved5 (__NR_BSD43 + 155) ++#define __NR_BSD43_reserved6 (__NR_BSD43 + 156) ++#define __NR_BSD43_nfs_mount (__NR_BSD43 + 157) ++#define __NR_BSD43_nfs_svc (__NR_BSD43 + 158) ++#define __NR_BSD43_getdirentries (__NR_BSD43 + 159) ++#define __NR_BSD43_statfs (__NR_BSD43 + 160) ++#define __NR_BSD43_fstatfs (__NR_BSD43 + 161) ++#define __NR_BSD43_unmount (__NR_BSD43 + 162) ++#define __NR_BSD43_async_daemon (__NR_BSD43 + 163) ++#define __NR_BSD43_nfs_getfh (__NR_BSD43 + 164) ++#define __NR_BSD43_getdomainname (__NR_BSD43 + 165) ++#define __NR_BSD43_setdomainname (__NR_BSD43 + 166) ++#define __NR_BSD43_pcfs_mount (__NR_BSD43 + 167) ++#define __NR_BSD43_quotactl (__NR_BSD43 + 168) ++#define __NR_BSD43_oldexportfs (__NR_BSD43 + 169) ++#define __NR_BSD43_smount (__NR_BSD43 + 170) ++#define __NR_BSD43_mipshwconf (__NR_BSD43 + 171) ++#define __NR_BSD43_exportfs (__NR_BSD43 + 172) ++#define __NR_BSD43_nfsfh_open (__NR_BSD43 + 173) ++#define __NR_BSD43_libattach (__NR_BSD43 + 174) ++#define __NR_BSD43_libdetach (__NR_BSD43 + 175) ++#define __NR_BSD43_accept (__NR_BSD43 + 176) ++#define __NR_BSD43_reserved7 (__NR_BSD43 + 177) ++#define __NR_BSD43_reserved8 (__NR_BSD43 + 178) ++#define __NR_BSD43_recvmsg (__NR_BSD43 + 179) ++#define __NR_BSD43_recvfrom (__NR_BSD43 + 180) ++#define __NR_BSD43_sendmsg (__NR_BSD43 + 181) ++#define __NR_BSD43_getpeername (__NR_BSD43 + 182) ++#define __NR_BSD43_getsockname (__NR_BSD43 + 183) ++#define __NR_BSD43_aread (__NR_BSD43 + 184) ++#define __NR_BSD43_awrite (__NR_BSD43 + 185) ++#define __NR_BSD43_listio (__NR_BSD43 + 186) ++#define __NR_BSD43_acancel (__NR_BSD43 + 187) ++#define __NR_BSD43_astatus (__NR_BSD43 + 188) ++#define __NR_BSD43_await (__NR_BSD43 + 189) ++#define __NR_BSD43_areadv (__NR_BSD43 + 190) ++#define __NR_BSD43_awritev (__NR_BSD43 + 191) ++ ++/* ++ * POSIX syscalls are in the range from 3000 to 3999 ++ */ ++#define __NR_POSIX 3000 ++#define __NR_POSIX_syscall (__NR_POSIX + 0) ++#define __NR_POSIX_exit (__NR_POSIX + 1) ++#define __NR_POSIX_fork (__NR_POSIX + 2) ++#define __NR_POSIX_read (__NR_POSIX + 3) ++#define __NR_POSIX_write (__NR_POSIX + 4) ++#define __NR_POSIX_open (__NR_POSIX + 5) ++#define __NR_POSIX_close (__NR_POSIX + 6) ++#define __NR_POSIX_wait (__NR_POSIX + 7) ++#define __NR_POSIX_creat (__NR_POSIX + 8) ++#define __NR_POSIX_link (__NR_POSIX + 9) ++#define __NR_POSIX_unlink (__NR_POSIX + 10) ++#define __NR_POSIX_exec (__NR_POSIX + 11) ++#define __NR_POSIX_chdir (__NR_POSIX + 12) ++#define __NR_POSIX_gtime (__NR_POSIX + 13) ++#define __NR_POSIX_mknod (__NR_POSIX + 14) ++#define __NR_POSIX_chmod (__NR_POSIX + 15) ++#define __NR_POSIX_chown (__NR_POSIX + 16) ++#define __NR_POSIX_sbreak (__NR_POSIX + 17) ++#define __NR_POSIX_stat (__NR_POSIX + 18) ++#define __NR_POSIX_lseek (__NR_POSIX + 19) ++#define __NR_POSIX_getpid (__NR_POSIX + 20) ++#define __NR_POSIX_mount (__NR_POSIX + 21) ++#define __NR_POSIX_umount (__NR_POSIX + 22) ++#define __NR_POSIX_setuid (__NR_POSIX + 23) ++#define __NR_POSIX_getuid (__NR_POSIX + 24) ++#define __NR_POSIX_stime (__NR_POSIX + 25) ++#define __NR_POSIX_ptrace (__NR_POSIX + 26) ++#define __NR_POSIX_alarm (__NR_POSIX + 27) ++#define __NR_POSIX_fstat (__NR_POSIX + 28) ++#define __NR_POSIX_pause (__NR_POSIX + 29) ++#define __NR_POSIX_utime (__NR_POSIX + 30) ++#define __NR_POSIX_stty (__NR_POSIX + 31) ++#define __NR_POSIX_gtty (__NR_POSIX + 32) ++#define __NR_POSIX_access (__NR_POSIX + 33) ++#define __NR_POSIX_nice (__NR_POSIX + 34) ++#define __NR_POSIX_statfs (__NR_POSIX + 35) ++#define __NR_POSIX_sync (__NR_POSIX + 36) ++#define __NR_POSIX_kill (__NR_POSIX + 37) ++#define __NR_POSIX_fstatfs (__NR_POSIX + 38) ++#define __NR_POSIX_getpgrp (__NR_POSIX + 39) ++#define __NR_POSIX_syssgi (__NR_POSIX + 40) ++#define __NR_POSIX_dup (__NR_POSIX + 41) ++#define __NR_POSIX_pipe (__NR_POSIX + 42) ++#define __NR_POSIX_times (__NR_POSIX + 43) ++#define __NR_POSIX_profil (__NR_POSIX + 44) ++#define __NR_POSIX_lock (__NR_POSIX + 45) ++#define __NR_POSIX_setgid (__NR_POSIX + 46) ++#define __NR_POSIX_getgid (__NR_POSIX + 47) ++#define __NR_POSIX_sig (__NR_POSIX + 48) ++#define __NR_POSIX_msgsys (__NR_POSIX + 49) ++#define __NR_POSIX_sysmips (__NR_POSIX + 50) ++#define __NR_POSIX_sysacct (__NR_POSIX + 51) ++#define __NR_POSIX_shmsys (__NR_POSIX + 52) ++#define __NR_POSIX_semsys (__NR_POSIX + 53) ++#define __NR_POSIX_ioctl (__NR_POSIX + 54) ++#define __NR_POSIX_uadmin (__NR_POSIX + 55) ++#define __NR_POSIX_exch (__NR_POSIX + 56) ++#define __NR_POSIX_utssys (__NR_POSIX + 57) ++#define __NR_POSIX_USG_reserved1 (__NR_POSIX + 58) ++#define __NR_POSIX_exece (__NR_POSIX + 59) ++#define __NR_POSIX_umask (__NR_POSIX + 60) ++#define __NR_POSIX_chroot (__NR_POSIX + 61) ++#define __NR_POSIX_fcntl (__NR_POSIX + 62) ++#define __NR_POSIX_ulimit (__NR_POSIX + 63) ++#define __NR_POSIX_SAFARI4_reserved1 (__NR_POSIX + 64) ++#define __NR_POSIX_SAFARI4_reserved2 (__NR_POSIX + 65) ++#define __NR_POSIX_SAFARI4_reserved3 (__NR_POSIX + 66) ++#define __NR_POSIX_SAFARI4_reserved4 (__NR_POSIX + 67) ++#define __NR_POSIX_SAFARI4_reserved5 (__NR_POSIX + 68) ++#define __NR_POSIX_SAFARI4_reserved6 (__NR_POSIX + 69) ++#define __NR_POSIX_advfs (__NR_POSIX + 70) ++#define __NR_POSIX_unadvfs (__NR_POSIX + 71) ++#define __NR_POSIX_rmount (__NR_POSIX + 72) ++#define __NR_POSIX_rumount (__NR_POSIX + 73) ++#define __NR_POSIX_rfstart (__NR_POSIX + 74) ++#define __NR_POSIX_reserved1 (__NR_POSIX + 75) ++#define __NR_POSIX_rdebug (__NR_POSIX + 76) ++#define __NR_POSIX_rfstop (__NR_POSIX + 77) ++#define __NR_POSIX_rfsys (__NR_POSIX + 78) ++#define __NR_POSIX_rmdir (__NR_POSIX + 79) ++#define __NR_POSIX_mkdir (__NR_POSIX + 80) ++#define __NR_POSIX_getdents (__NR_POSIX + 81) ++#define __NR_POSIX_sginap (__NR_POSIX + 82) ++#define __NR_POSIX_sgikopt (__NR_POSIX + 83) ++#define __NR_POSIX_sysfs (__NR_POSIX + 84) ++#define __NR_POSIX_getmsg (__NR_POSIX + 85) ++#define __NR_POSIX_putmsg (__NR_POSIX + 86) ++#define __NR_POSIX_poll (__NR_POSIX + 87) ++#define __NR_POSIX_sigreturn (__NR_POSIX + 88) ++#define __NR_POSIX_accept (__NR_POSIX + 89) ++#define __NR_POSIX_bind (__NR_POSIX + 90) ++#define __NR_POSIX_connect (__NR_POSIX + 91) ++#define __NR_POSIX_gethostid (__NR_POSIX + 92) ++#define __NR_POSIX_getpeername (__NR_POSIX + 93) ++#define __NR_POSIX_getsockname (__NR_POSIX + 94) ++#define __NR_POSIX_getsockopt (__NR_POSIX + 95) ++#define __NR_POSIX_listen (__NR_POSIX + 96) ++#define __NR_POSIX_recv (__NR_POSIX + 97) ++#define __NR_POSIX_recvfrom (__NR_POSIX + 98) ++#define __NR_POSIX_recvmsg (__NR_POSIX + 99) ++#define __NR_POSIX_select (__NR_POSIX + 100) ++#define __NR_POSIX_send (__NR_POSIX + 101) ++#define __NR_POSIX_sendmsg (__NR_POSIX + 102) ++#define __NR_POSIX_sendto (__NR_POSIX + 103) ++#define __NR_POSIX_sethostid (__NR_POSIX + 104) ++#define __NR_POSIX_setsockopt (__NR_POSIX + 105) ++#define __NR_POSIX_shutdown (__NR_POSIX + 106) ++#define __NR_POSIX_socket (__NR_POSIX + 107) ++#define __NR_POSIX_gethostname (__NR_POSIX + 108) ++#define __NR_POSIX_sethostname (__NR_POSIX + 109) ++#define __NR_POSIX_getdomainname (__NR_POSIX + 110) ++#define __NR_POSIX_setdomainname (__NR_POSIX + 111) ++#define __NR_POSIX_truncate (__NR_POSIX + 112) ++#define __NR_POSIX_ftruncate (__NR_POSIX + 113) ++#define __NR_POSIX_rename (__NR_POSIX + 114) ++#define __NR_POSIX_symlink (__NR_POSIX + 115) ++#define __NR_POSIX_readlink (__NR_POSIX + 116) ++#define __NR_POSIX_lstat (__NR_POSIX + 117) ++#define __NR_POSIX_nfs_mount (__NR_POSIX + 118) ++#define __NR_POSIX_nfs_svc (__NR_POSIX + 119) ++#define __NR_POSIX_nfs_getfh (__NR_POSIX + 120) ++#define __NR_POSIX_async_daemon (__NR_POSIX + 121) ++#define __NR_POSIX_exportfs (__NR_POSIX + 122) ++#define __NR_POSIX_SGI_setregid (__NR_POSIX + 123) ++#define __NR_POSIX_SGI_setreuid (__NR_POSIX + 124) ++#define __NR_POSIX_getitimer (__NR_POSIX + 125) ++#define __NR_POSIX_setitimer (__NR_POSIX + 126) ++#define __NR_POSIX_adjtime (__NR_POSIX + 127) ++#define __NR_POSIX_SGI_bsdgettime (__NR_POSIX + 128) ++#define __NR_POSIX_SGI_sproc (__NR_POSIX + 129) ++#define __NR_POSIX_SGI_prctl (__NR_POSIX + 130) ++#define __NR_POSIX_SGI_blkproc (__NR_POSIX + 131) ++#define __NR_POSIX_SGI_reserved1 (__NR_POSIX + 132) ++#define __NR_POSIX_SGI_sgigsc (__NR_POSIX + 133) ++#define __NR_POSIX_SGI_mmap (__NR_POSIX + 134) ++#define __NR_POSIX_SGI_munmap (__NR_POSIX + 135) ++#define __NR_POSIX_SGI_mprotect (__NR_POSIX + 136) ++#define __NR_POSIX_SGI_msync (__NR_POSIX + 137) ++#define __NR_POSIX_SGI_madvise (__NR_POSIX + 138) ++#define __NR_POSIX_SGI_mpin (__NR_POSIX + 139) ++#define __NR_POSIX_SGI_getpagesize (__NR_POSIX + 140) ++#define __NR_POSIX_SGI_libattach (__NR_POSIX + 141) ++#define __NR_POSIX_SGI_libdetach (__NR_POSIX + 142) ++#define __NR_POSIX_SGI_getpgrp (__NR_POSIX + 143) ++#define __NR_POSIX_SGI_setpgrp (__NR_POSIX + 144) ++#define __NR_POSIX_SGI_reserved2 (__NR_POSIX + 145) ++#define __NR_POSIX_SGI_reserved3 (__NR_POSIX + 146) ++#define __NR_POSIX_SGI_reserved4 (__NR_POSIX + 147) ++#define __NR_POSIX_SGI_reserved5 (__NR_POSIX + 148) ++#define __NR_POSIX_SGI_reserved6 (__NR_POSIX + 149) ++#define __NR_POSIX_cacheflush (__NR_POSIX + 150) ++#define __NR_POSIX_cachectl (__NR_POSIX + 151) ++#define __NR_POSIX_fchown (__NR_POSIX + 152) ++#define __NR_POSIX_fchmod (__NR_POSIX + 153) ++#define __NR_POSIX_wait3 (__NR_POSIX + 154) ++#define __NR_POSIX_mmap (__NR_POSIX + 155) ++#define __NR_POSIX_munmap (__NR_POSIX + 156) ++#define __NR_POSIX_madvise (__NR_POSIX + 157) ++#define __NR_POSIX_BSD_getpagesize (__NR_POSIX + 158) ++#define __NR_POSIX_setreuid (__NR_POSIX + 159) ++#define __NR_POSIX_setregid (__NR_POSIX + 160) ++#define __NR_POSIX_setpgid (__NR_POSIX + 161) ++#define __NR_POSIX_getgroups (__NR_POSIX + 162) ++#define __NR_POSIX_setgroups (__NR_POSIX + 163) ++#define __NR_POSIX_gettimeofday (__NR_POSIX + 164) ++#define __NR_POSIX_getrusage (__NR_POSIX + 165) ++#define __NR_POSIX_getrlimit (__NR_POSIX + 166) ++#define __NR_POSIX_setrlimit (__NR_POSIX + 167) ++#define __NR_POSIX_waitpid (__NR_POSIX + 168) ++#define __NR_POSIX_dup2 (__NR_POSIX + 169) ++#define __NR_POSIX_reserved2 (__NR_POSIX + 170) ++#define __NR_POSIX_reserved3 (__NR_POSIX + 171) ++#define __NR_POSIX_reserved4 (__NR_POSIX + 172) ++#define __NR_POSIX_reserved5 (__NR_POSIX + 173) ++#define __NR_POSIX_reserved6 (__NR_POSIX + 174) ++#define __NR_POSIX_reserved7 (__NR_POSIX + 175) ++#define __NR_POSIX_reserved8 (__NR_POSIX + 176) ++#define __NR_POSIX_reserved9 (__NR_POSIX + 177) ++#define __NR_POSIX_reserved10 (__NR_POSIX + 178) ++#define __NR_POSIX_reserved11 (__NR_POSIX + 179) ++#define __NR_POSIX_reserved12 (__NR_POSIX + 180) ++#define __NR_POSIX_reserved13 (__NR_POSIX + 181) ++#define __NR_POSIX_reserved14 (__NR_POSIX + 182) ++#define __NR_POSIX_reserved15 (__NR_POSIX + 183) ++#define __NR_POSIX_reserved16 (__NR_POSIX + 184) ++#define __NR_POSIX_reserved17 (__NR_POSIX + 185) ++#define __NR_POSIX_reserved18 (__NR_POSIX + 186) ++#define __NR_POSIX_reserved19 (__NR_POSIX + 187) ++#define __NR_POSIX_reserved20 (__NR_POSIX + 188) ++#define __NR_POSIX_reserved21 (__NR_POSIX + 189) ++#define __NR_POSIX_reserved22 (__NR_POSIX + 190) ++#define __NR_POSIX_reserved23 (__NR_POSIX + 191) ++#define __NR_POSIX_reserved24 (__NR_POSIX + 192) ++#define __NR_POSIX_reserved25 (__NR_POSIX + 193) ++#define __NR_POSIX_reserved26 (__NR_POSIX + 194) ++#define __NR_POSIX_reserved27 (__NR_POSIX + 195) ++#define __NR_POSIX_reserved28 (__NR_POSIX + 196) ++#define __NR_POSIX_reserved29 (__NR_POSIX + 197) ++#define __NR_POSIX_reserved30 (__NR_POSIX + 198) ++#define __NR_POSIX_reserved31 (__NR_POSIX + 199) ++#define __NR_POSIX_reserved32 (__NR_POSIX + 200) ++#define __NR_POSIX_reserved33 (__NR_POSIX + 201) ++#define __NR_POSIX_reserved34 (__NR_POSIX + 202) ++#define __NR_POSIX_reserved35 (__NR_POSIX + 203) ++#define __NR_POSIX_reserved36 (__NR_POSIX + 204) ++#define __NR_POSIX_reserved37 (__NR_POSIX + 205) ++#define __NR_POSIX_reserved38 (__NR_POSIX + 206) ++#define __NR_POSIX_reserved39 (__NR_POSIX + 207) ++#define __NR_POSIX_reserved40 (__NR_POSIX + 208) ++#define __NR_POSIX_reserved41 (__NR_POSIX + 209) ++#define __NR_POSIX_reserved42 (__NR_POSIX + 210) ++#define __NR_POSIX_reserved43 (__NR_POSIX + 211) ++#define __NR_POSIX_reserved44 (__NR_POSIX + 212) ++#define __NR_POSIX_reserved45 (__NR_POSIX + 213) ++#define __NR_POSIX_reserved46 (__NR_POSIX + 214) ++#define __NR_POSIX_reserved47 (__NR_POSIX + 215) ++#define __NR_POSIX_reserved48 (__NR_POSIX + 216) ++#define __NR_POSIX_reserved49 (__NR_POSIX + 217) ++#define __NR_POSIX_reserved50 (__NR_POSIX + 218) ++#define __NR_POSIX_reserved51 (__NR_POSIX + 219) ++#define __NR_POSIX_reserved52 (__NR_POSIX + 220) ++#define __NR_POSIX_reserved53 (__NR_POSIX + 221) ++#define __NR_POSIX_reserved54 (__NR_POSIX + 222) ++#define __NR_POSIX_reserved55 (__NR_POSIX + 223) ++#define __NR_POSIX_reserved56 (__NR_POSIX + 224) ++#define __NR_POSIX_reserved57 (__NR_POSIX + 225) ++#define __NR_POSIX_reserved58 (__NR_POSIX + 226) ++#define __NR_POSIX_reserved59 (__NR_POSIX + 227) ++#define __NR_POSIX_reserved60 (__NR_POSIX + 228) ++#define __NR_POSIX_reserved61 (__NR_POSIX + 229) ++#define __NR_POSIX_reserved62 (__NR_POSIX + 230) ++#define __NR_POSIX_reserved63 (__NR_POSIX + 231) ++#define __NR_POSIX_reserved64 (__NR_POSIX + 232) ++#define __NR_POSIX_reserved65 (__NR_POSIX + 233) ++#define __NR_POSIX_reserved66 (__NR_POSIX + 234) ++#define __NR_POSIX_reserved67 (__NR_POSIX + 235) ++#define __NR_POSIX_reserved68 (__NR_POSIX + 236) ++#define __NR_POSIX_reserved69 (__NR_POSIX + 237) ++#define __NR_POSIX_reserved70 (__NR_POSIX + 238) ++#define __NR_POSIX_reserved71 (__NR_POSIX + 239) ++#define __NR_POSIX_reserved72 (__NR_POSIX + 240) ++#define __NR_POSIX_reserved73 (__NR_POSIX + 241) ++#define __NR_POSIX_reserved74 (__NR_POSIX + 242) ++#define __NR_POSIX_reserved75 (__NR_POSIX + 243) ++#define __NR_POSIX_reserved76 (__NR_POSIX + 244) ++#define __NR_POSIX_reserved77 (__NR_POSIX + 245) ++#define __NR_POSIX_reserved78 (__NR_POSIX + 246) ++#define __NR_POSIX_reserved79 (__NR_POSIX + 247) ++#define __NR_POSIX_reserved80 (__NR_POSIX + 248) ++#define __NR_POSIX_reserved81 (__NR_POSIX + 249) ++#define __NR_POSIX_reserved82 (__NR_POSIX + 250) ++#define __NR_POSIX_reserved83 (__NR_POSIX + 251) ++#define __NR_POSIX_reserved84 (__NR_POSIX + 252) ++#define __NR_POSIX_reserved85 (__NR_POSIX + 253) ++#define __NR_POSIX_reserved86 (__NR_POSIX + 254) ++#define __NR_POSIX_reserved87 (__NR_POSIX + 255) ++#define __NR_POSIX_reserved88 (__NR_POSIX + 256) ++#define __NR_POSIX_reserved89 (__NR_POSIX + 257) ++#define __NR_POSIX_reserved90 (__NR_POSIX + 258) ++#define __NR_POSIX_reserved91 (__NR_POSIX + 259) ++#define __NR_POSIX_netboot (__NR_POSIX + 260) ++#define __NR_POSIX_netunboot (__NR_POSIX + 261) ++#define __NR_POSIX_rdump (__NR_POSIX + 262) ++#define __NR_POSIX_setsid (__NR_POSIX + 263) ++#define __NR_POSIX_getmaxsig (__NR_POSIX + 264) ++#define __NR_POSIX_sigpending (__NR_POSIX + 265) ++#define __NR_POSIX_sigprocmask (__NR_POSIX + 266) ++#define __NR_POSIX_sigsuspend (__NR_POSIX + 267) ++#define __NR_POSIX_sigaction (__NR_POSIX + 268) ++#define __NR_POSIX_MIPS_reserved1 (__NR_POSIX + 269) ++#define __NR_POSIX_MIPS_reserved2 (__NR_POSIX + 270) ++#define __NR_POSIX_MIPS_reserved3 (__NR_POSIX + 271) ++#define __NR_POSIX_MIPS_reserved4 (__NR_POSIX + 272) ++#define __NR_POSIX_MIPS_reserved5 (__NR_POSIX + 273) ++#define __NR_POSIX_MIPS_reserved6 (__NR_POSIX + 274) ++#define __NR_POSIX_MIPS_reserved7 (__NR_POSIX + 275) ++#define __NR_POSIX_MIPS_reserved8 (__NR_POSIX + 276) ++#define __NR_POSIX_MIPS_reserved9 (__NR_POSIX + 277) ++#define __NR_POSIX_MIPS_reserved10 (__NR_POSIX + 278) ++#define __NR_POSIX_MIPS_reserved11 (__NR_POSIX + 279) ++#define __NR_POSIX_TANDEM_reserved1 (__NR_POSIX + 280) ++#define __NR_POSIX_TANDEM_reserved2 (__NR_POSIX + 281) ++#define __NR_POSIX_TANDEM_reserved3 (__NR_POSIX + 282) ++#define __NR_POSIX_TANDEM_reserved4 (__NR_POSIX + 283) ++#define __NR_POSIX_TANDEM_reserved5 (__NR_POSIX + 284) ++#define __NR_POSIX_TANDEM_reserved6 (__NR_POSIX + 285) ++#define __NR_POSIX_TANDEM_reserved7 (__NR_POSIX + 286) ++#define __NR_POSIX_TANDEM_reserved8 (__NR_POSIX + 287) ++#define __NR_POSIX_TANDEM_reserved9 (__NR_POSIX + 288) ++#define __NR_POSIX_TANDEM_reserved10 (__NR_POSIX + 289) ++#define __NR_POSIX_TANDEM_reserved11 (__NR_POSIX + 290) ++#define __NR_POSIX_TANDEM_reserved12 (__NR_POSIX + 291) ++#define __NR_POSIX_TANDEM_reserved13 (__NR_POSIX + 292) ++#define __NR_POSIX_TANDEM_reserved14 (__NR_POSIX + 293) ++#define __NR_POSIX_TANDEM_reserved15 (__NR_POSIX + 294) ++#define __NR_POSIX_TANDEM_reserved16 (__NR_POSIX + 295) ++#define __NR_POSIX_TANDEM_reserved17 (__NR_POSIX + 296) ++#define __NR_POSIX_TANDEM_reserved18 (__NR_POSIX + 297) ++#define __NR_POSIX_TANDEM_reserved19 (__NR_POSIX + 298) ++#define __NR_POSIX_TANDEM_reserved20 (__NR_POSIX + 299) ++#define __NR_POSIX_SGI_reserved7 (__NR_POSIX + 300) ++#define __NR_POSIX_SGI_reserved8 (__NR_POSIX + 301) ++#define __NR_POSIX_SGI_reserved9 (__NR_POSIX + 302) ++#define __NR_POSIX_SGI_reserved10 (__NR_POSIX + 303) ++#define __NR_POSIX_SGI_reserved11 (__NR_POSIX + 304) ++#define __NR_POSIX_SGI_reserved12 (__NR_POSIX + 305) ++#define __NR_POSIX_SGI_reserved13 (__NR_POSIX + 306) ++#define __NR_POSIX_SGI_reserved14 (__NR_POSIX + 307) ++#define __NR_POSIX_SGI_reserved15 (__NR_POSIX + 308) ++#define __NR_POSIX_SGI_reserved16 (__NR_POSIX + 309) ++#define __NR_POSIX_SGI_reserved17 (__NR_POSIX + 310) ++#define __NR_POSIX_SGI_reserved18 (__NR_POSIX + 311) ++#define __NR_POSIX_SGI_reserved19 (__NR_POSIX + 312) ++#define __NR_POSIX_SGI_reserved20 (__NR_POSIX + 313) ++#define __NR_POSIX_SGI_reserved21 (__NR_POSIX + 314) ++#define __NR_POSIX_SGI_reserved22 (__NR_POSIX + 315) ++#define __NR_POSIX_SGI_reserved23 (__NR_POSIX + 316) ++#define __NR_POSIX_SGI_reserved24 (__NR_POSIX + 317) ++#define __NR_POSIX_SGI_reserved25 (__NR_POSIX + 318) ++#define __NR_POSIX_SGI_reserved26 (__NR_POSIX + 319) ++ ++#endif /* _ASM_RISCOS_SYSCALL_H */ +diff -ruN linux/include/asm-mips/semaphore-helper.h linux-mips/include/asm-mips/semaphore-helper.h +--- linux/include/asm-mips/semaphore-helper.h Sun Jul 9 22:18:15 2000 ++++ linux-mips/include/asm-mips/semaphore-helper.h Fri Nov 10 00:12:03 2000 +@@ -1,5 +1,4 @@ +-/* $Id: semaphore-helper.h,v 1.6 1999/10/20 21:10:58 ralf Exp $ +- * ++/* + * SMP- and interrupt-safe semaphores helper functions. + * + * (C) Copyright 1996 Linus Torvalds +@@ -75,6 +74,7 @@ + ret = 0; + } + restore_flags(flags); ++ + return ret; + } + +@@ -92,7 +92,7 @@ + "sc\t%0, %2\n\t" + "beqz\t%0, 1b\n\t" + "2:" +- : "=r"(ret), "=r"(tmp), "=m"(__atomic_fool_gcc(&sem->waking)) ++ : "=r" (ret), "=r" (tmp), "=m" (sem->waking) + : "0"(0)); + + return ret; +diff -ruN linux/include/asm-mips/semaphore.h linux-mips/include/asm-mips/semaphore.h +--- linux/include/asm-mips/semaphore.h Sat May 13 08:31:25 2000 ++++ linux-mips/include/asm-mips/semaphore.h Fri Nov 10 00:12:03 2000 +@@ -59,7 +59,7 @@ + #define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name,1) + #define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name,0) + +-extern inline void sema_init (struct semaphore *sem, int val) ++static inline void sema_init (struct semaphore *sem, int val) + { + atomic_set(&sem->count, val); + atomic_set(&sem->waking, 0); +@@ -84,7 +84,7 @@ + asmlinkage int __down_trylock(struct semaphore * sem); + asmlinkage void __up(struct semaphore * sem); + +-extern inline void down(struct semaphore * sem) ++static inline void down(struct semaphore * sem) + { + #if WAITQUEUE_DEBUG + CHECK_MAGIC(sem->__magic); +@@ -93,7 +93,7 @@ + __down(sem); + } + +-extern inline int down_interruptible(struct semaphore * sem) ++static inline int down_interruptible(struct semaphore * sem) + { + int ret = 0; + +@@ -107,7 +107,7 @@ + + #if !defined(CONFIG_CPU_HAS_LLSC) + +-extern inline int down_trylock(struct semaphore * sem) ++static inline int down_trylock(struct semaphore * sem) + { + int ret = 0; + if (atomic_dec_return(&sem->count) < 0) +@@ -139,7 +139,7 @@ + * } + * } + */ +-extern inline int down_trylock(struct semaphore * sem) ++static inline int down_trylock(struct semaphore * sem) + { + long ret, tmp, tmp2, sub; + +@@ -180,7 +180,7 @@ + * Note! This is subtle. We jump to wake people up only if + * the semaphore was negative (== somebody was waiting on it). + */ +-extern inline void up(struct semaphore * sem) ++static inline void up(struct semaphore * sem) + { + #if WAITQUEUE_DEBUG + CHECK_MAGIC(sem->__magic); +@@ -247,7 +247,7 @@ + #define DECLARE_RWSEM_WRITE_LOCKED(name) \ + __DECLARE_RWSEM_GENERIC(name, 0) + +-extern inline void init_rwsem(struct rw_semaphore *sem) ++static inline void init_rwsem(struct rw_semaphore *sem) + { + atomic_set(&sem->count, RW_LOCK_BIAS); + sem->granted = 0; +@@ -265,7 +265,7 @@ + extern void __down_write(struct rw_semaphore *sem, int count); + extern void __rwsem_wake(struct rw_semaphore *sem, unsigned long readers); + +-extern inline void down_read(struct rw_semaphore *sem) ++static inline void down_read(struct rw_semaphore *sem) + { + int count; + +@@ -288,7 +288,7 @@ + #endif + } + +-extern inline void down_write(struct rw_semaphore *sem) ++static inline void down_write(struct rw_semaphore *sem) + { + int count; + +@@ -317,7 +317,7 @@ + there was a writer waiting, and we've bumped the count to 0: we must + wake the writer up. */ + +-extern inline void up_read(struct rw_semaphore *sem) ++static inline void up_read(struct rw_semaphore *sem) + { + #if WAITQUEUE_DEBUG + CHECK_MAGIC(sem->__magic); +@@ -336,7 +336,7 @@ + /* + * Releasing the writer is easy -- just release it and wake up any sleepers. + */ +-extern inline void up_write(struct rw_semaphore *sem) ++static inline void up_write(struct rw_semaphore *sem) + { + int count; + +diff -ruN linux/include/asm-mips/serial.h linux-mips/include/asm-mips/serial.h +--- linux/include/asm-mips/serial.h Sat May 13 08:31:25 2000 ++++ linux-mips/include/asm-mips/serial.h Fri Nov 10 00:12:04 2000 +@@ -76,6 +76,18 @@ + #define JAZZ_SERIAL_PORT_DEFNS + #endif + ++#ifdef CONFIG_MIPS_EV96100 ++#include ++#include ++#define EV96100_SERIAL_PORT_DEFNS \ ++ { baud_base: EV96100_BASE_BAUD, port: EV96100_UART0_REGS_BASE, \ ++ irq: EV96100INT_UART_0, flags: STD_COM_FLAGS, type: 0x3, \ ++ iomem_base: EV96100_UART0_REGS_BASE }, ++#else ++#define EV96100_SERIAL_PORT_DEFNS ++#endif ++ ++ + #define STD_SERIAL_PORT_DEFNS \ + /* UART CLK PORT IRQ FLAGS */ \ + { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ +@@ -152,7 +164,8 @@ + #endif + + #define SERIAL_PORT_DFNS \ ++ EV96100_SERIAL_PORT_DEFNS \ + JAZZ_SERIAL_PORT_DEFNS \ + STD_SERIAL_PORT_DEFNS \ + EXTRA_SERIAL_PORT_DEFNS \ +- HUB6_SERIAL_PORT_DFNS ++ HUB6_SERIAL_PORT_DFNS +diff -ruN linux/include/asm-mips/sni.h linux-mips/include/asm-mips/sni.h +--- linux/include/asm-mips/sni.h Sat May 13 08:31:25 2000 ++++ linux-mips/include/asm-mips/sni.h Fri Nov 10 00:12:08 2000 +@@ -30,6 +30,14 @@ + #define PCIMT_ERRADDR 0xbfff0040 + #define PCIMT_SYNDROME 0xbfff0048 + #define PCIMT_ITPEND 0xbfff0050 ++#define IT_INT2 0x01 ++#define IT_INTD 0x02 ++#define IT_INTC 0x04 ++#define IT_INTB 0x08 ++#define IT_INTA 0x10 ++#define IT_EISA 0x20 ++#define IT_SCSI 0x40 ++#define IT_ETH 0x80 + #define PCIMT_IRQSEL 0xbfff0058 + #define PCIMT_TESTMEM 0xbfff0060 + #define PCIMT_ECCREG 0xbfff0068 +@@ -73,16 +81,18 @@ + * to the other interrupts generated by ASIC PCI. + */ + #define PCIMT_KEYBOARD_IRQ 1 +-#define PCIMT_IRQ_ETHERNET 16 +-#define PCIMT_IRQ_TEMPERATURE 17 +-#define PCIMT_IRQ_EISA_NMI 18 +-#define PCIMT_IRQ_POWER_OFF 19 +-#define PCIMT_IRQ_BUTTON 20 +-#define PCIMT_IRQ_INTA 21 +-#define PCIMT_IRQ_INTB 22 +-#define PCIMT_IRQ_INTC 23 +-#define PCIMT_IRQ_INTD 24 +-#define PCIMT_IRQ_SCSI 25 ++#define PCIMT_IRQ_INT2 16 /* What is that? */ ++#define PCIMT_IRQ_INTD 17 ++#define PCIMT_IRQ_INTC 18 ++#define PCIMT_IRQ_INTB 19 ++#define PCIMT_IRQ_INTA 20 ++#define PCIMT_IRQ_EISA 21 ++#define PCIMT_IRQ_SCSI 22 ++#define PCIMT_IRQ_ETHERNET 23 ++#define PCIMT_IRQ_TEMPERATURE 24 ++#define PCIMT_IRQ_EISA_NMI 25 ++#define PCIMT_IRQ_POWER_OFF 26 ++#define PCIMT_IRQ_BUTTON 27 + + /* + * Base address for the mapped 16mb EISA bus segment. +diff -ruN linux/include/asm-mips/spinlock.h linux-mips/include/asm-mips/spinlock.h +--- linux/include/asm-mips/spinlock.h Sat May 13 08:31:25 2000 ++++ linux-mips/include/asm-mips/spinlock.h Fri Nov 10 00:12:08 2000 +@@ -1,5 +1,4 @@ +-/* $Id: spinlock.h,v 1.8 2000/01/23 21:15:52 ralf Exp $ +- * ++/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. +@@ -29,9 +28,6 @@ + * We make no fairness assumptions. They have a cost. + */ + +-typedef struct { unsigned long a[100]; } __dummy_lock_t; +-#define __dummy_lock(lock) (*(__dummy_lock_t *)(lock)) +- + static inline void spin_lock(spinlock_t *lock) + { + unsigned int tmp; +@@ -45,8 +41,8 @@ + "beqz\t%1, 1b\n\t" + " sync\n\t" + ".set\treorder" +- : "=o" (__dummy_lock(lock)), "=&r" (tmp) +- : "o" (__dummy_lock(lock)) ++ : "=o" (lock->lock), "=&r" (tmp) ++ : "o" (lock->lock) + : "memory"); + } + +@@ -57,8 +53,8 @@ + "sync\n\t" + "sw\t$0, %0\n\t" + ".set\treorder" +- : "=o" (__dummy_lock(lock)) +- : "o" (__dummy_lock(lock)) ++ : "=o" (lock->lock) ++ : "o" (lock->lock) + : "memory"); + } + +@@ -92,8 +88,8 @@ + "beqz\t%1, 1b\n\t" + " sync\n\t" + ".set\treorder" +- : "=o" (__dummy_lock(rw)), "=&r" (tmp) +- : "o" (__dummy_lock(rw)) ++ : "=o" (rw->lock), "=&r" (tmp) ++ : "o" (rw->lock) + : "memory"); + } + +@@ -111,8 +107,8 @@ + "sc\t%1, %0\n\t" + "beqz\t%1, 1b\n\t" + ".set\treorder" +- : "=o" (__dummy_lock(rw)), "=&r" (tmp) +- : "o" (__dummy_lock(rw)) ++ : "=o" (rw->lock), "=&r" (tmp) ++ : "o" (rw->lock) + : "memory"); + } + +@@ -129,8 +125,8 @@ + "beqz\t%1, 1b\n\t" + " sync\n\t" + ".set\treorder" +- : "=o" (__dummy_lock(rw)), "=&r" (tmp) +- : "o" (__dummy_lock(rw)) ++ : "=o" (rw->lock), "=&r" (tmp) ++ : "o" (rw->lock) + : "memory"); + } + +@@ -141,8 +137,8 @@ + "sync\n\t" + "sw\t$0, %0\n\t" + ".set\treorder" +- : "=o" (__dummy_lock(rw)) +- : "o" (__dummy_lock(rw)) ++ : "=o" (rw->lock) ++ : "o" (rw->lock) + : "memory"); + } + +diff -ruN linux/include/asm-mips/stackframe.h linux-mips/include/asm-mips/stackframe.h +--- linux/include/asm-mips/stackframe.h Sat May 13 08:31:25 2000 ++++ linux-mips/include/asm-mips/stackframe.h Fri Nov 10 00:12:08 2000 +@@ -47,19 +47,28 @@ + #define __str2(x) #x + #define __str(x) __str2(x) + +-#define save_static(frame) \ +- __asm__ __volatile__( \ +- "sw\t$16,"__str(PT_R16)"(%0)\n\t" \ +- "sw\t$17,"__str(PT_R17)"(%0)\n\t" \ +- "sw\t$18,"__str(PT_R18)"(%0)\n\t" \ +- "sw\t$19,"__str(PT_R19)"(%0)\n\t" \ +- "sw\t$20,"__str(PT_R20)"(%0)\n\t" \ +- "sw\t$21,"__str(PT_R21)"(%0)\n\t" \ +- "sw\t$22,"__str(PT_R22)"(%0)\n\t" \ +- "sw\t$23,"__str(PT_R23)"(%0)\n\t" \ +- "sw\t$30,"__str(PT_R30)"(%0)\n\t" \ +- : /* No outputs */ \ +- : "r" (frame)) ++#define save_static_function(symbol) \ ++__asm__ ( \ ++ ".globl\t" #symbol "\n\t" \ ++ ".align\t2\n\t" \ ++ ".type\t" #symbol ", @function\n\t" \ ++ ".ent\t" #symbol ", 0\n" \ ++ #symbol":\n\t" \ ++ ".frame\t$29, 0, $31\n\t" \ ++ "sw\t$16,"__str(PT_R16)"($29)\t\t\t# save_static_function\n\t" \ ++ "sw\t$17,"__str(PT_R17)"($29)\n\t" \ ++ "sw\t$18,"__str(PT_R18)"($29)\n\t" \ ++ "sw\t$19,"__str(PT_R19)"($29)\n\t" \ ++ "sw\t$20,"__str(PT_R20)"($29)\n\t" \ ++ "sw\t$21,"__str(PT_R21)"($29)\n\t" \ ++ "sw\t$22,"__str(PT_R22)"($29)\n\t" \ ++ "sw\t$23,"__str(PT_R23)"($29)\n\t" \ ++ "sw\t$30,"__str(PT_R30)"($29)\n\t" \ ++ ".end\t" #symbol "\n\t" \ ++ ".size\t" #symbol",. - " #symbol) ++ ++/* Used in declaration of save_static functions. */ ++#define static_unused static __attribute__((unused)) + + #define SAVE_SOME \ + .set push; \ +diff -ruN linux/include/asm-mips/stat.h linux-mips/include/asm-mips/stat.h +--- linux/include/asm-mips/stat.h Sun Jul 9 22:18:15 2000 ++++ linux-mips/include/asm-mips/stat.h Mon Sep 11 23:53:16 2000 +@@ -17,8 +17,7 @@ + unsigned int st_ctime, st_res3; + unsigned int st_blksize; + int st_blocks; +- unsigned int st_flags; +- unsigned int st_gen; ++ unsigned int st_unused0[2]; + }; + + struct stat { +@@ -45,11 +44,7 @@ + long reserved2; + long st_blksize; + long st_blocks; +- char st_fstype[16]; /* Filesystem type name */ +- long st_pad4[8]; +- /* Linux specific fields */ +- unsigned int st_flags; +- unsigned int st_gen; ++ long st_pad4[14]; + }; + + /* +@@ -61,25 +56,36 @@ + struct stat64 { + unsigned long st_dev; + unsigned long st_pad0[3]; /* Reserved for st_dev expansion */ +- ino_t st_ino; ++ ++ unsigned long long st_ino; ++ + mode_t st_mode; + nlink_t st_nlink; ++ + uid_t st_uid; + gid_t st_gid; ++ + unsigned long st_rdev; + unsigned long st_pad1[3]; /* Reserved for st_rdev expansion */ ++ + long long st_size; ++ + /* + * Actually this should be timestruc_t st_atime, st_mtime and st_ctime + * but we don't have it under Linux. + */ + time_t st_atime; + unsigned long reserved0; /* Reserved for st_atime expansion */ ++ + time_t st_mtime; +- unsigned long reserved1; /* Reserved for st_atime expansion */ ++ unsigned long reserved1; /* Reserved for st_mtime expansion */ ++ + time_t st_ctime; +- unsigned long reserved2; /* Reserved for st_atime expansion */ ++ unsigned long reserved2; /* Reserved for st_ctime expansion */ ++ + unsigned long st_blksize; ++ unsigned long st_pad2; ++ + long long st_blocks; + }; + +diff -ruN linux/include/asm-mips/system.h linux-mips/include/asm-mips/system.h +--- linux/include/asm-mips/system.h Thu Aug 3 15:38:11 2000 ++++ linux-mips/include/asm-mips/system.h Fri Nov 10 00:12:09 2000 +@@ -1,5 +1,4 @@ +-/* $Id: system.h,v 1.20 1999/12/06 23:13:21 ralf Exp $ +- * ++/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. +@@ -61,56 +60,54 @@ + : "$1", "memory"); + } + +-#define __save_flags(x) \ +-__asm__ __volatile__( \ +- ".set\tpush\n\t" \ +- ".set\treorder\n\t" \ +- "mfc0\t%0,$12\n\t" \ +- ".set\tpop\n\t" \ +- : "=r" (x) \ +- : /* no inputs */ \ +- : "memory") +- +-#define __save_and_cli(x) \ +-__asm__ __volatile__( \ +- ".set\tpush\n\t" \ +- ".set\treorder\n\t" \ +- ".set\tnoat\n\t" \ +- "mfc0\t%0,$12\n\t" \ +- "ori\t$1,%0,1\n\t" \ +- "xori\t$1,1\n\t" \ +- ".set\tnoreorder\n\t" \ +- "mtc0\t$1,$12\n\t" \ +- "nop\n\t" \ +- "nop\n\t" \ +- "nop\n\t" \ +- ".set\tpop\n\t" \ +- : "=r" (x) \ +- : /* no inputs */ \ ++#define __save_flags(x) \ ++__asm__ __volatile__( \ ++ ".set\tpush\n\t" \ ++ ".set\treorder\n\t" \ ++ "mfc0\t%0,$12\n\t" \ ++ ".set\tpop\n\t" \ ++ : "=r" (x)) ++ ++#define __save_and_cli(x) \ ++__asm__ __volatile__( \ ++ ".set\tpush\n\t" \ ++ ".set\treorder\n\t" \ ++ ".set\tnoat\n\t" \ ++ "mfc0\t%0,$12\n\t" \ ++ "ori\t$1,%0,1\n\t" \ ++ "xori\t$1,1\n\t" \ ++ ".set\tnoreorder\n\t" \ ++ "mtc0\t$1,$12\n\t" \ ++ "nop\n\t" \ ++ "nop\n\t" \ ++ "nop\n\t" \ ++ ".set\tpop\n\t" \ ++ : "=r" (x) \ ++ : /* no inputs */ \ + : "$1", "memory") + +-extern void __inline__ +-__restore_flags(int flags) +-{ +- __asm__ __volatile__( +- ".set\tpush\n\t" +- ".set\treorder\n\t" +- "mfc0\t$8,$12\n\t" +- "li\t$9,0xff00\n\t" +- "and\t$8,$9\n\t" +- "nor\t$9,$0,$9\n\t" +- "and\t%0,$9\n\t" +- "or\t%0,$8\n\t" +- ".set\tnoreorder\n\t" +- "mtc0\t%0,$12\n\t" +- "nop\n\t" +- "nop\n\t" +- "nop\n\t" +- ".set\tpop\n\t" +- : +- : "r" (flags) +- : "$8", "$9", "memory"); +-} ++#define __restore_flags(flags) \ ++do { \ ++ unsigned long __tmp1; \ ++ \ ++ __asm__ __volatile__( \ ++ ".set\tnoreorder\t\t\t# __restore_flags\n\t" \ ++ ".set\tnoat\n\t" \ ++ "mfc0\t$1, $12\n\t" \ ++ "andi\t%0, 1\n\t" \ ++ "ori\t$1, 1\n\t" \ ++ "xori\t$1, 1\n\t" \ ++ "or\t%0, $1\n\t" \ ++ "mtc0\t%0, $12\n\t" \ ++ "nop\n\t" \ ++ "nop\n\t" \ ++ "nop\n\t" \ ++ ".set\tat\n\t" \ ++ ".set\treorder" \ ++ : "=r" (__tmp1) \ ++ : "0" (flags) \ ++ : "$1", "memory"); \ ++} while(0) + + /* + * Non-SMP versions ... +@@ -131,11 +128,14 @@ + * These are probably defined overly paranoid ... + */ + #ifdef CONFIG_CPU_HAS_WB ++ + #include + #define rmb() + #define wmb() wbflush() + #define mb() wbflush() +-#else ++ ++#else /* CONFIG_CPU_HAS_WB */ ++ + #define mb() \ + __asm__ __volatile__( \ + "# prevent instructions being moved around\n\t" \ +@@ -148,6 +148,17 @@ + : "memory") + #define rmb() mb() + #define wmb() mb() ++ ++#endif /* CONFIG_CPU_HAS_WB */ ++ ++#ifdef CONFIG_SMP ++#define smp_mb() mb() ++#define smp_rmb() rmb() ++#define smp_wmb() wmb() ++#else ++#define smp_mb() barrier() ++#define smp_rmb() barrier() ++#define smp_wmb() barrier() + #endif + + #define set_mb(var, value) \ +@@ -180,17 +191,17 @@ + unsigned long dummy; + + __asm__ __volatile__( +- ".set\tnoreorder\n\t" ++ ".set\tnoreorder\t\t\t# xchg_u32\n\t" + ".set\tnoat\n\t" +- "ll\t%0,(%1)\n" +- "1:\tmove\t$1,%2\n\t" +- "sc\t$1,(%1)\n\t" +- "beqzl\t$1,1b\n\t" +- "ll\t%0,(%1)\n\t" ++ "ll\t%0, %3\n" ++ "1:\tmove\t$1, %2\n\t" ++ "sc\t$1, %1\n\t" ++ "beqzl\t$1, 1b\n\t" ++ " ll\t%0, %3\n\t" + ".set\tat\n\t" + ".set\treorder" +- : "=r" (val), "=r" (m), "=r" (dummy) +- : "1" (m), "2" (val) ++ : "=r" (val), "=o" (*m), "=r" (dummy) ++ : "o" (*m), "2" (val) + : "memory"); + + return val; +@@ -207,54 +218,16 @@ + #endif /* Processor-dependent optimization */ + } + +-/* +- * Only used for 64 bit kernel. +- */ +-extern __inline__ unsigned long xchg_u64(volatile long * m, unsigned long val) +-{ +- unsigned long dummy; +- +- __asm__ __volatile__( +- ".set\tnoreorder\n\t" +- ".set\tnoat\n\t" +- "lld\t%0,(%1)\n" +- "1:\tmove\t$1,%2\n\t" +- "scd\t$1,(%1)\n\t" +- "beqzl\t$1,1b\n\t" +- "lld\t%0,(%1)\n\t" +- ".set\tat\n\t" +- ".set\treorder" +- : "=r" (val), "=r" (m), "=r" (dummy) +- : "1" (m), "2" (val) +- : "memory"); +- +- return val; +-} +- + #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) + #define tas(ptr) (xchg((ptr),1)) + +-/* +- * This function doesn't exist, so you'll get a linker error +- * if something tries to do an invalid xchg(). +- * +- * This only works if the compiler isn't horribly bad at optimizing. +- * gcc-2.5.8 reportedly can't handle this, but I define that one to +- * be dead anyway. +- */ +-extern void __xchg_called_with_bad_pointer(void); +- +-static __inline__ unsigned long __xchg(unsigned long x, volatile void * ptr, int size) ++static __inline__ unsigned long ++__xchg(unsigned long x, volatile void * ptr, int size) + { + switch (size) { + case 4: + return xchg_u32(ptr, x); +-#if defined(__mips64) +- case 8: +- return xchg_u64(ptr, x); +-#endif + } +- __xchg_called_with_bad_pointer(); + return x; + } + +diff -ruN linux/include/asm-mips/unaligned.h linux-mips/include/asm-mips/unaligned.h +--- linux/include/asm-mips/unaligned.h Sat May 13 08:31:25 2000 ++++ linux-mips/include/asm-mips/unaligned.h Fri Nov 10 00:12:11 2000 +@@ -1,10 +1,10 @@ +-/* $Id$ +- * ++/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * +- * Copyright (C) 1996, 1999 by Ralf Baechle ++ * Copyright (C) 1996, 1999, 2000 by Ralf Baechle ++ * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + */ + #ifndef _ASM_UNALIGNED_H + #define _ASM_UNALIGNED_H +@@ -13,133 +13,129 @@ + extern void __put_unaligned_bad_length(void); + + /* +- * Load quad unaligned. ++ * Load double unaligned. ++ * ++ * This could have been implemented in plain C like IA64 but egcs 1.0.3a ++ * inflates this to 23 instructions ... + */ +-extern __inline__ unsigned long ldq_u(const unsigned long long * __addr) ++extern inline unsigned long long __ldq_u(const unsigned long long * __addr) + { + unsigned long long __res; + +- __asm__("uld\t%0,(%1)" +- :"=&r" (__res) +- :"r" (__addr)); ++ __asm__("ulw\t%0, %1\n\t" ++ "ulw\t%D0, 4+%1" ++ : "=&r" (__res) ++ : "m" (*__addr)); + + return __res; + } + + /* +- * Load long unaligned. ++ * Load word unaligned. + */ +-extern __inline__ unsigned long ldl_u(const unsigned int * __addr) ++extern inline unsigned long __ldl_u(const unsigned int * __addr) + { + unsigned long __res; + +- __asm__("ulw\t%0,(%1)" +- :"=&r" (__res) +- :"r" (__addr)); ++ __asm__("ulw\t%0,%1" ++ : "=&r" (__res) ++ : "m" (*__addr)); + + return __res; + } + + /* +- * Load word unaligned. ++ * Load halfword unaligned. + */ +-extern __inline__ unsigned long ldw_u(const unsigned short * __addr) ++extern inline unsigned long __ldw_u(const unsigned short * __addr) + { + unsigned long __res; + +- __asm__("ulh\t%0,(%1)" +- :"=&r" (__res) +- :"r" (__addr)); ++ __asm__("ulh\t%0,%1" ++ : "=&r" (__res) ++ : "m" (*__addr)); + + return __res; + } + + /* +- * Store quad ununaligned. ++ * Store doubleword ununaligned. + */ +-extern __inline__ void stq_u(unsigned long __val, unsigned long long * __addr) ++extern inline void __stq_u(unsigned long __val, unsigned long long * __addr) + { +- __asm__ __volatile__( +- "usd\t%0,(%1)" +- : /* No results */ +- :"r" (__val), +- "r" (__addr)); ++ __asm__("usw\t%1, %0\n\t" ++ "usw\t%D1, 4+%0" ++ : "=m" (*__addr) ++ : "r" (__val)); + } + + /* + * Store long ununaligned. + */ +-extern __inline__ void stl_u(unsigned long __val, unsigned int * __addr) ++extern inline void __stl_u(unsigned long __val, unsigned int * __addr) + { +- __asm__ __volatile__( +- "usw\t%0,(%1)" +- : /* No results */ +- :"r" (__val), +- "r" (__addr)); ++ __asm__("usw\t%1, %0" ++ : "=m" (*__addr) ++ : "r" (__val)); + } + + /* + * Store word ununaligned. + */ +-extern __inline__ void stw_u(unsigned long __val, unsigned short * __addr) ++extern inline void __stw_u(unsigned long __val, unsigned short * __addr) + { +- __asm__ __volatile__( +- "ush\t%0,(%1)" +- : /* No results */ +- :"r" (__val), +- "r" (__addr)); +-} +- +-extern inline unsigned long __get_unaligned(const void *ptr, size_t size) +-{ +- unsigned long val; +- switch (size) { +- case 1: +- val = *(const unsigned char *)ptr; +- break; +- case 2: +- val = ldw_u((const unsigned short *)ptr); +- break; +- case 4: +- val = ldl_u((const unsigned int *)ptr); +- break; +- case 8: +- val = ldq_u((const unsigned long long *)ptr); +- break; +- default: +- __get_unaligned_bad_length(); +- break; +- } +- return val; +-} +- +-extern inline void __put_unaligned(unsigned long val, void *ptr, size_t size) +-{ +- switch (size) { +- case 1: +- *(unsigned char *)ptr = (val); +- break; +- case 2: +- stw_u(val, (unsigned short *)ptr); +- break; +- case 4: +- stl_u(val, (unsigned int *)ptr); +- break; +- case 8: +- stq_u(val, (unsigned long long *)ptr); +- break; +- default: +- __put_unaligned_bad_length(); +- break; +- } ++ __asm__("ush\t%1, %0" ++ : "=m" (*__addr) ++ : "r" (__val)); + } + + /* + * The main single-value unaligned transfer routines. + */ +-#define get_unaligned(ptr) \ +- ((__typeof__(*(ptr)))__get_unaligned((ptr), sizeof(*(ptr)))) +-#define put_unaligned(x,ptr) \ +- __put_unaligned((unsigned long)(x), (ptr), sizeof(*(ptr))) ++#define get_unaligned(ptr) \ ++({ \ ++ __typeof__(*(ptr)) __val; \ ++ \ ++ switch (sizeof(*(ptr))) { \ ++ case 1: \ ++ __val = *(const unsigned char *)ptr; \ ++ break; \ ++ case 2: \ ++ __val = __ldw_u((const unsigned short *)ptr); \ ++ break; \ ++ case 4: \ ++ __val = __ldl_u((const unsigned int *)ptr); \ ++ break; \ ++ case 8: \ ++ __val = __ldq_u((const unsigned long long *)ptr); \ ++ break; \ ++ default: \ ++ __get_unaligned_bad_length(); \ ++ break; \ ++ } \ ++ \ ++ __val; \ ++}) ++ ++#define put_unaligned(val,ptr) \ ++do { \ ++ switch (sizeof(*(ptr))) { \ ++ case 1: \ ++ *(unsigned char *)(ptr) = (val); \ ++ break; \ ++ case 2: \ ++ __stw_u(val, (unsigned short *)(ptr)); \ ++ break; \ ++ case 4: \ ++ __stl_u(val, (unsigned int *)(ptr)); \ ++ break; \ ++ case 8: \ ++ __stq_u(val, (unsigned long long *)(ptr)); \ ++ break; \ ++ default: \ ++ __put_unaligned_bad_length(); \ ++ break; \ ++ } \ ++} while(0) + + #endif /* _ASM_UNALIGNED_H */ +diff -ruN linux/include/asm-mips/unistd.h linux-mips/include/asm-mips/unistd.h +--- linux/include/asm-mips/unistd.h Fri Aug 11 14:29:03 2000 ++++ linux-mips/include/asm-mips/unistd.h Fri Nov 10 00:12:13 2000 +@@ -1,990 +1,16 @@ +-/* $Id: unistd.h,v 1.20 2000/02/18 00:24:48 ralf Exp $ +- * ++/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * +- * Copyright (C) 1995, 1996, 1997, 1998 by Ralf Baechle ++ * Copyright (C) 1995, 96, 97, 98, 99, 2000 by Ralf Baechle + * + * Changed system calls macros _syscall5 - _syscall7 to push args 5 to 7 onto + * the stack. Robin Farine for ACN S.A, Copyright (C) 1996 by ACN S.A + */ +-#ifndef __ASM_MIPS_UNISTD_H +-#define __ASM_MIPS_UNISTD_H +- +-/* +- * The syscalls 0 - 3999 are reserved for a down to the root syscall +- * compatibility with RISC/os and IRIX. We'll see how to deal with the +- * various "real" BSD variants like Ultrix, NetBSD ... +- */ +- +-/* +- * SVR4 syscalls are in the range from 1 to 999 +- */ +-#define __NR_SVR4 0 +-#define __NR_SVR4_syscall (__NR_SVR4 + 0) +-#define __NR_SVR4_exit (__NR_SVR4 + 1) +-#define __NR_SVR4_fork (__NR_SVR4 + 2) +-#define __NR_SVR4_read (__NR_SVR4 + 3) +-#define __NR_SVR4_write (__NR_SVR4 + 4) +-#define __NR_SVR4_open (__NR_SVR4 + 5) +-#define __NR_SVR4_close (__NR_SVR4 + 6) +-#define __NR_SVR4_wait (__NR_SVR4 + 7) +-#define __NR_SVR4_creat (__NR_SVR4 + 8) +-#define __NR_SVR4_link (__NR_SVR4 + 9) +-#define __NR_SVR4_unlink (__NR_SVR4 + 10) +-#define __NR_SVR4_exec (__NR_SVR4 + 11) +-#define __NR_SVR4_chdir (__NR_SVR4 + 12) +-#define __NR_SVR4_gtime (__NR_SVR4 + 13) +-#define __NR_SVR4_mknod (__NR_SVR4 + 14) +-#define __NR_SVR4_chmod (__NR_SVR4 + 15) +-#define __NR_SVR4_chown (__NR_SVR4 + 16) +-#define __NR_SVR4_sbreak (__NR_SVR4 + 17) +-#define __NR_SVR4_stat (__NR_SVR4 + 18) +-#define __NR_SVR4_lseek (__NR_SVR4 + 19) +-#define __NR_SVR4_getpid (__NR_SVR4 + 20) +-#define __NR_SVR4_mount (__NR_SVR4 + 21) +-#define __NR_SVR4_umount (__NR_SVR4 + 22) +-#define __NR_SVR4_setuid (__NR_SVR4 + 23) +-#define __NR_SVR4_getuid (__NR_SVR4 + 24) +-#define __NR_SVR4_stime (__NR_SVR4 + 25) +-#define __NR_SVR4_ptrace (__NR_SVR4 + 26) +-#define __NR_SVR4_alarm (__NR_SVR4 + 27) +-#define __NR_SVR4_fstat (__NR_SVR4 + 28) +-#define __NR_SVR4_pause (__NR_SVR4 + 29) +-#define __NR_SVR4_utime (__NR_SVR4 + 30) +-#define __NR_SVR4_stty (__NR_SVR4 + 31) +-#define __NR_SVR4_gtty (__NR_SVR4 + 32) +-#define __NR_SVR4_access (__NR_SVR4 + 33) +-#define __NR_SVR4_nice (__NR_SVR4 + 34) +-#define __NR_SVR4_statfs (__NR_SVR4 + 35) +-#define __NR_SVR4_sync (__NR_SVR4 + 36) +-#define __NR_SVR4_kill (__NR_SVR4 + 37) +-#define __NR_SVR4_fstatfs (__NR_SVR4 + 38) +-#define __NR_SVR4_setpgrp (__NR_SVR4 + 39) +-#define __NR_SVR4_cxenix (__NR_SVR4 + 40) +-#define __NR_SVR4_dup (__NR_SVR4 + 41) +-#define __NR_SVR4_pipe (__NR_SVR4 + 42) +-#define __NR_SVR4_times (__NR_SVR4 + 43) +-#define __NR_SVR4_profil (__NR_SVR4 + 44) +-#define __NR_SVR4_plock (__NR_SVR4 + 45) +-#define __NR_SVR4_setgid (__NR_SVR4 + 46) +-#define __NR_SVR4_getgid (__NR_SVR4 + 47) +-#define __NR_SVR4_sig (__NR_SVR4 + 48) +-#define __NR_SVR4_msgsys (__NR_SVR4 + 49) +-#define __NR_SVR4_sysmips (__NR_SVR4 + 50) +-#define __NR_SVR4_sysacct (__NR_SVR4 + 51) +-#define __NR_SVR4_shmsys (__NR_SVR4 + 52) +-#define __NR_SVR4_semsys (__NR_SVR4 + 53) +-#define __NR_SVR4_ioctl (__NR_SVR4 + 54) +-#define __NR_SVR4_uadmin (__NR_SVR4 + 55) +-#define __NR_SVR4_exch (__NR_SVR4 + 56) +-#define __NR_SVR4_utssys (__NR_SVR4 + 57) +-#define __NR_SVR4_fsync (__NR_SVR4 + 58) +-#define __NR_SVR4_exece (__NR_SVR4 + 59) +-#define __NR_SVR4_umask (__NR_SVR4 + 60) +-#define __NR_SVR4_chroot (__NR_SVR4 + 61) +-#define __NR_SVR4_fcntl (__NR_SVR4 + 62) +-#define __NR_SVR4_ulimit (__NR_SVR4 + 63) +-#define __NR_SVR4_reserved1 (__NR_SVR4 + 64) +-#define __NR_SVR4_reserved2 (__NR_SVR4 + 65) +-#define __NR_SVR4_reserved3 (__NR_SVR4 + 66) +-#define __NR_SVR4_reserved4 (__NR_SVR4 + 67) +-#define __NR_SVR4_reserved5 (__NR_SVR4 + 68) +-#define __NR_SVR4_reserved6 (__NR_SVR4 + 69) +-#define __NR_SVR4_advfs (__NR_SVR4 + 70) +-#define __NR_SVR4_unadvfs (__NR_SVR4 + 71) +-#define __NR_SVR4_unused1 (__NR_SVR4 + 72) +-#define __NR_SVR4_unused2 (__NR_SVR4 + 73) +-#define __NR_SVR4_rfstart (__NR_SVR4 + 74) +-#define __NR_SVR4_unused3 (__NR_SVR4 + 75) +-#define __NR_SVR4_rdebug (__NR_SVR4 + 76) +-#define __NR_SVR4_rfstop (__NR_SVR4 + 77) +-#define __NR_SVR4_rfsys (__NR_SVR4 + 78) +-#define __NR_SVR4_rmdir (__NR_SVR4 + 79) +-#define __NR_SVR4_mkdir (__NR_SVR4 + 80) +-#define __NR_SVR4_getdents (__NR_SVR4 + 81) +-#define __NR_SVR4_libattach (__NR_SVR4 + 82) +-#define __NR_SVR4_libdetach (__NR_SVR4 + 83) +-#define __NR_SVR4_sysfs (__NR_SVR4 + 84) +-#define __NR_SVR4_getmsg (__NR_SVR4 + 85) +-#define __NR_SVR4_putmsg (__NR_SVR4 + 86) +-#define __NR_SVR4_poll (__NR_SVR4 + 87) +-#define __NR_SVR4_lstat (__NR_SVR4 + 88) +-#define __NR_SVR4_symlink (__NR_SVR4 + 89) +-#define __NR_SVR4_readlink (__NR_SVR4 + 90) +-#define __NR_SVR4_setgroups (__NR_SVR4 + 91) +-#define __NR_SVR4_getgroups (__NR_SVR4 + 92) +-#define __NR_SVR4_fchmod (__NR_SVR4 + 93) +-#define __NR_SVR4_fchown (__NR_SVR4 + 94) +-#define __NR_SVR4_sigprocmask (__NR_SVR4 + 95) +-#define __NR_SVR4_sigsuspend (__NR_SVR4 + 96) +-#define __NR_SVR4_sigaltstack (__NR_SVR4 + 97) +-#define __NR_SVR4_sigaction (__NR_SVR4 + 98) +-#define __NR_SVR4_sigpending (__NR_SVR4 + 99) +-#define __NR_SVR4_setcontext (__NR_SVR4 + 100) +-#define __NR_SVR4_evsys (__NR_SVR4 + 101) +-#define __NR_SVR4_evtrapret (__NR_SVR4 + 102) +-#define __NR_SVR4_statvfs (__NR_SVR4 + 103) +-#define __NR_SVR4_fstatvfs (__NR_SVR4 + 104) +-#define __NR_SVR4_reserved7 (__NR_SVR4 + 105) +-#define __NR_SVR4_nfssys (__NR_SVR4 + 106) +-#define __NR_SVR4_waitid (__NR_SVR4 + 107) +-#define __NR_SVR4_sigsendset (__NR_SVR4 + 108) +-#define __NR_SVR4_hrtsys (__NR_SVR4 + 109) +-#define __NR_SVR4_acancel (__NR_SVR4 + 110) +-#define __NR_SVR4_async (__NR_SVR4 + 111) +-#define __NR_SVR4_priocntlset (__NR_SVR4 + 112) +-#define __NR_SVR4_pathconf (__NR_SVR4 + 113) +-#define __NR_SVR4_mincore (__NR_SVR4 + 114) +-#define __NR_SVR4_mmap (__NR_SVR4 + 115) +-#define __NR_SVR4_mprotect (__NR_SVR4 + 116) +-#define __NR_SVR4_munmap (__NR_SVR4 + 117) +-#define __NR_SVR4_fpathconf (__NR_SVR4 + 118) +-#define __NR_SVR4_vfork (__NR_SVR4 + 119) +-#define __NR_SVR4_fchdir (__NR_SVR4 + 120) +-#define __NR_SVR4_readv (__NR_SVR4 + 121) +-#define __NR_SVR4_writev (__NR_SVR4 + 122) +-#define __NR_SVR4_xstat (__NR_SVR4 + 123) +-#define __NR_SVR4_lxstat (__NR_SVR4 + 124) +-#define __NR_SVR4_fxstat (__NR_SVR4 + 125) +-#define __NR_SVR4_xmknod (__NR_SVR4 + 126) +-#define __NR_SVR4_clocal (__NR_SVR4 + 127) +-#define __NR_SVR4_setrlimit (__NR_SVR4 + 128) +-#define __NR_SVR4_getrlimit (__NR_SVR4 + 129) +-#define __NR_SVR4_lchown (__NR_SVR4 + 130) +-#define __NR_SVR4_memcntl (__NR_SVR4 + 131) +-#define __NR_SVR4_getpmsg (__NR_SVR4 + 132) +-#define __NR_SVR4_putpmsg (__NR_SVR4 + 133) +-#define __NR_SVR4_rename (__NR_SVR4 + 134) +-#define __NR_SVR4_nuname (__NR_SVR4 + 135) +-#define __NR_SVR4_setegid (__NR_SVR4 + 136) +-#define __NR_SVR4_sysconf (__NR_SVR4 + 137) +-#define __NR_SVR4_adjtime (__NR_SVR4 + 138) +-#define __NR_SVR4_sysinfo (__NR_SVR4 + 139) +-#define __NR_SVR4_reserved8 (__NR_SVR4 + 140) +-#define __NR_SVR4_seteuid (__NR_SVR4 + 141) +-#define __NR_SVR4_PYRAMID_statis (__NR_SVR4 + 142) +-#define __NR_SVR4_PYRAMID_tuning (__NR_SVR4 + 143) +-#define __NR_SVR4_PYRAMID_forcerr (__NR_SVR4 + 144) +-#define __NR_SVR4_PYRAMID_mpcntl (__NR_SVR4 + 145) +-#define __NR_SVR4_reserved9 (__NR_SVR4 + 146) +-#define __NR_SVR4_reserved10 (__NR_SVR4 + 147) +-#define __NR_SVR4_reserved11 (__NR_SVR4 + 148) +-#define __NR_SVR4_reserved12 (__NR_SVR4 + 149) +-#define __NR_SVR4_reserved13 (__NR_SVR4 + 150) +-#define __NR_SVR4_reserved14 (__NR_SVR4 + 151) +-#define __NR_SVR4_reserved15 (__NR_SVR4 + 152) +-#define __NR_SVR4_reserved16 (__NR_SVR4 + 153) +-#define __NR_SVR4_reserved17 (__NR_SVR4 + 154) +-#define __NR_SVR4_reserved18 (__NR_SVR4 + 155) +-#define __NR_SVR4_reserved19 (__NR_SVR4 + 156) +-#define __NR_SVR4_reserved20 (__NR_SVR4 + 157) +-#define __NR_SVR4_reserved21 (__NR_SVR4 + 158) +-#define __NR_SVR4_reserved22 (__NR_SVR4 + 159) +-#define __NR_SVR4_reserved23 (__NR_SVR4 + 160) +-#define __NR_SVR4_reserved24 (__NR_SVR4 + 161) +-#define __NR_SVR4_reserved25 (__NR_SVR4 + 162) +-#define __NR_SVR4_reserved26 (__NR_SVR4 + 163) +-#define __NR_SVR4_reserved27 (__NR_SVR4 + 164) +-#define __NR_SVR4_reserved28 (__NR_SVR4 + 165) +-#define __NR_SVR4_reserved29 (__NR_SVR4 + 166) +-#define __NR_SVR4_reserved30 (__NR_SVR4 + 167) +-#define __NR_SVR4_reserved31 (__NR_SVR4 + 168) +-#define __NR_SVR4_reserved32 (__NR_SVR4 + 169) +-#define __NR_SVR4_reserved33 (__NR_SVR4 + 170) +-#define __NR_SVR4_reserved34 (__NR_SVR4 + 171) +-#define __NR_SVR4_reserved35 (__NR_SVR4 + 172) +-#define __NR_SVR4_reserved36 (__NR_SVR4 + 173) +-#define __NR_SVR4_reserved37 (__NR_SVR4 + 174) +-#define __NR_SVR4_reserved38 (__NR_SVR4 + 175) +-#define __NR_SVR4_reserved39 (__NR_SVR4 + 176) +-#define __NR_SVR4_reserved40 (__NR_SVR4 + 177) +-#define __NR_SVR4_reserved41 (__NR_SVR4 + 178) +-#define __NR_SVR4_reserved42 (__NR_SVR4 + 179) +-#define __NR_SVR4_reserved43 (__NR_SVR4 + 180) +-#define __NR_SVR4_reserved44 (__NR_SVR4 + 181) +-#define __NR_SVR4_reserved45 (__NR_SVR4 + 182) +-#define __NR_SVR4_reserved46 (__NR_SVR4 + 183) +-#define __NR_SVR4_reserved47 (__NR_SVR4 + 184) +-#define __NR_SVR4_reserved48 (__NR_SVR4 + 185) +-#define __NR_SVR4_reserved49 (__NR_SVR4 + 186) +-#define __NR_SVR4_reserved50 (__NR_SVR4 + 187) +-#define __NR_SVR4_reserved51 (__NR_SVR4 + 188) +-#define __NR_SVR4_reserved52 (__NR_SVR4 + 189) +-#define __NR_SVR4_reserved53 (__NR_SVR4 + 190) +-#define __NR_SVR4_reserved54 (__NR_SVR4 + 191) +-#define __NR_SVR4_reserved55 (__NR_SVR4 + 192) +-#define __NR_SVR4_reserved56 (__NR_SVR4 + 193) +-#define __NR_SVR4_reserved57 (__NR_SVR4 + 194) +-#define __NR_SVR4_reserved58 (__NR_SVR4 + 195) +-#define __NR_SVR4_reserved59 (__NR_SVR4 + 196) +-#define __NR_SVR4_reserved60 (__NR_SVR4 + 197) +-#define __NR_SVR4_reserved61 (__NR_SVR4 + 198) +-#define __NR_SVR4_reserved62 (__NR_SVR4 + 199) +-#define __NR_SVR4_reserved63 (__NR_SVR4 + 200) +-#define __NR_SVR4_aread (__NR_SVR4 + 201) +-#define __NR_SVR4_awrite (__NR_SVR4 + 202) +-#define __NR_SVR4_listio (__NR_SVR4 + 203) +-#define __NR_SVR4_mips_acancel (__NR_SVR4 + 204) +-#define __NR_SVR4_astatus (__NR_SVR4 + 205) +-#define __NR_SVR4_await (__NR_SVR4 + 206) +-#define __NR_SVR4_areadv (__NR_SVR4 + 207) +-#define __NR_SVR4_awritev (__NR_SVR4 + 208) +-#define __NR_SVR4_MIPS_reserved1 (__NR_SVR4 + 209) +-#define __NR_SVR4_MIPS_reserved2 (__NR_SVR4 + 210) +-#define __NR_SVR4_MIPS_reserved3 (__NR_SVR4 + 211) +-#define __NR_SVR4_MIPS_reserved4 (__NR_SVR4 + 212) +-#define __NR_SVR4_MIPS_reserved5 (__NR_SVR4 + 213) +-#define __NR_SVR4_MIPS_reserved6 (__NR_SVR4 + 214) +-#define __NR_SVR4_MIPS_reserved7 (__NR_SVR4 + 215) +-#define __NR_SVR4_MIPS_reserved8 (__NR_SVR4 + 216) +-#define __NR_SVR4_MIPS_reserved9 (__NR_SVR4 + 217) +-#define __NR_SVR4_MIPS_reserved10 (__NR_SVR4 + 218) +-#define __NR_SVR4_MIPS_reserved11 (__NR_SVR4 + 219) +-#define __NR_SVR4_MIPS_reserved12 (__NR_SVR4 + 220) +-#define __NR_SVR4_CDC_reserved1 (__NR_SVR4 + 221) +-#define __NR_SVR4_CDC_reserved2 (__NR_SVR4 + 222) +-#define __NR_SVR4_CDC_reserved3 (__NR_SVR4 + 223) +-#define __NR_SVR4_CDC_reserved4 (__NR_SVR4 + 224) +-#define __NR_SVR4_CDC_reserved5 (__NR_SVR4 + 225) +-#define __NR_SVR4_CDC_reserved6 (__NR_SVR4 + 226) +-#define __NR_SVR4_CDC_reserved7 (__NR_SVR4 + 227) +-#define __NR_SVR4_CDC_reserved8 (__NR_SVR4 + 228) +-#define __NR_SVR4_CDC_reserved9 (__NR_SVR4 + 229) +-#define __NR_SVR4_CDC_reserved10 (__NR_SVR4 + 230) +-#define __NR_SVR4_CDC_reserved11 (__NR_SVR4 + 231) +-#define __NR_SVR4_CDC_reserved12 (__NR_SVR4 + 232) +-#define __NR_SVR4_CDC_reserved13 (__NR_SVR4 + 233) +-#define __NR_SVR4_CDC_reserved14 (__NR_SVR4 + 234) +-#define __NR_SVR4_CDC_reserved15 (__NR_SVR4 + 235) +-#define __NR_SVR4_CDC_reserved16 (__NR_SVR4 + 236) +-#define __NR_SVR4_CDC_reserved17 (__NR_SVR4 + 237) +-#define __NR_SVR4_CDC_reserved18 (__NR_SVR4 + 238) +-#define __NR_SVR4_CDC_reserved19 (__NR_SVR4 + 239) +-#define __NR_SVR4_CDC_reserved20 (__NR_SVR4 + 240) +- +-/* +- * SYS V syscalls are in the range from 1000 to 1999 +- */ +-#define __NR_SYSV 1000 +-#define __NR_SYSV_syscall (__NR_SYSV + 0) +-#define __NR_SYSV_exit (__NR_SYSV + 1) +-#define __NR_SYSV_fork (__NR_SYSV + 2) +-#define __NR_SYSV_read (__NR_SYSV + 3) +-#define __NR_SYSV_write (__NR_SYSV + 4) +-#define __NR_SYSV_open (__NR_SYSV + 5) +-#define __NR_SYSV_close (__NR_SYSV + 6) +-#define __NR_SYSV_wait (__NR_SYSV + 7) +-#define __NR_SYSV_creat (__NR_SYSV + 8) +-#define __NR_SYSV_link (__NR_SYSV + 9) +-#define __NR_SYSV_unlink (__NR_SYSV + 10) +-#define __NR_SYSV_execv (__NR_SYSV + 11) +-#define __NR_SYSV_chdir (__NR_SYSV + 12) +-#define __NR_SYSV_time (__NR_SYSV + 13) +-#define __NR_SYSV_mknod (__NR_SYSV + 14) +-#define __NR_SYSV_chmod (__NR_SYSV + 15) +-#define __NR_SYSV_chown (__NR_SYSV + 16) +-#define __NR_SYSV_brk (__NR_SYSV + 17) +-#define __NR_SYSV_stat (__NR_SYSV + 18) +-#define __NR_SYSV_lseek (__NR_SYSV + 19) +-#define __NR_SYSV_getpid (__NR_SYSV + 20) +-#define __NR_SYSV_mount (__NR_SYSV + 21) +-#define __NR_SYSV_umount (__NR_SYSV + 22) +-#define __NR_SYSV_setuid (__NR_SYSV + 23) +-#define __NR_SYSV_getuid (__NR_SYSV + 24) +-#define __NR_SYSV_stime (__NR_SYSV + 25) +-#define __NR_SYSV_ptrace (__NR_SYSV + 26) +-#define __NR_SYSV_alarm (__NR_SYSV + 27) +-#define __NR_SYSV_fstat (__NR_SYSV + 28) +-#define __NR_SYSV_pause (__NR_SYSV + 29) +-#define __NR_SYSV_utime (__NR_SYSV + 30) +-#define __NR_SYSV_stty (__NR_SYSV + 31) +-#define __NR_SYSV_gtty (__NR_SYSV + 32) +-#define __NR_SYSV_access (__NR_SYSV + 33) +-#define __NR_SYSV_nice (__NR_SYSV + 34) +-#define __NR_SYSV_statfs (__NR_SYSV + 35) +-#define __NR_SYSV_sync (__NR_SYSV + 36) +-#define __NR_SYSV_kill (__NR_SYSV + 37) +-#define __NR_SYSV_fstatfs (__NR_SYSV + 38) +-#define __NR_SYSV_setpgrp (__NR_SYSV + 39) +-#define __NR_SYSV_syssgi (__NR_SYSV + 40) +-#define __NR_SYSV_dup (__NR_SYSV + 41) +-#define __NR_SYSV_pipe (__NR_SYSV + 42) +-#define __NR_SYSV_times (__NR_SYSV + 43) +-#define __NR_SYSV_profil (__NR_SYSV + 44) +-#define __NR_SYSV_plock (__NR_SYSV + 45) +-#define __NR_SYSV_setgid (__NR_SYSV + 46) +-#define __NR_SYSV_getgid (__NR_SYSV + 47) +-#define __NR_SYSV_sig (__NR_SYSV + 48) +-#define __NR_SYSV_msgsys (__NR_SYSV + 49) +-#define __NR_SYSV_sysmips (__NR_SYSV + 50) +-#define __NR_SYSV_acct (__NR_SYSV + 51) +-#define __NR_SYSV_shmsys (__NR_SYSV + 52) +-#define __NR_SYSV_semsys (__NR_SYSV + 53) +-#define __NR_SYSV_ioctl (__NR_SYSV + 54) +-#define __NR_SYSV_uadmin (__NR_SYSV + 55) +-#define __NR_SYSV_sysmp (__NR_SYSV + 56) +-#define __NR_SYSV_utssys (__NR_SYSV + 57) +-#define __NR_SYSV_USG_reserved1 (__NR_SYSV + 58) +-#define __NR_SYSV_execve (__NR_SYSV + 59) +-#define __NR_SYSV_umask (__NR_SYSV + 60) +-#define __NR_SYSV_chroot (__NR_SYSV + 61) +-#define __NR_SYSV_fcntl (__NR_SYSV + 62) +-#define __NR_SYSV_ulimit (__NR_SYSV + 63) +-#define __NR_SYSV_SAFARI4_reserved1 (__NR_SYSV + 64) +-#define __NR_SYSV_SAFARI4_reserved2 (__NR_SYSV + 65) +-#define __NR_SYSV_SAFARI4_reserved3 (__NR_SYSV + 66) +-#define __NR_SYSV_SAFARI4_reserved4 (__NR_SYSV + 67) +-#define __NR_SYSV_SAFARI4_reserved5 (__NR_SYSV + 68) +-#define __NR_SYSV_SAFARI4_reserved6 (__NR_SYSV + 69) +-#define __NR_SYSV_advfs (__NR_SYSV + 70) +-#define __NR_SYSV_unadvfs (__NR_SYSV + 71) +-#define __NR_SYSV_rmount (__NR_SYSV + 72) +-#define __NR_SYSV_rumount (__NR_SYSV + 73) +-#define __NR_SYSV_rfstart (__NR_SYSV + 74) +-#define __NR_SYSV_getrlimit64 (__NR_SYSV + 75) +-#define __NR_SYSV_setrlimit64 (__NR_SYSV + 76) +-#define __NR_SYSV_nanosleep (__NR_SYSV + 77) +-#define __NR_SYSV_lseek64 (__NR_SYSV + 78) +-#define __NR_SYSV_rmdir (__NR_SYSV + 79) +-#define __NR_SYSV_mkdir (__NR_SYSV + 80) +-#define __NR_SYSV_getdents (__NR_SYSV + 81) +-#define __NR_SYSV_sginap (__NR_SYSV + 82) +-#define __NR_SYSV_sgikopt (__NR_SYSV + 83) +-#define __NR_SYSV_sysfs (__NR_SYSV + 84) +-#define __NR_SYSV_getmsg (__NR_SYSV + 85) +-#define __NR_SYSV_putmsg (__NR_SYSV + 86) +-#define __NR_SYSV_poll (__NR_SYSV + 87) +-#define __NR_SYSV_sigreturn (__NR_SYSV + 88) +-#define __NR_SYSV_accept (__NR_SYSV + 89) +-#define __NR_SYSV_bind (__NR_SYSV + 90) +-#define __NR_SYSV_connect (__NR_SYSV + 91) +-#define __NR_SYSV_gethostid (__NR_SYSV + 92) +-#define __NR_SYSV_getpeername (__NR_SYSV + 93) +-#define __NR_SYSV_getsockname (__NR_SYSV + 94) +-#define __NR_SYSV_getsockopt (__NR_SYSV + 95) +-#define __NR_SYSV_listen (__NR_SYSV + 96) +-#define __NR_SYSV_recv (__NR_SYSV + 97) +-#define __NR_SYSV_recvfrom (__NR_SYSV + 98) +-#define __NR_SYSV_recvmsg (__NR_SYSV + 99) +-#define __NR_SYSV_select (__NR_SYSV + 100) +-#define __NR_SYSV_send (__NR_SYSV + 101) +-#define __NR_SYSV_sendmsg (__NR_SYSV + 102) +-#define __NR_SYSV_sendto (__NR_SYSV + 103) +-#define __NR_SYSV_sethostid (__NR_SYSV + 104) +-#define __NR_SYSV_setsockopt (__NR_SYSV + 105) +-#define __NR_SYSV_shutdown (__NR_SYSV + 106) +-#define __NR_SYSV_socket (__NR_SYSV + 107) +-#define __NR_SYSV_gethostname (__NR_SYSV + 108) +-#define __NR_SYSV_sethostname (__NR_SYSV + 109) +-#define __NR_SYSV_getdomainname (__NR_SYSV + 110) +-#define __NR_SYSV_setdomainname (__NR_SYSV + 111) +-#define __NR_SYSV_truncate (__NR_SYSV + 112) +-#define __NR_SYSV_ftruncate (__NR_SYSV + 113) +-#define __NR_SYSV_rename (__NR_SYSV + 114) +-#define __NR_SYSV_symlink (__NR_SYSV + 115) +-#define __NR_SYSV_readlink (__NR_SYSV + 116) +-#define __NR_SYSV_lstat (__NR_SYSV + 117) +-#define __NR_SYSV_nfsmount (__NR_SYSV + 118) +-#define __NR_SYSV_nfssvc (__NR_SYSV + 119) +-#define __NR_SYSV_getfh (__NR_SYSV + 120) +-#define __NR_SYSV_async_daemon (__NR_SYSV + 121) +-#define __NR_SYSV_exportfs (__NR_SYSV + 122) +-#define __NR_SYSV_setregid (__NR_SYSV + 123) +-#define __NR_SYSV_setreuid (__NR_SYSV + 124) +-#define __NR_SYSV_getitimer (__NR_SYSV + 125) +-#define __NR_SYSV_setitimer (__NR_SYSV + 126) +-#define __NR_SYSV_adjtime (__NR_SYSV + 127) +-#define __NR_SYSV_BSD_getime (__NR_SYSV + 128) +-#define __NR_SYSV_sproc (__NR_SYSV + 129) +-#define __NR_SYSV_prctl (__NR_SYSV + 130) +-#define __NR_SYSV_procblk (__NR_SYSV + 131) +-#define __NR_SYSV_sprocsp (__NR_SYSV + 132) +-#define __NR_SYSV_sgigsc (__NR_SYSV + 133) +-#define __NR_SYSV_mmap (__NR_SYSV + 134) +-#define __NR_SYSV_munmap (__NR_SYSV + 135) +-#define __NR_SYSV_mprotect (__NR_SYSV + 136) +-#define __NR_SYSV_msync (__NR_SYSV + 137) +-#define __NR_SYSV_madvise (__NR_SYSV + 138) +-#define __NR_SYSV_pagelock (__NR_SYSV + 139) +-#define __NR_SYSV_getpagesize (__NR_SYSV + 140) +-#define __NR_SYSV_quotactl (__NR_SYSV + 141) +-#define __NR_SYSV_libdetach (__NR_SYSV + 142) +-#define __NR_SYSV_BSDgetpgrp (__NR_SYSV + 143) +-#define __NR_SYSV_BSDsetpgrp (__NR_SYSV + 144) +-#define __NR_SYSV_vhangup (__NR_SYSV + 145) +-#define __NR_SYSV_fsync (__NR_SYSV + 146) +-#define __NR_SYSV_fchdir (__NR_SYSV + 147) +-#define __NR_SYSV_getrlimit (__NR_SYSV + 148) +-#define __NR_SYSV_setrlimit (__NR_SYSV + 149) +-#define __NR_SYSV_cacheflush (__NR_SYSV + 150) +-#define __NR_SYSV_cachectl (__NR_SYSV + 151) +-#define __NR_SYSV_fchown (__NR_SYSV + 152) +-#define __NR_SYSV_fchmod (__NR_SYSV + 153) +-#define __NR_SYSV_wait3 (__NR_SYSV + 154) +-#define __NR_SYSV_socketpair (__NR_SYSV + 155) +-#define __NR_SYSV_sysinfo (__NR_SYSV + 156) +-#define __NR_SYSV_nuname (__NR_SYSV + 157) +-#define __NR_SYSV_xstat (__NR_SYSV + 158) +-#define __NR_SYSV_lxstat (__NR_SYSV + 159) +-#define __NR_SYSV_fxstat (__NR_SYSV + 160) +-#define __NR_SYSV_xmknod (__NR_SYSV + 161) +-#define __NR_SYSV_ksigaction (__NR_SYSV + 162) +-#define __NR_SYSV_sigpending (__NR_SYSV + 163) +-#define __NR_SYSV_sigprocmask (__NR_SYSV + 164) +-#define __NR_SYSV_sigsuspend (__NR_SYSV + 165) +-#define __NR_SYSV_sigpoll (__NR_SYSV + 166) +-#define __NR_SYSV_swapctl (__NR_SYSV + 167) +-#define __NR_SYSV_getcontext (__NR_SYSV + 168) +-#define __NR_SYSV_setcontext (__NR_SYSV + 169) +-#define __NR_SYSV_waitsys (__NR_SYSV + 170) +-#define __NR_SYSV_sigstack (__NR_SYSV + 171) +-#define __NR_SYSV_sigaltstack (__NR_SYSV + 172) +-#define __NR_SYSV_sigsendset (__NR_SYSV + 173) +-#define __NR_SYSV_statvfs (__NR_SYSV + 174) +-#define __NR_SYSV_fstatvfs (__NR_SYSV + 175) +-#define __NR_SYSV_getpmsg (__NR_SYSV + 176) +-#define __NR_SYSV_putpmsg (__NR_SYSV + 177) +-#define __NR_SYSV_lchown (__NR_SYSV + 178) +-#define __NR_SYSV_priocntl (__NR_SYSV + 179) +-#define __NR_SYSV_ksigqueue (__NR_SYSV + 180) +-#define __NR_SYSV_readv (__NR_SYSV + 181) +-#define __NR_SYSV_writev (__NR_SYSV + 182) +-#define __NR_SYSV_truncate64 (__NR_SYSV + 183) +-#define __NR_SYSV_ftruncate64 (__NR_SYSV + 184) +-#define __NR_SYSV_mmap64 (__NR_SYSV + 185) +-#define __NR_SYSV_dmi (__NR_SYSV + 186) +-#define __NR_SYSV_pread (__NR_SYSV + 187) +-#define __NR_SYSV_pwrite (__NR_SYSV + 188) ++#ifndef _ASM_UNISTD_H ++#define _ASM_UNISTD_H + +-/* +- * BSD 4.3 syscalls are in the range from 2000 to 2999 +- */ +-#define __NR_BSD43 2000 +-#define __NR_BSD43_syscall (__NR_BSD43 + 0) +-#define __NR_BSD43_exit (__NR_BSD43 + 1) +-#define __NR_BSD43_fork (__NR_BSD43 + 2) +-#define __NR_BSD43_read (__NR_BSD43 + 3) +-#define __NR_BSD43_write (__NR_BSD43 + 4) +-#define __NR_BSD43_open (__NR_BSD43 + 5) +-#define __NR_BSD43_close (__NR_BSD43 + 6) +-#define __NR_BSD43_wait (__NR_BSD43 + 7) +-#define __NR_BSD43_creat (__NR_BSD43 + 8) +-#define __NR_BSD43_link (__NR_BSD43 + 9) +-#define __NR_BSD43_unlink (__NR_BSD43 + 10) +-#define __NR_BSD43_exec (__NR_BSD43 + 11) +-#define __NR_BSD43_chdir (__NR_BSD43 + 12) +-#define __NR_BSD43_time (__NR_BSD43 + 13) +-#define __NR_BSD43_mknod (__NR_BSD43 + 14) +-#define __NR_BSD43_chmod (__NR_BSD43 + 15) +-#define __NR_BSD43_chown (__NR_BSD43 + 16) +-#define __NR_BSD43_sbreak (__NR_BSD43 + 17) +-#define __NR_BSD43_oldstat (__NR_BSD43 + 18) +-#define __NR_BSD43_lseek (__NR_BSD43 + 19) +-#define __NR_BSD43_getpid (__NR_BSD43 + 20) +-#define __NR_BSD43_oldmount (__NR_BSD43 + 21) +-#define __NR_BSD43_umount (__NR_BSD43 + 22) +-#define __NR_BSD43_setuid (__NR_BSD43 + 23) +-#define __NR_BSD43_getuid (__NR_BSD43 + 24) +-#define __NR_BSD43_stime (__NR_BSD43 + 25) +-#define __NR_BSD43_ptrace (__NR_BSD43 + 26) +-#define __NR_BSD43_alarm (__NR_BSD43 + 27) +-#define __NR_BSD43_oldfstat (__NR_BSD43 + 28) +-#define __NR_BSD43_pause (__NR_BSD43 + 29) +-#define __NR_BSD43_utime (__NR_BSD43 + 30) +-#define __NR_BSD43_stty (__NR_BSD43 + 31) +-#define __NR_BSD43_gtty (__NR_BSD43 + 32) +-#define __NR_BSD43_access (__NR_BSD43 + 33) +-#define __NR_BSD43_nice (__NR_BSD43 + 34) +-#define __NR_BSD43_ftime (__NR_BSD43 + 35) +-#define __NR_BSD43_sync (__NR_BSD43 + 36) +-#define __NR_BSD43_kill (__NR_BSD43 + 37) +-#define __NR_BSD43_stat (__NR_BSD43 + 38) +-#define __NR_BSD43_oldsetpgrp (__NR_BSD43 + 39) +-#define __NR_BSD43_lstat (__NR_BSD43 + 40) +-#define __NR_BSD43_dup (__NR_BSD43 + 41) +-#define __NR_BSD43_pipe (__NR_BSD43 + 42) +-#define __NR_BSD43_times (__NR_BSD43 + 43) +-#define __NR_BSD43_profil (__NR_BSD43 + 44) +-#define __NR_BSD43_msgsys (__NR_BSD43 + 45) +-#define __NR_BSD43_setgid (__NR_BSD43 + 46) +-#define __NR_BSD43_getgid (__NR_BSD43 + 47) +-#define __NR_BSD43_ssig (__NR_BSD43 + 48) +-#define __NR_BSD43_reserved1 (__NR_BSD43 + 49) +-#define __NR_BSD43_reserved2 (__NR_BSD43 + 50) +-#define __NR_BSD43_sysacct (__NR_BSD43 + 51) +-#define __NR_BSD43_phys (__NR_BSD43 + 52) +-#define __NR_BSD43_lock (__NR_BSD43 + 53) +-#define __NR_BSD43_ioctl (__NR_BSD43 + 54) +-#define __NR_BSD43_reboot (__NR_BSD43 + 55) +-#define __NR_BSD43_mpxchan (__NR_BSD43 + 56) +-#define __NR_BSD43_symlink (__NR_BSD43 + 57) +-#define __NR_BSD43_readlink (__NR_BSD43 + 58) +-#define __NR_BSD43_execve (__NR_BSD43 + 59) +-#define __NR_BSD43_umask (__NR_BSD43 + 60) +-#define __NR_BSD43_chroot (__NR_BSD43 + 61) +-#define __NR_BSD43_fstat (__NR_BSD43 + 62) +-#define __NR_BSD43_reserved3 (__NR_BSD43 + 63) +-#define __NR_BSD43_getpagesize (__NR_BSD43 + 64) +-#define __NR_BSD43_mremap (__NR_BSD43 + 65) +-#define __NR_BSD43_vfork (__NR_BSD43 + 66) +-#define __NR_BSD43_vread (__NR_BSD43 + 67) +-#define __NR_BSD43_vwrite (__NR_BSD43 + 68) +-#define __NR_BSD43_sbrk (__NR_BSD43 + 69) +-#define __NR_BSD43_sstk (__NR_BSD43 + 70) +-#define __NR_BSD43_mmap (__NR_BSD43 + 71) +-#define __NR_BSD43_vadvise (__NR_BSD43 + 72) +-#define __NR_BSD43_munmap (__NR_BSD43 + 73) +-#define __NR_BSD43_mprotect (__NR_BSD43 + 74) +-#define __NR_BSD43_madvise (__NR_BSD43 + 75) +-#define __NR_BSD43_vhangup (__NR_BSD43 + 76) +-#define __NR_BSD43_vlimit (__NR_BSD43 + 77) +-#define __NR_BSD43_mincore (__NR_BSD43 + 78) +-#define __NR_BSD43_getgroups (__NR_BSD43 + 79) +-#define __NR_BSD43_setgroups (__NR_BSD43 + 80) +-#define __NR_BSD43_getpgrp (__NR_BSD43 + 81) +-#define __NR_BSD43_setpgrp (__NR_BSD43 + 82) +-#define __NR_BSD43_setitimer (__NR_BSD43 + 83) +-#define __NR_BSD43_wait3 (__NR_BSD43 + 84) +-#define __NR_BSD43_swapon (__NR_BSD43 + 85) +-#define __NR_BSD43_getitimer (__NR_BSD43 + 86) +-#define __NR_BSD43_gethostname (__NR_BSD43 + 87) +-#define __NR_BSD43_sethostname (__NR_BSD43 + 88) +-#define __NR_BSD43_getdtablesize (__NR_BSD43 + 89) +-#define __NR_BSD43_dup2 (__NR_BSD43 + 90) +-#define __NR_BSD43_getdopt (__NR_BSD43 + 91) +-#define __NR_BSD43_fcntl (__NR_BSD43 + 92) +-#define __NR_BSD43_select (__NR_BSD43 + 93) +-#define __NR_BSD43_setdopt (__NR_BSD43 + 94) +-#define __NR_BSD43_fsync (__NR_BSD43 + 95) +-#define __NR_BSD43_setpriority (__NR_BSD43 + 96) +-#define __NR_BSD43_socket (__NR_BSD43 + 97) +-#define __NR_BSD43_connect (__NR_BSD43 + 98) +-#define __NR_BSD43_oldaccept (__NR_BSD43 + 99) +-#define __NR_BSD43_getpriority (__NR_BSD43 + 100) +-#define __NR_BSD43_send (__NR_BSD43 + 101) +-#define __NR_BSD43_recv (__NR_BSD43 + 102) +-#define __NR_BSD43_sigreturn (__NR_BSD43 + 103) +-#define __NR_BSD43_bind (__NR_BSD43 + 104) +-#define __NR_BSD43_setsockopt (__NR_BSD43 + 105) +-#define __NR_BSD43_listen (__NR_BSD43 + 106) +-#define __NR_BSD43_vtimes (__NR_BSD43 + 107) +-#define __NR_BSD43_sigvec (__NR_BSD43 + 108) +-#define __NR_BSD43_sigblock (__NR_BSD43 + 109) +-#define __NR_BSD43_sigsetmask (__NR_BSD43 + 110) +-#define __NR_BSD43_sigpause (__NR_BSD43 + 111) +-#define __NR_BSD43_sigstack (__NR_BSD43 + 112) +-#define __NR_BSD43_oldrecvmsg (__NR_BSD43 + 113) +-#define __NR_BSD43_oldsendmsg (__NR_BSD43 + 114) +-#define __NR_BSD43_vtrace (__NR_BSD43 + 115) +-#define __NR_BSD43_gettimeofday (__NR_BSD43 + 116) +-#define __NR_BSD43_getrusage (__NR_BSD43 + 117) +-#define __NR_BSD43_getsockopt (__NR_BSD43 + 118) +-#define __NR_BSD43_reserved4 (__NR_BSD43 + 119) +-#define __NR_BSD43_readv (__NR_BSD43 + 120) +-#define __NR_BSD43_writev (__NR_BSD43 + 121) +-#define __NR_BSD43_settimeofday (__NR_BSD43 + 122) +-#define __NR_BSD43_fchown (__NR_BSD43 + 123) +-#define __NR_BSD43_fchmod (__NR_BSD43 + 124) +-#define __NR_BSD43_oldrecvfrom (__NR_BSD43 + 125) +-#define __NR_BSD43_setreuid (__NR_BSD43 + 126) +-#define __NR_BSD43_setregid (__NR_BSD43 + 127) +-#define __NR_BSD43_rename (__NR_BSD43 + 128) +-#define __NR_BSD43_truncate (__NR_BSD43 + 129) +-#define __NR_BSD43_ftruncate (__NR_BSD43 + 130) +-#define __NR_BSD43_flock (__NR_BSD43 + 131) +-#define __NR_BSD43_semsys (__NR_BSD43 + 132) +-#define __NR_BSD43_sendto (__NR_BSD43 + 133) +-#define __NR_BSD43_shutdown (__NR_BSD43 + 134) +-#define __NR_BSD43_socketpair (__NR_BSD43 + 135) +-#define __NR_BSD43_mkdir (__NR_BSD43 + 136) +-#define __NR_BSD43_rmdir (__NR_BSD43 + 137) +-#define __NR_BSD43_utimes (__NR_BSD43 + 138) +-#define __NR_BSD43_sigcleanup (__NR_BSD43 + 139) +-#define __NR_BSD43_adjtime (__NR_BSD43 + 140) +-#define __NR_BSD43_oldgetpeername (__NR_BSD43 + 141) +-#define __NR_BSD43_gethostid (__NR_BSD43 + 142) +-#define __NR_BSD43_sethostid (__NR_BSD43 + 143) +-#define __NR_BSD43_getrlimit (__NR_BSD43 + 144) +-#define __NR_BSD43_setrlimit (__NR_BSD43 + 145) +-#define __NR_BSD43_killpg (__NR_BSD43 + 146) +-#define __NR_BSD43_shmsys (__NR_BSD43 + 147) +-#define __NR_BSD43_quota (__NR_BSD43 + 148) +-#define __NR_BSD43_qquota (__NR_BSD43 + 149) +-#define __NR_BSD43_oldgetsockname (__NR_BSD43 + 150) +-#define __NR_BSD43_sysmips (__NR_BSD43 + 151) +-#define __NR_BSD43_cacheflush (__NR_BSD43 + 152) +-#define __NR_BSD43_cachectl (__NR_BSD43 + 153) +-#define __NR_BSD43_debug (__NR_BSD43 + 154) +-#define __NR_BSD43_reserved5 (__NR_BSD43 + 155) +-#define __NR_BSD43_reserved6 (__NR_BSD43 + 156) +-#define __NR_BSD43_nfs_mount (__NR_BSD43 + 157) +-#define __NR_BSD43_nfs_svc (__NR_BSD43 + 158) +-#define __NR_BSD43_getdirentries (__NR_BSD43 + 159) +-#define __NR_BSD43_statfs (__NR_BSD43 + 160) +-#define __NR_BSD43_fstatfs (__NR_BSD43 + 161) +-#define __NR_BSD43_unmount (__NR_BSD43 + 162) +-#define __NR_BSD43_async_daemon (__NR_BSD43 + 163) +-#define __NR_BSD43_nfs_getfh (__NR_BSD43 + 164) +-#define __NR_BSD43_getdomainname (__NR_BSD43 + 165) +-#define __NR_BSD43_setdomainname (__NR_BSD43 + 166) +-#define __NR_BSD43_pcfs_mount (__NR_BSD43 + 167) +-#define __NR_BSD43_quotactl (__NR_BSD43 + 168) +-#define __NR_BSD43_oldexportfs (__NR_BSD43 + 169) +-#define __NR_BSD43_smount (__NR_BSD43 + 170) +-#define __NR_BSD43_mipshwconf (__NR_BSD43 + 171) +-#define __NR_BSD43_exportfs (__NR_BSD43 + 172) +-#define __NR_BSD43_nfsfh_open (__NR_BSD43 + 173) +-#define __NR_BSD43_libattach (__NR_BSD43 + 174) +-#define __NR_BSD43_libdetach (__NR_BSD43 + 175) +-#define __NR_BSD43_accept (__NR_BSD43 + 176) +-#define __NR_BSD43_reserved7 (__NR_BSD43 + 177) +-#define __NR_BSD43_reserved8 (__NR_BSD43 + 178) +-#define __NR_BSD43_recvmsg (__NR_BSD43 + 179) +-#define __NR_BSD43_recvfrom (__NR_BSD43 + 180) +-#define __NR_BSD43_sendmsg (__NR_BSD43 + 181) +-#define __NR_BSD43_getpeername (__NR_BSD43 + 182) +-#define __NR_BSD43_getsockname (__NR_BSD43 + 183) +-#define __NR_BSD43_aread (__NR_BSD43 + 184) +-#define __NR_BSD43_awrite (__NR_BSD43 + 185) +-#define __NR_BSD43_listio (__NR_BSD43 + 186) +-#define __NR_BSD43_acancel (__NR_BSD43 + 187) +-#define __NR_BSD43_astatus (__NR_BSD43 + 188) +-#define __NR_BSD43_await (__NR_BSD43 + 189) +-#define __NR_BSD43_areadv (__NR_BSD43 + 190) +-#define __NR_BSD43_awritev (__NR_BSD43 + 191) +- +-/* +- * POSIX syscalls are in the range from 3000 to 3999 +- */ +-#define __NR_POSIX 3000 +-#define __NR_POSIX_syscall (__NR_POSIX + 0) +-#define __NR_POSIX_exit (__NR_POSIX + 1) +-#define __NR_POSIX_fork (__NR_POSIX + 2) +-#define __NR_POSIX_read (__NR_POSIX + 3) +-#define __NR_POSIX_write (__NR_POSIX + 4) +-#define __NR_POSIX_open (__NR_POSIX + 5) +-#define __NR_POSIX_close (__NR_POSIX + 6) +-#define __NR_POSIX_wait (__NR_POSIX + 7) +-#define __NR_POSIX_creat (__NR_POSIX + 8) +-#define __NR_POSIX_link (__NR_POSIX + 9) +-#define __NR_POSIX_unlink (__NR_POSIX + 10) +-#define __NR_POSIX_exec (__NR_POSIX + 11) +-#define __NR_POSIX_chdir (__NR_POSIX + 12) +-#define __NR_POSIX_gtime (__NR_POSIX + 13) +-#define __NR_POSIX_mknod (__NR_POSIX + 14) +-#define __NR_POSIX_chmod (__NR_POSIX + 15) +-#define __NR_POSIX_chown (__NR_POSIX + 16) +-#define __NR_POSIX_sbreak (__NR_POSIX + 17) +-#define __NR_POSIX_stat (__NR_POSIX + 18) +-#define __NR_POSIX_lseek (__NR_POSIX + 19) +-#define __NR_POSIX_getpid (__NR_POSIX + 20) +-#define __NR_POSIX_mount (__NR_POSIX + 21) +-#define __NR_POSIX_umount (__NR_POSIX + 22) +-#define __NR_POSIX_setuid (__NR_POSIX + 23) +-#define __NR_POSIX_getuid (__NR_POSIX + 24) +-#define __NR_POSIX_stime (__NR_POSIX + 25) +-#define __NR_POSIX_ptrace (__NR_POSIX + 26) +-#define __NR_POSIX_alarm (__NR_POSIX + 27) +-#define __NR_POSIX_fstat (__NR_POSIX + 28) +-#define __NR_POSIX_pause (__NR_POSIX + 29) +-#define __NR_POSIX_utime (__NR_POSIX + 30) +-#define __NR_POSIX_stty (__NR_POSIX + 31) +-#define __NR_POSIX_gtty (__NR_POSIX + 32) +-#define __NR_POSIX_access (__NR_POSIX + 33) +-#define __NR_POSIX_nice (__NR_POSIX + 34) +-#define __NR_POSIX_statfs (__NR_POSIX + 35) +-#define __NR_POSIX_sync (__NR_POSIX + 36) +-#define __NR_POSIX_kill (__NR_POSIX + 37) +-#define __NR_POSIX_fstatfs (__NR_POSIX + 38) +-#define __NR_POSIX_getpgrp (__NR_POSIX + 39) +-#define __NR_POSIX_syssgi (__NR_POSIX + 40) +-#define __NR_POSIX_dup (__NR_POSIX + 41) +-#define __NR_POSIX_pipe (__NR_POSIX + 42) +-#define __NR_POSIX_times (__NR_POSIX + 43) +-#define __NR_POSIX_profil (__NR_POSIX + 44) +-#define __NR_POSIX_lock (__NR_POSIX + 45) +-#define __NR_POSIX_setgid (__NR_POSIX + 46) +-#define __NR_POSIX_getgid (__NR_POSIX + 47) +-#define __NR_POSIX_sig (__NR_POSIX + 48) +-#define __NR_POSIX_msgsys (__NR_POSIX + 49) +-#define __NR_POSIX_sysmips (__NR_POSIX + 50) +-#define __NR_POSIX_sysacct (__NR_POSIX + 51) +-#define __NR_POSIX_shmsys (__NR_POSIX + 52) +-#define __NR_POSIX_semsys (__NR_POSIX + 53) +-#define __NR_POSIX_ioctl (__NR_POSIX + 54) +-#define __NR_POSIX_uadmin (__NR_POSIX + 55) +-#define __NR_POSIX_exch (__NR_POSIX + 56) +-#define __NR_POSIX_utssys (__NR_POSIX + 57) +-#define __NR_POSIX_USG_reserved1 (__NR_POSIX + 58) +-#define __NR_POSIX_exece (__NR_POSIX + 59) +-#define __NR_POSIX_umask (__NR_POSIX + 60) +-#define __NR_POSIX_chroot (__NR_POSIX + 61) +-#define __NR_POSIX_fcntl (__NR_POSIX + 62) +-#define __NR_POSIX_ulimit (__NR_POSIX + 63) +-#define __NR_POSIX_SAFARI4_reserved1 (__NR_POSIX + 64) +-#define __NR_POSIX_SAFARI4_reserved2 (__NR_POSIX + 65) +-#define __NR_POSIX_SAFARI4_reserved3 (__NR_POSIX + 66) +-#define __NR_POSIX_SAFARI4_reserved4 (__NR_POSIX + 67) +-#define __NR_POSIX_SAFARI4_reserved5 (__NR_POSIX + 68) +-#define __NR_POSIX_SAFARI4_reserved6 (__NR_POSIX + 69) +-#define __NR_POSIX_advfs (__NR_POSIX + 70) +-#define __NR_POSIX_unadvfs (__NR_POSIX + 71) +-#define __NR_POSIX_rmount (__NR_POSIX + 72) +-#define __NR_POSIX_rumount (__NR_POSIX + 73) +-#define __NR_POSIX_rfstart (__NR_POSIX + 74) +-#define __NR_POSIX_reserved1 (__NR_POSIX + 75) +-#define __NR_POSIX_rdebug (__NR_POSIX + 76) +-#define __NR_POSIX_rfstop (__NR_POSIX + 77) +-#define __NR_POSIX_rfsys (__NR_POSIX + 78) +-#define __NR_POSIX_rmdir (__NR_POSIX + 79) +-#define __NR_POSIX_mkdir (__NR_POSIX + 80) +-#define __NR_POSIX_getdents (__NR_POSIX + 81) +-#define __NR_POSIX_sginap (__NR_POSIX + 82) +-#define __NR_POSIX_sgikopt (__NR_POSIX + 83) +-#define __NR_POSIX_sysfs (__NR_POSIX + 84) +-#define __NR_POSIX_getmsg (__NR_POSIX + 85) +-#define __NR_POSIX_putmsg (__NR_POSIX + 86) +-#define __NR_POSIX_poll (__NR_POSIX + 87) +-#define __NR_POSIX_sigreturn (__NR_POSIX + 88) +-#define __NR_POSIX_accept (__NR_POSIX + 89) +-#define __NR_POSIX_bind (__NR_POSIX + 90) +-#define __NR_POSIX_connect (__NR_POSIX + 91) +-#define __NR_POSIX_gethostid (__NR_POSIX + 92) +-#define __NR_POSIX_getpeername (__NR_POSIX + 93) +-#define __NR_POSIX_getsockname (__NR_POSIX + 94) +-#define __NR_POSIX_getsockopt (__NR_POSIX + 95) +-#define __NR_POSIX_listen (__NR_POSIX + 96) +-#define __NR_POSIX_recv (__NR_POSIX + 97) +-#define __NR_POSIX_recvfrom (__NR_POSIX + 98) +-#define __NR_POSIX_recvmsg (__NR_POSIX + 99) +-#define __NR_POSIX_select (__NR_POSIX + 100) +-#define __NR_POSIX_send (__NR_POSIX + 101) +-#define __NR_POSIX_sendmsg (__NR_POSIX + 102) +-#define __NR_POSIX_sendto (__NR_POSIX + 103) +-#define __NR_POSIX_sethostid (__NR_POSIX + 104) +-#define __NR_POSIX_setsockopt (__NR_POSIX + 105) +-#define __NR_POSIX_shutdown (__NR_POSIX + 106) +-#define __NR_POSIX_socket (__NR_POSIX + 107) +-#define __NR_POSIX_gethostname (__NR_POSIX + 108) +-#define __NR_POSIX_sethostname (__NR_POSIX + 109) +-#define __NR_POSIX_getdomainname (__NR_POSIX + 110) +-#define __NR_POSIX_setdomainname (__NR_POSIX + 111) +-#define __NR_POSIX_truncate (__NR_POSIX + 112) +-#define __NR_POSIX_ftruncate (__NR_POSIX + 113) +-#define __NR_POSIX_rename (__NR_POSIX + 114) +-#define __NR_POSIX_symlink (__NR_POSIX + 115) +-#define __NR_POSIX_readlink (__NR_POSIX + 116) +-#define __NR_POSIX_lstat (__NR_POSIX + 117) +-#define __NR_POSIX_nfs_mount (__NR_POSIX + 118) +-#define __NR_POSIX_nfs_svc (__NR_POSIX + 119) +-#define __NR_POSIX_nfs_getfh (__NR_POSIX + 120) +-#define __NR_POSIX_async_daemon (__NR_POSIX + 121) +-#define __NR_POSIX_exportfs (__NR_POSIX + 122) +-#define __NR_POSIX_SGI_setregid (__NR_POSIX + 123) +-#define __NR_POSIX_SGI_setreuid (__NR_POSIX + 124) +-#define __NR_POSIX_getitimer (__NR_POSIX + 125) +-#define __NR_POSIX_setitimer (__NR_POSIX + 126) +-#define __NR_POSIX_adjtime (__NR_POSIX + 127) +-#define __NR_POSIX_SGI_bsdgettime (__NR_POSIX + 128) +-#define __NR_POSIX_SGI_sproc (__NR_POSIX + 129) +-#define __NR_POSIX_SGI_prctl (__NR_POSIX + 130) +-#define __NR_POSIX_SGI_blkproc (__NR_POSIX + 131) +-#define __NR_POSIX_SGI_reserved1 (__NR_POSIX + 132) +-#define __NR_POSIX_SGI_sgigsc (__NR_POSIX + 133) +-#define __NR_POSIX_SGI_mmap (__NR_POSIX + 134) +-#define __NR_POSIX_SGI_munmap (__NR_POSIX + 135) +-#define __NR_POSIX_SGI_mprotect (__NR_POSIX + 136) +-#define __NR_POSIX_SGI_msync (__NR_POSIX + 137) +-#define __NR_POSIX_SGI_madvise (__NR_POSIX + 138) +-#define __NR_POSIX_SGI_mpin (__NR_POSIX + 139) +-#define __NR_POSIX_SGI_getpagesize (__NR_POSIX + 140) +-#define __NR_POSIX_SGI_libattach (__NR_POSIX + 141) +-#define __NR_POSIX_SGI_libdetach (__NR_POSIX + 142) +-#define __NR_POSIX_SGI_getpgrp (__NR_POSIX + 143) +-#define __NR_POSIX_SGI_setpgrp (__NR_POSIX + 144) +-#define __NR_POSIX_SGI_reserved2 (__NR_POSIX + 145) +-#define __NR_POSIX_SGI_reserved3 (__NR_POSIX + 146) +-#define __NR_POSIX_SGI_reserved4 (__NR_POSIX + 147) +-#define __NR_POSIX_SGI_reserved5 (__NR_POSIX + 148) +-#define __NR_POSIX_SGI_reserved6 (__NR_POSIX + 149) +-#define __NR_POSIX_cacheflush (__NR_POSIX + 150) +-#define __NR_POSIX_cachectl (__NR_POSIX + 151) +-#define __NR_POSIX_fchown (__NR_POSIX + 152) +-#define __NR_POSIX_fchmod (__NR_POSIX + 153) +-#define __NR_POSIX_wait3 (__NR_POSIX + 154) +-#define __NR_POSIX_mmap (__NR_POSIX + 155) +-#define __NR_POSIX_munmap (__NR_POSIX + 156) +-#define __NR_POSIX_madvise (__NR_POSIX + 157) +-#define __NR_POSIX_BSD_getpagesize (__NR_POSIX + 158) +-#define __NR_POSIX_setreuid (__NR_POSIX + 159) +-#define __NR_POSIX_setregid (__NR_POSIX + 160) +-#define __NR_POSIX_setpgid (__NR_POSIX + 161) +-#define __NR_POSIX_getgroups (__NR_POSIX + 162) +-#define __NR_POSIX_setgroups (__NR_POSIX + 163) +-#define __NR_POSIX_gettimeofday (__NR_POSIX + 164) +-#define __NR_POSIX_getrusage (__NR_POSIX + 165) +-#define __NR_POSIX_getrlimit (__NR_POSIX + 166) +-#define __NR_POSIX_setrlimit (__NR_POSIX + 167) +-#define __NR_POSIX_waitpid (__NR_POSIX + 168) +-#define __NR_POSIX_dup2 (__NR_POSIX + 169) +-#define __NR_POSIX_reserved2 (__NR_POSIX + 170) +-#define __NR_POSIX_reserved3 (__NR_POSIX + 171) +-#define __NR_POSIX_reserved4 (__NR_POSIX + 172) +-#define __NR_POSIX_reserved5 (__NR_POSIX + 173) +-#define __NR_POSIX_reserved6 (__NR_POSIX + 174) +-#define __NR_POSIX_reserved7 (__NR_POSIX + 175) +-#define __NR_POSIX_reserved8 (__NR_POSIX + 176) +-#define __NR_POSIX_reserved9 (__NR_POSIX + 177) +-#define __NR_POSIX_reserved10 (__NR_POSIX + 178) +-#define __NR_POSIX_reserved11 (__NR_POSIX + 179) +-#define __NR_POSIX_reserved12 (__NR_POSIX + 180) +-#define __NR_POSIX_reserved13 (__NR_POSIX + 181) +-#define __NR_POSIX_reserved14 (__NR_POSIX + 182) +-#define __NR_POSIX_reserved15 (__NR_POSIX + 183) +-#define __NR_POSIX_reserved16 (__NR_POSIX + 184) +-#define __NR_POSIX_reserved17 (__NR_POSIX + 185) +-#define __NR_POSIX_reserved18 (__NR_POSIX + 186) +-#define __NR_POSIX_reserved19 (__NR_POSIX + 187) +-#define __NR_POSIX_reserved20 (__NR_POSIX + 188) +-#define __NR_POSIX_reserved21 (__NR_POSIX + 189) +-#define __NR_POSIX_reserved22 (__NR_POSIX + 190) +-#define __NR_POSIX_reserved23 (__NR_POSIX + 191) +-#define __NR_POSIX_reserved24 (__NR_POSIX + 192) +-#define __NR_POSIX_reserved25 (__NR_POSIX + 193) +-#define __NR_POSIX_reserved26 (__NR_POSIX + 194) +-#define __NR_POSIX_reserved27 (__NR_POSIX + 195) +-#define __NR_POSIX_reserved28 (__NR_POSIX + 196) +-#define __NR_POSIX_reserved29 (__NR_POSIX + 197) +-#define __NR_POSIX_reserved30 (__NR_POSIX + 198) +-#define __NR_POSIX_reserved31 (__NR_POSIX + 199) +-#define __NR_POSIX_reserved32 (__NR_POSIX + 200) +-#define __NR_POSIX_reserved33 (__NR_POSIX + 201) +-#define __NR_POSIX_reserved34 (__NR_POSIX + 202) +-#define __NR_POSIX_reserved35 (__NR_POSIX + 203) +-#define __NR_POSIX_reserved36 (__NR_POSIX + 204) +-#define __NR_POSIX_reserved37 (__NR_POSIX + 205) +-#define __NR_POSIX_reserved38 (__NR_POSIX + 206) +-#define __NR_POSIX_reserved39 (__NR_POSIX + 207) +-#define __NR_POSIX_reserved40 (__NR_POSIX + 208) +-#define __NR_POSIX_reserved41 (__NR_POSIX + 209) +-#define __NR_POSIX_reserved42 (__NR_POSIX + 210) +-#define __NR_POSIX_reserved43 (__NR_POSIX + 211) +-#define __NR_POSIX_reserved44 (__NR_POSIX + 212) +-#define __NR_POSIX_reserved45 (__NR_POSIX + 213) +-#define __NR_POSIX_reserved46 (__NR_POSIX + 214) +-#define __NR_POSIX_reserved47 (__NR_POSIX + 215) +-#define __NR_POSIX_reserved48 (__NR_POSIX + 216) +-#define __NR_POSIX_reserved49 (__NR_POSIX + 217) +-#define __NR_POSIX_reserved50 (__NR_POSIX + 218) +-#define __NR_POSIX_reserved51 (__NR_POSIX + 219) +-#define __NR_POSIX_reserved52 (__NR_POSIX + 220) +-#define __NR_POSIX_reserved53 (__NR_POSIX + 221) +-#define __NR_POSIX_reserved54 (__NR_POSIX + 222) +-#define __NR_POSIX_reserved55 (__NR_POSIX + 223) +-#define __NR_POSIX_reserved56 (__NR_POSIX + 224) +-#define __NR_POSIX_reserved57 (__NR_POSIX + 225) +-#define __NR_POSIX_reserved58 (__NR_POSIX + 226) +-#define __NR_POSIX_reserved59 (__NR_POSIX + 227) +-#define __NR_POSIX_reserved60 (__NR_POSIX + 228) +-#define __NR_POSIX_reserved61 (__NR_POSIX + 229) +-#define __NR_POSIX_reserved62 (__NR_POSIX + 230) +-#define __NR_POSIX_reserved63 (__NR_POSIX + 231) +-#define __NR_POSIX_reserved64 (__NR_POSIX + 232) +-#define __NR_POSIX_reserved65 (__NR_POSIX + 233) +-#define __NR_POSIX_reserved66 (__NR_POSIX + 234) +-#define __NR_POSIX_reserved67 (__NR_POSIX + 235) +-#define __NR_POSIX_reserved68 (__NR_POSIX + 236) +-#define __NR_POSIX_reserved69 (__NR_POSIX + 237) +-#define __NR_POSIX_reserved70 (__NR_POSIX + 238) +-#define __NR_POSIX_reserved71 (__NR_POSIX + 239) +-#define __NR_POSIX_reserved72 (__NR_POSIX + 240) +-#define __NR_POSIX_reserved73 (__NR_POSIX + 241) +-#define __NR_POSIX_reserved74 (__NR_POSIX + 242) +-#define __NR_POSIX_reserved75 (__NR_POSIX + 243) +-#define __NR_POSIX_reserved76 (__NR_POSIX + 244) +-#define __NR_POSIX_reserved77 (__NR_POSIX + 245) +-#define __NR_POSIX_reserved78 (__NR_POSIX + 246) +-#define __NR_POSIX_reserved79 (__NR_POSIX + 247) +-#define __NR_POSIX_reserved80 (__NR_POSIX + 248) +-#define __NR_POSIX_reserved81 (__NR_POSIX + 249) +-#define __NR_POSIX_reserved82 (__NR_POSIX + 250) +-#define __NR_POSIX_reserved83 (__NR_POSIX + 251) +-#define __NR_POSIX_reserved84 (__NR_POSIX + 252) +-#define __NR_POSIX_reserved85 (__NR_POSIX + 253) +-#define __NR_POSIX_reserved86 (__NR_POSIX + 254) +-#define __NR_POSIX_reserved87 (__NR_POSIX + 255) +-#define __NR_POSIX_reserved88 (__NR_POSIX + 256) +-#define __NR_POSIX_reserved89 (__NR_POSIX + 257) +-#define __NR_POSIX_reserved90 (__NR_POSIX + 258) +-#define __NR_POSIX_reserved91 (__NR_POSIX + 259) +-#define __NR_POSIX_netboot (__NR_POSIX + 260) +-#define __NR_POSIX_netunboot (__NR_POSIX + 261) +-#define __NR_POSIX_rdump (__NR_POSIX + 262) +-#define __NR_POSIX_setsid (__NR_POSIX + 263) +-#define __NR_POSIX_getmaxsig (__NR_POSIX + 264) +-#define __NR_POSIX_sigpending (__NR_POSIX + 265) +-#define __NR_POSIX_sigprocmask (__NR_POSIX + 266) +-#define __NR_POSIX_sigsuspend (__NR_POSIX + 267) +-#define __NR_POSIX_sigaction (__NR_POSIX + 268) +-#define __NR_POSIX_MIPS_reserved1 (__NR_POSIX + 269) +-#define __NR_POSIX_MIPS_reserved2 (__NR_POSIX + 270) +-#define __NR_POSIX_MIPS_reserved3 (__NR_POSIX + 271) +-#define __NR_POSIX_MIPS_reserved4 (__NR_POSIX + 272) +-#define __NR_POSIX_MIPS_reserved5 (__NR_POSIX + 273) +-#define __NR_POSIX_MIPS_reserved6 (__NR_POSIX + 274) +-#define __NR_POSIX_MIPS_reserved7 (__NR_POSIX + 275) +-#define __NR_POSIX_MIPS_reserved8 (__NR_POSIX + 276) +-#define __NR_POSIX_MIPS_reserved9 (__NR_POSIX + 277) +-#define __NR_POSIX_MIPS_reserved10 (__NR_POSIX + 278) +-#define __NR_POSIX_MIPS_reserved11 (__NR_POSIX + 279) +-#define __NR_POSIX_TANDEM_reserved1 (__NR_POSIX + 280) +-#define __NR_POSIX_TANDEM_reserved2 (__NR_POSIX + 281) +-#define __NR_POSIX_TANDEM_reserved3 (__NR_POSIX + 282) +-#define __NR_POSIX_TANDEM_reserved4 (__NR_POSIX + 283) +-#define __NR_POSIX_TANDEM_reserved5 (__NR_POSIX + 284) +-#define __NR_POSIX_TANDEM_reserved6 (__NR_POSIX + 285) +-#define __NR_POSIX_TANDEM_reserved7 (__NR_POSIX + 286) +-#define __NR_POSIX_TANDEM_reserved8 (__NR_POSIX + 287) +-#define __NR_POSIX_TANDEM_reserved9 (__NR_POSIX + 288) +-#define __NR_POSIX_TANDEM_reserved10 (__NR_POSIX + 289) +-#define __NR_POSIX_TANDEM_reserved11 (__NR_POSIX + 290) +-#define __NR_POSIX_TANDEM_reserved12 (__NR_POSIX + 291) +-#define __NR_POSIX_TANDEM_reserved13 (__NR_POSIX + 292) +-#define __NR_POSIX_TANDEM_reserved14 (__NR_POSIX + 293) +-#define __NR_POSIX_TANDEM_reserved15 (__NR_POSIX + 294) +-#define __NR_POSIX_TANDEM_reserved16 (__NR_POSIX + 295) +-#define __NR_POSIX_TANDEM_reserved17 (__NR_POSIX + 296) +-#define __NR_POSIX_TANDEM_reserved18 (__NR_POSIX + 297) +-#define __NR_POSIX_TANDEM_reserved19 (__NR_POSIX + 298) +-#define __NR_POSIX_TANDEM_reserved20 (__NR_POSIX + 299) +-#define __NR_POSIX_SGI_reserved7 (__NR_POSIX + 300) +-#define __NR_POSIX_SGI_reserved8 (__NR_POSIX + 301) +-#define __NR_POSIX_SGI_reserved9 (__NR_POSIX + 302) +-#define __NR_POSIX_SGI_reserved10 (__NR_POSIX + 303) +-#define __NR_POSIX_SGI_reserved11 (__NR_POSIX + 304) +-#define __NR_POSIX_SGI_reserved12 (__NR_POSIX + 305) +-#define __NR_POSIX_SGI_reserved13 (__NR_POSIX + 306) +-#define __NR_POSIX_SGI_reserved14 (__NR_POSIX + 307) +-#define __NR_POSIX_SGI_reserved15 (__NR_POSIX + 308) +-#define __NR_POSIX_SGI_reserved16 (__NR_POSIX + 309) +-#define __NR_POSIX_SGI_reserved17 (__NR_POSIX + 310) +-#define __NR_POSIX_SGI_reserved18 (__NR_POSIX + 311) +-#define __NR_POSIX_SGI_reserved19 (__NR_POSIX + 312) +-#define __NR_POSIX_SGI_reserved20 (__NR_POSIX + 313) +-#define __NR_POSIX_SGI_reserved21 (__NR_POSIX + 314) +-#define __NR_POSIX_SGI_reserved22 (__NR_POSIX + 315) +-#define __NR_POSIX_SGI_reserved23 (__NR_POSIX + 316) +-#define __NR_POSIX_SGI_reserved24 (__NR_POSIX + 317) +-#define __NR_POSIX_SGI_reserved25 (__NR_POSIX + 318) +-#define __NR_POSIX_SGI_reserved26 (__NR_POSIX + 319) +- +-/* +- * Linux syscalls are in the range from 4000 to 4999 +- * Hopefully these syscall numbers are unused ... If not everyone using +- * statically linked binaries is pretty upsh*t. You've been warned. +- */ + #define __NR_Linux 4000 + #define __NR_syscall (__NR_Linux + 0) + #define __NR_exit (__NR_Linux + 1) +@@ -1045,7 +71,7 @@ + #define __NR_mpx (__NR_Linux + 56) + #define __NR_setpgid (__NR_Linux + 57) + #define __NR_ulimit (__NR_Linux + 58) +-#define __NR_oldolduname (__NR_Linux + 59) ++#define __NR_unused59 (__NR_Linux + 59) + #define __NR_umask (__NR_Linux + 60) + #define __NR_chroot (__NR_Linux + 61) + #define __NR_ustat (__NR_Linux + 62) +@@ -1095,7 +121,7 @@ + #define __NR_stat (__NR_Linux + 106) + #define __NR_lstat (__NR_Linux + 107) + #define __NR_fstat (__NR_Linux + 108) +-#define __NR_olduname (__NR_Linux + 109) ++#define __NR_unused109 (__NR_Linux + 109) + #define __NR_iopl (__NR_Linux + 110) + #define __NR_vhangup (__NR_Linux + 111) + #define __NR_idle (__NR_Linux + 112) +@@ -1206,11 +232,12 @@ + #define __NR_mincore (__NR_Linux + 217) + #define __NR_madvise (__NR_Linux + 218) + #define __NR_getdents64 (__NR_Linux + 219) ++#define __NR_fcntl64 (__NR_Linux + 220) + + /* + * Offset of the last Linux flavoured syscall + */ +-#define __NR_Linux_syscalls 219 ++#define __NR_Linux_syscalls 220 + + #ifndef _LANGUAGE_ASSEMBLY + +@@ -1218,13 +245,15 @@ + #define _syscall0(type,name) \ + type name(void) \ + { \ +-register long __res __asm__ ("$2"); \ +-register long __err __asm__ ("$7"); \ ++long __res, __err; \ + __asm__ volatile ("li\t$2,%2\n\t" \ +- "syscall" \ ++ "syscall\n\t" \ ++ "move\t%0, $2\n\t" \ ++ "move\t%1, $7" \ + : "=r" (__res), "=r" (__err) \ + : "i" (__NR_##name) \ +- : "$8","$9","$10","$11","$12","$13","$14","$15","$24"); \ ++ : "$2","$7","$8","$9","$10","$11","$12","$13","$14","$15", \ ++ "$24"); \ + if (__err == 0) \ + return (type) __res; \ + errno = __res; \ +@@ -1238,14 +267,15 @@ + #define _syscall1(type,name,atype,a) \ + type name(atype a) \ + { \ +-register long __res __asm__ ("$2"); \ +-register long __err __asm__ ("$7"); \ ++long __res, __err; \ + __asm__ volatile ("move\t$4,%3\n\t" \ + "li\t$2,%2\n\t" \ +- "syscall" \ +- : "=r" (__res), "=r" (__err) \ +- : "i" (__NR_##name),"r" ((long)(a)) \ +- : "$4","$8","$9","$10","$11","$12","$13","$14","$15","$24"); \ ++ "syscall\n\t" \ ++ "move\t%0, $2\n\t" \ ++ "move\t%1, $7" \ ++ : "=r" (__res), "=r" (__err) \ ++ : "i" (__NR_##name),"r" ((long)(a)) \ ++ : "$2","$4","$7","$8","$9","$10","$11","$12","$13","$14","$15","$24"); \ + if (__err == 0) \ + return (type) __res; \ + errno = __res; \ +@@ -1255,17 +285,18 @@ + #define _syscall2(type,name,atype,a,btype,b) \ + type name(atype a,btype b) \ + { \ +-register long __res __asm__ ("$2"); \ +-register long __err __asm__ ("$7"); \ ++long __res, __err; \ + __asm__ volatile ("move\t$4,%3\n\t" \ + "move\t$5,%4\n\t" \ + "li\t$2,%2\n\t" \ +- "syscall" \ ++ "syscall\n\t" \ ++ "move\t%0, $2\n\t" \ ++ "move\t%1, $7" \ + : "=r" (__res), "=r" (__err) \ + : "i" (__NR_##name),"r" ((long)(a)), \ + "r" ((long)(b)) \ +- : "$4","$5","$8","$9","$10","$11","$12","$13","$14","$15", \ +- "$24"); \ ++ : "$2","$4","$5","$7","$8","$9","$10","$11","$12","$13", \ ++ "$14","$15", "$24"); \ + if (__err == 0) \ + return (type) __res; \ + errno = __res; \ +@@ -1275,19 +306,20 @@ + #define _syscall3(type,name,atype,a,btype,b,ctype,c) \ + type name (atype a, btype b, ctype c) \ + { \ +-register long __res __asm__ ("$2"); \ +-register long __err __asm__ ("$7"); \ ++long __res, __err; \ + __asm__ volatile ("move\t$4,%3\n\t" \ + "move\t$5,%4\n\t" \ + "move\t$6,%5\n\t" \ + "li\t$2,%2\n\t" \ +- "syscall" \ ++ "syscall\n\t" \ ++ "move\t%0, $2\n\t" \ ++ "move\t%1, $7" \ + : "=r" (__res), "=r" (__err) \ + : "i" (__NR_##name),"r" ((long)(a)), \ + "r" ((long)(b)), \ + "r" ((long)(c)) \ +- : "$4","$5","$6","$8","$9","$10","$11","$12","$13","$14", \ +- "$15","$24"); \ ++ : "$2","$4","$5","$6","$7","$8","$9","$10","$11","$12", \ ++ "$13","$14","$15","$24"); \ + if (__err == 0) \ + return (type) __res; \ + errno = __res; \ +@@ -1297,21 +329,22 @@ + #define _syscall4(type,name,atype,a,btype,b,ctype,c,dtype,d) \ + type name (atype a, btype b, ctype c, dtype d) \ + { \ +-register long __res __asm__ ("$2"); \ +-register long __err __asm__ ("$7"); \ ++long __res, __err; \ + __asm__ volatile ("move\t$4,%3\n\t" \ + "move\t$5,%4\n\t" \ + "move\t$6,%5\n\t" \ + "move\t$7,%6\n\t" \ + "li\t$2,%2\n\t" \ +- "syscall" \ ++ "syscall\n\t" \ ++ "move\t%0, $2\n\t" \ ++ "move\t%1, $7" \ + : "=r" (__res), "=r" (__err) \ + : "i" (__NR_##name),"r" ((long)(a)), \ + "r" ((long)(b)), \ + "r" ((long)(c)), \ + "r" ((long)(d)) \ +- : "$4","$5","$6","$8","$9","$10","$11","$12","$13","$14", \ +- "$15","$24"); \ ++ : "$2","$4","$5","$6","$7","$8","$9","$10","$11","$12", \ ++ "$13","$14","$15","$24"); \ + if (__err == 0) \ + return (type) __res; \ + errno = __res; \ +@@ -1321,8 +354,7 @@ + #define _syscall5(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e) \ + type name (atype a,btype b,ctype c,dtype d,etype e) \ + { \ +-register long __res __asm__ ("$2"); \ +-register long __err __asm__ ("$7"); \ ++long __res, __err; \ + __asm__ volatile ("move\t$4,%3\n\t" \ + "move\t$5,%4\n\t" \ + "move\t$6,%5\n\t" \ +@@ -1331,7 +363,9 @@ + "subu\t$29,24\n\t" \ + "sw\t$2,16($29)\n\t" \ + "li\t$2,%2\n\t" \ +- "syscall\n\t" \ ++ "syscall\n\t" \ ++ "move\t%0, $2\n\t" \ ++ "move\t%1, $7\n\t" \ + "addiu\t$29,24" \ + : "=r" (__res), "=r" (__err) \ + : "i" (__NR_##name),"r" ((long)(a)), \ +@@ -1350,8 +384,7 @@ + #define _syscall6(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e,ftype,f) \ + type name (atype a,btype b,ctype c,dtype d,etype e,ftype f) \ + { \ +-register long __res __asm__ ("$2"); \ +-register long __err __asm__ ("$7"); \ ++long __res, __err; \ + __asm__ volatile ("move\t$4,%3\n\t" \ + "move\t$5,%4\n\t" \ + "move\t$6,%5\n\t" \ +@@ -1362,7 +395,9 @@ + "sw\t$2,16($29)\n\t" \ + "sw\t$3,20($29)\n\t" \ + "li\t$2,%2\n\t" \ +- "syscall\n\t" \ ++ "syscall\n\t" \ ++ "move\t%0, $2\n\t" \ ++ "move\t%1, $7\n\t" \ + "addiu\t$29,24" \ + : "=r" (__res), "=r" (__err) \ + : "i" (__NR_##name),"r" ((long)(a)), \ +@@ -1382,8 +417,7 @@ + #define _syscall7(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e,ftype,f,gtype,g) \ + type name (atype a,btype b,ctype c,dtype d,etype e,ftype f,gtype g) \ + { \ +-register long __res __asm__ ("$2"); \ +-register long __err __asm__ ("$7"); \ ++long __res, __err; \ + __asm__ volatile ("move\t$4,%3\n\t" \ + "move\t$5,%4\n\t" \ + "move\t$6,%5\n\t" \ +@@ -1396,7 +430,9 @@ + "sw\t$3,20($29)\n\t" \ + "sw\t$2,24($29)\n\t" \ + "li\t$2,%2\n\t" \ +- "syscall\n\t" \ ++ "syscall\n\t" \ ++ "move\t%0, $2\n\t" \ ++ "move\t%1, $7\n\t" \ + "addiu\t$29,32" \ + : "=r" (__res), "=r" (__err) \ + : "i" (__NR_##name),"r" ((long)(a)), \ +@@ -1450,4 +486,4 @@ + #endif /* !defined (__KERNEL_SYSCALLS__) */ + #endif /* !defined (_LANGUAGE_ASSEMBLY) */ + +-#endif /* __ASM_MIPS_UNISTD_H */ ++#endif /* _ASM_UNISTD_H */ +diff -ruN linux/include/asm-mips/xxx linux-mips/include/asm-mips/xxx +--- linux/include/asm-mips/xxx Wed Dec 31 16:00:00 1969 ++++ linux-mips/include/asm-mips/xxx Fri Nov 10 00:12:13 2000 +@@ -0,0 +1,187 @@ ++*************** ++*** 174,180 **** ++ extern __inline__ void set_bit(int nr, volatile void * addr) ++ { ++ int mask; ++- int *a = addr; ++ __bi_flags; ++ ++ a += nr >> 5; ++--- 202,208 ---- ++ extern __inline__ void set_bit(int nr, volatile void * addr) ++ { ++ int mask; +++ volatile int *a = addr; ++ __bi_flags; ++ ++ a += nr >> 5; ++*************** ++*** 184,219 **** ++ __bi_restore_flags(flags); ++ } ++ ++- extern __inline__ void clear_bit(int nr, volatile void * addr) ++ { ++ int mask; ++- int *a = addr; ++- __bi_flags; ++ ++ a += nr >> 5; ++ mask = 1 << (nr & 0x1f); ++- __bi_save_and_cli(flags); ++- *a &= ~mask; ++- __bi_restore_flags(flags); ++ } ++ ++- extern __inline__ void change_bit(int nr, volatile void * addr) ++ { ++ int mask; ++- int *a = addr; ++ __bi_flags; ++ ++ a += nr >> 5; ++ mask = 1 << (nr & 0x1f); ++ __bi_save_and_cli(flags); ++- *a ^= mask; ++ __bi_restore_flags(flags); ++ } ++ ++ extern __inline__ int test_and_set_bit(int nr, volatile void * addr) ++ { ++ int mask, retval; ++- int *a = addr; ++ __bi_flags; ++ ++ a += nr >> 5; ++--- 212,249 ---- ++ __bi_restore_flags(flags); ++ } ++ +++ extern __inline__ void __set_bit(int nr, volatile void * addr) ++ { ++ int mask; +++ volatile int *a = addr; ++ ++ a += nr >> 5; ++ mask = 1 << (nr & 0x1f); +++ *a |= mask; ++ } ++ +++ extern __inline__ void clear_bit(int nr, volatile void * addr) ++ { ++ int mask; +++ volatile int *a = addr; ++ __bi_flags; ++ ++ a += nr >> 5; ++ mask = 1 << (nr & 0x1f); ++ __bi_save_and_cli(flags); +++ *a &= ~mask; ++ __bi_restore_flags(flags); ++ } ++ +++ /* +++ * It will also imply a memory barrier, thus it must clobber memory +++ * to make sure to reload anything that was cached into registers +++ * outside _this_ critical section. +++ */ ++ extern __inline__ int test_and_set_bit(int nr, volatile void * addr) ++ { ++ int mask, retval; +++ volatile int *a = addr; ++ __bi_flags; ++ ++ a += nr >> 5; ++*************** ++*** 226,235 **** ++ return retval; ++ } ++ ++ extern __inline__ int test_and_clear_bit(int nr, volatile void * addr) ++ { ++ int mask, retval; ++- int *a = addr; ++ __bi_flags; ++ ++ a += nr >> 5; ++--- 256,278 ---- ++ return retval; ++ } ++ +++ extern __inline__ int __test_and_set_bit(int nr, volatile void * addr) +++ { +++ int mask, retval; +++ volatile int *a = addr; +++ +++ a += nr >> 5; +++ mask = 1 << (nr & 0x1f); +++ retval = (mask & *a) != 0; +++ *a |= mask; +++ +++ return retval; +++ } +++ ++ extern __inline__ int test_and_clear_bit(int nr, volatile void * addr) ++ { ++ int mask, retval; +++ volatile int *a = addr; ++ __bi_flags; ++ ++ a += nr >> 5; ++*************** ++*** 242,251 **** ++ return retval; ++ } ++ ++ extern __inline__ int test_and_change_bit(int nr, volatile void * addr) ++ { ++ int mask, retval; ++- int *a = addr; ++ __bi_flags; ++ ++ a += nr >> 5; ++--- 285,307 ---- ++ return retval; ++ } ++ +++ extern __inline__ int __test_and_clear_bit(int nr, volatile void * addr) +++ { +++ int mask, retval; +++ volatile int *a = addr; +++ +++ a += nr >> 5; +++ mask = 1 << (nr & 0x1f); +++ retval = (mask & *a) != 0; +++ *a &= ~mask; +++ +++ return retval; +++ } +++ ++ extern __inline__ int test_and_change_bit(int nr, volatile void * addr) ++ { ++ int mask, retval; +++ volatile int *a = addr; ++ __bi_flags; ++ ++ a += nr >> 5; ++*************** ++*** 259,267 **** ++ } ++ ++ #undef __bi_flags ++- #undef __bi_cli() ++- #undef __bi_save_flags(x) ++- #undef __bi_restore_flags(x) ++ ++ #endif /* MIPS I */ ++ ++--- 315,323 ---- ++ } ++ ++ #undef __bi_flags +++ #undef __bi_cli +++ #undef __bi_save_flags +++ #undef __bi_restore_flags ++ ++ #endif /* MIPS I */ ++ +diff -ruN linux/include/linux/pci_ids.h linux-mips/include/linux/pci_ids.h +--- linux/include/linux/pci_ids.h Thu Nov 23 15:51:51 2000 ++++ linux-mips/include/linux/pci_ids.h Fri Nov 10 00:17:29 2000 +@@ -318,6 +318,7 @@ + #define PCI_VENDOR_ID_NEC 0x1033 + #define PCI_DEVICE_ID_NEC_PCX2 0x0046 + #define PCI_DEVICE_ID_NEC_NILE4 0x005a ++#define PCI_DEVICE_ID_NEC_VRC5476 0x009b + + #define PCI_VENDOR_ID_FD 0x1036 + #define PCI_DEVICE_ID_FD_36C70 0x0000 +diff -ruN linux/include/linux/sched.h linux-mips/include/linux/sched.h +--- linux/include/linux/sched.h Thu Nov 23 15:51:51 2000 ++++ linux-mips/include/linux/sched.h Fri Nov 10 00:17:40 2000 +@@ -552,6 +552,8 @@ + extern int in_group_p(gid_t); + extern int in_egroup_p(gid_t); + ++extern void release(struct task_struct * p); ++ + extern void proc_caches_init(void); + extern void flush_signals(struct task_struct *); + extern void flush_signal_handlers(struct task_struct *); diff --git a/devel/mipsel-linux-kernel-headers/files/patch-bb-mips-lv-2000-11-23 b/devel/mipsel-linux-kernel-headers/files/patch-bb-mips-lv-2000-11-23 new file mode 100644 index 000000000000..d2304fb40444 --- /dev/null +++ b/devel/mipsel-linux-kernel-headers/files/patch-bb-mips-lv-2000-11-23 @@ -0,0 +1,7471 @@ +diff -ruN linux-mips/include/asm-mips/betty.h linux-vr/include/asm-mips/betty.h +--- linux-mips/include/asm-mips/betty.h Wed Dec 31 16:00:00 1969 ++++ linux-vr/include/asm-mips/betty.h Tue May 2 07:28:47 2000 +@@ -0,0 +1,170 @@ ++/* $Id: betty.h,v 1.1 2000/05/02 14:28:47 nop Exp $ ++ * ++ * Definitions for "Betty" companion chip (audio/telecom/touch panel) ++ * for the r39xx processors. Known as the Toshiba TC35143F or Philips UCB1200. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ */ ++ ++#ifndef __BETTY_H__ ++#define __BETTY_H__ ++ ++ ++#define BIT(x) (1 << x) ++ ++ ++/* Registers */ ++ ++#define BETTY_REG_IO_PORT_DATA 0 ++#define BETTY_REG_IO_PORT_DIRECTION 1 ++#define BETTY_REG_RISING_INT_ENABLE 2 ++#define BETTY_REG_FALLING_INT_ENABLE 3 ++#define BETTY_REG_INT_CLEAR_STATUS 4 ++#define BETTY_REG_TEL_CTRL_A 5 ++#define BETTY_REG_TEL_CTRL_B 6 ++#define BETTY_REG_AUD_CTRL_A 7 ++#define BETTY_REG_AUD_CTRL_B 8 ++#define BETTY_REG_TOUCHSCREEN_CTRL 9 ++#define BETTY_REG_ADC_CTRL 10 ++#define BETTY_REG_ADC_DATA 11 ++#define BETTY_REG_ID 12 ++#define BETTY_REG_MODE 13 ++ ++/* 0 - I/O port data register */ ++ ++#define BETTY_IO_DATA_MASK 0x03ff ++#define BETTY_IO_DATA_SHIFT 0 ++ ++/* 1 - I/O port direction register */ ++ ++#define BETTY_IO_DIR_MASK 0x03ff ++#define BETTY_IO_DIR_SHIFT 0 ++#define BETTY_SIB_ZERO BIT(15) ++ ++/* 2 - Rising edge interrupt enable register */ ++ ++#define BETTY_IO_RIS_INT_MASK 0x03ff ++#define BETTY_IO_RIS_INT_SHIFT 0 ++#define BETTY_ADC_RIS_INT BIT(11) ++#define BETTY_TSPX_RIS_INT BIT(12) ++#define BETTY_TSMX_RIS_INT BIT(13) ++#define BETTY_TCLIP_RIS_INT BIT(14) ++#define BETTY_ACLIP_RIS_INT BIT(15) ++ ++/* 3 - Falling edge interrupt enable register */ ++ ++#define BETTY_IO_FAL_INT_MASK 0x03ff ++#define BETTY_IO_FAL_INT_SHIFT 0 ++#define BETTY_ADC_FAL_INT BIT(11) ++#define BETTY_TSPX_FAL_INT BIT(12) ++#define BETTY_TSMX_FAL_INT BIT(13) ++#define BETTY_TCLIP_FAL_INT BIT(14) ++#define BETTY_ACLIP_FAL_INT BIT(15) ++ ++/* 4 - Interrupt clear/status register */ ++ ++#define BETTY_IO_INT_MASK 0x03ff ++#define BETTY_IO_INT_SHIFT 0 ++#define BETTY_ADC_INT BIT(11) ++#define BETTY_TSPX_INT BIT(12) ++#define BETTY_TSMX_INT BIT(13) ++#define BETTY_TCLIP_INT BIT(14) ++#define BETTY_ACLIP_INT BIT(15) ++ ++/* 5 - Telecom control register A */ ++ ++#define BETTY_TEL_DIV_MASK 0x007f ++#define BETTY_TEL_DIV_SHIFT 0 ++#define BETTY_TEL_LOOP BIT(7) ++ ++/* 6 - Telecom control register B */ ++ ++#define BETTY_TEL_VOICE_ENA BIT(3) ++#define BETTY_TEL_CLIP_DETECT BIT(4) ++#define BETTY_TEL_ATT BIT(6) ++#define BETTY_TEL_SIDE_ENA BIT(11) ++#define BETTY_TEL_MUTE BIT(13) ++#define BETTY_TEL_IN_ENA BIT(14) ++#define BETTY_TEL_OUT_ENA BIT(15) ++ ++/* 7 - Audio control register A */ ++ ++#define BETTY_AUD_DIV_MASK 0x007f ++#define BETTY_AUD_DIV_SHIFT 0 ++#define BETTY_AUD_GAIN_MASK 0x0f80 ++#define BETTY_AUD_GAIN_SHIFT 7 ++ ++/* 8 - Audio control register B */ ++ ++#define BETTY_AUD_ATT_MASK 0x001f ++#define BETTY_AUD_ATT_SHIFT 0 ++#define BETTY_AUD_CLIP_DETECT BIT(6) ++#define BETTY_AUD_LOOP BIT(8) ++#define BETTY_AUD_MUTE BIT(13) ++#define BETTY_AUD_IN_ENA BIT(14) ++#define BETTY_AUD_OUT_ENA BIT(15) ++ ++/* 9 - Touch screen control register */ ++ ++#define BETTY_TSMX_POW BIT(0) ++#define BETTY_TSPX_POW BIT(1) ++#define BETTY_TSMY_POW BIT(2) ++#define BETTY_TSPY_POW BIT(3) ++#define BETTY_TSMX_GND BIT(4) ++#define BETTY_TSPX_GND BIT(5) ++#define BETTY_TSMY_GND BIT(6) ++#define BETTY_TSPY_GND BIT(7) ++#define BETTY_TSC_MODE_MASK (BIT(8) | BIT(9)) ++#define BETTY_TSC_MODE_SHIFT 8 ++#define BETTY_TSC_BIAS_ENA BIT(11) ++#define BETTY_TSPX_LOW BIT(12) ++#define BETTY_TSMX_LOW BIT(13) ++ ++/* 10 - ADC control register */ ++ ++#define BETTY_ADC_SYNC_ENA BIT(0) ++#define BETTY_VREFBYP_CON BIT(1) ++#define BETTY_ADC_INPUT_MASK (BIT(2) | BIT(3) | BIT(4)) ++#define BETTY_ADC_INPUT_SHIFT 2 ++#define BETTY_ADC_INPUT_TSPX 0 ++#define BETTY_ADC_INPUT_TSMX 1 ++#define BETTY_ADC_INPUT_TSPY 2 ++#define BETTY_ADC_INPUT_TSMY 3 ++#define BETTY_ADC_INPUT_AD0 4 ++#define BETTY_ADC_INPUT_AD1 5 ++#define BETTY_ADC_INPUT_AD2 6 ++#define BETTY_ADC_INPUT_AD3 7 ++#define BETTY_EXT_REF_ENA BIT(5) ++#define BETTY_ADC_START BIT(7) ++#define BETTY_ADC_ENA BIT(15) ++ ++/* 11 - ADC data register */ ++ ++#define BETTY_ADC_DATA_MASK 0x7fe0 ++#define BETTY_ADC_DATA_SHIFT 5 ++#define BETTY_ADC_DAT_VAL BIT(15) ++ ++/* 12 - ID register */ ++ ++#define BETTY_VERSION_MASK 0x003f ++#define BETTY_VERSION_SHIFT 0 ++#define BETTY_DEVICE_MASK 0x0fc0 ++#define BETTY_DEVICE_SHIFT 6 ++#define BETTY_SUPPLIER_MASK 0xf000 ++#define BETTY_SUPPLIER_SHIFT 12 ++ ++/* 13 - Mode register */ ++ ++#define BETTY_AUD_TEST BIT(0) ++#define BETTY_TEL_TEST BIT(1) ++#define BETTY_PROD_TEST_MODE (BIT(2) | BIT(3) | BIT(4)) ++#define BETTY_DYN_VFLAG_ENA BIT(12) ++#define BETTY_AUD_OFF_CAN BIT(13) ++ ++/* 14 - Reserved */ ++ ++/* 15 - Null Register - Returns 0xffff */ ++ ++#endif __BETTY_H__ +diff -ruN linux-mips/include/asm-mips/bootinfo.h linux-vr/include/asm-mips/bootinfo.h +--- linux-mips/include/asm-mips/bootinfo.h Fri Nov 10 00:11:41 2000 ++++ linux-vr/include/asm-mips/bootinfo.h Sun Nov 12 12:33:02 2000 +@@ -24,9 +24,13 @@ + #define MACH_GROUP_BAGET 9 /* Baget */ + #define MACH_GROUP_ORION 10 /* CoSine Orion */ + #define MACH_GROUP_GALILEO 11 /* Galileo Eval Boards*/ ++#define MACH_GROUP_VR41XX 12 /* NEC VR41XX-based, mostly PDAs and handhelds */ ++#define MACH_GROUP_R39XX 13 /* Toshiba R39XX / Philips Poseidon based */ + + #define GROUP_NAMES { "unknown", "Jazz", "Digital", "ARC", \ +- "SNI", "ACN", "SGI", "Cobalt", "NEC DDB", "Baget", "Orion", "Galileo" } ++ "SNI", "ACN", "SGI", "Cobalt", "NEC DDB", "Baget", "Orion", "Galileo" , \ ++ "VR41XX", "R39XX" \ ++} + + /* + * Valid machtype values for group unknown (low order halfword of mips_machtype) +@@ -108,6 +112,65 @@ + #define GROUP_NEC_DDB_NAMES { "Vrc-5074", "Vrc-5476"} + + /* ++ * Valid machtype for MACH_GROUP_VR41XX ++ */ ++#define MACH_VR41XX_UNKNOWN 0 ++#define MACH_VR41XX_VADEM_CLIO_1000 1 ++#define MACH_VR41XX_CASIO_E105 2 ++#define MACH_VR41XX_EVEREX_FREESTYLE 3 ++#define MACH_CASIO_E10 4 ++#define MACH_CASIO_E15 5 ++#define MACH_NEC_MOBILEPRO_700 6 ++#define MACH_NEC_MOBILEPRO_750C 7 ++#define MACH_NEC_MOBILEPRO_770 8 ++#define MACH_NEC_MOBILEPRO_800 9 ++#define MACH_NEC_MOBILEGEAR2_R300 10 ++#define MACH_NEC_MOBILEGEAR2_R320 11 ++#define MACH_NEC_MOBILEGEAR2_R430 12 ++#define MACH_NEC_MOBILEGEAR2_R500 13 ++#define MACH_NEC_MOBILEGEAR2_R510 14 ++#define MACH_NEC_MOBILEGEAR2_R520 15 ++#define MACH_NEC_MOBILEGEAR2_R530 16 ++#define MACH_NEC_MOBILEGEAR2_R700 17 ++#define MACH_NEC_OSPREY 18 ++#define MACH_NEC_UEB30 19 ++#define MACH_VR41XX_VADEM_CLIO_1050 20 ++#define MACH_VR41XX_COMPAQ_AERO_21XX 21 ++#define MACH_VR41XX_COMPAQ_AERO_15XX 22 ++#define MACH_VR41XX_IBM_WORKPAD_Z50 23 ++#define MACH_VR41XX_AGENDA_VR3 24 ++#define MACH_DOCOMO_SIGMARION 25 ++#define MACH_NEC_HARRIER 26 ++#define MACH_VR41XX_CASIO_E125 27 ++ ++#define GROUP_VR41XX_NAMES { \ ++ "unknown", "Vadem Clio", "Casio E-105", \ ++ "Everex Freestyle", "Casio E-10", "Casio E-15", "NEC MobilePro 700", \ ++ "NEC MobilePro 750C", "NEC MobilePro 770", "NEC MobilePro 800", \ ++ "NEC MobileGear2 R300", "NEC MobileGear2 R320", \ ++ "NEC MobileGear2 R430", "NEC MobileGear2 R500", \ ++ "NEC MobileGear2 R510", "NEC MobileGear2 R520", \ ++ "NEC MobileGear2 R530", "NEC MobileGear2 R700", \ ++ "NEC Osprey", "NEC Eval Rev30", "Vadem Clio 1050", \ ++ "Compaq Aero 21XX", "Compaq Aero 15XX", "IBM Workpad z50", \ ++ "Agenda VR3", "DoCoMo sigmarion", "NEC Harrier", "Casio E-125" \ ++} ++ ++/* ++ * Valid machtype for MACH_GROUP_R39XX ++ */ ++#define MACH_R39XX_UNKNOWN 0 ++#define MACH_R39XX_PHILIPS_NINO 1 ++#define MACH_R39XX_SHARP_MOBILON 2 ++#define MACH_R39XX_COMPAQ 3 ++#define MACH_R39XX_VTECH_HELIO 4 ++#define MACH_R39XX_PHILIPS_VELO 5 ++ ++#define GROUP_R39XX_NAMES { \ ++ "unknown", "Philips Nino", "Sharp Mobilon", "Compaq 8XX/201X", "VTech Helio", "Philips Velo" \ ++} ++ ++/* + * Valid machtype for group BAGET + */ + #define MACH_BAGET201 0 /* BT23-201 */ +@@ -155,15 +218,19 @@ + #define CPU_NEVADA 27 /* RM5230, RM5260 */ + #define CPU_RM7000 28 + #define CPU_R5432 29 +-#define CPU_LAST 29 ++#define CPU_VR41XX 30 ++#define CPU_R3912 31 ++#define CPU_LAST 31 + + #define CPU_NAMES { "unknown", "R2000", "R3000", "R3000A", "R3041", "R3051", \ + "R3052", "R3081", "R3081E", "R4000PC", "R4000SC", "R4000MC", \ + "R4200", "R4400PC", "R4400SC", "R4400MC", "R4600", "R6000", \ + "R6000A", "R8000", "R10000", "R4300", "R4650", "R4700", "R5000", \ +- "R5000A", "R4640", "Nevada", "RM7000", "R5432" } ++ "R5000A", "R4640", "Nevada", "RM7000", "R5432" , \ ++ "VR41XX", "R39XX" } + +-#define CL_SIZE (80) ++/* Linux VR needs more than 80. */ ++#define CL_SIZE 256 + + #ifndef _LANGUAGE_ASSEMBLY + +diff -ruN linux-mips/include/asm-mips/cpu.h linux-vr/include/asm-mips/cpu.h +--- linux-mips/include/asm-mips/cpu.h Fri Nov 10 00:11:41 2000 ++++ linux-vr/include/asm-mips/cpu.h Sun Nov 12 12:33:02 2000 +@@ -24,12 +24,14 @@ + #define PRID_IMP_R4700 0x2100 + #define PRID_IMP_R4640 0x2200 + #define PRID_IMP_R4650 0x2200 /* Same as R4640 */ ++#define PRID_IMP_R3912 0x2200 + #define PRID_IMP_R5000 0x2300 + #define PRID_IMP_R5432 0x5400 + #define PRID_IMP_SONIC 0x2400 + #define PRID_IMP_MAGIC 0x2500 + #define PRID_IMP_RM7000 0x2700 + #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */ ++#define PRID_IMP_VR41XX 0x0c00 + + #define PRID_IMP_UNKNOWN 0xff00 + +diff -ruN linux-mips/include/asm-mips/dma.h linux-vr/include/asm-mips/dma.h +--- linux-mips/include/asm-mips/dma.h Tue Apr 11 20:57:09 2000 ++++ linux-vr/include/asm-mips/dma.h Thu Nov 23 15:03:56 2000 +@@ -83,7 +83,12 @@ + * Deskstations or Acer PICA but not the much more versatile DMA logic used + * for the local devices on Acer PICA or Magnums. + */ ++#ifdef CONFIG_CPU_VR41XX ++/* VR41xx DMA can transfer under first 32MB physical memory area */ ++#define MAX_DMA_ADDRESS (PAGE_OFFSET + 0x02000000) ++#else + #define MAX_DMA_ADDRESS (PAGE_OFFSET + 0x01000000) ++#endif + + /* 8237 DMA controllers */ + #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */ +diff -ruN linux-mips/include/asm-mips/elf.h linux-vr/include/asm-mips/elf.h +--- linux-mips/include/asm-mips/elf.h Wed Jul 12 23:25:03 2000 ++++ linux-vr/include/asm-mips/elf.h Sun Nov 12 12:33:02 2000 +@@ -28,8 +28,6 @@ + if ((__h->e_machine != EM_MIPS) && \ + (__h->e_machine != EM_MIPS_RS4_BE)) \ + __res = 0; \ +- if (__h->e_flags & EF_MIPS_ARCH) \ +- __res = 0; \ + \ + __res; \ + }) +diff -ruN linux-mips/include/asm-mips/fpu_emulator.h linux-vr/include/asm-mips/fpu_emulator.h +--- linux-mips/include/asm-mips/fpu_emulator.h Wed Dec 31 16:00:00 1969 ++++ linux-vr/include/asm-mips/fpu_emulator.h Tue Apr 25 08:00:22 2000 +@@ -0,0 +1,44 @@ ++/* ++ * Definitiona for the Algorithmics FPU Emulator port into MIPS Linux ++ */ ++/************************************************************************** ++ * ++ * include/asm-mips/fpu_emulator.h ++ * ++ * Kevin D. Kissell, kevink@acm.org ++ * Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved. ++ * ++ * ######################################################################## ++ * ++ * This program is free software; you can distribute it and/or modify it ++ * under the terms of the GNU General Public License (Version 2) as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. ++ * ++ *************************************************************************/ ++/* ++ * Further private data for which no space exists in mips_fpu_soft_struct. ++ * This should be subsumed into the mips_fpu_soft_struct structure as ++ * defined in processor.h as soon as the absurd wired absolute assembler ++ * offsets become dynamic at compile time. ++ */ ++ ++struct mips_fpu_emulator_private { ++ unsigned int eir; ++ struct { ++ unsigned int emulated; ++ unsigned int loads; ++ unsigned int stores; ++ unsigned int cp1ops; ++ unsigned int cp1xops; ++ unsigned int errors; ++ } stats; ++}; +diff -ruN linux-mips/include/asm-mips/inst.h linux-vr/include/asm-mips/inst.h +--- linux-mips/include/asm-mips/inst.h Thu Dec 9 21:03:20 1999 ++++ linux-vr/include/asm-mips/inst.h Tue Apr 25 20:20:34 2000 +@@ -21,7 +21,7 @@ + cop0_op, cop1_op, cop2_op, cop1x_op, + beql_op, bnel_op, blezl_op, bgtzl_op, + daddi_op, daddiu_op, ldl_op, ldr_op, +- major_1c_op, major_1d_op, major_1e_op, major_1f_op, ++ major_1c_op, jalx_op, major_1e_op, major_1f_op, + lb_op, lh_op, lwl_op, lw_op, + lbu_op, lhu_op, lwr_op, lwu_op, + sb_op, sh_op, swl_op, sw_op, +@@ -80,6 +80,15 @@ + }; + + /* ++ * rt field of cop.bc_op opcodes ++ */ ++ ++enum bcop_op { ++ bcf_op, bct_op, bcfl_op, bctl_op ++}; ++ ++ ++/* + * func field of cop0 coi opcodes. + */ + enum cop0_coi_func { +@@ -147,6 +156,73 @@ + madd_op = 0x08, msub_op = 0x0a, + nmadd_op = 0x0c, nmsub_op = 0x0e + }; ++ ++/* ++ * Previous versions of this file used bitfields to ++ * decode MIPS instruction. This has been shown ++ * to be non-portable, particularly across little-endian ++ * compilers. ++ * ++ * These macros allow extraction of one of the above ++ * enum values from a MIPS instruction as fetched from ++ * memory. ++ */ ++ ++/* In case some other massaging is needed, keep MIPSInst as wrapper */ ++ ++#define MIPSInst(x) x ++ ++#define I_OPCODE_SFT 26 ++#define MIPSInst_OPCODE(x) (MIPSInst(x) >> I_OPCODE_SFT) ++ ++#define I_JTARGET_SFT 0 ++#define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff) ++ ++#define I_RS_SFT 21 ++#define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT) ++ ++#define I_RT_SFT 16 ++#define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT) ++ ++#define I_IMM_SFT 0 ++#define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff))) ++#define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff) ++ ++#define I_CACHEOP_SFT 18 ++#define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT) ++ ++#define I_CACHESEL_SFT 16 ++#define MIPSInst_CACHESEL(x) ((MIPSInst(x) & 0x00030000) >> I_CACHESEL_SFT) ++ ++#define I_RD_SFT 11 ++#define MIPSInst_RD(x) ((MIPSInst(x) & 0x0000f800) >> I_RD_SFT) ++ ++#define I_RE_SFT 6 ++#define MIPSInst_RE(x) ((MIPSInst(x) & 0x000007c0) >> I_RE_SFT) ++ ++#define I_FUNC_SFT 0 ++#define MIPSInst_FUNC(x) (MIPSInst(x) & 0x0000003f) ++ ++#define I_FFMT_SFT 21 ++#define MIPSInst_FFMT(x) ((MIPSInst(x) & 0x01e00000) >> I_FFMT_SFT) ++ ++#define I_FT_SFT 16 ++#define MIPSInst_FT(x) ((MIPSInst(x) & 0x001f0000) >> I_FT_SFT) ++ ++#define I_FS_SFT 11 ++#define MIPSInst_FS(x) ((MIPSInst(x) & 0x0000f800) >> I_FS_SFT) ++ ++#define I_FD_SFT 6 ++#define MIPSInst_FD(x) ((MIPSInst(x) & 0x000007c0) >> I_FD_SFT) ++ ++#define I_FR_SFT 21 ++#define MIPSInst_FR(x) ((MIPSInst(x) & 0x03e00000) >> I_FR_SFT) ++ ++#define I_FMA_FUNC_SFT 2 ++#define MIPSInst_FMA_FUNC(x) ((MIPSInst(x) & 0x0000003c) >> I_FMA_FUNC_SFT) ++ ++#define I_FMA_FFMT_SFT 0 ++#define MIPSInst_FMA_FFMT(x) (MIPSInst(x) & 0x00000003) + + /* + * Damn ... bitfields depend from byteorder :-( +diff -ruN linux-mips/include/asm-mips/io.h linux-vr/include/asm-mips/io.h +--- linux-mips/include/asm-mips/io.h Fri Nov 10 00:11:47 2000 ++++ linux-vr/include/asm-mips/io.h Thu Nov 23 15:03:51 2000 +@@ -13,6 +13,10 @@ + + /* + * Slowdown I/O port space accesses for antique hardware. ++ * ++ * Notice: just because this is mips you can't assume it has no broken ++ * hardware. For example I've just inserted pcmcia ne2k into my ++ * philips velo. Ouch. + */ + #undef CONF_SLOWDOWN_IO + +@@ -48,34 +52,19 @@ + * instruction, so the lower 16 bits must be zero. Should be true on + * on any sane architecture; generic code does not use this assumption. + */ +-extern unsigned long mips_io_port_base; + +-/* +- * Thanks to James van Artsdalen for a better timing-fix than +- * the two short jumps: using outb's to a nonexistent port seems +- * to guarantee better timings even on fast machines. +- * +- * On the other hand, I'd like to be sure of a non-existent port: +- * I feel a bit unsafe about using 0x80 (should be safe, though) +- * +- * Linus +- * +- */ ++#include + ++extern unsigned long mips_io_port_base; + #define __SLOW_DOWN_IO \ +- __asm__ __volatile__( \ +- "sb\t$0,0x80(%0)" \ +- : : "r" (mips_io_port_base)); ++ { int i; for (i=0; i<100; i++) barrier(); } + +-#ifdef CONF_SLOWDOWN_IO + #ifdef REALLY_SLOW_IO + #define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; } + #else + #define SLOW_DOWN_IO __SLOW_DOWN_IO + #endif +-#else +-#define SLOW_DOWN_IO +-#endif ++ + + /* + * Change virtual addresses to physical addresses and vv. +@@ -91,11 +80,10 @@ + return (void *)KSEG0ADDR(address); + } + +-extern void * ioremap(unsigned long phys_addr, unsigned long size); +-extern void iounmap(void *addr); +- + /* + * IO bus memory addresses are also 1:1 with the physical address ++ * Note: These functions are only to be used to translate between ++ * bus and vitual for system RAM, not for shared peripheral RAM + */ + extern inline unsigned long virt_to_bus(volatile void * address) + { +@@ -114,11 +102,6 @@ + extern unsigned long isa_slot_offset; + + /* +- * readX/writeX() are used to access memory mapped devices. On some +- * architectures the memory mapped IO stuff needs to be accessed +- * differently. On the x86 architecture, we just read/write the +- * memory location directly. +- * + * On MIPS, we have the whole physical address space mapped at all + * times, so "ioremap()" and "iounmap()" do not need to do anything. + * (This isn't true for all machines but we still handle these cases +@@ -126,10 +109,33 @@ + * + * We cheat a bit and always return uncachable areas until we've fixed + * the drivers to handle caching properly. ++ * ++ * Note that although the return value of these functions looks like a ++ * virtual address (and is used as such by read/write[bwl]), it cannot ++ * simply be used as such, but must only be used with read/write[bwl]() ++ * or mem*io(), below. ++ * ++ * The offset argument is supposedly a bus address, but we mask off the ++ * non-significant bits because sometimes they contain extra information ++ * (for systems with multiple PCI busses, at least). + */ + extern inline void * ioremap(unsigned long offset, unsigned long size) + { ++#ifdef CONFIG_CPU_VR4122 ++ return (void *) KSEG1ADDR(offset); ++#else ++#ifdef CONFIG_ISA ++ return (void *)(isa_slot_offset + (offset & 0x03ffffff)); ++#ifdef CONFIG_PCI ++#error "using ISA mapping for PCI bus addresses, that's just wrong" ++#endif ++#else + return (void *) KSEG1ADDR(offset); ++#if 0 // I'm silencing this warning, because it makes r39xx compiles annoying ++#warning "using 1:1 bus to pyhsical mapping, not sure if that's right" ++#endif ++#endif ++#endif + } + + /* +@@ -139,7 +145,21 @@ + */ + extern inline void * ioremap_nocache (unsigned long offset, unsigned long size) + { ++#ifdef CONFIG_CPU_VR4122 + return (void *) KSEG1ADDR(offset); ++#else ++#ifdef CONFIG_ISA ++ return (void *) KSEG1ADDR(isa_slot_offset + (offset & 0x03ffffff)); ++#ifdef CONFIG_PCI ++#error "using ISA mapping for PCI bus addresses, that's just wrong" ++#endif ++#else ++ return (void *) KSEG1ADDR(offset); ++#if 0 // this one too - note that these do need to be addressed for non-isa ++#warning "using 1:1 bus to pyhsical mapping, not sure if that's right" ++#endif ++#endif ++#endif + } + + extern inline void iounmap(void *addr) +@@ -147,10 +167,17 @@ + } + + /* +- * XXX We need system specific versions of these to handle EISA address bits +- * 24-31 on SNI. +- * XXX more SNI hacks. ++ * readX/writeX() are used to access memory mapped devices. Some architectures ++ * require special handling for this, but MIPS can just read/write the memory ++ * location directly. ++ * ++ * Note that the argument to these is niether a virtual addresses, a physical ++ * addresses, nor a bus addresses. The address argument is a "ioremap cookie", ++ * (cleverly disguised as a virtual address) as returned by ioremap(). The ++ * return value of ioremap() should never be used directly and nothing but the ++ * return value of ioremap() should be used with readX/writeX (or memXio). + */ ++ + #define readb(addr) (*(volatile unsigned char *)(addr)) + #define readw(addr) (*(volatile unsigned short *)(addr)) + #define readl(addr) (*(volatile unsigned int *)(addr)) +@@ -169,28 +196,21 @@ + #define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) + #define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) + +-/* END SNI HACKS ... */ +- + /* +- * ISA space is 'always mapped' on currently supported MIPS systems, no need +- * to explicitly ioremap() it. The fact that the ISA IO space is mapped +- * to PAGE_OFFSET is pure coincidence - it does not mean ISA values +- * are physical addresses. The following constant pointer can be +- * used as the IO-area pointer (it can be iounmapped as well, so the +- * analogy with PCI is quite large): +- */ +-#define __ISA_IO_base ((char *)(PAGE_OFFSET)) +- +-#define isa_readb(a) readb(a) +-#define isa_readw(a) readw(a) +-#define isa_readl(a) readl(a) +-#define isa_writeb(b,a) writeb(b,a) +-#define isa_writew(w,a) writew(w,a) +-#define isa_writel(l,a) writel(l,a) +- +-#define isa_memset_io(a,b,c) memset_io((a),(b),(c)) +-#define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),(b),(c)) +-#define isa_memcpy_toio(a,b,c) memcpy_toio((a),(b),(c)) ++ * These are for convenience porting old ISA drivers, as an alternative to ++ * adding a call to ioremap(). The proper thing to do is use ioremap(), ++ * these are here mostly becuase they're easy to implement. ++ */ ++ ++#define isa_readb(a) readb(isa_slot_offset + (a)) ++#define isa_readw(a) readw(isa_slot_offset + (a)) ++#define isa_readl(a) readl(isa_slot_offset + (a)) ++#define isa_writeb(b,a) writeb(b,isa_slot_offset + (a)) ++#define isa_writew(w,a) writew(w,isa_slot_offset + (a)) ++#define isa_writel(l,a) writel(l,isa_slot_offset + (a)) ++#define isa_memset_io(a,b,c) memset_io(isa_slot_offset + (a),(b),(c)) ++#define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),isa_slot_offset + (b),(c)) ++#define isa_memcpy_toio(a,b,c) memcpy_toio(isa_slot_offset + (a),(b),(c) + + /* + * We don't have csum_partial_copy_fromio() yet, so we cheat here and +@@ -465,7 +485,11 @@ + __insl((port),(addr),(count))) + #endif + ++#ifdef CONFIG_CPU_VR4122 ++#define IO_SPACE_LIMIT 0xffffffff ++#else + #define IO_SPACE_LIMIT 0xffff ++#endif + + /* + * The caches on some architectures aren't dma-coherent and have need to +diff -ruN linux-mips/include/asm-mips/isadep.h linux-vr/include/asm-mips/isadep.h +--- linux-mips/include/asm-mips/isadep.h Tue Apr 11 20:57:14 2000 ++++ linux-vr/include/asm-mips/isadep.h Tue Sep 19 07:39:30 2000 +@@ -12,7 +12,7 @@ + #ifndef __ASM_MIPS_ISADEP_H + #define __ASM_MIPS_ISADEP_H + +-#if defined(CONFIG_CPU_R3000) ++#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_R39XX) + /* + * R2000 or R3000 + */ +diff -ruN linux-mips/include/asm-mips/keyboard.h linux-vr/include/asm-mips/keyboard.h +--- linux-mips/include/asm-mips/keyboard.h Mon Jul 10 15:22:07 2000 ++++ linux-vr/include/asm-mips/keyboard.h Thu Nov 23 15:04:53 2000 +@@ -1,4 +1,4 @@ +-/* $Id: keyboard.h,v 1.14 1999/08/19 22:56:33 ralf Exp $ ++/* $Id: keyboard.h,v 1.18 1999/12/01 17:14:54 harald Exp $ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive +@@ -15,6 +15,18 @@ + #include + #include + ++#if defined(CONFIG_CLASS_PDA) || defined(CONFIG_NEC_HARRIER) ++ ++extern int kbd_setkeycode(unsigned int scancode, unsigned int keycode); ++extern int kbd_getkeycode(unsigned int scancode); ++extern int kbd_translate(unsigned char scancode, unsigned char *keycode, ++ char raw_mode); ++extern char kbd_unexpected_up(unsigned char keycode); ++extern void kbd_leds(unsigned char leds); ++extern void kbd_init_hw(void); ++ ++#else ++ + #define DISABLE_KBD_DURING_INTERRUPTS 0 + + extern int pckbd_setkeycode(unsigned int scancode, unsigned int keycode); +@@ -35,7 +47,11 @@ + #define kbd_init_hw pckbd_init_hw + #define kbd_sysrq_xlate pckbd_sysrq_xlate + ++#ifndef CONFIG_CLASS_PDA + #define SYSRQ_KEY 0x54 ++#else ++#define SYSRQ_KEY 12345678 /* Impossible value: we'd have to provide translation map, and that's not exactly easy */ ++#endif + + /* Some stoneage hardware needs delays after some operations. */ + #define kbd_pause() do { } while(0) +@@ -69,6 +85,8 @@ + #define kbd_write_output(val) kbd_ops->kbd_write_output(val) + #define kbd_write_command(val) kbd_ops->kbd_write_command(val) + #define kbd_read_status() kbd_ops->kbd_read_status() ++ ++#endif /* CONFIG_CLASS_PDA */ + + #endif /* __KERNEL */ + +diff -ruN linux-mips/include/asm-mips/linux_logo.h linux-vr/include/asm-mips/linux_logo.h +--- linux-mips/include/asm-mips/linux_logo.h Tue Apr 11 20:57:19 2000 ++++ linux-vr/include/asm-mips/linux_logo.h Thu Nov 23 15:04:44 2000 +@@ -21,921 +21,21 @@ + + #include + #include ++#include + +-#define linux_logo_banner "Linux/MIPS version " UTS_RELEASE ++#ifdef CONFIG_CPU_VR41XX ++ #include ++ #include + +-#define LINUX_LOGO_COLORS 212 ++ #define linux_logo_banner "Linux VR version " UTS_RELEASE + +-#ifdef INCLUDE_LINUX_LOGO_DATA +- +-unsigned char linux_logo_red[] __initdata = { +- 0x03, 0x82, 0xE9, 0xBF, 0x42, 0xC9, 0x7E, 0xC0, +- 0xE9, 0xE3, 0xC2, 0x24, 0xA4, 0x65, 0xEC, 0xC4, +- 0x82, 0x9F, 0xF3, 0x12, 0x5F, 0xA0, 0xC2, 0xED, +- 0x3E, 0xD5, 0xDB, 0xA0, 0x1C, 0xF4, 0xEB, 0xA4, +- 0xCD, 0x0A, 0x9A, 0x51, 0xCC, 0xBE, 0xC0, 0xBA, +- 0x74, 0xDC, 0xAA, 0xF6, 0xD3, 0xC5, 0xE6, 0x26, +- 0xC2, 0x83, 0x38, 0xEA, 0x49, 0xB0, 0xED, 0xE5, +- 0xF4, 0x96, 0x96, 0x1B, 0xFA, 0xCC, 0xF2, 0x0F, +- 0xCD, 0xE5, 0xF4, 0xD3, 0x50, 0x7A, 0xB5, 0xDE, +- 0xD5, 0xB6, 0x60, 0x0A, 0x6A, 0xEA, 0xD4, 0xEB, +- 0xC1, 0xCA, 0xEA, 0xEC, 0x2A, 0x96, 0x95, 0xDC, +- 0xE4, 0xCE, 0xEC, 0x1E, 0xDC, 0x8A, 0xD1, 0xF6, +- 0x3C, 0x5E, 0xC6, 0xB4, 0xB2, 0xAC, 0xBA, 0x9E, +- 0x0F, 0x59, 0xBA, 0xFA, 0xCC, 0xBF, 0x82, 0xCE, +- 0xE6, 0x4F, 0xAA, 0x4C, 0xCA, 0x8E, 0x8E, 0xDF, +- 0x2C, 0xB6, 0x3B, 0xDE, 0xCE, 0xEE, 0x46, 0x4A, +- 0x6F, 0x7A, 0x82, 0xE4, 0xAA, 0x88, 0xE2, 0xCE, +- 0xAE, 0xB6, 0x70, 0xC2, 0x9A, 0xDA, 0x35, 0x9E, +- 0x95, 0xC0, 0x7E, 0x8C, 0xC2, 0xB6, 0xCE, 0xB9, +- 0xD5, 0xAA, 0xC1, 0xF4, 0xC7, 0xB6, 0xB6, 0xA3, +- 0xF2, 0x68, 0xDB, 0x76, 0xDC, 0x57, 0xD3, 0xA8, +- 0xC0, 0xEF, 0x46, 0xF4, 0x2F, 0xD7, 0x53, 0x36, +- 0xE6, 0xA7, 0xCA, 0xCB, 0x7E, 0xE4, 0x86, 0x9A, +- 0xCE, 0x94, 0xB4, 0x1D, 0xDA, 0xCE, 0x6C, 0xE6, +- 0x9E, 0xC6, 0xDA, 0x16, 0xFA, 0xAA, 0x56, 0xB6, +- 0xFE, 0x6E, 0xEA, 0xCE, 0xE5, 0xCC, 0xDB, 0xD3, +- 0xED, 0xDC, 0xF4, 0x72 +-}; +- +-unsigned char linux_logo_green[] __initdata = { +- 0x03, 0x82, 0xC4, 0x83, 0x42, 0xA2, 0x4A, 0xA4, +- 0xE5, 0xA6, 0xC2, 0x24, 0xA4, 0x65, 0xB4, 0x94, +- 0x66, 0x87, 0xB6, 0x12, 0x44, 0x6C, 0x96, 0xD4, +- 0x36, 0x95, 0xB2, 0x92, 0x0E, 0xF4, 0xBC, 0x77, +- 0xA5, 0x0A, 0x92, 0x52, 0xB4, 0x9A, 0x8C, 0xB2, +- 0x74, 0xC2, 0x8E, 0xBD, 0xA2, 0xCA, 0xD2, 0x12, +- 0xB6, 0x61, 0x24, 0xDA, 0x33, 0x79, 0xCB, 0xAC, +- 0xDA, 0x84, 0x7A, 0x1B, 0xFA, 0x8D, 0xBE, 0x06, +- 0x93, 0xBB, 0xBC, 0xAB, 0x44, 0x62, 0x83, 0xDA, +- 0x9B, 0xA2, 0x4C, 0x04, 0x6A, 0xB6, 0xC8, 0xBD, +- 0x8D, 0xB6, 0xAD, 0xEC, 0x2A, 0x68, 0x62, 0x9D, +- 0xC4, 0xC4, 0xB4, 0x13, 0xA3, 0x8A, 0xD2, 0xD6, +- 0x3C, 0x5D, 0x8C, 0x7E, 0x82, 0xAC, 0x96, 0x7E, +- 0x0D, 0x5A, 0xBA, 0xBB, 0xCC, 0xBE, 0x76, 0xB6, +- 0xDE, 0x4E, 0x9A, 0x3C, 0xBE, 0x8E, 0x6E, 0xCB, +- 0x1C, 0xAA, 0x2E, 0xBE, 0xAA, 0xDE, 0x3E, 0x4B, +- 0x4D, 0x7A, 0x54, 0xE4, 0x8E, 0x6E, 0xCA, 0x9B, +- 0x70, 0x9E, 0x5A, 0xAA, 0x9A, 0xBE, 0x34, 0x9E, +- 0x71, 0x9E, 0x7E, 0x5F, 0xAA, 0x8A, 0xBE, 0x91, +- 0xCE, 0x88, 0x92, 0xDB, 0xC6, 0xAB, 0x8A, 0x72, +- 0xE2, 0x44, 0xC3, 0x54, 0xAA, 0x45, 0xBB, 0x92, +- 0xBA, 0xC4, 0x46, 0xCA, 0x2D, 0xD6, 0x3B, 0x1A, +- 0xC2, 0x7E, 0xA6, 0xCB, 0x7A, 0xDC, 0x86, 0x72, +- 0xB6, 0x94, 0xB4, 0x1C, 0xBC, 0xAE, 0x4C, 0xD6, +- 0x62, 0x86, 0xD3, 0x16, 0xF6, 0x7A, 0x55, 0x79, +- 0xFE, 0x6E, 0xC6, 0xC6, 0xAA, 0x93, 0xDC, 0x9D, +- 0xAE, 0xA4, 0xD4, 0x56 +-}; +- +-unsigned char linux_logo_blue[] __initdata = { +- 0x04, 0x84, 0x10, 0x0C, 0x41, 0x14, 0x04, 0x78, +- 0xC7, 0x0E, 0xC4, 0x24, 0xA4, 0x64, 0x0C, 0x0D, +- 0x17, 0x24, 0x0D, 0x13, 0x11, 0x07, 0x40, 0x22, +- 0x0C, 0x0C, 0x11, 0x78, 0x06, 0xF4, 0x0B, 0x0A, +- 0x47, 0x0B, 0x7C, 0x54, 0x6C, 0x0C, 0x0D, 0x9C, +- 0x73, 0x54, 0x14, 0x0C, 0x0F, 0xC7, 0x94, 0x04, +- 0x94, 0x17, 0x0A, 0x6C, 0x08, 0x0F, 0x14, 0x0B, +- 0x12, 0x68, 0x28, 0x11, 0xFA, 0x0A, 0x34, 0x09, +- 0x0A, 0x2F, 0x15, 0x19, 0x14, 0x3C, 0x06, 0xC4, +- 0x0B, 0x84, 0x24, 0x08, 0x69, 0x38, 0xBC, 0x15, +- 0x1F, 0xA0, 0x0A, 0xEC, 0x2A, 0x0C, 0x0C, 0x0C, +- 0x2C, 0xA0, 0x15, 0x07, 0x0B, 0x8C, 0xD3, 0x10, +- 0x3B, 0x5C, 0x0C, 0x04, 0x3C, 0xAC, 0x54, 0x1C, +- 0x0B, 0x5B, 0xBB, 0x0A, 0xC1, 0xBB, 0x5C, 0x3C, +- 0xBC, 0x4D, 0x74, 0x10, 0x8C, 0x8C, 0x14, 0x91, +- 0x0C, 0x74, 0x17, 0x0C, 0x48, 0x9C, 0x3C, 0x4C, +- 0x09, 0x7C, 0x05, 0xE4, 0x34, 0x38, 0x6C, 0x11, +- 0x08, 0x7C, 0x18, 0x2C, 0x9C, 0x4C, 0x34, 0x9C, +- 0x29, 0x54, 0x7C, 0x0C, 0x78, 0x18, 0x9C, 0x14, +- 0xBA, 0x30, 0x27, 0x31, 0xC2, 0x97, 0x24, 0x09, +- 0xB4, 0x04, 0x87, 0x0C, 0x14, 0x1F, 0x7C, 0x64, +- 0xB0, 0x0F, 0x45, 0x10, 0x2C, 0xD4, 0x0A, 0x04, +- 0x44, 0x1F, 0x2C, 0xCC, 0x7C, 0xD8, 0x84, 0x0C, +- 0x8C, 0x94, 0xB4, 0x1D, 0x20, 0x5C, 0x18, 0xB4, +- 0x04, 0x09, 0xBC, 0x14, 0xF4, 0x08, 0x54, 0x07, +- 0xFC, 0x6C, 0x24, 0xB4, 0x15, 0x18, 0xDB, 0x17, +- 0x17, 0x18, 0x21, 0x24 +-}; +- +-unsigned char linux_logo[] __initdata = { +- 0xBC, 0xAC, 0x7D, 0x95, 0xAF, 0x85, 0x2C, 0x2C, +- 0xAC, 0xD9, 0x95, 0x7D, 0x95, 0xAC, 0x2C, 0xAF, +- 0x7D, 0x48, 0xB2, 0xAC, 0x85, 0xDA, 0xDA, 0x2C, +- 0x7D, 0x48, 0x21, 0x2C, 0x8D, 0x2A, 0x8A, 0xDA, +- 0x85, 0x2C, 0xD9, 0xAC, 0x2C, 0x2C, 0xD9, 0xD9, +- 0xAF, 0x85, 0x85, 0x85, 0x8D, 0xBC, 0x2A, 0x2A, +- 0xBC, 0x8C, 0xBC, 0xAC, 0x7D, 0x95, 0xAF, 0x85, +- 0x2C, 0x2C, 0xAC, 0xD9, 0x95, 0x7D, 0x95, 0xAC, +- 0x2C, 0xAF, 0x7D, 0x48, 0xB2, 0xAC, 0x85, 0xDA, +- 0xDA, 0x2C, 0x7D, 0x48, 0x21, 0x2C, 0x8D, 0x2A, +- 0xAF, 0xA1, 0x48, 0x7D, 0xAF, 0x2C, 0x2C, 0xAC, +- 0xD9, 0xD9, 0x95, 0x7D, 0x95, 0xAC, 0xD9, 0x7D, +- 0x48, 0xE9, 0x21, 0xAF, 0xDA, 0xDA, 0x85, 0x2C, +- 0xD9, 0xD9, 0xAC, 0xDA, 0x8A, 0xDA, 0x85, 0x2C, +- 0x2C, 0xAC, 0xD9, 0xAC, 0xAF, 0xAF, 0x2C, 0x2C, +- 0x2C, 0x85, 0x2C, 0x2C, 0x85, 0xDA, 0xDA, 0xDA, +- 0xDA, 0xDA, 0xAF, 0xA1, 0x48, 0x7D, 0xAF, 0x2C, +- 0x2C, 0xAC, 0xD9, 0xD9, 0x95, 0x7D, 0x95, 0xAC, +- 0xD9, 0x7D, 0x48, 0xE9, 0x21, 0xAF, 0xDA, 0xDA, +- 0x85, 0x2C, 0xD9, 0xD9, 0xAC, 0xDA, 0x8A, 0xDA, +- 0x7D, 0x48, 0x48, 0x7D, 0x2C, 0x85, 0x2C, 0xAF, +- 0xD9, 0xD9, 0x7D, 0x95, 0xD9, 0xD9, 0xD9, 0x7D, +- 0xB2, 0x21, 0xD9, 0x85, 0xDA, 0xDA, 0x85, 0x2C, +- 0xAF, 0x2C, 0x2C, 0xDA, 0x85, 0x85, 0x2C, 0x2C, +- 0xAC, 0xD9, 0xD9, 0xAF, 0xDA, 0x85, 0x2C, 0x2C, +- 0x85, 0xDA, 0xDA, 0x85, 0x85, 0xDA, 0x85, 0x85, +- 0x85, 0xAF, 0x7D, 0x48, 0x48, 0x7D, 0x2C, 0x85, +- 0x2C, 0xAF, 0xD9, 0xD9, 0x7D, 0x95, 0xD9, 0xD9, +- 0xD9, 0x7D, 0xB2, 0x21, 0xD9, 0x85, 0xDA, 0xDA, +- 0x85, 0x2C, 0xAF, 0x2C, 0x2C, 0xDA, 0xDA, 0x85, +- 0xA1, 0xE9, 0x48, 0x95, 0x85, 0xDA, 0x85, 0xAF, +- 0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9, 0x95, 0x95, +- 0xD9, 0xAC, 0x85, 0x85, 0xDA, 0xDA, 0x85, 0x2C, +- 0xAC, 0xAC, 0x2C, 0x2C, 0x85, 0x2C, 0x2C, 0xAC, +- 0xD9, 0xD9, 0x2C, 0x91, 0x41, 0x20, 0x6B, 0x20, +- 0x6B, 0x20, 0x6B, 0xAE, 0x2C, 0x85, 0x2C, 0x2C, +- 0xAC, 0xD9, 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0x8D, 0xBC, 0xDA, 0xD9, 0x95, +- 0x95, 0xD9, 0xD9, 0xAF, 0x2C, 0x2C, 0x2C, 0x85, +- 0x2C, 0xAF, 0xAF, 0x85, 0x85, 0x85, 0x2C, 0xAC, +- 0xD9, 0xAF, 0xAF, 0xAF, 0x2C, 0x2C, 0x2C, 0x85, +- 0x8A, 0x2A, 0x8D, 0x2C, 0xD9, 0x95, 0xAC, 0xAC, +- 0xD9, 0xD9, 0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xAF, +- 0xAF, 0x2C, 0x85, 0x85, 0x85, 0x85, 0x85, 0x2C, +- 0x85, 0x2C, 0xD9, 0xD9, 0xD9, 0x2C, 0x2C, 0x2C, +- 0x2C, 0x85, 0x85, 0xAF, 0xAF, 0x85, 0x85, 0x85, +- 0xAF, 0xD9, 0xD9, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C, +- 0x2C, 0x85, 0x8A, 0x2A, 0x8D, 0x2C, 0xD9, 0xD9, +- 0x2C, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, +- 0x85, 0xAF, 0xAC, 0x2C, 0x2C, 0x2C, 0x2C, 0xAC, +- 0xD9, 0xD9, 0xAF, 0x85, 0x85, 0x85, 0xDA, 0xDA, +- 0x8A, 0x8A, 0x85, 0xAC, 0xD9, 0xD9, 0xAC, 0xD9, +- 0xD6, 0xD6, 0x7D, 0x95, 0x7D, 0xD9, 0xAF, 0xAF, +- 0xAF, 0x2C, 0x85, 0x85, 0xDA, 0x85, 0x2C, 0x85, +- 0x85, 0x2C, 0xAF, 0xAC, 0xAF, 0xAF, 0x2C, 0x2C, +- 0x2C, 0x2C, 0x2C, 0xAF, 0xAC, 0x2C, 0x2C, 0x2C, +- 0x2C, 0xAF, 0xD9, 0xAC, 0xAF, 0x2C, 0x85, 0x85, +- 0x85, 0xDA, 0x8D, 0x8A, 0x85, 0xAC, 0x95, 0xD9 +-}; +- +-#define INCLUDE_LINUX_LOGOBW +-#define INCLUDE_LINUX_LOGO16 +-#include ++ #define LINUX_LOGO_COLORS 214 ++ #define INCLUDE_LINUX_LOGO16 ++ #define INCLUDE_LINUX_LOGOBW + ++ #ifdef INCLUDE_LINUX_LOGO_DATA ++ #include "linux_logo_vr.h" ++ #endif + #else +- +-/* prototypes only */ +-extern unsigned char linux_logo_red[]; +-extern unsigned char linux_logo_green[]; +-extern unsigned char linux_logo_blue[]; +-extern unsigned char linux_logo[]; +-extern unsigned char linux_logo_bw[]; +-extern unsigned char linux_logo16_red[]; +-extern unsigned char linux_logo16_green[]; +-extern unsigned char linux_logo16_blue[]; +-extern unsigned char linux_logo16[]; +- ++ #include "linux_logo_sgi.h" + #endif +diff -ruN linux-mips/include/asm-mips/linux_logo_sgi.h linux-vr/include/asm-mips/linux_logo_sgi.h +--- linux-mips/include/asm-mips/linux_logo_sgi.h Wed Dec 31 16:00:00 1969 ++++ linux-vr/include/asm-mips/linux_logo_sgi.h Tue Feb 15 05:38:58 2000 +@@ -0,0 +1,941 @@ ++/* $Id: linux_logo_sgi.h,v 1.1 2000/02/15 13:38:58 brad Exp $ ++ * ++ * include/asm-mips/linux_logo.h: This is a linux logo ++ * to be displayed on boot. ++ * ++ * Copyright (C) 1996 Larry Ewing (lewing@isc.tamu.edu) ++ * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) ++ * ++ * You can put anything here, but: ++ * LINUX_LOGO_COLORS has to be less than 224 ++ * image size has to be 80x80 ++ * values have to start from 0x20 ++ * (i.e. RGB(linux_logo_red[0], ++ * linux_logo_green[0], ++ * linux_logo_blue[0]) is color 0x20) ++ * BW image has to be 80x80 as well, with MS bit ++ * on the left ++ * Serial_console ascii image can be any size, ++ * but should contain %s to display the version ++ */ ++ ++#include ++#include ++ ++#define linux_logo_banner "Linux/MIPS version " UTS_RELEASE ++ ++#define LINUX_LOGO_COLORS 212 ++ ++#ifdef INCLUDE_LINUX_LOGO_DATA ++ ++unsigned char linux_logo_red[] __initdata = { ++ 0x03, 0x82, 0xE9, 0xBF, 0x42, 0xC9, 0x7E, 0xC0, ++ 0xE9, 0xE3, 0xC2, 0x24, 0xA4, 0x65, 0xEC, 0xC4, ++ 0x82, 0x9F, 0xF3, 0x12, 0x5F, 0xA0, 0xC2, 0xED, ++ 0x3E, 0xD5, 0xDB, 0xA0, 0x1C, 0xF4, 0xEB, 0xA4, ++ 0xCD, 0x0A, 0x9A, 0x51, 0xCC, 0xBE, 0xC0, 0xBA, ++ 0x74, 0xDC, 0xAA, 0xF6, 0xD3, 0xC5, 0xE6, 0x26, ++ 0xC2, 0x83, 0x38, 0xEA, 0x49, 0xB0, 0xED, 0xE5, ++ 0xF4, 0x96, 0x96, 0x1B, 0xFA, 0xCC, 0xF2, 0x0F, ++ 0xCD, 0xE5, 0xF4, 0xD3, 0x50, 0x7A, 0xB5, 0xDE, ++ 0xD5, 0xB6, 0x60, 0x0A, 0x6A, 0xEA, 0xD4, 0xEB, ++ 0xC1, 0xCA, 0xEA, 0xEC, 0x2A, 0x96, 0x95, 0xDC, ++ 0xE4, 0xCE, 0xEC, 0x1E, 0xDC, 0x8A, 0xD1, 0xF6, ++ 0x3C, 0x5E, 0xC6, 0xB4, 0xB2, 0xAC, 0xBA, 0x9E, ++ 0x0F, 0x59, 0xBA, 0xFA, 0xCC, 0xBF, 0x82, 0xCE, ++ 0xE6, 0x4F, 0xAA, 0x4C, 0xCA, 0x8E, 0x8E, 0xDF, ++ 0x2C, 0xB6, 0x3B, 0xDE, 0xCE, 0xEE, 0x46, 0x4A, ++ 0x6F, 0x7A, 0x82, 0xE4, 0xAA, 0x88, 0xE2, 0xCE, ++ 0xAE, 0xB6, 0x70, 0xC2, 0x9A, 0xDA, 0x35, 0x9E, ++ 0x95, 0xC0, 0x7E, 0x8C, 0xC2, 0xB6, 0xCE, 0xB9, ++ 0xD5, 0xAA, 0xC1, 0xF4, 0xC7, 0xB6, 0xB6, 0xA3, ++ 0xF2, 0x68, 0xDB, 0x76, 0xDC, 0x57, 0xD3, 0xA8, ++ 0xC0, 0xEF, 0x46, 0xF4, 0x2F, 0xD7, 0x53, 0x36, ++ 0xE6, 0xA7, 0xCA, 0xCB, 0x7E, 0xE4, 0x86, 0x9A, ++ 0xCE, 0x94, 0xB4, 0x1D, 0xDA, 0xCE, 0x6C, 0xE6, ++ 0x9E, 0xC6, 0xDA, 0x16, 0xFA, 0xAA, 0x56, 0xB6, ++ 0xFE, 0x6E, 0xEA, 0xCE, 0xE5, 0xCC, 0xDB, 0xD3, ++ 0xED, 0xDC, 0xF4, 0x72 ++}; ++ ++unsigned char linux_logo_green[] __initdata = { ++ 0x03, 0x82, 0xC4, 0x83, 0x42, 0xA2, 0x4A, 0xA4, ++ 0xE5, 0xA6, 0xC2, 0x24, 0xA4, 0x65, 0xB4, 0x94, ++ 0x66, 0x87, 0xB6, 0x12, 0x44, 0x6C, 0x96, 0xD4, ++ 0x36, 0x95, 0xB2, 0x92, 0x0E, 0xF4, 0xBC, 0x77, ++ 0xA5, 0x0A, 0x92, 0x52, 0xB4, 0x9A, 0x8C, 0xB2, ++ 0x74, 0xC2, 0x8E, 0xBD, 0xA2, 0xCA, 0xD2, 0x12, ++ 0xB6, 0x61, 0x24, 0xDA, 0x33, 0x79, 0xCB, 0xAC, ++ 0xDA, 0x84, 0x7A, 0x1B, 0xFA, 0x8D, 0xBE, 0x06, ++ 0x93, 0xBB, 0xBC, 0xAB, 0x44, 0x62, 0x83, 0xDA, ++ 0x9B, 0xA2, 0x4C, 0x04, 0x6A, 0xB6, 0xC8, 0xBD, ++ 0x8D, 0xB6, 0xAD, 0xEC, 0x2A, 0x68, 0x62, 0x9D, ++ 0xC4, 0xC4, 0xB4, 0x13, 0xA3, 0x8A, 0xD2, 0xD6, ++ 0x3C, 0x5D, 0x8C, 0x7E, 0x82, 0xAC, 0x96, 0x7E, ++ 0x0D, 0x5A, 0xBA, 0xBB, 0xCC, 0xBE, 0x76, 0xB6, ++ 0xDE, 0x4E, 0x9A, 0x3C, 0xBE, 0x8E, 0x6E, 0xCB, ++ 0x1C, 0xAA, 0x2E, 0xBE, 0xAA, 0xDE, 0x3E, 0x4B, ++ 0x4D, 0x7A, 0x54, 0xE4, 0x8E, 0x6E, 0xCA, 0x9B, ++ 0x70, 0x9E, 0x5A, 0xAA, 0x9A, 0xBE, 0x34, 0x9E, ++ 0x71, 0x9E, 0x7E, 0x5F, 0xAA, 0x8A, 0xBE, 0x91, ++ 0xCE, 0x88, 0x92, 0xDB, 0xC6, 0xAB, 0x8A, 0x72, ++ 0xE2, 0x44, 0xC3, 0x54, 0xAA, 0x45, 0xBB, 0x92, ++ 0xBA, 0xC4, 0x46, 0xCA, 0x2D, 0xD6, 0x3B, 0x1A, ++ 0xC2, 0x7E, 0xA6, 0xCB, 0x7A, 0xDC, 0x86, 0x72, ++ 0xB6, 0x94, 0xB4, 0x1C, 0xBC, 0xAE, 0x4C, 0xD6, ++ 0x62, 0x86, 0xD3, 0x16, 0xF6, 0x7A, 0x55, 0x79, ++ 0xFE, 0x6E, 0xC6, 0xC6, 0xAA, 0x93, 0xDC, 0x9D, ++ 0xAE, 0xA4, 0xD4, 0x56 ++}; ++ ++unsigned char linux_logo_blue[] __initdata = { ++ 0x04, 0x84, 0x10, 0x0C, 0x41, 0x14, 0x04, 0x78, ++ 0xC7, 0x0E, 0xC4, 0x24, 0xA4, 0x64, 0x0C, 0x0D, ++ 0x17, 0x24, 0x0D, 0x13, 0x11, 0x07, 0x40, 0x22, ++ 0x0C, 0x0C, 0x11, 0x78, 0x06, 0xF4, 0x0B, 0x0A, ++ 0x47, 0x0B, 0x7C, 0x54, 0x6C, 0x0C, 0x0D, 0x9C, ++ 0x73, 0x54, 0x14, 0x0C, 0x0F, 0xC7, 0x94, 0x04, ++ 0x94, 0x17, 0x0A, 0x6C, 0x08, 0x0F, 0x14, 0x0B, ++ 0x12, 0x68, 0x28, 0x11, 0xFA, 0x0A, 0x34, 0x09, ++ 0x0A, 0x2F, 0x15, 0x19, 0x14, 0x3C, 0x06, 0xC4, ++ 0x0B, 0x84, 0x24, 0x08, 0x69, 0x38, 0xBC, 0x15, ++ 0x1F, 0xA0, 0x0A, 0xEC, 0x2A, 0x0C, 0x0C, 0x0C, ++ 0x2C, 0xA0, 0x15, 0x07, 0x0B, 0x8C, 0xD3, 0x10, ++ 0x3B, 0x5C, 0x0C, 0x04, 0x3C, 0xAC, 0x54, 0x1C, ++ 0x0B, 0x5B, 0xBB, 0x0A, 0xC1, 0xBB, 0x5C, 0x3C, ++ 0xBC, 0x4D, 0x74, 0x10, 0x8C, 0x8C, 0x14, 0x91, ++ 0x0C, 0x74, 0x17, 0x0C, 0x48, 0x9C, 0x3C, 0x4C, ++ 0x09, 0x7C, 0x05, 0xE4, 0x34, 0x38, 0x6C, 0x11, ++ 0x08, 0x7C, 0x18, 0x2C, 0x9C, 0x4C, 0x34, 0x9C, ++ 0x29, 0x54, 0x7C, 0x0C, 0x78, 0x18, 0x9C, 0x14, ++ 0xBA, 0x30, 0x27, 0x31, 0xC2, 0x97, 0x24, 0x09, ++ 0xB4, 0x04, 0x87, 0x0C, 0x14, 0x1F, 0x7C, 0x64, ++ 0xB0, 0x0F, 0x45, 0x10, 0x2C, 0xD4, 0x0A, 0x04, ++ 0x44, 0x1F, 0x2C, 0xCC, 0x7C, 0xD8, 0x84, 0x0C, ++ 0x8C, 0x94, 0xB4, 0x1D, 0x20, 0x5C, 0x18, 0xB4, ++ 0x04, 0x09, 0xBC, 0x14, 0xF4, 0x08, 0x54, 0x07, ++ 0xFC, 0x6C, 0x24, 0xB4, 0x15, 0x18, 0xDB, 0x17, ++ 0x17, 0x18, 0x21, 0x24 ++}; ++ ++unsigned char linux_logo[] __initdata = { ++ 0xBC, 0xAC, 0x7D, 0x95, 0xAF, 0x85, 0x2C, 0x2C, ++ 0xAC, 0xD9, 0x95, 0x7D, 0x95, 0xAC, 0x2C, 0xAF, ++ 0x7D, 0x48, 0xB2, 0xAC, 0x85, 0xDA, 0xDA, 0x2C, ++ 0x7D, 0x48, 0x21, 0x2C, 0x8D, 0x2A, 0x8A, 0xDA, ++ 0x85, 0x2C, 0xD9, 0xAC, 0x2C, 0x2C, 0xD9, 0xD9, ++ 0xAF, 0x85, 0x85, 0x85, 0x8D, 0xBC, 0x2A, 0x2A, ++ 0xBC, 0x8C, 0xBC, 0xAC, 0x7D, 0x95, 0xAF, 0x85, ++ 0x2C, 0x2C, 0xAC, 0xD9, 0x95, 0x7D, 0x95, 0xAC, ++ 0x2C, 0xAF, 0x7D, 0x48, 0xB2, 0xAC, 0x85, 0xDA, ++ 0xDA, 0x2C, 0x7D, 0x48, 0x21, 0x2C, 0x8D, 0x2A, ++ 0xAF, 0xA1, 0x48, 0x7D, 0xAF, 0x2C, 0x2C, 0xAC, ++ 0xD9, 0xD9, 0x95, 0x7D, 0x95, 0xAC, 0xD9, 0x7D, ++ 0x48, 0xE9, 0x21, 0xAF, 0xDA, 0xDA, 0x85, 0x2C, ++ 0xD9, 0xD9, 0xAC, 0xDA, 0x8A, 0xDA, 0x85, 0x2C, ++ 0x2C, 0xAC, 0xD9, 0xAC, 0xAF, 0xAF, 0x2C, 0x2C, ++ 0x2C, 0x85, 0x2C, 0x2C, 0x85, 0xDA, 0xDA, 0xDA, ++ 0xDA, 0xDA, 0xAF, 0xA1, 0x48, 0x7D, 0xAF, 0x2C, ++ 0x2C, 0xAC, 0xD9, 0xD9, 0x95, 0x7D, 0x95, 0xAC, ++ 0xD9, 0x7D, 0x48, 0xE9, 0x21, 0xAF, 0xDA, 0xDA, ++ 0x85, 0x2C, 0xD9, 0xD9, 0xAC, 0xDA, 0x8A, 0xDA, ++ 0x7D, 0x48, 0x48, 0x7D, 0x2C, 0x85, 0x2C, 0xAF, ++ 0xD9, 0xD9, 0x7D, 0x95, 0xD9, 0xD9, 0xD9, 0x7D, ++ 0xB2, 0x21, 0xD9, 0x85, 0xDA, 0xDA, 0x85, 0x2C, ++ 0xAF, 0x2C, 0x2C, 0xDA, 0x85, 0x85, 0x2C, 0x2C, ++ 0xAC, 0xD9, 0xD9, 0xAF, 0xDA, 0x85, 0x2C, 0x2C, ++ 0x85, 0xDA, 0xDA, 0x85, 0x85, 0xDA, 0x85, 0x85, ++ 0x85, 0xAF, 0x7D, 0x48, 0x48, 0x7D, 0x2C, 0x85, ++ 0x2C, 0xAF, 0xD9, 0xD9, 0x7D, 0x95, 0xD9, 0xD9, ++ 0xD9, 0x7D, 0xB2, 0x21, 0xD9, 0x85, 0xDA, 0xDA, ++ 0x85, 0x2C, 0xAF, 0x2C, 0x2C, 0xDA, 0xDA, 0x85, ++ 0xA1, 0xE9, 0x48, 0x95, 0x85, 0xDA, 0x85, 0xAF, ++ 0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9, 0x95, 0x95, ++ 0xD9, 0xAC, 0x85, 0x85, 0xDA, 0xDA, 0x85, 0x2C, ++ 0xAC, 0xAC, 0x2C, 0x2C, 0x85, 0x2C, 0x2C, 0xAC, ++ 0xD9, 0xD9, 0x2C, 0x91, 0x41, 0x20, 0x6B, 0x20, ++ 0x6B, 0x20, 0x6B, 0xAE, 0x2C, 0x85, 0x2C, 0x2C, ++ 0xAC, 0xD9, 0xA1, 0xE9, 0x48, 0x95, 0x85, 0xDA, ++ 0x85, 0xAF, 0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9, ++ 0x95, 0x95, 0xD9, 0xAC, 0x85, 0x85, 0xDA, 0xDA, ++ 0x85, 0x2C, 0xAC, 0xAC, 0x2C, 0x2C, 0x2C, 0x2C, ++ 0xA1, 0xA1, 0xD6, 0xAF, 0xDA, 0xDA, 0x85, 0x2C, ++ 0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9, 0xD9, 0xD9, ++ 0x2C, 0x2C, 0xDA, 0xDA, 0xDA, 0x85, 0x2C, 0xD9, ++ 0xD9, 0xD9, 0xD9, 0xAC, 0xAC, 0xAC, 0xAF, 0xAC, ++ 0x2C, 0xB2, 0x88, 0x20, 0x20, 0x20, 0x20, 0x20, ++ 0x20, 0x20, 0x20, 0x20, 0x6B, 0x80, 0x85, 0x2C, ++ 0xD9, 0xD6, 0xA1, 0xA1, 0xD6, 0xAF, 0xDA, 0xDA, ++ 0x85, 0x2C, 0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9, ++ 0xD9, 0xD9, 0x2C, 0x2C, 0xDA, 0xDA, 0xDA, 0x85, ++ 0x2C, 0xD9, 0xD9, 0xD9, 0xD9, 0xAF, 0xAF, 0xAF, ++ 0xD6, 0xD6, 0xD9, 0x2C, 0xDA, 0xDA, 0x2C, 0xAC, ++ 0xD9, 0x7D, 0x95, 0xD9, 0xD9, 0xD9, 0xAF, 0x2C, ++ 0x85, 0x85, 0x85, 0x85, 0x2C, 0x2C, 0xAC, 0xD9, ++ 0xD9, 0xD9, 0xAF, 0xAF, 0x2C, 0x2C, 0xAF, 0xDA, ++ 0xAE, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, ++ 0x20, 0x20, 0x20, 0x41, 0xE3, 0x20, 0x6B, 0x48, ++ 0xAC, 0x95, 0xD6, 0xD6, 0xD9, 0x2C, 0xDA, 0xDA, ++ 0x2C, 0xAC, 0xD9, 0x7D, 0x95, 0xD9, 0xD9, 0xD9, ++ 0xAF, 0x2C, 0x85, 0x85, 0x85, 0x85, 0x2C, 0x2C, ++ 0xAC, 0xD9, 0xD9, 0xD9, 0xAF, 0xAF, 0xAF, 0xAF, ++ 0xD9, 0xD9, 0xD9, 0x2C, 0x85, 0x85, 0x2C, 0xD9, ++ 0x7D, 0x21, 0xD6, 0xD9, 0xAF, 0x2C, 0x85, 0x85, ++ 0x85, 0x85, 0x85, 0x85, 0x2C, 0xAF, 0xAF, 0xAC, ++ 0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x89, ++ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, ++ 0x20, 0x20, 0x20, 0x74, 0x43, 0x80, 0x41, 0x20, ++ 0x9F, 0x2C, 0xD9, 0xD9, 0xD9, 0x2C, 0x85, 0x85, ++ 0x2C, 0xD9, 0x7D, 0x21, 0xD6, 0xD9, 0xAF, 0x2C, ++ 0x85, 0x85, 0x85, 0x85, 0x85, 0x85, 0x2C, 0xAF, ++ 0xAF, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, ++ 0xD9, 0x7D, 0xD9, 0xAF, 0x85, 0x85, 0x2C, 0xD9, ++ 0xB2, 0x21, 0x7D, 0xD9, 0xAF, 0x2C, 0x85, 0x85, ++ 0x85, 0x2C, 0x2C, 0x2C, 0x2C, 0xAF, 0xAF, 0xAC, ++ 0xAF, 0xAC, 0xAF, 0xAF, 0xAC, 0xAC, 0x85, 0x41, ++ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, ++ 0x20, 0x20, 0x20, 0xAE, 0x48, 0x89, 0x74, 0x41, ++ 0x6B, 0xD6, 0xD9, 0x7D, 0xD9, 0xAF, 0x85, 0x85, ++ 0x2C, 0xD9, 0xB2, 0x21, 0x7D, 0xD9, 0xAF, 0x2C, ++ 0x85, 0x85, 0x85, 0x2C, 0x2C, 0x2C, 0x2C, 0xAF, ++ 0xAF, 0xAC, 0xAF, 0xAC, 0xAC, 0x2C, 0xAF, 0xAC, ++ 0x2C, 0x7D, 0xD9, 0x2C, 0xDA, 0x85, 0x2C, 0x7D, ++ 0xB2, 0xD6, 0xD9, 0xAF, 0x85, 0x85, 0x85, 0x85, ++ 0xAF, 0xAC, 0xAC, 0xAF, 0xAF, 0xAC, 0xAC, 0xD9, ++ 0x95, 0x7D, 0x95, 0x95, 0xD9, 0xD9, 0x48, 0x20, ++ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, ++ 0x20, 0x20, 0x6B, 0xAE, 0xE6, 0x80, 0x2B, 0x88, ++ 0x20, 0x33, 0xDA, 0x95, 0xD9, 0x2C, 0xDA, 0x85, ++ 0x2C, 0x7D, 0xB2, 0xD6, 0xD9, 0xAF, 0x85, 0x85, ++ 0x85, 0x85, 0xAF, 0xAC, 0xAC, 0xAF, 0xAF, 0xAC, ++ 0xAC, 0xD9, 0x95, 0x95, 0x7D, 0x95, 0x95, 0xD9, ++ 0x85, 0xD9, 0x2C, 0x85, 0xDA, 0xDA, 0xD9, 0x21, ++ 0xA1, 0xD9, 0xAF, 0x2C, 0x85, 0xDA, 0x85, 0xAF, ++ 0xD9, 0xD9, 0xAC, 0xAC, 0xAC, 0xD9, 0x7D, 0xD6, ++ 0xD6, 0x7D, 0x95, 0xD9, 0xD9, 0x85, 0xDB, 0x20, ++ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, ++ 0x20, 0x20, 0x20, 0xDB, 0xE3, 0x6B, 0x20, 0x20, ++ 0x20, 0x20, 0xE9, 0xD9, 0x2C, 0x85, 0xDA, 0xDA, ++ 0xD9, 0x21, 0xA1, 0xD9, 0xAF, 0x2C, 0x85, 0xDA, ++ 0x85, 0xAF, 0xD9, 0xD9, 0xAC, 0xAC, 0xAC, 0xD9, ++ 0x7D, 0xD6, 0xD6, 0x7D, 0x95, 0xD9, 0xD9, 0xD9, ++ 0xDA, 0x2C, 0x85, 0xDA, 0xDA, 0x85, 0x95, 0x21, ++ 0x21, 0xD9, 0x85, 0x85, 0x85, 0x2C, 0x2C, 0xD9, ++ 0x95, 0x95, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, ++ 0xAC, 0xAC, 0x2C, 0xAF, 0x2C, 0x85, 0x20, 0x20, ++ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, ++ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, ++ 0x20, 0x20, 0x88, 0xDA, 0x85, 0xDA, 0xDA, 0x85, ++ 0x95, 0x21, 0x21, 0xD9, 0x85, 0x85, 0x85, 0x2C, ++ 0x2C, 0xD9, 0x95, 0x95, 0xD9, 0xD9, 0xD9, 0xD9, ++ 0xD9, 0xD9, 0xD9, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C, ++ 0xDA, 0x2C, 0x85, 0x85, 0x2C, 0xD9, 0xD6, 0xB2, ++ 0x95, 0x2C, 0x85, 0x85, 0xAF, 0xAC, 0x95, 0x95, ++ 0x7D, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0x2C, 0x85, ++ 0x85, 0x85, 0x85, 0x85, 0x85, 0xAC, 0x20, 0x20, ++ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, ++ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, ++ 0x20, 0x20, 0x20, 0xAC, 0x85, 0x85, 0x2C, 0xD9, ++ 0xD6, 0xB2, 0x95, 0x2C, 0x85, 0x85, 0xAF, 0xAC, ++ 0x95, 0x95, 0x7D, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, ++ 0x2C, 0x85, 0x85, 0x85, 0x85, 0x85, 0x85, 0x85, ++ 0x85, 0x2C, 0x2C, 0x2C, 0xAC, 0x95, 0xD6, 0x7D, ++ 0xD9, 0x2C, 0x2C, 0xAF, 0x95, 0x7D, 0x7D, 0x95, ++ 0x95, 0xD9, 0xD9, 0x95, 0xD9, 0xD9, 0x2C, 0x85, ++ 0xDA, 0xDA, 0xDA, 0x85, 0x85, 0x21, 0x20, 0x20, ++ 0x6B, 0x41, 0xDB, 0x6B, 0x20, 0x20, 0x20, 0x20, ++ 0x20, 0x20, 0x20, 0x41, 0xDB, 0xDB, 0x20, 0x20, ++ 0x20, 0x20, 0x20, 0xE6, 0x2C, 0x2C, 0xAC, 0x95, ++ 0xD6, 0x7D, 0xD9, 0x2C, 0x2C, 0xAF, 0x95, 0x7D, ++ 0x7D, 0x95, 0x95, 0xD9, 0xD9, 0x95, 0xD9, 0xD9, ++ 0x2C, 0x85, 0xDA, 0xDA, 0xDA, 0x85, 0x2C, 0x2C, ++ 0x2C, 0xAF, 0xAC, 0xD9, 0x95, 0xD6, 0xD6, 0xD9, ++ 0x2C, 0x2C, 0x2C, 0xD9, 0xD6, 0xD6, 0xD9, 0xAF, ++ 0xAC, 0x95, 0xD6, 0x7D, 0x7D, 0xD9, 0x2C, 0x85, ++ 0xDA, 0xDA, 0x2C, 0xAF, 0xAF, 0x21, 0x20, 0x20, ++ 0x88, 0x2B, 0x88, 0x74, 0x20, 0x20, 0x20, 0x20, ++ 0x20, 0xAE, 0x2D, 0x2D, 0x74, 0x74, 0x88, 0x20, ++ 0x20, 0x20, 0x20, 0x80, 0xAC, 0xD9, 0x95, 0xD6, ++ 0xD6, 0xD9, 0x2C, 0x2C, 0x2C, 0xD9, 0xD6, 0xD6, ++ 0xD9, 0xAF, 0xAC, 0x95, 0xD6, 0x7D, 0x7D, 0xD9, ++ 0x2C, 0xDA, 0xDA, 0x85, 0x2C, 0xAF, 0xAF, 0xAF, ++ 0x2C, 0xAF, 0xD9, 0x95, 0xD6, 0xD6, 0x95, 0xAF, ++ 0x2C, 0x2C, 0xD9, 0x95, 0xD6, 0x95, 0xAF, 0x2C, ++ 0xAC, 0x7D, 0x21, 0x95, 0xD9, 0x2C, 0x85, 0x85, ++ 0x85, 0xAF, 0xD9, 0x95, 0xD9, 0x7D, 0x20, 0x33, ++ 0x7D, 0x8A, 0x7D, 0x5B, 0x6B, 0x20, 0x20, 0x6B, ++ 0xE6, 0xD9, 0x85, 0x2A, 0xDA, 0x2B, 0x41, 0x20, ++ 0x20, 0x20, 0x6B, 0x74, 0xD9, 0x95, 0xD6, 0xD6, ++ 0x95, 0xAF, 0x2C, 0x2C, 0xD9, 0x95, 0xD6, 0x95, ++ 0xAF, 0x2C, 0xAC, 0x7D, 0x21, 0x95, 0xD9, 0x2C, ++ 0x85, 0x85, 0x85, 0x2C, 0xD9, 0xD9, 0xD9, 0xD9, ++ 0x85, 0xD9, 0x7D, 0x21, 0x21, 0x7D, 0xAC, 0x2C, ++ 0x2C, 0xAC, 0xD9, 0x7D, 0xD9, 0xAF, 0x2C, 0x85, ++ 0xAC, 0x7D, 0x7D, 0xAC, 0x85, 0xDA, 0x8A, 0xDA, ++ 0x85, 0xAF, 0xD9, 0x7D, 0xD9, 0x95, 0x20, 0x91, ++ 0xBC, 0x73, 0xEE, 0x7D, 0x20, 0x20, 0x20, 0x80, ++ 0x4D, 0x3D, 0x73, 0x73, 0xA3, 0xD6, 0x20, 0x20, ++ 0x20, 0x20, 0x20, 0x2B, 0x7D, 0x21, 0x21, 0x7D, ++ 0xAC, 0x2C, 0x2C, 0xAC, 0xD9, 0x7D, 0xD9, 0xAF, ++ 0x2C, 0x85, 0xAC, 0x7D, 0x7D, 0xAC, 0x85, 0xDA, ++ 0x8A, 0x8A, 0x85, 0xAC, 0xD9, 0x7D, 0xD9, 0xAC, ++ 0x2C, 0xD9, 0xD6, 0xB2, 0xB2, 0x7D, 0xAF, 0x85, ++ 0x2C, 0xD9, 0x95, 0x95, 0xAF, 0x2C, 0x2C, 0x2C, ++ 0xD9, 0xD9, 0xAC, 0x85, 0x8D, 0x2A, 0x2A, 0xDA, ++ 0xAF, 0xD9, 0x95, 0x95, 0xD9, 0xAC, 0x20, 0xAF, ++ 0x2C, 0xE6, 0x8D, 0x73, 0xE3, 0x20, 0x20, 0x48, ++ 0x5C, 0xDA, 0x5B, 0x43, 0xBC, 0x73, 0x2B, 0x20, ++ 0x20, 0x20, 0x20, 0x41, 0xD6, 0xB2, 0xB2, 0x7D, ++ 0xAF, 0x85, 0x2C, 0xD9, 0x95, 0x95, 0xAF, 0x2C, ++ 0x2C, 0x2C, 0xD9, 0xD9, 0xAC, 0x85, 0x8A, 0x2A, ++ 0x8D, 0xDA, 0xAF, 0xD9, 0x95, 0x95, 0xD9, 0xAF, ++ 0xAC, 0xD9, 0xD6, 0xB2, 0x21, 0xD9, 0x2C, 0x85, ++ 0x2C, 0xD9, 0x95, 0xD9, 0xAF, 0x2C, 0x2C, 0xAC, ++ 0xAC, 0xAF, 0x85, 0x8D, 0xBC, 0xBC, 0xDA, 0xD9, ++ 0xD6, 0xA1, 0xA1, 0x21, 0xD9, 0xAC, 0x20, 0x2A, ++ 0xCC, 0xAE, 0x9F, 0xE4, 0xAE, 0x5B, 0x74, 0xA1, ++ 0xE4, 0xAE, 0x20, 0x9F, 0x89, 0xE8, 0xE6, 0x20, ++ 0x20, 0x20, 0x20, 0x41, 0xD6, 0xB2, 0x21, 0xD9, ++ 0x2C, 0x85, 0x2C, 0xD9, 0x95, 0xD9, 0xAF, 0x2C, ++ 0x2C, 0xAC, 0xAC, 0xAF, 0x85, 0x8D, 0xBC, 0x2A, ++ 0xDA, 0xD9, 0xD6, 0xA1, 0xA1, 0x21, 0xD9, 0xD9, ++ 0xD9, 0x95, 0x21, 0xA1, 0x21, 0xAC, 0x85, 0x85, ++ 0xAC, 0xD9, 0xD9, 0xAF, 0x2C, 0x2C, 0xAF, 0xAC, ++ 0xAF, 0x85, 0x8A, 0x2A, 0x2A, 0xDA, 0xD9, 0xA1, ++ 0x48, 0xE9, 0x48, 0x21, 0x95, 0xAC, 0x20, 0x2A, ++ 0xDB, 0x41, 0x74, 0xBC, 0x2B, 0x7B, 0x7B, 0x80, ++ 0x73, 0x41, 0x20, 0x6B, 0x2B, 0xE8, 0x2D, 0x20, ++ 0x20, 0x20, 0x20, 0x33, 0x21, 0xA1, 0x21, 0xAC, ++ 0x85, 0x85, 0xAC, 0xD9, 0xD9, 0xAF, 0x2C, 0x2C, ++ 0xAF, 0xAC, 0xAF, 0x85, 0x8A, 0xBC, 0x2A, 0xDA, ++ 0xD9, 0xA1, 0x48, 0xE9, 0x48, 0x21, 0xD9, 0xD9, ++ 0xA1, 0xB2, 0xB2, 0x48, 0xD6, 0xAC, 0x2C, 0x2C, ++ 0xD9, 0x95, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, ++ 0x85, 0x8A, 0x8D, 0x8D, 0x85, 0x95, 0xA1, 0x6C, ++ 0x6C, 0x48, 0xD6, 0xD9, 0x2C, 0x85, 0x20, 0x2C, ++ 0x89, 0x20, 0x3C, 0xB9, 0xA7, 0x63, 0xD2, 0xB9, ++ 0xC6, 0x9A, 0x20, 0x20, 0x43, 0x5C, 0xE6, 0x20, ++ 0x20, 0x20, 0x20, 0x33, 0xB2, 0x48, 0xD6, 0xAC, ++ 0x2C, 0x2C, 0xD9, 0x95, 0xAF, 0x2C, 0x2C, 0x2C, ++ 0x2C, 0x2C, 0x85, 0x8A, 0x8D, 0x8D, 0x85, 0x95, ++ 0xA1, 0x6C, 0x6C, 0x48, 0xD6, 0xD9, 0xAF, 0xAC, ++ 0xA1, 0xD6, 0x7D, 0xB2, 0xD6, 0xAF, 0x85, 0x85, ++ 0xD9, 0x95, 0x2C, 0x85, 0xDA, 0x85, 0x85, 0x2C, ++ 0x85, 0x8A, 0x8D, 0xDA, 0xD9, 0x48, 0x81, 0x2D, ++ 0x48, 0xD6, 0xD9, 0xAC, 0x2C, 0x85, 0x20, 0x2D, ++ 0xEE, 0x93, 0xD1, 0xA7, 0x3E, 0x3E, 0x3A, 0x25, ++ 0x56, 0xAB, 0xAA, 0xC5, 0xEE, 0xEE, 0x33, 0x20, ++ 0x20, 0x20, 0x20, 0x41, 0xD9, 0xB2, 0xD6, 0xAF, ++ 0x85, 0x85, 0xD9, 0x95, 0x2C, 0x85, 0xDA, 0x85, ++ 0x85, 0x2C, 0x85, 0x8A, 0x8D, 0xDA, 0xD9, 0x48, ++ 0x81, 0x2D, 0x48, 0xD6, 0xD9, 0xAF, 0x2C, 0x2C, ++ 0xAC, 0xAF, 0xD9, 0x7D, 0xD6, 0x2C, 0x85, 0x2C, ++ 0xD9, 0xD9, 0x2C, 0xDA, 0xDA, 0xDA, 0x2C, 0x2C, ++ 0x85, 0x8D, 0x8D, 0x2C, 0x21, 0x2D, 0x2D, 0xE9, ++ 0xD6, 0xD9, 0xAF, 0x2C, 0x85, 0xDA, 0x20, 0xE3, ++ 0xB4, 0xBE, 0xF1, 0x3E, 0x9B, 0x22, 0x56, 0xF2, ++ 0xBB, 0x7F, 0x56, 0xDC, 0x8F, 0x5A, 0x5F, 0x20, ++ 0x20, 0x20, 0x20, 0x6B, 0x2C, 0x7D, 0xD6, 0x2C, ++ 0x85, 0x2C, 0xD9, 0xD9, 0x2C, 0xDA, 0xDA, 0xDA, ++ 0x2C, 0x2C, 0x85, 0x8D, 0x8A, 0x85, 0x21, 0x2D, ++ 0x2D, 0xE9, 0xD6, 0xD9, 0xAF, 0x2C, 0x85, 0x85, ++ 0x2A, 0x85, 0xAC, 0x95, 0x95, 0x2C, 0x85, 0x85, ++ 0xAC, 0xAF, 0x85, 0xDA, 0xDA, 0x85, 0x2C, 0x2C, ++ 0xDA, 0x8A, 0x8A, 0xAF, 0xA1, 0x2D, 0xE9, 0xD6, ++ 0xD9, 0xAC, 0x85, 0x85, 0x85, 0xDA, 0x20, 0x52, ++ 0x55, 0xED, 0x57, 0x3E, 0x22, 0x56, 0x37, 0xBB, ++ 0xBB, 0x58, 0x7F, 0x7F, 0x56, 0x5E, 0xC5, 0x20, ++ 0x20, 0x20, 0x20, 0x20, 0x2C, 0x95, 0x95, 0x2C, ++ 0x85, 0x85, 0xAC, 0xAF, 0x85, 0xDA, 0xDA, 0x85, ++ 0x2C, 0x2C, 0xDA, 0x8D, 0xDA, 0xAF, 0xA1, 0x2D, ++ 0xE9, 0xD6, 0xD9, 0xAF, 0x2C, 0x85, 0x85, 0x85, ++ 0xCD, 0xAF, 0xD9, 0x95, 0xD9, 0x2C, 0xDA, 0x85, ++ 0xAF, 0xD9, 0x85, 0xDA, 0x85, 0x2C, 0xAC, 0xAF, ++ 0x85, 0x8A, 0x85, 0xD9, 0x48, 0x48, 0xB2, 0x95, ++ 0x95, 0xAC, 0x2C, 0x85, 0xDA, 0xDA, 0x6B, 0xB3, ++ 0x46, 0x7C, 0x2E, 0x9B, 0x22, 0x56, 0xBB, 0x37, ++ 0x58, 0x58, 0xF2, 0x3A, 0x46, 0x63, 0x64, 0x20, ++ 0x20, 0x20, 0x20, 0x20, 0x2D, 0x95, 0xD9, 0x2C, ++ 0xDA, 0x85, 0xAF, 0xD9, 0x85, 0xDA, 0x85, 0x2C, ++ 0xAC, 0xAF, 0x85, 0xDA, 0x85, 0xD9, 0x48, 0x48, ++ 0xB2, 0x95, 0x95, 0xD9, 0x85, 0xDA, 0x85, 0x85, ++ 0xBC, 0xB2, 0xB2, 0x7D, 0xD9, 0x2C, 0xDA, 0x85, ++ 0xAF, 0xD9, 0x85, 0xDA, 0x85, 0x85, 0xAF, 0x2C, ++ 0x85, 0xDA, 0x2C, 0x7D, 0xA1, 0x48, 0xB2, 0x21, ++ 0xD6, 0xD9, 0x85, 0xDA, 0x85, 0xDA, 0x41, 0x51, ++ 0xB7, 0xEC, 0x2E, 0x22, 0x56, 0x37, 0xBB, 0xF2, ++ 0x37, 0xEA, 0x2F, 0x2F, 0x77, 0xA7, 0x38, 0x20, ++ 0x20, 0x6B, 0x20, 0x20, 0x5B, 0x2C, 0xD9, 0x2C, ++ 0xDA, 0x85, 0xAF, 0xD9, 0x85, 0xDA, 0x85, 0x85, ++ 0xAF, 0x2C, 0xDA, 0xDA, 0x2C, 0x7D, 0xA1, 0x48, ++ 0xB2, 0x21, 0xD6, 0xD9, 0x2C, 0xDA, 0x85, 0xAF, ++ 0x2C, 0x2D, 0x48, 0x7D, 0xAF, 0x2C, 0x85, 0x2C, ++ 0xD9, 0xAC, 0xAF, 0x85, 0x85, 0x2C, 0x2C, 0x2C, ++ 0x85, 0x2C, 0xD9, 0xD6, 0xA1, 0xA1, 0x48, 0xA1, ++ 0x21, 0x2C, 0xDA, 0xDA, 0x2C, 0x85, 0x41, 0x98, ++ 0xA2, 0xA7, 0x6F, 0xC9, 0x37, 0xF2, 0xF2, 0x9B, ++ 0xB7, 0x66, 0x60, 0x4C, 0xED, 0x84, 0x3C, 0x20, ++ 0x5B, 0x2D, 0x2B, 0x6B, 0x20, 0xAF, 0xAF, 0x2C, ++ 0x85, 0x2C, 0xD9, 0xAC, 0xAF, 0x85, 0x85, 0x2C, ++ 0x2C, 0x2C, 0x2C, 0x85, 0xD9, 0xD6, 0xA1, 0xA1, ++ 0x48, 0xA1, 0xD6, 0xAF, 0xDA, 0x8A, 0x2C, 0xD9, ++ 0xB2, 0x2D, 0x48, 0x95, 0x2C, 0x2C, 0x2C, 0x85, ++ 0xAC, 0xAC, 0xAF, 0x85, 0xDA, 0x85, 0xAF, 0xAC, ++ 0xAF, 0x2C, 0xD9, 0xD6, 0xD6, 0xD6, 0x21, 0xD6, ++ 0xD9, 0xDA, 0x8D, 0xDA, 0xAF, 0x2C, 0x20, 0x88, ++ 0x42, 0x51, 0x3F, 0x2F, 0x45, 0xB7, 0x66, 0x55, ++ 0x46, 0x60, 0x5D, 0x36, 0xD8, 0x71, 0x43, 0x20, ++ 0x20, 0x2D, 0xB2, 0x80, 0x20, 0x2D, 0x2C, 0x2C, ++ 0x2C, 0x85, 0xAC, 0xAC, 0xAF, 0x85, 0xDA, 0x85, ++ 0xAF, 0xAC, 0xAC, 0xAF, 0xD9, 0xD6, 0xD6, 0xD6, ++ 0x21, 0xD6, 0xD9, 0xDA, 0x8D, 0x8A, 0x2C, 0xD9, ++ 0xB2, 0x48, 0xD6, 0xAC, 0xAF, 0x2C, 0x2C, 0x85, ++ 0x2C, 0xAC, 0x2C, 0xDA, 0xDA, 0x85, 0xAF, 0xD9, ++ 0xD9, 0xAC, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xAC, ++ 0x85, 0x8D, 0xBC, 0xDA, 0xD9, 0xDA, 0x20, 0xE3, ++ 0xDA, 0x69, 0x96, 0xB5, 0xF1, 0x68, 0x5D, 0x82, ++ 0xE1, 0xBE, 0x27, 0x8D, 0x4D, 0xD3, 0x7D, 0x20, ++ 0x20, 0xDB, 0xA1, 0xCA, 0x20, 0x88, 0x85, 0x2C, ++ 0x2C, 0x85, 0x2C, 0xAC, 0x2C, 0xDA, 0xDA, 0x85, ++ 0xAF, 0xD9, 0xAC, 0xAF, 0xD9, 0xD9, 0xD9, 0xD9, ++ 0xD9, 0xAC, 0xDA, 0x8D, 0xBC, 0xDA, 0xD9, 0x95, ++ 0xD9, 0x95, 0xAC, 0x2C, 0x2C, 0x2C, 0x2C, 0x85, ++ 0x85, 0xAF, 0xAF, 0x85, 0x85, 0x2C, 0x2C, 0xAC, ++ 0xD9, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0x85, ++ 0x8D, 0x2A, 0x2A, 0x85, 0xD9, 0x95, 0x20, 0xDB, ++ 0x8D, 0x8D, 0x99, 0xB0, 0x35, 0xE5, 0x3F, 0x35, ++ 0xB9, 0x50, 0x8A, 0x4D, 0x73, 0xE8, 0xA3, 0xCC, ++ 0x20, 0x20, 0x33, 0x6B, 0x20, 0x20, 0xCC, 0x85, ++ 0x2C, 0x85, 0x85, 0xAF, 0xAF, 0x85, 0x85, 0x85, ++ 0x2C, 0xD9, 0xD9, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C, ++ 0x2C, 0x85, 0x8A, 0x2A, 0x8D, 0x2C, 0xD9, 0xD9, ++ 0xAF, 0xAF, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C, 0x85, ++ 0x2C, 0xAF, 0xAF, 0xAF, 0x2C, 0x2C, 0x2C, 0xAC, ++ 0xD9, 0xAC, 0xAF, 0x2C, 0x85, 0x85, 0xDA, 0xDA, ++ 0x8A, 0x8A, 0x85, 0xD9, 0x2C, 0x2B, 0x20, 0xAE, ++ 0xA3, 0xBC, 0x8D, 0xC8, 0xA9, 0xC7, 0x92, 0x47, ++ 0x8D, 0x8D, 0x7E, 0xE4, 0xE8, 0xE8, 0x5C, 0x2C, ++ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x6B, 0xAF, ++ 0x2C, 0x85, 0x2C, 0xAF, 0xAF, 0xAF, 0x2C, 0x2C, ++ 0x2C, 0xAF, 0xD9, 0xAC, 0x2C, 0x2C, 0x85, 0x85, ++ 0x85, 0xDA, 0x8D, 0x8A, 0x85, 0xAC, 0x95, 0xD9, ++ 0xAC, 0xAC, 0xAC, 0xAC, 0x2C, 0xAF, 0xAF, 0x2C, ++ 0x2C, 0xAF, 0xAF, 0xAC, 0x2C, 0xAF, 0x2C, 0xAF, ++ 0xD9, 0xAC, 0x2C, 0x2C, 0x85, 0x85, 0x85, 0x85, ++ 0x85, 0x2C, 0xD9, 0xD9, 0x2D, 0x6B, 0x41, 0x2A, ++ 0xE8, 0xA3, 0xC8, 0x8D, 0x8A, 0x8A, 0x8A, 0x8D, ++ 0x4D, 0xA3, 0x3D, 0xE8, 0xE8, 0xE8, 0xE8, 0x5C, ++ 0xAE, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0xDB, ++ 0xDA, 0x2C, 0x2C, 0xAF, 0xAF, 0xAC, 0xAC, 0xAF, ++ 0x2C, 0xAC, 0xD9, 0xAC, 0x2C, 0x2C, 0x85, 0x85, ++ 0x85, 0x85, 0x85, 0x2C, 0xD9, 0x95, 0x7D, 0xD9, ++ 0x7D, 0x7D, 0xD9, 0xAC, 0xAC, 0xAF, 0xAF, 0xAF, ++ 0x2C, 0x2C, 0xAC, 0xAC, 0xD9, 0xAC, 0xAC, 0xD9, ++ 0x95, 0xD9, 0xAC, 0xAF, 0xAF, 0xAC, 0xAF, 0xAC, ++ 0xD9, 0x7D, 0x7D, 0x7D, 0x33, 0x41, 0x2D, 0xE8, ++ 0xE8, 0x5C, 0xD3, 0x8D, 0x8D, 0x8D, 0x8D, 0x7E, ++ 0x3D, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, ++ 0xDA, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, ++ 0x81, 0x2C, 0x2C, 0x2C, 0xAC, 0xAC, 0xAC, 0xAC, ++ 0xAC, 0xD9, 0x95, 0x95, 0xAC, 0xAF, 0xAF, 0xAF, ++ 0xAF, 0xAC, 0xD9, 0x95, 0x7D, 0xD6, 0xD6, 0x7D, ++ 0x21, 0xD6, 0x95, 0xD9, 0xD9, 0xAC, 0xAF, 0xAF, ++ 0x2C, 0xAF, 0xAC, 0xAC, 0xD9, 0xD9, 0xD9, 0xD9, ++ 0x21, 0x21, 0x7D, 0x95, 0x95, 0x7D, 0xD6, 0x21, ++ 0xB2, 0xA1, 0x2C, 0x88, 0x20, 0xE3, 0xA3, 0xE8, ++ 0xE8, 0xE8, 0xE4, 0xEE, 0xD3, 0x7E, 0x73, 0x5C, ++ 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, ++ 0x5C, 0x2B, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, ++ 0x20, 0x2C, 0xAF, 0xAF, 0xAC, 0xD9, 0xD9, 0xD9, ++ 0xD9, 0xD9, 0xD6, 0x21, 0x7D, 0x95, 0x95, 0x7D, ++ 0xD6, 0xB2, 0xA1, 0xA1, 0xB2, 0xD6, 0x21, 0x21, ++ 0x21, 0xD9, 0xD9, 0xD9, 0xAC, 0xAF, 0xAC, 0xAF, ++ 0x2C, 0x2C, 0xAC, 0xD9, 0xD9, 0xD9, 0xD9, 0x95, ++ 0x7D, 0xB2, 0xD6, 0x95, 0xD9, 0x95, 0xD6, 0xA1, ++ 0xA1, 0xAF, 0x5B, 0x20, 0x20, 0xD6, 0xE8, 0xE8, ++ 0xE8, 0xE8, 0xE8, 0xE8, 0x5C, 0xE8, 0xE8, 0xE8, ++ 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, ++ 0xE8, 0x48, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, ++ 0x20, 0xE3, 0x8A, 0x2C, 0xAC, 0xAC, 0xD9, 0xD9, ++ 0xD9, 0x95, 0xD6, 0xB2, 0xD6, 0x95, 0xD9, 0x95, ++ 0x21, 0xB2, 0xA1, 0xB2, 0xD6, 0xD6, 0xD6, 0xA1, ++ 0xD9, 0x2C, 0x2C, 0x2C, 0xAF, 0xAF, 0xAC, 0xAF, ++ 0x2C, 0x2C, 0xAF, 0xAC, 0xD9, 0xAC, 0xD9, 0xD9, ++ 0xD9, 0x95, 0xAC, 0x2C, 0x2C, 0xAC, 0x95, 0x7D, ++ 0xD9, 0x91, 0x20, 0x20, 0xE3, 0xA3, 0xE8, 0xE8, ++ 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, ++ 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, ++ 0xE8, 0x85, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, ++ 0x20, 0x20, 0x2B, 0x8A, 0xAF, 0xAC, 0xD9, 0xAC, ++ 0xD9, 0xD9, 0xD9, 0x95, 0xAC, 0x2C, 0x2C, 0xAC, ++ 0x95, 0x7D, 0x95, 0x95, 0xD9, 0x95, 0x7D, 0x21, ++ 0x2C, 0xDA, 0xDA, 0x85, 0x2C, 0xAF, 0xAF, 0xAF, ++ 0xAF, 0xAF, 0x2C, 0xAF, 0xAF, 0xAC, 0xAC, 0xAC, ++ 0xD9, 0xAF, 0x85, 0x85, 0x2C, 0xAF, 0xD9, 0xAF, ++ 0x48, 0x20, 0x20, 0x20, 0xE6, 0xA3, 0xE8, 0xE8, ++ 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, ++ 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0x5C, ++ 0xE4, 0x73, 0x41, 0x20, 0x20, 0x20, 0x20, 0x20, ++ 0x20, 0x20, 0x20, 0x2B, 0xDA, 0xAF, 0xAF, 0xAC, ++ 0xAC, 0xAF, 0xD9, 0x2C, 0x85, 0x85, 0x2C, 0xAF, ++ 0xD9, 0xD9, 0xAC, 0xAF, 0xAC, 0xD9, 0xD9, 0xD9, ++ 0x85, 0xDA, 0xDA, 0x85, 0x2C, 0x2C, 0xAC, 0xAF, ++ 0xAF, 0xAF, 0xAF, 0x2C, 0xAF, 0xAF, 0xAC, 0xAC, ++ 0xAF, 0x2C, 0x2C, 0x2C, 0xAC, 0x95, 0x95, 0xA1, ++ 0x20, 0x20, 0x20, 0x20, 0xE9, 0x8C, 0x5C, 0xE8, ++ 0xE8, 0xE8, 0xE8, 0x3D, 0x73, 0x73, 0xE8, 0xE8, ++ 0xE8, 0xE8, 0xE8, 0xE4, 0x73, 0x73, 0x73, 0xCD, ++ 0x7E, 0xA3, 0x74, 0x20, 0x20, 0x20, 0x20, 0x20, ++ 0x20, 0x20, 0x20, 0x20, 0x24, 0x85, 0xAF, 0xAF, ++ 0xAC, 0xAC, 0xAC, 0xAF, 0x85, 0x2C, 0xAC, 0x95, ++ 0x95, 0xD9, 0xAC, 0xAC, 0xAC, 0xD9, 0xAC, 0xAF, ++ 0x8A, 0x8A, 0xDA, 0xDA, 0x85, 0x2C, 0x2C, 0x2C, ++ 0x2C, 0x2C, 0x2C, 0xAF, 0xAF, 0xAC, 0xAF, 0xAC, ++ 0xAC, 0xAF, 0xAF, 0xD9, 0xD6, 0xD6, 0x2C, 0x88, ++ 0x20, 0x20, 0x20, 0x88, 0xB2, 0xDA, 0x7E, 0x73, ++ 0xE8, 0xE8, 0xE8, 0x3D, 0x73, 0xE8, 0xE8, 0xE8, ++ 0xE8, 0xE8, 0xE8, 0xA3, 0xCD, 0xD3, 0x2A, 0x2A, ++ 0x2A, 0x8C, 0x8D, 0x88, 0x20, 0xE3, 0x6B, 0x20, ++ 0x20, 0x20, 0x20, 0x20, 0x41, 0x85, 0xAF, 0xAC, ++ 0xAC, 0xAC, 0xAC, 0xAF, 0xAC, 0xD9, 0x7D, 0xD6, ++ 0x7D, 0x7D, 0xD9, 0x95, 0xD9, 0xAC, 0xAC, 0xAF, ++ 0xD3, 0x8D, 0xDA, 0xDA, 0x85, 0x85, 0x2C, 0x2C, ++ 0x2C, 0xAF, 0xAF, 0xAC, 0xD9, 0xD9, 0xD9, 0xD9, ++ 0xAF, 0xAF, 0xAC, 0xD9, 0x95, 0x7D, 0xAC, 0x20, ++ 0x20, 0x20, 0x20, 0xDB, 0x2C, 0xA3, 0x5C, 0xE8, ++ 0xE8, 0xE8, 0xE8, 0x5C, 0x3D, 0x3D, 0xE8, 0xE8, ++ 0xE8, 0xE4, 0xE8, 0xE8, 0xE8, 0xE4, 0x73, 0xEE, ++ 0xD3, 0x2A, 0xEE, 0xAC, 0x20, 0x33, 0x2B, 0xE3, ++ 0x20, 0x20, 0x20, 0x20, 0x20, 0x9F, 0xAF, 0xD9, ++ 0xD9, 0xAC, 0xAF, 0xAF, 0xAC, 0xD9, 0x95, 0x7D, ++ 0xD9, 0x95, 0x95, 0x95, 0x95, 0xD9, 0xAF, 0xAF, ++ 0x7E, 0x85, 0x85, 0x2C, 0x85, 0x85, 0x85, 0x2C, ++ 0x2C, 0x2C, 0xAF, 0xD9, 0xD9, 0x95, 0xD9, 0xAC, ++ 0xAC, 0xAF, 0xAF, 0xAC, 0xAC, 0xAC, 0x91, 0x20, ++ 0x33, 0xE3, 0x41, 0x48, 0x73, 0x5C, 0xE8, 0xE8, ++ 0xE8, 0xE8, 0xE8, 0xA3, 0xD6, 0x6C, 0x85, 0xE8, ++ 0xDA, 0xAE, 0xB2, 0xA3, 0x5C, 0xE8, 0xE8, 0xE8, ++ 0x3D, 0xEE, 0x4D, 0xA3, 0x24, 0x20, 0x6B, 0xDB, ++ 0x2B, 0x20, 0x20, 0x20, 0x20, 0x20, 0x85, 0x95, ++ 0xD9, 0xD9, 0xAC, 0xAF, 0xAF, 0xAC, 0xD9, 0xAC, ++ 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xAC, 0xD9, 0xAC, ++ 0x8A, 0xD9, 0xAC, 0xD9, 0xAC, 0xAC, 0x2C, 0x2C, ++ 0xAF, 0xAF, 0xAF, 0xAC, 0xD9, 0xD9, 0xD9, 0xD9, ++ 0xAF, 0xAF, 0xAF, 0xAC, 0xAC, 0x85, 0x33, 0x20, ++ 0xCC, 0x20, 0xE3, 0xA3, 0xE8, 0xE8, 0xE8, 0xE8, ++ 0xE8, 0xA3, 0xD9, 0x81, 0xAC, 0xDA, 0x2D, 0x5C, ++ 0x48, 0x41, 0x88, 0x74, 0x21, 0xA3, 0xE8, 0xE8, ++ 0xE8, 0xE8, 0x73, 0x8C, 0x8A, 0x20, 0x20, 0x20, ++ 0xDB, 0x33, 0x20, 0x20, 0x20, 0x20, 0xE6, 0xD9, ++ 0xD9, 0xAC, 0xAC, 0xAF, 0xAC, 0xAF, 0xAC, 0xAF, ++ 0xAF, 0xAC, 0xD9, 0xAF, 0xD9, 0xAC, 0xAC, 0xAF, ++ 0x85, 0xD9, 0x95, 0xD9, 0x95, 0xD9, 0xD9, 0xAC, ++ 0xAF, 0xAC, 0xAF, 0xAF, 0x2C, 0xAF, 0x2C, 0x2C, ++ 0xAF, 0xAF, 0xAF, 0xAC, 0xAC, 0x2C, 0x20, 0x5B, ++ 0x33, 0x20, 0xD6, 0xE8, 0xE8, 0xE8, 0xE8, 0x73, ++ 0xAF, 0x2D, 0xD9, 0xDA, 0xB2, 0x81, 0x81, 0xE4, ++ 0xA1, 0x91, 0x2B, 0x88, 0x33, 0x80, 0xAF, 0x73, ++ 0xE8, 0xE8, 0xE8, 0x5C, 0xA3, 0x80, 0x41, 0xCC, ++ 0x2B, 0xCC, 0x20, 0x20, 0x20, 0x20, 0x88, 0xDA, ++ 0x2C, 0x2C, 0x2C, 0xAF, 0xAF, 0xAC, 0xAC, 0xAF, ++ 0xAF, 0xAF, 0xAF, 0xAC, 0xAF, 0xAF, 0xAF, 0x2C, ++ 0x85, 0xD9, 0xD9, 0xD9, 0xD9, 0xAC, 0xAC, 0xD9, ++ 0xD9, 0xD9, 0xAC, 0x2C, 0x2C, 0x2C, 0x85, 0x85, ++ 0x85, 0x2C, 0x2C, 0xAF, 0x2C, 0x91, 0x20, 0xAE, ++ 0x20, 0xDB, 0x3D, 0xE8, 0xE8, 0x5C, 0xB2, 0x80, ++ 0xB2, 0xAF, 0x48, 0xB2, 0x48, 0x89, 0x89, 0x3D, ++ 0x21, 0x48, 0x6C, 0x2D, 0x2B, 0x41, 0xE3, 0xAE, ++ 0xD9, 0x5C, 0xE8, 0xE8, 0xE8, 0x95, 0x33, 0x80, ++ 0xAE, 0x33, 0x2B, 0x20, 0x20, 0x20, 0x20, 0x95, ++ 0x85, 0x2C, 0x85, 0x2C, 0x2C, 0xAF, 0x2C, 0x2C, ++ 0x2C, 0xAF, 0xAC, 0xAF, 0xAF, 0x2C, 0x2C, 0x2C, ++ 0xDA, 0xAF, 0xD9, 0xD9, 0xAF, 0x2C, 0x2C, 0x2C, ++ 0xAC, 0xD9, 0xAC, 0xAF, 0x2C, 0x85, 0x2C, 0x85, ++ 0x85, 0x2C, 0x2C, 0x2C, 0x8A, 0x41, 0xDB, 0x33, ++ 0x20, 0x95, 0xE8, 0xE8, 0xE8, 0xA3, 0xDB, 0x88, ++ 0xDB, 0x80, 0xD6, 0x7E, 0x85, 0x2D, 0xE6, 0x5C, ++ 0x21, 0x48, 0xD9, 0x7E, 0xD6, 0x2B, 0xCC, 0xAC, ++ 0x85, 0xBC, 0xE8, 0xE8, 0xE8, 0xCD, 0x88, 0x5B, ++ 0x41, 0x20, 0xAE, 0x20, 0x20, 0x20, 0x20, 0x74, ++ 0xDA, 0x85, 0x85, 0x85, 0x2C, 0x2C, 0x2C, 0x2C, ++ 0xAF, 0xAC, 0xD9, 0xD9, 0xAC, 0xAC, 0xAC, 0xD9, ++ 0x8A, 0xAF, 0xAC, 0xAC, 0x2C, 0x85, 0x2C, 0xAF, ++ 0xD9, 0xD9, 0xAF, 0xAF, 0xAF, 0x2C, 0xAF, 0x2C, ++ 0x2C, 0x2C, 0x2C, 0xAF, 0x95, 0x20, 0x74, 0x20, ++ 0x33, 0xA3, 0xE8, 0xE8, 0xE8, 0xE4, 0x7D, 0xCC, ++ 0x6B, 0x33, 0xAE, 0x2C, 0x85, 0x2D, 0x9F, 0x73, ++ 0xA1, 0x2D, 0x2C, 0xDA, 0x89, 0x48, 0xD3, 0xD9, ++ 0x21, 0xA3, 0xE8, 0xE8, 0xE8, 0xE8, 0xE3, 0x20, ++ 0x20, 0x20, 0xDB, 0x41, 0x20, 0x20, 0x20, 0x20, ++ 0xDA, 0x2C, 0x2C, 0x2C, 0x2C, 0xAF, 0xAC, 0xAC, ++ 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0x95, 0x95, 0xD9, ++ 0x2C, 0xD9, 0xD9, 0xAC, 0x2C, 0x2C, 0x85, 0xAF, ++ 0xAF, 0xAF, 0xAC, 0xAC, 0xD9, 0xAC, 0xAF, 0xAC, ++ 0xAC, 0x95, 0xD6, 0x7D, 0xAE, 0x88, 0x2B, 0x20, ++ 0x6C, 0xE8, 0xE8, 0xE8, 0x73, 0xEE, 0x73, 0x2C, ++ 0x89, 0x2B, 0x41, 0x33, 0xCC, 0xCC, 0x80, 0x3D, ++ 0x2D, 0x74, 0x80, 0x48, 0x8D, 0x95, 0x48, 0x95, ++ 0xEE, 0x5C, 0x5C, 0xE8, 0xE8, 0xE8, 0x24, 0x20, ++ 0x20, 0x20, 0x5B, 0xDB, 0x20, 0x20, 0x20, 0x20, ++ 0xAF, 0xAC, 0xD9, 0x95, 0xD6, 0xD6, 0xD6, 0x7D, ++ 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0xD9, 0xAC, ++ 0xAC, 0xD9, 0xD9, 0xAC, 0x2C, 0x2C, 0x2C, 0xAF, ++ 0xAC, 0xAC, 0xAC, 0xAC, 0xD9, 0xAC, 0xAC, 0xD9, ++ 0xD6, 0x48, 0xE9, 0x95, 0x20, 0x2B, 0x41, 0x6B, ++ 0x8D, 0xE8, 0xE8, 0xCD, 0x2B, 0x2B, 0x2C, 0x73, ++ 0xCD, 0x48, 0xCA, 0x5B, 0x41, 0x5B, 0x74, 0xDA, ++ 0x80, 0xE6, 0xC8, 0x85, 0xA1, 0x7D, 0x8D, 0x3D, ++ 0x7E, 0xE9, 0x7D, 0xEE, 0xE8, 0xE8, 0x81, 0x20, ++ 0x20, 0x20, 0xE3, 0xE3, 0x20, 0x20, 0x20, 0x20, ++ 0x2D, 0xD9, 0xD6, 0x48, 0x6C, 0xE9, 0xA1, 0xD6, ++ 0xD9, 0xD9, 0xAC, 0xD9, 0xD9, 0x95, 0xAC, 0x2C, ++ 0x2C, 0x2C, 0x2C, 0xD9, 0xAC, 0x2C, 0x2C, 0x2C, ++ 0xAF, 0x2C, 0xAF, 0xD9, 0xAC, 0xAF, 0xAF, 0x95, ++ 0xB2, 0xE9, 0x21, 0x2B, 0x41, 0x2B, 0x20, 0x5B, ++ 0x3D, 0xE8, 0xE8, 0x8D, 0x2B, 0x88, 0x5B, 0xE6, ++ 0xBC, 0x73, 0x85, 0x89, 0x80, 0x5B, 0xE3, 0xAE, ++ 0x2C, 0x8A, 0xD6, 0xB2, 0x2C, 0xA3, 0xA3, 0xD9, ++ 0xA1, 0x2C, 0x85, 0x8D, 0xE8, 0xE8, 0x48, 0x20, ++ 0x20, 0x20, 0xE3, 0x88, 0x20, 0x20, 0x20, 0x20, ++ 0xAE, 0xD9, 0xB2, 0xE9, 0x6C, 0x48, 0xD6, 0xD9, ++ 0x2C, 0x85, 0x2C, 0xD9, 0x7D, 0xD9, 0x2C, 0x85, ++ 0x8D, 0x85, 0x2C, 0xAC, 0xAF, 0x2C, 0x2C, 0x85, ++ 0x2C, 0x2C, 0xAF, 0xAC, 0xAC, 0xAF, 0xAF, 0xD9, ++ 0xB2, 0x48, 0xB2, 0x20, 0x20, 0xCC, 0x20, 0x9F, ++ 0xE8, 0xE8, 0xE8, 0xCD, 0x48, 0x89, 0xDB, 0x88, ++ 0x2B, 0xE9, 0xCD, 0x2A, 0x48, 0x80, 0xAE, 0xAE, ++ 0x7D, 0x48, 0x21, 0xEE, 0x3D, 0x2C, 0x48, 0x85, ++ 0x2C, 0x95, 0x7D, 0x8C, 0xE8, 0xE8, 0xB2, 0x20, ++ 0x20, 0x20, 0xDB, 0x20, 0x20, 0x20, 0x20, 0x20, ++ 0xDB, 0x2C, 0xB2, 0x48, 0x48, 0x7D, 0xD9, 0xAF, ++ 0x85, 0x8A, 0x85, 0x7D, 0xB2, 0x95, 0x85, 0xDA, ++ 0xD3, 0x85, 0xAF, 0xAC, 0x2C, 0x85, 0x85, 0x2C, ++ 0xAC, 0xAC, 0xAC, 0xD9, 0xD9, 0xAC, 0x2C, 0x2C, ++ 0xD9, 0xAC, 0x5B, 0x20, 0x20, 0xAE, 0x20, 0x2D, ++ 0xE8, 0xE8, 0xE8, 0x7E, 0xD6, 0x48, 0xE9, 0xAE, ++ 0x88, 0x5B, 0x80, 0x6C, 0xAE, 0xCA, 0x91, 0xE9, ++ 0x43, 0x9F, 0xE6, 0x2C, 0x48, 0x21, 0xBC, 0x95, ++ 0x95, 0xD6, 0x21, 0x7E, 0xE8, 0xE8, 0x7D, 0x20, ++ 0x20, 0x20, 0x2B, 0x20, 0x20, 0x20, 0x20, 0x20, ++ 0x6B, 0xDA, 0xD9, 0x48, 0xB2, 0xD9, 0x2C, 0x85, ++ 0xDA, 0xDA, 0x2C, 0xA1, 0x48, 0xAC, 0xDA, 0x8D, ++ 0x2A, 0xAC, 0x7D, 0x95, 0xAF, 0x85, 0x2C, 0x2C, ++ 0xAC, 0xD9, 0x95, 0x7D, 0x95, 0xAC, 0x2C, 0xAF, ++ 0x7D, 0xD6, 0x20, 0x20, 0x88, 0x9F, 0x20, 0xA1, ++ 0xE8, 0xE8, 0xE8, 0xA3, 0xD6, 0x6C, 0xB2, 0x2C, ++ 0x89, 0xE3, 0x88, 0xDB, 0xCC, 0x24, 0x7D, 0xEE, ++ 0xB2, 0xCC, 0xAE, 0x2D, 0xDA, 0x2C, 0xD6, 0x2C, ++ 0xB2, 0x2D, 0xD6, 0xEE, 0xE8, 0xE8, 0x95, 0x20, ++ 0x20, 0x20, 0xDB, 0x20, 0x20, 0x20, 0x20, 0x20, ++ 0x6B, 0xDA, 0x95, 0xA1, 0xB2, 0xAC, 0x85, 0x85, ++ 0xDA, 0x2C, 0x95, 0xA1, 0x21, 0x2C, 0x8A, 0x2A, ++ 0xAF, 0xA1, 0x48, 0xD6, 0xAF, 0x2C, 0x2C, 0xAC, ++ 0xD9, 0xD9, 0x95, 0x7D, 0x95, 0xAC, 0xD9, 0x7D, ++ 0x48, 0xE6, 0x20, 0x20, 0x33, 0x89, 0x6B, 0x95, ++ 0xE8, 0xE8, 0xE8, 0xA3, 0x21, 0x48, 0xAF, 0xAF, ++ 0x9F, 0xE9, 0x43, 0x33, 0x33, 0x2D, 0xDA, 0xCD, ++ 0xD6, 0xAE, 0x85, 0x2C, 0x7D, 0xD6, 0x91, 0xB8, ++ 0xD4, 0x48, 0x7D, 0xA3, 0xE8, 0xE8, 0x95, 0x20, ++ 0x20, 0x33, 0xE3, 0x20, 0x20, 0x20, 0x20, 0x20, ++ 0x20, 0x2C, 0x48, 0x6C, 0xB2, 0xAF, 0xDA, 0xDA, ++ 0x85, 0xAF, 0xD9, 0x95, 0xAC, 0xDA, 0x8A, 0xDA, ++ 0x7D, 0x48, 0x48, 0x7D, 0x2C, 0x85, 0x2C, 0xAF, ++ 0xD9, 0xD9, 0x7D, 0x95, 0xD9, 0xD9, 0x95, 0xD6, ++ 0x21, 0x24, 0x20, 0x20, 0x20, 0x5B, 0xDB, 0xAC, ++ 0xE8, 0xE8, 0xE8, 0x3D, 0x7D, 0x48, 0xE6, 0x2D, ++ 0x85, 0x81, 0x81, 0x48, 0xAE, 0xCA, 0x89, 0xCC, ++ 0xAE, 0xDB, 0x2D, 0x95, 0x21, 0xCC, 0xDB, 0xAE, ++ 0x91, 0xE9, 0x7D, 0x73, 0xE8, 0xE8, 0x48, 0x20, ++ 0x6B, 0x74, 0x41, 0x88, 0x6B, 0x20, 0x20, 0x20, ++ 0x6B, 0x95, 0xB2, 0xD6, 0xD9, 0x85, 0xDA, 0xDA, ++ 0xDA, 0x2C, 0xAF, 0xAF, 0x2C, 0xDA, 0xDA, 0x85, ++ 0xA1, 0xE9, 0x48, 0x95, 0x85, 0xDA, 0x85, 0xAC, ++ 0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9, 0xD9, 0x95, ++ 0x95, 0x6C, 0x41, 0x93, 0x93, 0x41, 0xDB, 0x95, ++ 0xE8, 0xE8, 0xE8, 0x3D, 0x95, 0xD4, 0x6C, 0x21, ++ 0x2D, 0x95, 0xCD, 0x2C, 0xD6, 0xD9, 0x6C, 0x91, ++ 0x89, 0x7D, 0xAC, 0x2A, 0x8D, 0xE6, 0xCC, 0x88, ++ 0x74, 0x48, 0xD9, 0xE4, 0xE8, 0xE8, 0xE6, 0x88, ++ 0x2B, 0x88, 0x20, 0x33, 0xDB, 0x2B, 0xDB, 0x20, ++ 0x91, 0x7D, 0xD9, 0xD9, 0x85, 0x85, 0xDA, 0xDA, ++ 0x85, 0xAF, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C, ++ 0xA1, 0xA1, 0xD6, 0xAF, 0x85, 0xDA, 0x85, 0x2C, ++ 0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xD9, 0xD9, 0xAC, ++ 0x2C, 0x47, 0x87, 0x3E, 0x3E, 0xA4, 0x7B, 0x80, ++ 0xA3, 0xE8, 0xE8, 0x5C, 0x7D, 0x48, 0xE6, 0xD9, ++ 0xBC, 0xEE, 0x7D, 0x43, 0xD6, 0x21, 0x43, 0x6C, ++ 0x43, 0x7D, 0x7D, 0xB2, 0x8A, 0xEE, 0x2C, 0xCA, ++ 0xAE, 0x48, 0x2C, 0xE4, 0xE8, 0x5C, 0xCC, 0x88, ++ 0x20, 0x20, 0x20, 0x20, 0x20, 0x41, 0x91, 0xE3, ++ 0x21, 0xD9, 0x2C, 0x2C, 0xDA, 0xDA, 0xDA, 0x85, ++ 0x2C, 0xAC, 0xD9, 0xD9, 0xAC, 0xAF, 0xAF, 0xAF, ++ 0xD6, 0x7D, 0xD9, 0x2C, 0xDA, 0xDA, 0x85, 0xAC, ++ 0xD9, 0x7D, 0x7D, 0xD9, 0xD9, 0xD9, 0x2C, 0x2C, ++ 0xB8, 0x9C, 0xEC, 0x62, 0x6F, 0x62, 0x70, 0x3C, ++ 0xAE, 0xCD, 0xE8, 0xE8, 0x8C, 0x7D, 0xC8, 0x3D, ++ 0x8A, 0xE9, 0x2D, 0x9E, 0xA1, 0xD6, 0x48, 0x73, ++ 0x81, 0xD6, 0xD6, 0xAE, 0x5B, 0x2D, 0xA3, 0xA3, ++ 0x21, 0x21, 0xCD, 0xE8, 0xC0, 0x56, 0x31, 0x20, ++ 0x20, 0x20, 0x20, 0x20, 0x20, 0x33, 0xCC, 0xDB, ++ 0x42, 0x85, 0x85, 0x85, 0x85, 0x85, 0x2C, 0x2C, ++ 0xAC, 0xD9, 0xD9, 0xD9, 0xAC, 0xAF, 0xAF, 0xAF, ++ 0xD9, 0x95, 0xAC, 0x2C, 0x85, 0x85, 0x2C, 0xD9, ++ 0x7D, 0xD6, 0xD6, 0xD9, 0xAC, 0xAF, 0x8A, 0xBC, ++ 0xC2, 0x68, 0x2E, 0x4B, 0xC9, 0x8B, 0x62, 0x87, ++ 0x3C, 0x74, 0xBC, 0xE8, 0xE8, 0xE4, 0xEE, 0xA1, ++ 0xE9, 0x21, 0xE6, 0x89, 0x48, 0x7D, 0xB2, 0x5C, ++ 0x6C, 0x7D, 0x21, 0x80, 0xE3, 0x33, 0xCC, 0x2C, ++ 0x3D, 0x3D, 0xE8, 0xE8, 0xEC, 0xCB, 0x5A, 0x6B, ++ 0x20, 0x20, 0x20, 0x20, 0x20, 0x88, 0x41, 0x51, ++ 0x49, 0x28, 0x85, 0x85, 0x85, 0x85, 0x2C, 0xAF, ++ 0xAC, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, ++ 0xD9, 0x95, 0xD9, 0x2C, 0x85, 0x85, 0x2C, 0xD9, ++ 0xB2, 0xB2, 0x2C, 0x2A, 0x79, 0x79, 0x97, 0x44, ++ 0xED, 0x29, 0x32, 0x62, 0x4B, 0x62, 0x6F, 0x22, ++ 0xF3, 0x6B, 0x33, 0x85, 0x73, 0xE4, 0x2D, 0x2B, ++ 0xCC, 0x9F, 0xDA, 0xBC, 0x48, 0xD6, 0xA1, 0xE4, ++ 0xE9, 0xD6, 0xD9, 0x2A, 0xB2, 0x2B, 0x2B, 0xA1, ++ 0xB8, 0xE8, 0xE8, 0xE8, 0xEC, 0x3E, 0x30, 0x20, ++ 0x20, 0x20, 0x20, 0x20, 0x20, 0x6B, 0x54, 0xDC, ++ 0xC9, 0x53, 0xBC, 0x2C, 0x2C, 0x2C, 0xAF, 0xAF, ++ 0xAF, 0xAC, 0xAF, 0xAC, 0xAC, 0x2C, 0xAF, 0xAC, ++ 0x2C, 0x7D, 0xD9, 0x2C, 0x85, 0xDA, 0xAF, 0x7D, ++ 0xB2, 0xAC, 0xC6, 0xBA, 0x4C, 0xEF, 0xA7, 0xEF, ++ 0xEC, 0x7A, 0x62, 0x4B, 0x62, 0x4B, 0x8B, 0x4B, ++ 0x3A, 0x52, 0x20, 0x6B, 0x21, 0x73, 0xAC, 0x2B, ++ 0x41, 0x33, 0x48, 0x67, 0xA1, 0xD6, 0xD6, 0x5C, ++ 0xE9, 0xD6, 0x2C, 0xEE, 0xB2, 0x9F, 0x8A, 0x95, ++ 0x4D, 0xE8, 0xE8, 0x3D, 0x7A, 0x57, 0xD1, 0x7B, ++ 0x20, 0x20, 0x20, 0x20, 0x6B, 0xCF, 0xBA, 0x3E, ++ 0x3E, 0xD0, 0xBC, 0xAC, 0xAC, 0x2C, 0x2C, 0xAC, ++ 0xD9, 0xD9, 0x95, 0x95, 0x7D, 0x95, 0x95, 0xD9, ++ 0x85, 0xD9, 0xAF, 0xDA, 0xDA, 0x85, 0xAC, 0x21, ++ 0xB2, 0x2A, 0xBA, 0x57, 0x2E, 0x2E, 0x2E, 0x7A, ++ 0x32, 0x62, 0x8B, 0x4B, 0x8B, 0x4B, 0x4B, 0x4B, ++ 0xC9, 0x4A, 0x5F, 0x20, 0x20, 0x2D, 0xA3, 0xD9, ++ 0xCA, 0x88, 0xDB, 0x24, 0x48, 0x7D, 0xB2, 0xE4, ++ 0x2D, 0x7D, 0x7D, 0x81, 0xA1, 0xDA, 0x21, 0xDA, ++ 0xE4, 0xE8, 0xEE, 0xF1, 0x2E, 0x57, 0x82, 0x76, ++ 0x52, 0x4F, 0x4F, 0x98, 0xDE, 0xB5, 0xEC, 0x2E, ++ 0x3E, 0x6D, 0x85, 0x2C, 0xAC, 0xAC, 0xD9, 0xD9, ++ 0x95, 0xD6, 0x7D, 0x7D, 0x95, 0xD9, 0xD9, 0xD9, ++ 0xDA, 0x2C, 0x85, 0xDA, 0xDA, 0x2C, 0x95, 0xB2, ++ 0x21, 0xB8, 0xED, 0x2E, 0x3E, 0x4B, 0xC9, 0x4B, ++ 0x8B, 0x62, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, ++ 0x22, 0x6F, 0xCE, 0x20, 0x20, 0x20, 0x80, 0xCD, ++ 0xDA, 0x2D, 0x2B, 0xDB, 0xE9, 0xD6, 0x95, 0x5C, ++ 0x2D, 0x7D, 0x7D, 0xAF, 0xAF, 0xAC, 0xEE, 0x5C, ++ 0xE8, 0xE8, 0xEB, 0x25, 0x7A, 0x57, 0x39, 0xE1, ++ 0x83, 0xA8, 0x55, 0x83, 0x82, 0x57, 0x32, 0x8B, ++ 0x62, 0x6D, 0xEB, 0x95, 0xD9, 0xD9, 0xD9, 0xD9, ++ 0xD9, 0xD9, 0xD9, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C, ++ 0xDA, 0x2C, 0x85, 0x85, 0x85, 0xAC, 0xD6, 0x21, ++ 0x95, 0x6E, 0xED, 0x57, 0x62, 0x4B, 0x8B, 0x4B, ++ 0x4B, 0x62, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x62, ++ 0x62, 0x62, 0x25, 0x3C, 0x20, 0x20, 0x20, 0xE3, ++ 0x2A, 0xBC, 0x7D, 0xCA, 0x6C, 0xD6, 0x95, 0x3D, ++ 0x81, 0x7D, 0xD6, 0xD6, 0xDA, 0x73, 0xE8, 0xE8, ++ 0xE8, 0x4D, 0x94, 0xED, 0x72, 0x3A, 0xF1, 0xA7, ++ 0x39, 0xED, 0x39, 0xEF, 0x57, 0x32, 0x8B, 0x4B, ++ 0x62, 0x62, 0xA6, 0x2A, 0xD9, 0xD9, 0xD9, 0xD9, ++ 0x2C, 0x2C, 0x85, 0x85, 0x85, 0x85, 0x85, 0x85, ++ 0x85, 0x2C, 0x2C, 0xAF, 0xAC, 0x95, 0x21, 0x7D, ++ 0xAC, 0x8C, 0x46, 0xC4, 0x62, 0x8B, 0x4B, 0x4B, ++ 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, ++ 0x4B, 0x62, 0xC9, 0x30, 0x7B, 0x20, 0x20, 0x20, ++ 0x41, 0x4D, 0x3D, 0x85, 0x48, 0x21, 0xDA, 0x3D, ++ 0xE9, 0xD6, 0xD9, 0xCD, 0x5C, 0xE8, 0xE8, 0xE8, ++ 0xE8, 0x4D, 0x71, 0x46, 0xEC, 0x2E, 0x72, 0xEC, ++ 0x29, 0x29, 0x7C, 0x29, 0x2E, 0x4B, 0x4B, 0x62, ++ 0x62, 0x4B, 0x3A, 0xAD, 0xE2, 0xAF, 0xD9, 0xD9, ++ 0x2C, 0xDA, 0xDA, 0xDA, 0xDA, 0x85, 0x2C, 0x2C, ++ 0x2C, 0xAF, 0xAC, 0xD9, 0x95, 0xD6, 0xD6, 0xD9, ++ 0x2C, 0x8C, 0xBA, 0x7C, 0x2E, 0x4B, 0x4B, 0x4B, ++ 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, ++ 0x4B, 0x62, 0xC9, 0xDC, 0x34, 0x20, 0x20, 0x20, ++ 0x20, 0xAC, 0xE8, 0x5C, 0x8C, 0xBC, 0xE4, 0xE8, ++ 0xEE, 0x2A, 0xA3, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, ++ 0xE4, 0x7E, 0x65, 0x46, 0x29, 0x62, 0x62, 0x2E, ++ 0x2E, 0x72, 0x2E, 0x2E, 0x32, 0x4B, 0x4B, 0x62, ++ 0x4B, 0x4B, 0x4B, 0x32, 0x61, 0x9D, 0x2C, 0xD9, ++ 0x2C, 0x85, 0xDA, 0x85, 0x2C, 0xAF, 0xAF, 0xAF, ++ 0x2C, 0xAC, 0xD9, 0x95, 0xD6, 0x7D, 0x95, 0xAC, ++ 0x2C, 0xDA, 0x40, 0x7C, 0x2E, 0x4B, 0x4B, 0x4B, ++ 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, ++ 0x4B, 0x62, 0x62, 0x22, 0xB7, 0xCE, 0x20, 0x20, ++ 0x20, 0x95, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, ++ 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0x5C, ++ 0x3D, 0xE9, 0x9A, 0x46, 0x7C, 0x32, 0x8B, 0x62, ++ 0x4B, 0x8B, 0x8B, 0x4B, 0x4B, 0x4B, 0x4B, 0x62, ++ 0x4B, 0x4B, 0x4B, 0x4B, 0x62, 0x61, 0x4E, 0xDA, ++ 0x85, 0x85, 0x85, 0x2C, 0xD9, 0xD9, 0xD9, 0xD9, ++ 0x85, 0xD9, 0x7D, 0x21, 0x21, 0xD6, 0xAC, 0x2C, ++ 0x2C, 0xDA, 0xDD, 0x77, 0x8B, 0x62, 0x4B, 0x4B, ++ 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, ++ 0x3E, 0x8B, 0x32, 0xC9, 0x22, 0x68, 0x88, 0x33, ++ 0xA1, 0x73, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, ++ 0xE8, 0xE8, 0xE8, 0x5C, 0x5C, 0x5C, 0x5C, 0x3D, ++ 0x89, 0x20, 0x54, 0x23, 0x29, 0x2E, 0x4B, 0x62, ++ 0x4B, 0x3E, 0x4B, 0x62, 0x4B, 0x4B, 0x4B, 0x8B, ++ 0x8B, 0xC9, 0x6F, 0x4B, 0x8B, 0x4B, 0x78, 0xE2, ++ 0x8A, 0x8A, 0x85, 0xAC, 0xD9, 0x7D, 0xD9, 0xAC, ++ 0x2C, 0xD9, 0xD6, 0xB2, 0x21, 0x7D, 0xAF, 0x85, ++ 0x2C, 0xDA, 0x40, 0xEF, 0x62, 0x62, 0x4B, 0x4B, ++ 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, ++ 0x4B, 0x4B, 0x8B, 0x4B, 0xC9, 0x63, 0xB4, 0x5C, ++ 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, ++ 0xE8, 0xE8, 0xE8, 0xE8, 0x5C, 0x5C, 0xCD, 0xAE, ++ 0x20, 0x20, 0xCE, 0xE1, 0x57, 0x32, 0x4B, 0x4B, ++ 0x8B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, ++ 0x8B, 0x4B, 0x62, 0x4B, 0x62, 0x2E, 0x61, 0x28, ++ 0x8D, 0xDA, 0xAF, 0xD9, 0x95, 0x95, 0xD9, 0xAF, ++ 0xAF, 0xD9, 0xD6, 0xB2, 0x21, 0xD9, 0x2C, 0x85, ++ 0xAF, 0xEB, 0xE1, 0x57, 0x2E, 0x62, 0x4B, 0x4B, ++ 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, ++ 0x4B, 0x4B, 0x4B, 0x4B, 0x3E, 0x9B, 0x31, 0x6E, ++ 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, ++ 0x5C, 0xE8, 0xE8, 0xE8, 0x3D, 0x7D, 0x33, 0x6B, ++ 0x20, 0x20, 0x34, 0x23, 0x29, 0x3E, 0x4B, 0x4B, ++ 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, ++ 0x4B, 0x3E, 0x62, 0x62, 0x2E, 0xC4, 0x49, 0xD5, ++ 0xDA, 0xD9, 0xD6, 0xA1, 0xA1, 0x21, 0xD9, 0xD9, ++ 0xD9, 0x95, 0x21, 0x48, 0xD6, 0xAC, 0x85, 0x85, ++ 0xAF, 0xB6, 0x5D, 0x2E, 0x32, 0x4B, 0x4B, 0x4B, ++ 0x4B, 0x4B, 0x62, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, ++ 0x4B, 0x4B, 0x4B, 0x4B, 0x62, 0x2E, 0x45, 0xDE, ++ 0xDA, 0x5C, 0xE8, 0x5C, 0xE8, 0xE8, 0x5C, 0xE8, ++ 0x5C, 0x5C, 0xA3, 0xAC, 0x2B, 0x20, 0x20, 0x20, ++ 0x20, 0x20, 0x34, 0x23, 0x29, 0x62, 0x4B, 0x4B, ++ 0x4B, 0x4B, 0x4B, 0x4B, 0x62, 0x4B, 0x4B, 0x4B, ++ 0x4B, 0x3E, 0x3E, 0x63, 0x40, 0x97, 0x28, 0xDA, ++ 0xD9, 0xA1, 0x48, 0xE9, 0x48, 0x21, 0xD9, 0xD9, ++ 0xA1, 0xB2, 0xB2, 0xA1, 0x21, 0xAC, 0x85, 0x2C, ++ 0xDA, 0x36, 0x77, 0x72, 0x62, 0x8B, 0x62, 0x4B, ++ 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, 0x4B, ++ 0x4B, 0x4B, 0x4B, 0x4B, 0x3E, 0xEC, 0x2F, 0x51, ++ 0xE3, 0xAE, 0x48, 0x2C, 0xDA, 0xDA, 0x85, 0xAC, ++ 0x48, 0x9E, 0x88, 0x20, 0x20, 0x20, 0x20, 0x20, ++ 0x20, 0x41, 0xA0, 0x23, 0x72, 0x2E, 0x4B, 0x4B, ++ 0x4B, 0x62, 0x62, 0x4B, 0x4B, 0x4B, 0x2E, 0x8B, ++ 0xF0, 0x4C, 0x40, 0xC2, 0x90, 0x8D, 0x85, 0xD9, ++ 0xA1, 0x6C, 0x6C, 0x48, 0xD6, 0xD9, 0xAF, 0xAC, ++ 0xA1, 0xD6, 0xD6, 0xB2, 0xD6, 0xAC, 0x85, 0x85, ++ 0x4D, 0xBE, 0x39, 0x4C, 0x57, 0x2E, 0x2E, 0x2E, ++ 0x3E, 0x3E, 0x62, 0x3E, 0x4B, 0x4B, 0x4B, 0x4B, ++ 0x4B, 0x4B, 0x4B, 0x8B, 0x8B, 0x57, 0x60, 0x76, ++ 0x52, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, ++ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, ++ 0x20, 0x3C, 0xA0, 0x23, 0x7C, 0x2E, 0x4B, 0x4B, ++ 0x8B, 0x62, 0x4B, 0x4B, 0x3E, 0x7A, 0xF0, 0x29, ++ 0x36, 0x97, 0xBC, 0x8A, 0x8D, 0xDA, 0xD9, 0x48, ++ 0x81, 0x2D, 0x48, 0xD6, 0xD9, 0xAF, 0x2C, 0x2C, ++ 0xAC, 0xAF, 0xD9, 0x7D, 0x7D, 0x2C, 0x85, 0x85, ++ 0x85, 0xB4, 0x66, 0x23, 0x46, 0x2F, 0x60, 0x68, ++ 0x77, 0x29, 0x29, 0xF0, 0x2E, 0x2E, 0x62, 0x4B, ++ 0x4B, 0x4B, 0x4B, 0x4B, 0x32, 0x7C, 0x83, 0xB3, ++ 0x54, 0x6B, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, ++ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, ++ 0x6B, 0x7B, 0xC3, 0xE7, 0x39, 0x72, 0x62, 0x62, ++ 0x62, 0x62, 0x62, 0x2E, 0x29, 0x77, 0xA7, 0x36, ++ 0xB8, 0x85, 0x85, 0x8D, 0x8D, 0x85, 0xB2, 0x2D, ++ 0x2D, 0xE9, 0xD6, 0xD9, 0xAF, 0x2C, 0x85, 0x85, ++ 0x2A, 0x85, 0xAC, 0x95, 0x95, 0xAF, 0x85, 0x85, ++ 0xAF, 0x8C, 0xDF, 0xC6, 0xB1, 0xD1, 0xE5, 0xE7, ++ 0x83, 0x23, 0x5D, 0x60, 0x39, 0x77, 0xEC, 0x2E, ++ 0x2E, 0x32, 0x32, 0x2E, 0x7C, 0x5D, 0x35, 0xA2, ++ 0x54, 0x6B, 0x6B, 0x20, 0x6B, 0x20, 0x20, 0x20, ++ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, ++ 0x6B, 0x88, 0xC1, 0x35, 0xE1, 0x77, 0x57, 0x2E, ++ 0x2E, 0x72, 0x29, 0x77, 0x60, 0xB5, 0x44, 0xE2, ++ 0x2C, 0x2C, 0xDA, 0x8A, 0xDA, 0xAF, 0xA1, 0x2D, ++ 0xE9, 0xD6, 0xD9, 0xAF, 0x2C, 0x85, 0x85, 0x85, ++ 0xEE, 0xAF, 0xD9, 0x7D, 0xD9, 0x2C, 0xDA, 0x85, ++ 0xAC, 0xAF, 0x85, 0xDA, 0x8A, 0x2A, 0xE2, 0x50, ++ 0x86, 0xD7, 0x75, 0x35, 0xA8, 0xE7, 0xE1, 0x5D, ++ 0x68, 0x7C, 0xF1, 0x68, 0xE1, 0xBF, 0xA2, 0xC1, ++ 0x52, 0x2B, 0x7D, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C, ++ 0x2C, 0x85, 0x85, 0x85, 0x2C, 0x2C, 0x2C, 0x95, ++ 0xE9, 0x74, 0xCE, 0xE0, 0xE7, 0x60, 0x77, 0x77, ++ 0x7C, 0xEF, 0x5D, 0x23, 0x3F, 0xB6, 0x8A, 0x2C, ++ 0xAC, 0xAF, 0x85, 0x8A, 0x85, 0xD9, 0x48, 0x48, ++ 0xB2, 0x95, 0x95, 0xD9, 0x85, 0xDA, 0x85, 0x85, ++ 0xD3, 0xB2, 0x21, 0x7D, 0xAC, 0x2C, 0xDA, 0x85, ++ 0xAC, 0xAC, 0x85, 0x85, 0x85, 0x2C, 0xAF, 0x2C, ++ 0xDA, 0x8C, 0x79, 0xC7, 0xB0, 0x51, 0xB3, 0x35, ++ 0xBF, 0xE5, 0xE7, 0xA8, 0xE0, 0xA2, 0xC1, 0x34, ++ 0x7D, 0x85, 0xAC, 0xD9, 0xAC, 0xAF, 0xAC, 0xAC, ++ 0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0xAF, 0xAF, 0x85, ++ 0xC8, 0xCD, 0x6A, 0x26, 0x35, 0x3F, 0x83, 0x23, ++ 0x23, 0xE7, 0xBF, 0x96, 0xEB, 0xDA, 0xDA, 0x2C, ++ 0x2C, 0x2C, 0x85, 0xDA, 0x2C, 0x7D, 0xA1, 0x48, ++ 0xB2, 0x21, 0xD6, 0xD9, 0x2C, 0xDA, 0x85, 0xAF, ++ 0xAF, 0x2D, 0xE9, 0x7D, 0xAC, 0x2C, 0x85, 0x2C, ++ 0xD9, 0xD9, 0xAF, 0x85, 0x85, 0x85, 0x2C, 0x2C, ++ 0x2C, 0x85, 0xD9, 0x21, 0xAC, 0x2C, 0xBD, 0xA5, ++ 0xC3, 0xA2, 0xA2, 0xA2, 0x26, 0xC1, 0xCE, 0x2A, ++ 0xAF, 0x95, 0xD9, 0x2C, 0x2C, 0x85, 0x2C, 0xAF, ++ 0xAC, 0x2C, 0x85, 0x2C, 0xAF, 0x2C, 0x85, 0xDA, ++ 0x8D, 0x2A, 0x85, 0x34, 0xC1, 0xB3, 0x76, 0x35, ++ 0xE0, 0x30, 0xA5, 0xB6, 0x2C, 0x85, 0x85, 0x85, ++ 0xAF, 0x2C, 0x85, 0x85, 0xD9, 0xD6, 0xA1, 0xA1, ++ 0x48, 0xA1, 0xD6, 0xAF, 0xDA, 0x8A, 0x2C, 0xD9, ++ 0xB2, 0x2D, 0x48, 0xD9, 0xAF, 0x2C, 0x2C, 0x85, ++ 0xAF, 0xAC, 0x2C, 0x85, 0x85, 0x85, 0xAF, 0xAC, ++ 0xAC, 0x2C, 0xD9, 0xD6, 0xD6, 0x21, 0xB2, 0x2C, ++ 0xC8, 0x3B, 0x65, 0xC5, 0xCE, 0x8E, 0xC8, 0x2C, ++ 0xD9, 0x95, 0xAC, 0x2C, 0x2C, 0x2C, 0xAF, 0xAC, ++ 0xAC, 0xAF, 0x2C, 0x85, 0x2C, 0x2C, 0x2C, 0x85, ++ 0xDA, 0x2C, 0xD6, 0xAF, 0x59, 0x65, 0xDE, 0xF3, ++ 0xF3, 0x59, 0xBC, 0xAC, 0xAF, 0x85, 0x85, 0x85, ++ 0xAF, 0xD9, 0xAF, 0x2C, 0xD9, 0xD6, 0xD6, 0xD6, ++ 0x21, 0xD6, 0xD9, 0xDA, 0x8D, 0x8A, 0x2C, 0xD9, ++ 0xB2, 0xA1, 0xD6, 0xAC, 0x2C, 0x2C, 0x2C, 0x85, ++ 0x2C, 0xAC, 0x2C, 0xDA, 0xDA, 0x85, 0xAF, 0xD9, ++ 0xD9, 0xAC, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xAC, ++ 0x85, 0x2A, 0x4D, 0xBC, 0x85, 0xAC, 0xAF, 0xAF, ++ 0xAC, 0xD9, 0xAF, 0x2C, 0xAF, 0xD9, 0xD9, 0xAC, ++ 0xAC, 0xAF, 0x85, 0x2C, 0x85, 0x2C, 0x2C, 0x2C, ++ 0x2C, 0xD9, 0xB2, 0xD4, 0xD6, 0x2C, 0x8A, 0xDA, ++ 0xC8, 0x85, 0x2C, 0xAC, 0x2C, 0xDA, 0xDA, 0x85, ++ 0xAF, 0xAC, 0xD9, 0xAC, 0xD9, 0xD9, 0xD9, 0xD9, ++ 0xD9, 0xAC, 0xDA, 0x8D, 0xBC, 0xDA, 0xD9, 0x95, ++ 0x95, 0xD9, 0xD9, 0xAF, 0x2C, 0x2C, 0x2C, 0x85, ++ 0x2C, 0xAF, 0xAF, 0x85, 0x85, 0x85, 0x2C, 0xAC, ++ 0xD9, 0xAF, 0xAF, 0xAF, 0x2C, 0x2C, 0x2C, 0x85, ++ 0x8A, 0x2A, 0x8D, 0x2C, 0xD9, 0x95, 0xAC, 0xAC, ++ 0xD9, 0xD9, 0xD9, 0xD9, 0x95, 0x95, 0xD9, 0xAF, ++ 0xAF, 0x2C, 0x85, 0x85, 0x85, 0x85, 0x85, 0x2C, ++ 0x85, 0x2C, 0xD9, 0xD9, 0xD9, 0x2C, 0x2C, 0x2C, ++ 0x2C, 0x85, 0x85, 0xAF, 0xAF, 0x85, 0x85, 0x85, ++ 0xAF, 0xD9, 0xD9, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C, ++ 0x2C, 0x85, 0x8A, 0x2A, 0x8D, 0x2C, 0xD9, 0xD9, ++ 0x2C, 0xAC, 0xAF, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, ++ 0x85, 0xAF, 0xAC, 0x2C, 0x2C, 0x2C, 0x2C, 0xAC, ++ 0xD9, 0xD9, 0xAF, 0x85, 0x85, 0x85, 0xDA, 0xDA, ++ 0x8A, 0x8A, 0x85, 0xAC, 0xD9, 0xD9, 0xAC, 0xD9, ++ 0xD6, 0xD6, 0x7D, 0x95, 0x7D, 0xD9, 0xAF, 0xAF, ++ 0xAF, 0x2C, 0x85, 0x85, 0xDA, 0x85, 0x2C, 0x85, ++ 0x85, 0x2C, 0xAF, 0xAC, 0xAF, 0xAF, 0x2C, 0x2C, ++ 0x2C, 0x2C, 0x2C, 0xAF, 0xAC, 0x2C, 0x2C, 0x2C, ++ 0x2C, 0xAF, 0xD9, 0xAC, 0xAF, 0x2C, 0x85, 0x85, ++ 0x85, 0xDA, 0x8D, 0x8A, 0x85, 0xAC, 0x95, 0xD9 ++}; ++ ++#define INCLUDE_LINUX_LOGOBW ++#define INCLUDE_LINUX_LOGO16 ++#include ++ ++#else ++ ++/* prototypes only */ ++extern unsigned char linux_logo_red[]; ++extern unsigned char linux_logo_green[]; ++extern unsigned char linux_logo_blue[]; ++extern unsigned char linux_logo[]; ++extern unsigned char linux_logo_bw[]; ++extern unsigned char linux_logo16_red[]; ++extern unsigned char linux_logo16_green[]; ++extern unsigned char linux_logo16_blue[]; ++extern unsigned char linux_logo16[]; ++ ++#endif +diff -ruN linux-mips/include/asm-mips/linux_logo_vr.h linux-vr/include/asm-mips/linux_logo_vr.h +--- linux-mips/include/asm-mips/linux_logo_vr.h Wed Dec 31 16:00:00 1969 ++++ linux-vr/include/asm-mips/linux_logo_vr.h Tue Feb 15 05:38:58 2000 +@@ -0,0 +1,644 @@ ++#if LINUX_LOGO_COLORS == 214 ++ ++unsigned char linux_logo_red[] __initdata = { ++ 0xc6, 0x9e, 0x8a, 0x8e, 0xae, 0xa6, 0x96, 0x76, 0x7e, 0xb6, 0x86, 0xbe, 0xc2, 0xce, 0x6e, 0x6a, ++ 0x56, 0x0e, 0x02, 0x06, 0x36, 0x3e, 0x12, 0x0a, 0x5e, 0x2a, 0x4e, 0x26, 0x1e, 0x16, 0x66, 0xe6, ++ 0xee, 0xfa, 0x2e, 0xf6, 0x1e, 0xfe, 0x52, 0x2e, 0x1e, 0x46, 0x1e, 0xaa, 0xca, 0xd2, 0xca, 0xa6, ++ 0xd6, 0x3a, 0xda, 0x4e, 0xaa, 0xce, 0xea, 0xda, 0xee, 0xc2, 0x72, 0x5a, 0xe6, 0xc6, 0xba, 0xde, ++ 0xee, 0xde, 0xea, 0xee, 0xf6, 0xf6, 0xda, 0xce, 0x96, 0x16, 0x3a, 0xae, 0xca, 0xe6, 0xf6, 0xf2, ++ 0xd6, 0x0e, 0x86, 0xbe, 0xee, 0xf6, 0xba, 0xde, 0x52, 0xca, 0x8a, 0xba, 0xde, 0xea, 0xee, 0xc6, ++ 0xd2, 0x3e, 0x82, 0xb2, 0xce, 0xb2, 0x9e, 0xa2, 0xb6, 0xce, 0xc2, 0xd2, 0xca, 0xc6, 0xba, 0x96, ++ 0xd6, 0xc6, 0xc6, 0xc6, 0xba, 0xa6, 0xaa, 0xc6, 0xb6, 0xaa, 0xaa, 0xb6, 0x46, 0xd2, 0xaa, 0x72, ++ 0xe2, 0x3a, 0xfa, 0x1a, 0x1e, 0xba, 0xa2, 0xf6, 0xaa, 0xce, 0xee, 0xf6, 0xf2, 0x9e, 0xda, 0xea, ++ 0xfa, 0xe6, 0xf6, 0x0a, 0x7e, 0xce, 0xd2, 0xe6, 0xce, 0xe2, 0x4a, 0xc2, 0xce, 0x36, 0xce, 0xf2, ++ 0xaa, 0x92, 0x26, 0x6a, 0xd6, 0x5e, 0xbe, 0xb6, 0xb6, 0xc2, 0xd6, 0xca, 0x66, 0x7a, 0xde, 0xea, ++ 0xea, 0xe6, 0xe6, 0xe2, 0xe6, 0xda, 0xda, 0xee, 0xce, 0xde, 0x52, 0x42, 0xbe, 0x6e, 0xbe, 0xd6, ++ 0x6e, 0xba, 0x96, 0x7e, 0xe6, 0xd2, 0xc2, 0xaa, 0xae, 0xca, 0xc2, 0xba, 0x92, 0x9e, 0x96, 0x9e, ++ 0x96, 0x62, 0x8a, 0x76, 0x7a, 0x82, 0x72, 0x72, 0x96, 0xe6, 0xe6, 0xde, 0x00, 0x00, 0x00, 0x00 ++}; ++ ++unsigned char linux_logo_green[] __initdata = { ++ 0xc6, 0x9e, 0x8a, 0x8e, 0xae, 0xa6, 0x96, 0x76, 0x7e, 0xb6, 0x86, 0xbe, 0xc2, 0xce, 0x6e, 0x6a, ++ 0x56, 0x0e, 0x02, 0x06, 0x36, 0x3e, 0x12, 0x0a, 0x5e, 0x2a, 0x4e, 0x26, 0x1e, 0x16, 0x66, 0xe6, ++ 0xee, 0xfa, 0x2e, 0xf6, 0x1e, 0xfe, 0x5a, 0x1e, 0x12, 0x3e, 0x0e, 0x8a, 0xa2, 0xaa, 0xa6, 0x86, ++ 0xba, 0x2e, 0xda, 0x3e, 0x7e, 0x9a, 0xbe, 0xb2, 0xca, 0xaa, 0x5a, 0x46, 0xde, 0xaa, 0x8a, 0xa2, ++ 0xb6, 0xbe, 0xc6, 0xd6, 0xda, 0xd6, 0xbe, 0xb6, 0x7a, 0x0e, 0x26, 0x7a, 0x92, 0xae, 0xda, 0xbe, ++ 0xd6, 0x06, 0x62, 0x8e, 0xb6, 0xd6, 0x8e, 0xa6, 0x46, 0xca, 0x5e, 0x92, 0xaa, 0xbe, 0xc6, 0x96, ++ 0xa2, 0x36, 0x56, 0x82, 0x92, 0x82, 0x92, 0x72, 0x7a, 0x8e, 0x96, 0xba, 0xba, 0xca, 0xa2, 0x6e, ++ 0x9a, 0x86, 0xbe, 0xbe, 0xaa, 0x6e, 0x7a, 0xb6, 0x9e, 0x92, 0x9a, 0xaa, 0x46, 0xd2, 0xaa, 0x72, ++ 0xe2, 0x3a, 0xf6, 0x1a, 0x1a, 0xb2, 0x7e, 0xbe, 0x8e, 0xaa, 0xae, 0xbe, 0xe2, 0x8a, 0xc2, 0xae, ++ 0xba, 0xaa, 0xca, 0x06, 0x66, 0xc6, 0xc2, 0xd2, 0xae, 0xa6, 0x32, 0x92, 0x9e, 0x1a, 0xc6, 0xb6, ++ 0x8e, 0x62, 0x12, 0x46, 0xce, 0x42, 0x82, 0x76, 0x86, 0x8e, 0xca, 0xbe, 0x46, 0x6a, 0xc2, 0xe6, ++ 0xda, 0xc2, 0xb6, 0xca, 0xba, 0xbe, 0xd2, 0xde, 0xa6, 0x9e, 0x3a, 0x26, 0x9a, 0x4e, 0x9e, 0x96, ++ 0x4e, 0x92, 0x62, 0x4a, 0xd6, 0xbe, 0x9e, 0x76, 0x6e, 0xb2, 0xb2, 0x96, 0x6e, 0x62, 0x72, 0x6a, ++ 0x86, 0x4e, 0x6e, 0x56, 0x62, 0x76, 0x5e, 0x56, 0x82, 0xc6, 0xde, 0xca, 0x00, 0x00, 0x00, 0x00 ++}; ++ ++unsigned char linux_logo_blue[] __initdata = { ++ 0xc4, 0x9c, 0x8c, 0x8c, 0xac, 0xa4, 0x94, 0x74, 0x7c, 0xb4, 0x84, 0xbc, 0xc4, 0xc4, 0x6c, 0x6c, ++ 0x54, 0x0c, 0x04, 0x04, 0x34, 0x3c, 0x14, 0x0c, 0x5c, 0x2c, 0x4c, 0x24, 0x1c, 0x14, 0x64, 0xe4, ++ 0xec, 0xfc, 0x2c, 0xf4, 0x0c, 0xfc, 0x5c, 0x0c, 0x04, 0x3c, 0x04, 0x3c, 0x14, 0x1c, 0x2c, 0x24, ++ 0x7c, 0x14, 0xdc, 0x14, 0x24, 0x0c, 0x0c, 0x14, 0x14, 0x2c, 0x1c, 0x1c, 0xdc, 0x74, 0x24, 0x0c, ++ 0x14, 0x0c, 0x14, 0x24, 0x34, 0x14, 0x24, 0x3c, 0x2c, 0x0c, 0x0c, 0x14, 0x1c, 0x0c, 0x14, 0x34, ++ 0xd4, 0x0c, 0x14, 0x0c, 0x0c, 0x24, 0x14, 0x1c, 0x14, 0xcc, 0x0c, 0x14, 0x14, 0x14, 0x0c, 0x0c, ++ 0x0c, 0x0c, 0x04, 0x04, 0x0c, 0x3c, 0x7c, 0x0c, 0x0c, 0x0c, 0x44, 0x8c, 0xac, 0xc4, 0x7c, 0x24, ++ 0x0c, 0x0c, 0xb4, 0xac, 0x7c, 0x0c, 0x0c, 0x94, 0x7c, 0x64, 0x74, 0x94, 0x44, 0xd4, 0xac, 0x74, ++ 0xe4, 0x3c, 0xfc, 0x1c, 0x1c, 0x9c, 0x1c, 0x14, 0x34, 0x4c, 0x14, 0x0c, 0xb4, 0x2c, 0x84, 0x0c, ++ 0x0c, 0x14, 0x14, 0x0c, 0x14, 0xa4, 0x94, 0x94, 0x5c, 0x0c, 0x0c, 0x2c, 0x1c, 0x04, 0xb4, 0x0c, ++ 0x14, 0x14, 0x04, 0x04, 0xbc, 0x14, 0x0c, 0x0c, 0x1c, 0x14, 0xbc, 0x8c, 0x0c, 0x4c, 0x54, 0xc4, ++ 0x6c, 0x44, 0x44, 0x6c, 0x2c, 0x4c, 0xbc, 0x9c, 0x44, 0x0c, 0x0c, 0x0c, 0x0c, 0x1c, 0x4c, 0x0c, ++ 0x0c, 0x2c, 0x0c, 0x04, 0xb4, 0x94, 0x5c, 0x0c, 0x04, 0x74, 0x8c, 0x54, 0x14, 0x04, 0x2c, 0x04, ++ 0x74, 0x24, 0x3c, 0x0c, 0x3c, 0x5c, 0x3c, 0x24, 0x5c, 0x2c, 0xbc, 0x94, 0x00, 0x00, 0x00, 0x00 ++}; ++ ++unsigned char linux_logo[] __initdata = { ++ 0x20, 0x21, 0x22, 0x23, 0x21, 0x24, 0x25, 0x25, 0x21, 0x26, 0x23, 0x22, 0x23, 0x21, 0x25, 0x21, ++ 0x23, 0x27, 0x28, 0x21, 0x24, 0x29, 0x29, 0x25, 0x22, 0x27, 0x2a, 0x25, 0x2b, 0x2c, 0x2b, 0x29, ++ 0x24, 0x25, 0x26, 0x21, 0x25, 0x25, 0x26, 0x26, 0x21, 0x24, 0x24, 0x24, 0x2b, 0x20, 0x2c, 0x2c, ++ 0x20, 0x2d, 0x20, 0x21, 0x22, 0x23, 0x21, 0x24, 0x25, 0x25, 0x21, 0x26, 0x23, 0x22, 0x23, 0x21, ++ 0x25, 0x21, 0x23, 0x27, 0x28, 0x21, 0x24, 0x29, 0x29, 0x25, 0x22, 0x27, 0x2a, 0x25, 0x2b, 0x2c, ++ 0x21, 0x27, 0x27, 0x22, 0x25, 0x25, 0x25, 0x21, 0x26, 0x26, 0x23, 0x22, 0x23, 0x26, 0x26, 0x23, ++ 0x27, 0x2e, 0x2a, 0x21, 0x29, 0x29, 0x24, 0x25, 0x26, 0x26, 0x21, 0x29, 0x2b, 0x29, 0x24, 0x25, ++ 0x25, 0x21, 0x26, 0x21, 0x21, 0x21, 0x25, 0x25, 0x24, 0x24, 0x25, 0x25, 0x24, 0x29, 0x29, 0x29, ++ 0x29, 0x29, 0x21, 0x27, 0x27, 0x22, 0x25, 0x25, 0x25, 0x21, 0x26, 0x26, 0x23, 0x22, 0x23, 0x26, ++ 0x26, 0x23, 0x27, 0x2e, 0x2a, 0x21, 0x29, 0x29, 0x24, 0x25, 0x26, 0x26, 0x21, 0x29, 0x2b, 0x29, ++ 0x22, 0x27, 0x27, 0x2a, 0x25, 0x24, 0x25, 0x21, 0x26, 0x26, 0x22, 0x23, 0x26, 0x26, 0x26, 0x2a, ++ 0x28, 0x2a, 0x21, 0x24, 0x29, 0x29, 0x24, 0x25, 0x21, 0x21, 0x25, 0x24, 0x29, 0x24, 0x25, 0x25, ++ 0x21, 0x26, 0x23, 0x21, 0x29, 0x24, 0x25, 0x21, 0x24, 0x29, 0x29, 0x24, 0x24, 0x29, 0x24, 0x24, ++ 0x24, 0x25, 0x22, 0x27, 0x27, 0x2a, 0x25, 0x24, 0x25, 0x21, 0x26, 0x26, 0x22, 0x23, 0x26, 0x26, ++ 0x26, 0x2a, 0x28, 0x2a, 0x21, 0x24, 0x29, 0x29, 0x24, 0x25, 0x21, 0x21, 0x25, 0x29, 0x29, 0x24, ++ 0x28, 0x2f, 0x27, 0x26, 0x25, 0x29, 0x24, 0x21, 0x26, 0x26, 0x23, 0x23, 0x26, 0x26, 0x23, 0x23, ++ 0x26, 0x21, 0x25, 0x24, 0x29, 0x29, 0x24, 0x25, 0x21, 0x21, 0x25, 0x25, 0x25, 0x25, 0x25, 0x21, ++ 0x26, 0x26, 0x25, 0x30, 0x31, 0x32, 0x33, 0x33, 0x33, 0x32, 0x33, 0x34, 0x25, 0x24, 0x25, 0x25, ++ 0x21, 0x23, 0x28, 0x2f, 0x27, 0x26, 0x25, 0x29, 0x24, 0x21, 0x26, 0x26, 0x23, 0x23, 0x26, 0x26, ++ 0x23, 0x23, 0x26, 0x21, 0x25, 0x24, 0x29, 0x29, 0x24, 0x25, 0x21, 0x21, 0x25, 0x25, 0x25, 0x25, ++ 0x28, 0x28, 0x2a, 0x25, 0x24, 0x29, 0x24, 0x25, 0x26, 0x26, 0x23, 0x26, 0x26, 0x26, 0x26, 0x26, ++ 0x21, 0x25, 0x29, 0x29, 0x29, 0x24, 0x25, 0x21, 0x26, 0x26, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, ++ 0x25, 0x28, 0x31, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x33, 0x35, 0x24, 0x21, ++ 0x26, 0x22, 0x28, 0x28, 0x2a, 0x25, 0x24, 0x29, 0x24, 0x25, 0x26, 0x26, 0x23, 0x26, 0x26, 0x26, ++ 0x26, 0x26, 0x21, 0x25, 0x29, 0x29, 0x29, 0x24, 0x25, 0x21, 0x26, 0x26, 0x26, 0x21, 0x21, 0x21, ++ 0x2a, 0x2a, 0x26, 0x25, 0x29, 0x29, 0x24, 0x21, 0x26, 0x22, 0x23, 0x23, 0x26, 0x26, 0x25, 0x25, ++ 0x24, 0x29, 0x24, 0x24, 0x25, 0x25, 0x21, 0x26, 0x26, 0x26, 0x21, 0x21, 0x25, 0x21, 0x21, 0x29, ++ 0x34, 0x33, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x31, 0x36, 0x33, 0x37, 0x27, ++ 0x21, 0x23, 0x2a, 0x2a, 0x26, 0x25, 0x29, 0x29, 0x24, 0x21, 0x26, 0x22, 0x23, 0x23, 0x26, 0x26, ++ 0x25, 0x25, 0x24, 0x29, 0x24, 0x24, 0x24, 0x25, 0x26, 0x26, 0x26, 0x26, 0x25, 0x21, 0x25, 0x25, ++ 0x26, 0x26, 0x21, 0x25, 0x24, 0x24, 0x25, 0x26, 0x22, 0x2a, 0x22, 0x26, 0x21, 0x21, 0x24, 0x24, ++ 0x24, 0x24, 0x24, 0x24, 0x25, 0x21, 0x21, 0x21, 0x21, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x38, ++ 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x33, 0x39, 0x30, 0x34, 0x31, 0x32, ++ 0x3a, 0x25, 0x26, 0x26, 0x21, 0x25, 0x24, 0x24, 0x25, 0x26, 0x22, 0x2a, 0x22, 0x26, 0x21, 0x21, ++ 0x24, 0x24, 0x24, 0x24, 0x24, 0x25, 0x25, 0x25, 0x21, 0x26, 0x21, 0x21, 0x25, 0x25, 0x25, 0x25, ++ 0x21, 0x22, 0x26, 0x25, 0x24, 0x24, 0x21, 0x23, 0x2a, 0x28, 0x22, 0x26, 0x21, 0x24, 0x24, 0x24, ++ 0x25, 0x25, 0x25, 0x25, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x24, 0x33, ++ 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x34, 0x27, 0x38, 0x39, 0x37, ++ 0x32, 0x2a, 0x21, 0x22, 0x26, 0x25, 0x24, 0x24, 0x21, 0x23, 0x2a, 0x28, 0x22, 0x26, 0x21, 0x24, ++ 0x24, 0x24, 0x25, 0x21, 0x25, 0x25, 0x21, 0x21, 0x21, 0x21, 0x21, 0x25, 0x21, 0x21, 0x21, 0x21, ++ 0x21, 0x22, 0x26, 0x25, 0x29, 0x29, 0x25, 0x22, 0x28, 0x2a, 0x26, 0x21, 0x25, 0x29, 0x29, 0x24, ++ 0x21, 0x21, 0x21, 0x25, 0x25, 0x21, 0x26, 0x26, 0x23, 0x23, 0x23, 0x26, 0x23, 0x26, 0x27, 0x32, ++ 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x33, 0x34, 0x30, 0x35, 0x3b, 0x31, ++ 0x32, 0x31, 0x29, 0x2a, 0x26, 0x25, 0x29, 0x29, 0x25, 0x22, 0x28, 0x2a, 0x26, 0x21, 0x25, 0x29, ++ 0x29, 0x24, 0x25, 0x21, 0x21, 0x25, 0x25, 0x21, 0x21, 0x26, 0x22, 0x23, 0x23, 0x23, 0x23, 0x26, ++ 0x29, 0x26, 0x21, 0x24, 0x29, 0x24, 0x26, 0x2a, 0x28, 0x26, 0x21, 0x24, 0x24, 0x24, 0x24, 0x21, ++ 0x26, 0x26, 0x26, 0x21, 0x26, 0x26, 0x23, 0x22, 0x2a, 0x22, 0x23, 0x26, 0x26, 0x24, 0x3c, 0x32, ++ 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x33, 0x3c, 0x3d, 0x33, 0x32, 0x32, ++ 0x33, 0x33, 0x2e, 0x26, 0x25, 0x24, 0x29, 0x24, 0x26, 0x2a, 0x28, 0x26, 0x21, 0x24, 0x24, 0x24, ++ 0x24, 0x21, 0x26, 0x26, 0x21, 0x21, 0x26, 0x26, 0x22, 0x22, 0x22, 0x22, 0x23, 0x26, 0x26, 0x26, ++ 0x29, 0x25, 0x24, 0x29, 0x29, 0x24, 0x23, 0x2a, 0x2a, 0x21, 0x25, 0x24, 0x24, 0x25, 0x25, 0x26, ++ 0x23, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x21, 0x25, 0x21, 0x25, 0x29, 0x32, 0x32, ++ 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, ++ 0x32, 0x32, 0x31, 0x29, 0x24, 0x29, 0x29, 0x24, 0x23, 0x2a, 0x2a, 0x21, 0x25, 0x24, 0x24, 0x25, ++ 0x25, 0x26, 0x23, 0x23, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x21, 0x25, 0x25, 0x25, 0x25, ++ 0x29, 0x24, 0x24, 0x24, 0x24, 0x26, 0x2a, 0x28, 0x23, 0x21, 0x24, 0x24, 0x25, 0x21, 0x23, 0x26, ++ 0x22, 0x23, 0x26, 0x26, 0x26, 0x26, 0x21, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x21, 0x32, 0x32, ++ 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x33, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, ++ 0x32, 0x32, 0x33, 0x21, 0x24, 0x24, 0x24, 0x26, 0x2a, 0x28, 0x23, 0x21, 0x24, 0x24, 0x25, 0x21, ++ 0x23, 0x23, 0x22, 0x23, 0x26, 0x26, 0x26, 0x26, 0x21, 0x25, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, ++ 0x25, 0x25, 0x25, 0x21, 0x21, 0x23, 0x2a, 0x2a, 0x21, 0x25, 0x25, 0x21, 0x23, 0x2a, 0x22, 0x23, ++ 0x23, 0x26, 0x26, 0x23, 0x26, 0x26, 0x25, 0x29, 0x29, 0x29, 0x29, 0x24, 0x25, 0x2a, 0x32, 0x32, ++ 0x33, 0x37, 0x3c, 0x37, 0x32, 0x32, 0x32, 0x32, 0x32, 0x33, 0x33, 0x37, 0x3b, 0x3c, 0x32, 0x32, ++ 0x32, 0x32, 0x32, 0x30, 0x25, 0x21, 0x21, 0x23, 0x2a, 0x2a, 0x21, 0x25, 0x25, 0x21, 0x23, 0x22, ++ 0x22, 0x23, 0x26, 0x23, 0x26, 0x23, 0x26, 0x21, 0x25, 0x29, 0x29, 0x29, 0x29, 0x24, 0x25, 0x25, ++ 0x24, 0x21, 0x21, 0x26, 0x23, 0x2a, 0x22, 0x26, 0x25, 0x25, 0x25, 0x26, 0x2a, 0x2a, 0x26, 0x21, ++ 0x21, 0x23, 0x22, 0x22, 0x22, 0x21, 0x25, 0x24, 0x29, 0x29, 0x25, 0x25, 0x21, 0x2a, 0x32, 0x32, ++ 0x31, 0x3b, 0x36, 0x3b, 0x33, 0x32, 0x32, 0x32, 0x33, 0x34, 0x3e, 0x3e, 0x3b, 0x39, 0x31, 0x32, ++ 0x32, 0x32, 0x32, 0x35, 0x21, 0x26, 0x23, 0x2a, 0x22, 0x26, 0x25, 0x25, 0x25, 0x26, 0x2a, 0x2a, ++ 0x26, 0x21, 0x26, 0x26, 0x22, 0x22, 0x22, 0x26, 0x25, 0x24, 0x29, 0x24, 0x25, 0x25, 0x21, 0x21, ++ 0x24, 0x21, 0x26, 0x23, 0x22, 0x2a, 0x23, 0x21, 0x24, 0x21, 0x21, 0x23, 0x22, 0x23, 0x21, 0x25, ++ 0x21, 0x2a, 0x2a, 0x22, 0x26, 0x25, 0x24, 0x24, 0x25, 0x25, 0x26, 0x23, 0x26, 0x22, 0x32, 0x36, ++ 0x22, 0x2b, 0x2a, 0x3c, 0x37, 0x32, 0x32, 0x33, 0x30, 0x26, 0x24, 0x2c, 0x29, 0x39, 0x37, 0x32, ++ 0x32, 0x32, 0x33, 0x39, 0x26, 0x23, 0x22, 0x2a, 0x23, 0x21, 0x24, 0x21, 0x21, 0x23, 0x2a, 0x23, ++ 0x21, 0x24, 0x21, 0x2a, 0x2a, 0x23, 0x26, 0x25, 0x24, 0x24, 0x24, 0x21, 0x26, 0x26, 0x26, 0x21, ++ 0x25, 0x26, 0x22, 0x2a, 0x28, 0x22, 0x21, 0x25, 0x25, 0x21, 0x23, 0x22, 0x26, 0x21, 0x24, 0x24, ++ 0x21, 0x22, 0x22, 0x21, 0x24, 0x29, 0x29, 0x2b, 0x24, 0x21, 0x26, 0x23, 0x26, 0x23, 0x32, 0x3a, ++ 0x20, 0x3f, 0x3f, 0x22, 0x32, 0x32, 0x32, 0x35, 0x2d, 0x40, 0x40, 0x40, 0x3f, 0x2a, 0x33, 0x32, ++ 0x32, 0x32, 0x32, 0x3b, 0x22, 0x2a, 0x28, 0x22, 0x21, 0x25, 0x25, 0x21, 0x23, 0x22, 0x26, 0x21, ++ 0x24, 0x25, 0x26, 0x22, 0x22, 0x21, 0x24, 0x29, 0x29, 0x2b, 0x24, 0x21, 0x26, 0x23, 0x26, 0x26, ++ 0x25, 0x26, 0x2a, 0x2a, 0x28, 0x22, 0x21, 0x25, 0x25, 0x26, 0x23, 0x23, 0x21, 0x25, 0x25, 0x25, ++ 0x26, 0x26, 0x21, 0x24, 0x2b, 0x20, 0x2b, 0x29, 0x21, 0x26, 0x22, 0x23, 0x26, 0x21, 0x33, 0x21, ++ 0x25, 0x30, 0x2b, 0x40, 0x36, 0x32, 0x32, 0x27, 0x41, 0x29, 0x3d, 0x30, 0x2c, 0x40, 0x3b, 0x32, ++ 0x32, 0x32, 0x32, 0x37, 0x2a, 0x2a, 0x28, 0x22, 0x21, 0x25, 0x25, 0x26, 0x26, 0x26, 0x21, 0x25, ++ 0x24, 0x25, 0x26, 0x23, 0x21, 0x24, 0x2b, 0x20, 0x2b, 0x29, 0x25, 0x26, 0x22, 0x23, 0x21, 0x21, ++ 0x21, 0x26, 0x2a, 0x28, 0x2a, 0x26, 0x25, 0x24, 0x25, 0x26, 0x23, 0x26, 0x25, 0x21, 0x25, 0x21, ++ 0x21, 0x21, 0x24, 0x2b, 0x20, 0x2c, 0x29, 0x21, 0x2a, 0x28, 0x28, 0x2a, 0x26, 0x26, 0x32, 0x20, ++ 0x42, 0x34, 0x3a, 0x43, 0x34, 0x44, 0x39, 0x28, 0x41, 0x34, 0x33, 0x3a, 0x38, 0x45, 0x46, 0x32, ++ 0x32, 0x32, 0x32, 0x37, 0x2a, 0x28, 0x2a, 0x26, 0x25, 0x24, 0x25, 0x26, 0x22, 0x26, 0x25, 0x21, ++ 0x25, 0x21, 0x21, 0x25, 0x24, 0x2b, 0x20, 0x20, 0x29, 0x26, 0x2a, 0x28, 0x28, 0x2a, 0x23, 0x26, ++ 0x26, 0x23, 0x2a, 0x28, 0x2a, 0x21, 0x24, 0x24, 0x21, 0x26, 0x26, 0x21, 0x25, 0x21, 0x21, 0x21, ++ 0x21, 0x24, 0x2b, 0x2c, 0x2c, 0x29, 0x26, 0x28, 0x2e, 0x2e, 0x27, 0x2a, 0x26, 0x21, 0x32, 0x2c, ++ 0x3c, 0x37, 0x42, 0x2d, 0x47, 0x48, 0x36, 0x49, 0x40, 0x37, 0x32, 0x33, 0x3b, 0x41, 0x2f, 0x32, ++ 0x32, 0x32, 0x32, 0x3d, 0x2a, 0x28, 0x2a, 0x21, 0x24, 0x24, 0x21, 0x26, 0x26, 0x21, 0x25, 0x21, ++ 0x21, 0x21, 0x21, 0x24, 0x2b, 0x20, 0x2c, 0x29, 0x26, 0x28, 0x2e, 0x2e, 0x27, 0x2a, 0x26, 0x26, ++ 0x28, 0x2a, 0x28, 0x27, 0x2a, 0x21, 0x25, 0x25, 0x21, 0x23, 0x21, 0x25, 0x25, 0x24, 0x25, 0x25, ++ 0x24, 0x29, 0x2b, 0x2b, 0x24, 0x23, 0x27, 0x3e, 0x2e, 0x27, 0x2a, 0x26, 0x21, 0x24, 0x32, 0x25, ++ 0x46, 0x33, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 0x50, 0x51, 0x32, 0x33, 0x3a, 0x41, 0x30, 0x32, ++ 0x32, 0x32, 0x32, 0x36, 0x28, 0x27, 0x2a, 0x21, 0x24, 0x25, 0x26, 0x23, 0x21, 0x25, 0x25, 0x24, ++ 0x25, 0x25, 0x24, 0x29, 0x2b, 0x2b, 0x24, 0x23, 0x28, 0x3e, 0x2f, 0x27, 0x2a, 0x26, 0x21, 0x21, ++ 0x27, 0x2a, 0x22, 0x28, 0x2a, 0x21, 0x24, 0x25, 0x26, 0x26, 0x25, 0x24, 0x24, 0x24, 0x24, 0x25, ++ 0x24, 0x2b, 0x2c, 0x29, 0x26, 0x27, 0x3e, 0x3e, 0x27, 0x2a, 0x26, 0x21, 0x25, 0x24, 0x32, 0x3e, ++ 0x52, 0x53, 0x54, 0x55, 0x56, 0x56, 0x57, 0x4c, 0x58, 0x59, 0x5a, 0x5b, 0x52, 0x5c, 0x36, 0x32, ++ 0x32, 0x32, 0x32, 0x37, 0x26, 0x28, 0x2a, 0x21, 0x24, 0x24, 0x26, 0x23, 0x25, 0x24, 0x24, 0x24, ++ 0x24, 0x25, 0x24, 0x2b, 0x2b, 0x29, 0x26, 0x27, 0x3e, 0x3e, 0x27, 0x2a, 0x26, 0x21, 0x25, 0x25, ++ 0x21, 0x21, 0x26, 0x22, 0x23, 0x25, 0x24, 0x24, 0x26, 0x26, 0x25, 0x29, 0x29, 0x24, 0x24, 0x25, ++ 0x29, 0x2b, 0x2b, 0x24, 0x2a, 0x3e, 0x38, 0x2e, 0x2a, 0x26, 0x21, 0x25, 0x24, 0x29, 0x32, 0x3d, ++ 0x5d, 0x5e, 0x5f, 0x60, 0x61, 0x62, 0x58, 0x63, 0x64, 0x65, 0x58, 0x66, 0x67, 0x68, 0x69, 0x33, ++ 0x32, 0x32, 0x32, 0x33, 0x25, 0x22, 0x22, 0x21, 0x24, 0x25, 0x26, 0x26, 0x25, 0x29, 0x29, 0x29, ++ 0x25, 0x25, 0x29, 0x2c, 0x2b, 0x25, 0x2a, 0x3e, 0x38, 0x2e, 0x2a, 0x26, 0x21, 0x24, 0x25, 0x24, ++ 0x20, 0x24, 0x21, 0x23, 0x23, 0x25, 0x24, 0x24, 0x21, 0x21, 0x24, 0x29, 0x29, 0x24, 0x25, 0x21, ++ 0x29, 0x2b, 0x29, 0x21, 0x28, 0x3e, 0x2e, 0x2a, 0x26, 0x21, 0x24, 0x24, 0x24, 0x29, 0x32, 0x6a, ++ 0x6b, 0x6c, 0x6d, 0x56, 0x62, 0x58, 0x63, 0x64, 0x64, 0x6e, 0x6e, 0x65, 0x58, 0x6f, 0x5b, 0x32, ++ 0x32, 0x32, 0x32, 0x33, 0x25, 0x23, 0x26, 0x25, 0x24, 0x24, 0x21, 0x21, 0x24, 0x29, 0x29, 0x24, ++ 0x25, 0x21, 0x24, 0x2b, 0x2b, 0x21, 0x27, 0x2f, 0x2e, 0x2a, 0x26, 0x21, 0x25, 0x24, 0x24, 0x24, ++ 0x70, 0x21, 0x26, 0x22, 0x26, 0x25, 0x29, 0x24, 0x21, 0x21, 0x24, 0x29, 0x29, 0x25, 0x21, 0x25, ++ 0x24, 0x2b, 0x24, 0x26, 0x28, 0x27, 0x28, 0x23, 0x26, 0x21, 0x25, 0x24, 0x29, 0x29, 0x71, 0x72, ++ 0x73, 0x5f, 0x74, 0x56, 0x62, 0x58, 0x64, 0x63, 0x6e, 0x6e, 0x75, 0x57, 0x76, 0x77, 0x78, 0x32, ++ 0x32, 0x32, 0x32, 0x32, 0x3e, 0x23, 0x26, 0x25, 0x29, 0x24, 0x21, 0x21, 0x24, 0x29, 0x24, 0x25, ++ 0x21, 0x25, 0x29, 0x2b, 0x24, 0x26, 0x28, 0x2e, 0x2a, 0x23, 0x26, 0x21, 0x24, 0x29, 0x29, 0x24, ++ 0x79, 0x28, 0x28, 0x22, 0x26, 0x25, 0x24, 0x24, 0x26, 0x21, 0x24, 0x24, 0x24, 0x25, 0x21, 0x25, ++ 0x24, 0x29, 0x25, 0x2a, 0x28, 0x28, 0x28, 0x28, 0x2a, 0x26, 0x24, 0x29, 0x24, 0x29, 0x33, 0x7a, ++ 0x7b, 0x7c, 0x56, 0x7d, 0x58, 0x63, 0x64, 0x75, 0x63, 0x7e, 0x7f, 0x7f, 0x80, 0x55, 0x81, 0x32, ++ 0x32, 0x33, 0x32, 0x32, 0x3c, 0x25, 0x26, 0x25, 0x29, 0x24, 0x21, 0x21, 0x25, 0x29, 0x24, 0x25, ++ 0x21, 0x25, 0x24, 0x29, 0x25, 0x22, 0x28, 0x27, 0x28, 0x28, 0x2a, 0x26, 0x25, 0x29, 0x24, 0x21, ++ 0x21, 0x3e, 0x27, 0x22, 0x21, 0x25, 0x24, 0x25, 0x21, 0x26, 0x21, 0x24, 0x29, 0x24, 0x25, 0x25, ++ 0x24, 0x24, 0x26, 0x2a, 0x28, 0x27, 0x28, 0x28, 0x2a, 0x25, 0x29, 0x29, 0x25, 0x24, 0x37, 0x47, ++ 0x82, 0x55, 0x56, 0x62, 0x63, 0x75, 0x75, 0x61, 0x76, 0x83, 0x84, 0x80, 0x6c, 0x85, 0x69, 0x32, ++ 0x3c, 0x3e, 0x3b, 0x33, 0x32, 0x21, 0x21, 0x25, 0x24, 0x25, 0x26, 0x26, 0x25, 0x24, 0x29, 0x24, ++ 0x25, 0x21, 0x24, 0x25, 0x26, 0x2a, 0x28, 0x28, 0x28, 0x28, 0x2a, 0x21, 0x29, 0x29, 0x25, 0x21, ++ 0x2a, 0x3e, 0x27, 0x26, 0x21, 0x25, 0x25, 0x25, 0x21, 0x21, 0x21, 0x24, 0x24, 0x24, 0x21, 0x26, ++ 0x21, 0x21, 0x26, 0x2a, 0x2a, 0x2a, 0x28, 0x2a, 0x26, 0x29, 0x2b, 0x29, 0x21, 0x25, 0x32, 0x37, ++ 0x86, 0x72, 0x87, 0x7f, 0x7f, 0x7b, 0x83, 0x88, 0x73, 0x84, 0x89, 0x8a, 0x8b, 0x8c, 0x30, 0x32, ++ 0x33, 0x38, 0x2a, 0x34, 0x33, 0x2f, 0x21, 0x25, 0x25, 0x24, 0x21, 0x26, 0x21, 0x24, 0x24, 0x24, ++ 0x25, 0x26, 0x21, 0x25, 0x26, 0x2a, 0x2a, 0x2a, 0x28, 0x2a, 0x26, 0x29, 0x2b, 0x2b, 0x21, 0x26, ++ 0x28, 0x27, 0x2a, 0x21, 0x25, 0x25, 0x25, 0x24, 0x25, 0x21, 0x25, 0x24, 0x29, 0x24, 0x25, 0x26, ++ 0x26, 0x21, 0x21, 0x26, 0x26, 0x26, 0x26, 0x21, 0x24, 0x2b, 0x8d, 0x29, 0x26, 0x29, 0x32, 0x3c, ++ 0x29, 0x8e, 0x8f, 0x76, 0x77, 0x90, 0x89, 0x89, 0x91, 0x5e, 0x8e, 0x92, 0x8d, 0x20, 0x22, 0x33, ++ 0x33, 0x3b, 0x27, 0x3a, 0x32, 0x37, 0x29, 0x25, 0x25, 0x24, 0x25, 0x21, 0x25, 0x24, 0x29, 0x24, ++ 0x21, 0x21, 0x26, 0x21, 0x26, 0x26, 0x26, 0x26, 0x26, 0x21, 0x29, 0x2b, 0x20, 0x29, 0x26, 0x23, ++ 0x26, 0x26, 0x26, 0x25, 0x25, 0x25, 0x25, 0x24, 0x25, 0x25, 0x25, 0x24, 0x24, 0x25, 0x25, 0x21, ++ 0x26, 0x21, 0x21, 0x25, 0x25, 0x25, 0x25, 0x24, 0x2b, 0x2c, 0x2c, 0x24, 0x26, 0x26, 0x32, 0x3c, ++ 0x2b, 0x93, 0x94, 0x68, 0x95, 0x96, 0x87, 0x87, 0x4b, 0x97, 0x2b, 0x79, 0x40, 0x45, 0x3f, 0x39, ++ 0x32, 0x33, 0x31, 0x33, 0x32, 0x32, 0x42, 0x24, 0x25, 0x24, 0x24, 0x25, 0x25, 0x24, 0x24, 0x24, ++ 0x21, 0x21, 0x26, 0x21, 0x21, 0x25, 0x25, 0x25, 0x25, 0x24, 0x2b, 0x20, 0x2b, 0x24, 0x26, 0x26, ++ 0x21, 0x21, 0x21, 0x21, 0x25, 0x25, 0x25, 0x24, 0x24, 0x21, 0x21, 0x25, 0x25, 0x25, 0x25, 0x21, ++ 0x26, 0x26, 0x25, 0x25, 0x24, 0x24, 0x29, 0x29, 0x2b, 0x2b, 0x24, 0x26, 0x25, 0x3c, 0x32, 0x34, ++ 0x3f, 0x8d, 0x2b, 0x8c, 0x98, 0x99, 0x9a, 0x9b, 0x2b, 0x2c, 0x2d, 0x43, 0x45, 0x45, 0x41, 0x25, ++ 0x32, 0x32, 0x33, 0x32, 0x32, 0x32, 0x33, 0x21, 0x25, 0x24, 0x25, 0x21, 0x21, 0x25, 0x25, 0x25, ++ 0x25, 0x21, 0x26, 0x26, 0x25, 0x25, 0x24, 0x24, 0x29, 0x29, 0x2b, 0x2b, 0x24, 0x26, 0x23, 0x26, ++ 0x21, 0x26, 0x21, 0x21, 0x25, 0x25, 0x21, 0x25, 0x25, 0x21, 0x21, 0x21, 0x21, 0x21, 0x25, 0x21, ++ 0x26, 0x21, 0x25, 0x25, 0x24, 0x24, 0x29, 0x24, 0x24, 0x25, 0x26, 0x26, 0x3e, 0x33, 0x37, 0x2c, ++ 0x45, 0x3f, 0x2b, 0x2b, 0x2b, 0x2b, 0x2b, 0x2b, 0x20, 0x3f, 0x43, 0x45, 0x45, 0x45, 0x45, 0x41, ++ 0x34, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x3c, 0x29, 0x25, 0x25, 0x21, 0x21, 0x21, 0x21, 0x25, ++ 0x21, 0x21, 0x26, 0x21, 0x25, 0x25, 0x24, 0x24, 0x24, 0x24, 0x24, 0x25, 0x21, 0x22, 0x22, 0x26, ++ 0x22, 0x23, 0x26, 0x21, 0x21, 0x21, 0x21, 0x21, 0x25, 0x25, 0x21, 0x26, 0x21, 0x21, 0x21, 0x26, ++ 0x26, 0x23, 0x26, 0x25, 0x21, 0x21, 0x21, 0x21, 0x26, 0x22, 0x22, 0x22, 0x3d, 0x37, 0x3e, 0x45, ++ 0x45, 0x41, 0x79, 0x2b, 0x2b, 0x2b, 0x2c, 0x70, 0x43, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, ++ 0x29, 0x32, 0x32, 0x32, 0x32, 0x32, 0x33, 0x33, 0x38, 0x25, 0x25, 0x25, 0x21, 0x26, 0x21, 0x21, ++ 0x21, 0x26, 0x26, 0x23, 0x26, 0x21, 0x25, 0x21, 0x21, 0x21, 0x26, 0x22, 0x2a, 0x2a, 0x2a, 0x22, ++ 0x2a, 0x2a, 0x23, 0x26, 0x26, 0x21, 0x21, 0x21, 0x25, 0x21, 0x21, 0x26, 0x26, 0x26, 0x26, 0x23, ++ 0x2a, 0x2a, 0x2a, 0x23, 0x22, 0x22, 0x2a, 0x28, 0x28, 0x28, 0x25, 0x31, 0x32, 0x3d, 0x3f, 0x45, ++ 0x45, 0x45, 0x43, 0x52, 0x79, 0x2d, 0x3f, 0x41, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, ++ 0x41, 0x39, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x33, 0x25, 0x21, 0x21, 0x21, 0x26, 0x26, 0x26, ++ 0x26, 0x23, 0x2a, 0x2a, 0x22, 0x22, 0x22, 0x22, 0x2a, 0x28, 0x28, 0x28, 0x2a, 0x2a, 0x2a, 0x2a, ++ 0x2a, 0x26, 0x26, 0x26, 0x21, 0x21, 0x21, 0x21, 0x25, 0x25, 0x21, 0x26, 0x26, 0x26, 0x26, 0x26, ++ 0x22, 0x2a, 0x22, 0x26, 0x26, 0x23, 0x2a, 0x28, 0x28, 0x21, 0x3c, 0x32, 0x33, 0x2a, 0x45, 0x45, ++ 0x45, 0x45, 0x45, 0x45, 0x41, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, ++ 0x45, 0x27, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x3d, 0x2b, 0x25, 0x21, 0x26, 0x26, 0x26, ++ 0x26, 0x26, 0x22, 0x2a, 0x2a, 0x26, 0x26, 0x23, 0x2a, 0x28, 0x28, 0x28, 0x2a, 0x22, 0x2a, 0x28, ++ 0x26, 0x25, 0x25, 0x25, 0x21, 0x25, 0x21, 0x21, 0x25, 0x25, 0x25, 0x26, 0x26, 0x26, 0x26, 0x26, ++ 0x23, 0x23, 0x21, 0x25, 0x25, 0x21, 0x26, 0x22, 0x26, 0x3a, 0x32, 0x32, 0x3d, 0x3f, 0x45, 0x45, ++ 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, ++ 0x45, 0x29, 0x33, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x3b, 0x2b, 0x21, 0x21, 0x26, 0x26, ++ 0x26, 0x26, 0x23, 0x26, 0x21, 0x25, 0x25, 0x21, 0x26, 0x22, 0x23, 0x23, 0x23, 0x23, 0x22, 0x2a, ++ 0x25, 0x29, 0x29, 0x25, 0x25, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x25, 0x21, 0x21, 0x21, 0x21, ++ 0x21, 0x21, 0x25, 0x24, 0x25, 0x21, 0x26, 0x21, 0x2e, 0x33, 0x32, 0x32, 0x30, 0x3f, 0x45, 0x45, ++ 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, ++ 0x43, 0x3f, 0x33, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x33, 0x3b, 0x29, 0x21, 0x21, 0x21, ++ 0x21, 0x21, 0x21, 0x21, 0x25, 0x24, 0x25, 0x21, 0x26, 0x26, 0x21, 0x21, 0x21, 0x26, 0x26, 0x26, ++ 0x24, 0x29, 0x29, 0x24, 0x25, 0x25, 0x21, 0x25, 0x25, 0x25, 0x21, 0x25, 0x21, 0x21, 0x26, 0x21, ++ 0x21, 0x25, 0x25, 0x25, 0x21, 0x23, 0x23, 0x28, 0x32, 0x32, 0x32, 0x32, 0x2e, 0x2d, 0x41, 0x45, ++ 0x45, 0x45, 0x45, 0x43, 0x40, 0x40, 0x45, 0x45, 0x45, 0x45, 0x45, 0x43, 0x40, 0x40, 0x3f, 0x70, ++ 0x70, 0x40, 0x42, 0x32, 0x32, 0x33, 0x32, 0x32, 0x32, 0x32, 0x32, 0x33, 0x9c, 0x24, 0x21, 0x21, ++ 0x21, 0x26, 0x21, 0x25, 0x24, 0x25, 0x21, 0x23, 0x23, 0x26, 0x21, 0x21, 0x21, 0x26, 0x26, 0x21, ++ 0x2b, 0x2b, 0x2b, 0x29, 0x24, 0x25, 0x25, 0x21, 0x25, 0x21, 0x25, 0x21, 0x21, 0x21, 0x21, 0x21, ++ 0x21, 0x21, 0x21, 0x26, 0x2a, 0x2a, 0x25, 0x31, 0x33, 0x32, 0x32, 0x31, 0x28, 0x29, 0x9d, 0x40, ++ 0x45, 0x45, 0x45, 0x43, 0x40, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x3f, 0x70, 0x79, 0x20, 0x2c, ++ 0x2c, 0x79, 0x2b, 0x36, 0x32, 0x3d, 0x33, 0x32, 0x32, 0x32, 0x32, 0x32, 0x33, 0x24, 0x21, 0x21, ++ 0x21, 0x21, 0x21, 0x21, 0x21, 0x26, 0x2a, 0x2a, 0x2a, 0x22, 0x23, 0x23, 0x23, 0x21, 0x21, 0x25, ++ 0x79, 0x2b, 0x29, 0x29, 0x24, 0x24, 0x24, 0x25, 0x25, 0x25, 0x25, 0x21, 0x26, 0x26, 0x26, 0x21, ++ 0x21, 0x25, 0x21, 0x26, 0x23, 0x23, 0x21, 0x33, 0x32, 0x32, 0x33, 0x3c, 0x25, 0x5c, 0x45, 0x45, ++ 0x45, 0x45, 0x45, 0x41, 0x41, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x43, 0x40, 0x52, ++ 0x20, 0x2c, 0x52, 0x21, 0x32, 0x36, 0x3b, 0x3d, 0x32, 0x32, 0x32, 0x32, 0x32, 0x3a, 0x21, 0x26, ++ 0x26, 0x26, 0x21, 0x21, 0x21, 0x26, 0x23, 0x23, 0x26, 0x26, 0x23, 0x23, 0x23, 0x26, 0x21, 0x21, ++ 0x9d, 0x24, 0x24, 0x24, 0x24, 0x24, 0x25, 0x25, 0x24, 0x21, 0x21, 0x21, 0x26, 0x23, 0x23, 0x26, ++ 0x21, 0x21, 0x21, 0x21, 0x21, 0x26, 0x3a, 0x32, 0x3d, 0x3d, 0x37, 0x27, 0x40, 0x45, 0x45, 0x45, ++ 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, ++ 0x43, 0x52, 0x20, 0x3f, 0x9c, 0x32, 0x33, 0x3c, 0x3b, 0x32, 0x32, 0x32, 0x33, 0x33, 0x25, 0x23, ++ 0x23, 0x21, 0x21, 0x25, 0x21, 0x21, 0x26, 0x21, 0x26, 0x26, 0x26, 0x26, 0x26, 0x21, 0x26, 0x21, ++ 0x2b, 0x26, 0x26, 0x26, 0x21, 0x21, 0x25, 0x21, 0x25, 0x21, 0x21, 0x26, 0x26, 0x26, 0x26, 0x21, ++ 0x21, 0x21, 0x21, 0x21, 0x21, 0x24, 0x36, 0x32, 0x42, 0x32, 0x3d, 0x3f, 0x45, 0x45, 0x45, 0x45, ++ 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, ++ 0x45, 0x45, 0x3f, 0x2d, 0x2b, 0x32, 0x33, 0x33, 0x3b, 0x36, 0x32, 0x32, 0x32, 0x33, 0x38, 0x26, ++ 0x26, 0x26, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x26, 0x26, 0x21, 0x21, ++ 0x25, 0x26, 0x23, 0x26, 0x23, 0x26, 0x26, 0x21, 0x21, 0x21, 0x21, 0x25, 0x25, 0x25, 0x25, 0x25, ++ 0x25, 0x21, 0x21, 0x26, 0x21, 0x25, 0x32, 0x3c, 0x3d, 0x32, 0x2a, 0x45, 0x45, 0x45, 0x45, 0x45, ++ 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, ++ 0x45, 0x45, 0x45, 0x41, 0x3f, 0x35, 0x37, 0x39, 0x3c, 0x42, 0x33, 0x32, 0x32, 0x32, 0x37, 0x29, ++ 0x25, 0x25, 0x21, 0x21, 0x21, 0x26, 0x21, 0x25, 0x21, 0x21, 0x21, 0x21, 0x21, 0x25, 0x21, 0x25, ++ 0x24, 0x26, 0x26, 0x26, 0x26, 0x21, 0x21, 0x26, 0x26, 0x26, 0x21, 0x21, 0x25, 0x25, 0x24, 0x25, ++ 0x24, 0x25, 0x25, 0x21, 0x25, 0x3a, 0x33, 0x34, 0x32, 0x3c, 0x43, 0x45, 0x45, 0x45, 0x45, 0x45, ++ 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, ++ 0x45, 0x45, 0x45, 0x45, 0x45, 0x23, 0x36, 0x9c, 0x42, 0x36, 0x3b, 0x32, 0x32, 0x32, 0x32, 0x22, ++ 0x24, 0x24, 0x24, 0x25, 0x25, 0x21, 0x21, 0x25, 0x25, 0x21, 0x21, 0x21, 0x21, 0x25, 0x25, 0x25, ++ 0x29, 0x25, 0x26, 0x26, 0x21, 0x25, 0x25, 0x25, 0x26, 0x23, 0x26, 0x25, 0x25, 0x24, 0x25, 0x24, ++ 0x24, 0x24, 0x25, 0x25, 0x2b, 0x37, 0x3c, 0x31, 0x33, 0x23, 0x45, 0x9e, 0x32, 0x32, 0x32, 0x32, ++ 0x30, 0x45, 0x45, 0x45, 0x30, 0x32, 0x32, 0x32, 0x30, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, ++ 0x3c, 0x9f, 0xa0, 0x45, 0x45, 0x9d, 0x31, 0x3d, 0x31, 0x32, 0x34, 0x32, 0x32, 0x32, 0x32, 0x42, ++ 0x29, 0x24, 0x24, 0x24, 0x25, 0x24, 0x25, 0x25, 0x25, 0x26, 0x26, 0x26, 0x21, 0x21, 0x21, 0x26, ++ 0x29, 0x21, 0x21, 0x21, 0x25, 0x24, 0x25, 0x25, 0x21, 0x21, 0x21, 0x21, 0x21, 0x25, 0x21, 0x25, ++ 0x25, 0x25, 0x25, 0x21, 0x23, 0x32, 0x42, 0x32, 0x3d, 0x3f, 0x45, 0x45, 0x45, 0x32, 0x32, 0x23, ++ 0x45, 0x45, 0x45, 0x43, 0x45, 0x23, 0x32, 0x20, 0x45, 0x45, 0x30, 0x32, 0x32, 0x45, 0x45, 0x23, ++ 0x32, 0x32, 0xa1, 0x45, 0x45, 0x45, 0x3c, 0x32, 0x32, 0x32, 0x3b, 0x37, 0x32, 0x32, 0x32, 0x33, ++ 0x29, 0x25, 0x25, 0x25, 0x21, 0x21, 0x21, 0x26, 0x21, 0x26, 0x26, 0x23, 0x26, 0x23, 0x23, 0x26, ++ 0x25, 0x26, 0x26, 0x21, 0x25, 0x25, 0x24, 0x21, 0x26, 0x21, 0x26, 0x21, 0x21, 0x21, 0x21, 0x21, ++ 0x26, 0x23, 0x2a, 0x23, 0x42, 0x31, 0x3b, 0x32, 0x2f, 0x45, 0x45, 0x45, 0x45, 0xa1, 0x32, 0x30, ++ 0x45, 0x45, 0x45, 0x43, 0x45, 0x3c, 0xa1, 0x45, 0x45, 0x45, 0x30, 0x32, 0xa1, 0x45, 0x45, 0x45, ++ 0xa1, 0x32, 0x32, 0x45, 0x45, 0x45, 0x35, 0x32, 0x32, 0x32, 0x3d, 0x3c, 0x32, 0x32, 0x32, 0x32, ++ 0x21, 0x21, 0x26, 0x23, 0x22, 0x22, 0x2a, 0x22, 0x22, 0x22, 0x23, 0x23, 0x23, 0x23, 0x26, 0x21, ++ 0x21, 0x26, 0x26, 0x21, 0x21, 0x25, 0x25, 0x25, 0x21, 0x21, 0x26, 0x26, 0x26, 0x21, 0x21, 0x26, ++ 0x22, 0x27, 0x2f, 0x26, 0x32, 0x3b, 0x37, 0x33, 0x2b, 0x45, 0x45, 0x45, 0x45, 0x30, 0x32, 0xa1, ++ 0x45, 0x45, 0x45, 0x40, 0x23, 0x32, 0x20, 0x45, 0x45, 0x45, 0x32, 0x32, 0x30, 0x45, 0x45, 0x45, ++ 0x30, 0x32, 0x32, 0x45, 0x45, 0x45, 0x3e, 0x32, 0x32, 0x32, 0x3d, 0x3d, 0x32, 0x32, 0x32, 0x32, ++ 0x3e, 0x26, 0x22, 0x27, 0x2f, 0x27, 0x28, 0x2a, 0x26, 0x21, 0x21, 0x26, 0x23, 0x26, 0x26, 0x25, ++ 0x25, 0x25, 0x21, 0x21, 0x21, 0x25, 0x25, 0x25, 0x21, 0x25, 0x21, 0x21, 0x21, 0x21, 0x21, 0x26, ++ 0x28, 0x2e, 0x2a, 0x3b, 0x33, 0x3b, 0x33, 0x3d, 0x41, 0x45, 0x45, 0x45, 0x45, 0x9f, 0x32, 0x32, ++ 0x45, 0x45, 0x45, 0x40, 0x3c, 0x9f, 0x45, 0x45, 0x45, 0xa0, 0x32, 0x32, 0x9e, 0x45, 0x45, 0x45, ++ 0x3c, 0x32, 0x9f, 0x45, 0x45, 0x45, 0x27, 0x32, 0x32, 0x32, 0x3d, 0x36, 0x32, 0x32, 0x32, 0x32, ++ 0x34, 0x21, 0x28, 0x2e, 0x2f, 0x27, 0x2a, 0x26, 0x25, 0x24, 0x25, 0x26, 0x22, 0x23, 0x25, 0x29, ++ 0x2b, 0x24, 0x25, 0x21, 0x21, 0x24, 0x25, 0x24, 0x25, 0x25, 0x21, 0x21, 0x21, 0x21, 0x21, 0x26, ++ 0x2a, 0x2e, 0x2a, 0x32, 0x32, 0x39, 0x32, 0x9c, 0x45, 0x45, 0x45, 0x45, 0x45, 0x9e, 0x32, 0x32, ++ 0x45, 0x45, 0x41, 0x28, 0x32, 0xa0, 0x45, 0x45, 0x45, 0x9e, 0x32, 0x32, 0x20, 0x45, 0xa0, 0x30, ++ 0x32, 0xa1, 0xa0, 0x45, 0x45, 0x45, 0x28, 0x32, 0x32, 0x32, 0x3c, 0x33, 0x32, 0x32, 0x32, 0x32, ++ 0x3c, 0x25, 0x28, 0x27, 0x27, 0x22, 0x21, 0x21, 0x24, 0x2b, 0x24, 0x22, 0x28, 0x26, 0x25, 0x29, ++ 0x79, 0x24, 0x21, 0x21, 0x25, 0x25, 0x24, 0x25, 0x21, 0x21, 0x26, 0x26, 0x26, 0x21, 0x25, 0x25, ++ 0x23, 0x21, 0x3c, 0x32, 0x32, 0x34, 0x33, 0x3e, 0x45, 0x45, 0x45, 0x45, 0x45, 0x20, 0x32, 0x32, ++ 0x9e, 0x45, 0xa2, 0xa3, 0x9f, 0x45, 0x45, 0x45, 0x45, 0x9f, 0x32, 0x32, 0x30, 0x30, 0x32, 0x30, ++ 0x9e, 0x45, 0x45, 0x45, 0x45, 0x45, 0x23, 0x32, 0x32, 0x32, 0x3b, 0x32, 0x32, 0x32, 0x32, 0x32, ++ 0x33, 0x29, 0x26, 0x27, 0x28, 0x26, 0x25, 0x24, 0x24, 0x29, 0x21, 0x28, 0x28, 0x26, 0x29, 0x2b, ++ 0x20, 0x21, 0x22, 0x23, 0x25, 0x25, 0x25, 0x25, 0x26, 0x21, 0x23, 0x22, 0x22, 0x21, 0x25, 0x21, ++ 0x22, 0x2a, 0x32, 0x32, 0x36, 0x9c, 0x32, 0x28, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x32, 0x32, ++ 0x9e, 0x45, 0x22, 0x32, 0xa0, 0x45, 0x45, 0x45, 0x45, 0x30, 0x32, 0xa1, 0x9e, 0xa1, 0x32, 0x3c, ++ 0x20, 0x45, 0x45, 0x45, 0x45, 0x45, 0x23, 0x32, 0x32, 0x33, 0x3b, 0x32, 0x32, 0x32, 0x32, 0x32, ++ 0x33, 0x29, 0x23, 0x27, 0x28, 0x26, 0x24, 0x29, 0x29, 0x25, 0x23, 0x27, 0x2a, 0x24, 0x2b, 0x2c, ++ 0x21, 0x27, 0x27, 0x2a, 0x21, 0x24, 0x25, 0x21, 0x26, 0x26, 0x22, 0x22, 0x26, 0x26, 0x26, 0x22, ++ 0x27, 0x38, 0x32, 0x32, 0x31, 0x38, 0x37, 0x23, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x3c, 0x32, ++ 0x30, 0xa0, 0x32, 0x2f, 0x45, 0x45, 0x45, 0x45, 0x45, 0x3c, 0x32, 0x30, 0x45, 0x45, 0xa1, 0x32, ++ 0x3c, 0x45, 0x45, 0x45, 0x45, 0x45, 0x23, 0x32, 0x32, 0x31, 0x36, 0x32, 0x32, 0x32, 0x33, 0x32, ++ 0x32, 0x25, 0x27, 0x2e, 0x2a, 0x25, 0x29, 0x29, 0x24, 0x25, 0x26, 0x23, 0x21, 0x24, 0x2b, 0x29, ++ 0x22, 0x27, 0x27, 0x22, 0x25, 0x24, 0x25, 0x21, 0x26, 0x26, 0x22, 0x22, 0x26, 0x26, 0x26, 0x2a, ++ 0x28, 0x9c, 0x32, 0x33, 0x33, 0x3d, 0x3c, 0x21, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x30, 0x32, ++ 0x30, 0x9f, 0xa4, 0x43, 0x45, 0x45, 0x45, 0x45, 0x45, 0x32, 0x32, 0x23, 0x45, 0x45, 0x9e, 0x32, ++ 0x32, 0x20, 0x45, 0x45, 0x45, 0x45, 0x27, 0x32, 0x37, 0x39, 0x37, 0x31, 0x33, 0x32, 0x32, 0x32, ++ 0x33, 0x23, 0x28, 0x2a, 0x26, 0x24, 0x29, 0x29, 0x24, 0x25, 0x25, 0x21, 0x24, 0x24, 0x29, 0x24, ++ 0x28, 0x2e, 0x27, 0x26, 0x25, 0x29, 0x24, 0x21, 0x26, 0x26, 0x23, 0x23, 0x26, 0x26, 0x23, 0x23, ++ 0x26, 0x2f, 0x37, 0x53, 0x53, 0x37, 0x3c, 0x23, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x9f, 0x32, ++ 0x32, 0x32, 0x22, 0x40, 0x45, 0x45, 0x45, 0x45, 0x9e, 0x32, 0x32, 0x9e, 0x45, 0x45, 0xa0, 0x32, ++ 0x32, 0x9f, 0x45, 0x45, 0x45, 0x45, 0x30, 0x31, 0x3c, 0x31, 0x33, 0x36, 0x3c, 0x3b, 0x3c, 0x32, ++ 0x3a, 0x22, 0x26, 0x21, 0x25, 0x24, 0x29, 0x29, 0x24, 0x21, 0x21, 0x21, 0x25, 0x25, 0x25, 0x25, ++ 0x28, 0x28, 0x2a, 0x25, 0x24, 0x29, 0x24, 0x25, 0x26, 0x26, 0x23, 0x26, 0x26, 0x26, 0x26, 0x26, ++ 0x21, 0xa5, 0xa6, 0x56, 0xa7, 0xa8, 0x48, 0x35, 0x3f, 0x45, 0x45, 0x45, 0x45, 0x45, 0x9e, 0x32, ++ 0x32, 0x3c, 0x41, 0x43, 0x45, 0x45, 0x45, 0x45, 0x23, 0x32, 0x32, 0x45, 0x45, 0x45, 0x45, 0xa1, ++ 0x32, 0x3c, 0x45, 0x45, 0x45, 0x41, 0x51, 0x36, 0x32, 0x32, 0x32, 0x32, 0x32, 0x37, 0x3a, 0x3d, ++ 0x2a, 0x26, 0x21, 0x24, 0x29, 0x29, 0x29, 0x24, 0x25, 0x21, 0x26, 0x26, 0x21, 0x21, 0x21, 0x21, ++ 0x2a, 0x2a, 0x26, 0x25, 0x29, 0x29, 0x24, 0x21, 0x26, 0x22, 0x23, 0x23, 0x26, 0x26, 0x25, 0x25, ++ 0x9d, 0xa9, 0xaa, 0xa7, 0x7d, 0xab, 0x5e, 0x4a, 0x34, 0x52, 0x45, 0x45, 0x45, 0x45, 0x20, 0x32, ++ 0x32, 0x23, 0x43, 0x40, 0x45, 0x45, 0x45, 0x30, 0x3c, 0x32, 0x32, 0x30, 0x23, 0x45, 0x45, 0x20, ++ 0x32, 0x32, 0x3c, 0x30, 0xac, 0x58, 0xad, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x36, 0x42, 0x3c, ++ 0x86, 0x24, 0x24, 0x24, 0x24, 0x24, 0x25, 0x25, 0x21, 0x26, 0x26, 0x26, 0x21, 0x21, 0x25, 0x25, ++ 0x26, 0x23, 0x21, 0x25, 0x24, 0x24, 0x25, 0x26, 0x22, 0x2a, 0x22, 0x26, 0x21, 0x21, 0x2b, 0x79, ++ 0xae, 0x55, 0xaf, 0xab, 0x7d, 0xb0, 0xa7, 0x4f, 0x71, 0x39, 0x20, 0x45, 0x45, 0x45, 0x45, 0x9e, ++ 0x9e, 0x45, 0x41, 0x40, 0x45, 0x45, 0x45, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x20, 0x45, 0x45, 0x45, ++ 0xa0, 0x9e, 0x9e, 0x9e, 0xb1, 0xb2, 0x68, 0xb3, 0x32, 0x32, 0x32, 0x32, 0x32, 0x36, 0x37, 0xb4, ++ 0xce, 0xcf, 0x24, 0x24, 0x24, 0x24, 0x25, 0x21, 0x21, 0x26, 0x21, 0x25, 0x25, 0x25, 0x25, 0x25, ++ 0x21, 0x22, 0x26, 0x25, 0x24, 0x24, 0x21, 0x26, 0x28, 0x28, 0x25, 0x2c, 0xb5, 0xb6, 0xb7, 0xb8, ++ 0x6c, 0xb9, 0xa7, 0xab, 0x7e, 0xa7, 0x56, 0x7d, 0x5a, 0xb3, 0x36, 0x24, 0x45, 0x45, 0x45, 0x45, ++ 0x45, 0x45, 0x41, 0x43, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, ++ 0x45, 0x45, 0x45, 0x45, 0xb1, 0x56, 0xb4, 0xb3, 0x32, 0x32, 0x32, 0x32, 0x32, 0xb3, 0xba, 0x60, ++ 0x7e, 0xd0, 0x20, 0x25, 0x21, 0x25, 0x25, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, 0x21, ++ 0x25, 0x2a, 0x26, 0x25, 0x29, 0x29, 0x25, 0x23, 0x2a, 0x26, 0x50, 0xbb, 0x80, 0x55, 0xbc, 0x80, ++ 0xb9, 0x60, 0xa7, 0xb0, 0xab, 0xab, 0xab, 0xab, 0x57, 0x6a, 0x33, 0x33, 0x2a, 0x45, 0x45, 0x45, ++ 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, ++ 0x45, 0x45, 0x45, 0x43, 0x60, 0x6d, 0x54, 0x48, 0x32, 0x32, 0x32, 0x32, 0xb3, 0xbd, 0x8a, 0x61, ++ 0x56, 0xd1, 0x20, 0x21, 0x21, 0x21, 0x25, 0x21, 0x21, 0x26, 0x23, 0x23, 0x23, 0x23, 0x23, 0x26, ++ 0x24, 0x26, 0x21, 0x24, 0x29, 0x24, 0x26, 0x28, 0x28, 0xbe, 0xbb, 0x7c, 0x56, 0x74, 0x74, 0x74, ++ 0xbf, 0xa7, 0xb0, 0xab, 0xab, 0xab, 0xab, 0xab, 0x7e, 0xc0, 0x71, 0x32, 0x32, 0x3e, 0x45, 0x45, ++ 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, ++ 0x45, 0x45, 0x52, 0x80, 0x74, 0x6d, 0x89, 0xc1, 0x6a, 0xc2, 0x4a, 0x6a, 0xc3, 0x76, 0x6d, 0x74, ++ 0xa7, 0xd2, 0x24, 0x25, 0x21, 0x21, 0x26, 0x26, 0x22, 0x22, 0x2a, 0x22, 0x23, 0x26, 0x26, 0x26, ++ 0x2b, 0x25, 0x24, 0x29, 0x29, 0x24, 0x26, 0x28, 0x2a, 0xc4, 0x84, 0x6d, 0x56, 0xab, 0xab, 0xab, ++ 0xa7, 0xb0, 0xab, 0xab, 0xb0, 0xab, 0xab, 0xab, 0x7e, 0x7d, 0xc5, 0x32, 0x32, 0x32, 0x9c, 0x43, ++ 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, ++ 0x45, 0x45, 0x2d, 0x80, 0x57, 0x6d, 0x90, 0x91, 0xc6, 0xc7, 0xc7, 0xc8, 0xc9, 0xb9, 0xbf, 0xa7, ++ 0xa7, 0x60, 0xbe, 0x23, 0x26, 0x26, 0x26, 0x26, 0x26, 0x26, 0x21, 0x21, 0x25, 0x25, 0x25, 0x25, ++ 0x29, 0x24, 0x24, 0x24, 0x24, 0x26, 0x2a, 0x2a, 0x23, 0xca, 0x84, 0x6d, 0xb0, 0xab, 0xab, 0xab, ++ 0xa7, 0xab, 0xab, 0xa7, 0xab, 0xab, 0xa7, 0xb0, 0x7d, 0xa7, 0x4c, 0x4a, 0x32, 0x32, 0x32, 0x3d, ++ 0x2c, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, ++ 0x45, 0x8d, 0xcb, 0x6c, 0x6d, 0x60, 0x5f, 0x55, 0x84, 0x6c, 0x84, 0x90, 0x7c, 0xbf, 0xb0, 0xab, ++ 0xa7, 0xa7, 0xd3, 0x92, 0x26, 0x26, 0x26, 0x26, 0x25, 0x25, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, ++ 0x25, 0x25, 0x25, 0x21, 0x21, 0x23, 0x2a, 0x2a, 0x21, 0x2d, 0xc9, 0xb1, 0x74, 0xab, 0xab, 0xab, ++ 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xa7, 0xab, 0x62, 0xb4, 0x48, 0x32, 0x32, 0x32, ++ 0x31, 0x70, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, ++ 0x41, 0x79, 0x97, 0xc9, 0xb9, 0x74, 0x74, 0xb1, 0xb9, 0xb9, 0x5f, 0x6d, 0x74, 0xb0, 0xab, 0xab, ++ 0x56, 0xab, 0xd4, 0xd5, 0xd6, 0x21, 0x26, 0x26, 0x25, 0x24, 0x29, 0x29, 0x29, 0x24, 0x25, 0x25, ++ 0x24, 0x21, 0x21, 0x26, 0x23, 0x2a, 0x2a, 0x26, 0x25, 0x2d, 0xbb, 0x5f, 0xa7, 0xab, 0xab, 0xab, ++ 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xa7, 0x7e, 0x66, 0xcc, 0x32, 0x32, 0x32, ++ 0x32, 0x21, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, ++ 0xa2, 0x9d, 0xcd, 0x73, 0xb9, 0x74, 0xbf, 0x74, 0x74, 0x74, 0xaf, 0x74, 0xbf, 0xa7, 0xab, 0xb0, ++ 0xab, 0xab, 0xb0, 0x60, 0xd4, 0xd7, 0x25, 0x26, 0x25, 0x24, 0x29, 0x24, 0x25, 0x25, 0x21, 0x21, ++ 0x25, 0x21, 0x26, 0x23, 0x22, 0x22, 0x23, 0x21, 0x25, 0x2b, 0xd8, 0xd9, 0x56, 0xab, 0xab, 0xab, ++ 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xb0, 0x56, 0x58, 0x7b, 0xda, 0x32, 0x32, ++ 0x32, 0x26, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x41, ++ 0x43, 0x2f, 0xdb, 0x73, 0xb9, 0x74, 0xb0, 0xa7, 0xa7, 0xb0, 0xb0, 0xab, 0xab, 0xab, 0xab, 0xab, ++ 0xab, 0x56, 0xab, 0xab, 0xab, 0xd4, 0xb7, 0x29, 0x24, 0x24, 0x24, 0x21, 0x26, 0x26, 0x26, 0x21, ++ 0x24, 0x26, 0x22, 0x2a, 0x28, 0x2a, 0x21, 0x25, 0x25, 0x29, 0xb8, 0xd9, 0xbf, 0xab, 0xab, 0xab, ++ 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xa7, 0xa7, 0xb0, 0x7d, 0x62, 0x90, 0x31, 0x36, ++ 0x28, 0x40, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x41, 0x45, 0x41, 0x40, ++ 0x38, 0x33, 0xba, 0x73, 0xb9, 0xa7, 0xa7, 0xa7, 0xa7, 0xa7, 0xa7, 0xa7, 0xab, 0xab, 0xab, 0xb0, ++ 0xab, 0xab, 0x7e, 0xab, 0xb0, 0xab, 0xf9, 0xd6, 0x2b, 0x2b, 0x24, 0x21, 0x26, 0x23, 0x26, 0x26, ++ 0x25, 0x26, 0x2a, 0x2a, 0x2a, 0x22, 0x21, 0x24, 0x25, 0x24, 0xd8, 0x5f, 0xa7, 0xa7, 0xab, 0xab, ++ 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xa7, 0xb0, 0xa7, 0x7e, 0x4d, 0x94, 0x41, ++ 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x41, 0x41, 0x52, 0x34, ++ 0x32, 0x32, 0xda, 0x91, 0xb9, 0xbf, 0xab, 0xa7, 0xab, 0xb0, 0xab, 0xab, 0xab, 0xab, 0xab, 0xb0, ++ 0xab, 0xb0, 0xa7, 0xa7, 0xa7, 0x74, 0xd4, 0xfa, 0x2b, 0x29, 0x25, 0x26, 0x22, 0x23, 0x21, 0x21, ++ 0x21, 0x26, 0x2a, 0x28, 0x2a, 0x26, 0x25, 0x24, 0x21, 0xbe, 0xc9, 0x5f, 0xbf, 0xa7, 0xab, 0xab, ++ 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0x56, 0x61, 0x4f, 0xca, ++ 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x45, 0x41, 0x45, 0x41, 0x45, 0x40, 0x22, 0x31, 0x32, ++ 0x32, 0x32, 0xc5, 0xc6, 0x6d, 0x56, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, ++ 0x7d, 0x7d, 0xab, 0xa7, 0x74, 0x7c, 0xce, 0x3f, 0x29, 0x26, 0x2a, 0x28, 0x28, 0x2a, 0x23, 0x26, ++ 0x26, 0x23, 0x2a, 0x27, 0x2a, 0x21, 0x24, 0x24, 0x21, 0x8b, 0x84, 0x74, 0xbf, 0xab, 0xab, 0xab, ++ 0xab, 0xab, 0xa7, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xa7, 0x74, 0xdc, 0xdd, ++ 0x29, 0x41, 0x45, 0x41, 0x45, 0x45, 0x41, 0x45, 0x41, 0x41, 0x40, 0x21, 0x3b, 0x33, 0x32, 0x32, ++ 0x32, 0x32, 0xcc, 0xc6, 0xb9, 0xbf, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, ++ 0xab, 0x56, 0x56, 0x4d, 0xd8, 0xfb, 0xcf, 0x29, 0x26, 0x28, 0x2e, 0x2e, 0x27, 0x2a, 0x26, 0x26, ++ 0x28, 0x2a, 0x28, 0x28, 0x2a, 0x26, 0x24, 0x25, 0x2b, 0xde, 0xdf, 0xaf, 0xa7, 0xa7, 0xab, 0xab, ++ 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0xab, 0x56, 0xb1, 0x7f, 0x7a, ++ 0x3d, 0x42, 0x28, 0x25, 0x29, 0x29, 0x24, 0x26, 0x27, 0x49, 0x37, 0x32, 0x32, 0x32, 0x32, 0x32, ++ 0x32, 0x31, 0xe0, 0xc6, 0xaf, 0x74, 0xab, 0xab, 0xab, 0xa7, 0xa7, 0xab, 0xab, 0xa7, 0xa7, 0xb0, ++ 0xaa, 0x80, 0xd8, 0xae, 0xfa, 0x92, 0x24, 0x26, 0x28, 0x3e, 0x2f, 0x27, 0x2a, 0x26, 0x21, 0x21, ++ 0x27, 0x2a, 0x2a, 0x28, 0x22, 0x21, 0x24, 0x25, 0xbe, 0xe1, 0xdf, 0x5f, 0x6d, 0x6d, 0x74, 0x74, ++ 0x56, 0x56, 0xa7, 0x56, 0xa7, 0xa7, 0xab, 0xb0, 0xab, 0xab, 0xab, 0xb0, 0xb0, 0x6d, 0x84, 0xe2, ++ 0x6a, 0x32, 0x33, 0x33, 0x32, 0x32, 0x33, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, ++ 0x32, 0x48, 0xe0, 0xc6, 0x5f, 0xbf, 0xab, 0xab, 0xa7, 0xb0, 0xab, 0xab, 0x56, 0xaf, 0xb1, 0xb9, ++ 0x6c, 0xfb, 0x20, 0x2b, 0x2b, 0x29, 0x26, 0x27, 0x3e, 0x3e, 0x27, 0x2a, 0x26, 0x21, 0x25, 0x25, ++ 0x21, 0x21, 0x26, 0x22, 0x22, 0x21, 0x24, 0x24, 0x29, 0x5d, 0x83, 0xc6, 0xc9, 0x7f, 0x55, 0xd9, ++ 0xd9, 0xb9, 0xb9, 0xaf, 0x74, 0x74, 0xa7, 0xab, 0xab, 0xab, 0xab, 0xab, 0x74, 0x5f, 0x88, 0x7a, ++ 0xba, 0xb3, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, ++ 0x32, 0x48, 0xe3, 0xc7, 0xdf, 0x6d, 0xa7, 0xa7, 0xa7, 0xa7, 0x56, 0x74, 0xb9, 0x5f, 0xbc, 0x8a, ++ 0xc4, 0x24, 0x24, 0x2b, 0x2b, 0x25, 0x28, 0x3e, 0x38, 0x2e, 0x2a, 0x26, 0x21, 0x24, 0x25, 0x24, ++ 0x20, 0x24, 0x21, 0x23, 0x26, 0x21, 0x24, 0x25, 0x21, 0x2d, 0xe4, 0xe5, 0xe6, 0x54, 0xe7, 0x88, ++ 0xc6, 0xc6, 0x89, 0x89, 0xdf, 0xd9, 0xb1, 0x74, 0x74, 0xbf, 0xbf, 0xbf, 0x5f, 0x7f, 0x95, 0x82, ++ 0xba, 0xb3, 0x32, 0x32, 0xb3, 0x32, 0x33, 0x32, 0x32, 0x32, 0x33, 0x32, 0x32, 0x32, 0x32, 0x32, ++ 0x33, 0x36, 0xcc, 0xe8, 0x91, 0xd9, 0x6d, 0x74, 0x74, 0xaf, 0xb9, 0xd9, 0x89, 0x5e, 0xe9, 0x70, ++ 0x25, 0x25, 0x29, 0x2b, 0x2b, 0x25, 0x27, 0x2f, 0x2e, 0x2a, 0x26, 0x21, 0x25, 0x24, 0x24, 0x24, ++ 0x70, 0x21, 0x26, 0x23, 0x26, 0x25, 0x29, 0x24, 0x21, 0x21, 0x24, 0x29, 0x2b, 0x2b, 0xd6, 0xea, ++ 0xeb, 0x87, 0xec, 0x87, 0xe8, 0xc7, 0x91, 0x89, 0x90, 0x80, 0xb9, 0x90, 0x91, 0xe8, 0x82, 0xc3, ++ 0x6a, 0x3b, 0x22, 0x21, 0x25, 0x25, 0x25, 0x25, 0x24, 0x24, 0x24, 0x24, 0x25, 0x25, 0x25, 0x23, ++ 0x2e, 0x39, 0xda, 0xed, 0xc7, 0x84, 0xd9, 0xd9, 0x5f, 0xd9, 0x89, 0xc6, 0x96, 0x8b, 0x2b, 0x25, ++ 0x21, 0x21, 0x24, 0x2b, 0x24, 0x26, 0x28, 0x2e, 0x2a, 0x23, 0x26, 0x21, 0x24, 0x29, 0x29, 0x24, ++ 0x79, 0x28, 0x28, 0x22, 0x21, 0x25, 0x29, 0x24, 0x21, 0x26, 0x25, 0x24, 0x29, 0x24, 0x21, 0x25, ++ 0x29, 0xca, 0x93, 0x99, 0xee, 0x7a, 0x7a, 0xef, 0xe7, 0x96, 0x88, 0xe7, 0xed, 0x82, 0xc3, 0x5b, ++ 0xf0, 0x29, 0x26, 0x26, 0x21, 0x21, 0x21, 0x26, 0x21, 0x25, 0x25, 0x24, 0x21, 0x21, 0x25, 0x24, ++ 0x2b, 0x70, 0xf1, 0x82, 0xef, 0xe7, 0x88, 0xc6, 0xc6, 0x88, 0x87, 0x8f, 0xbe, 0x29, 0x29, 0x25, ++ 0x25, 0x25, 0x24, 0x29, 0x21, 0x22, 0x28, 0x27, 0x28, 0x28, 0x2a, 0x26, 0x25, 0x29, 0x24, 0x21, ++ 0x21, 0x3e, 0x27, 0x22, 0x21, 0x25, 0x24, 0x25, 0x26, 0x21, 0x25, 0x24, 0x24, 0x25, 0x25, 0x25, ++ 0x25, 0x24, 0x26, 0x2a, 0x21, 0x25, 0x9b, 0xf2, 0xf3, 0xf3, 0x82, 0x82, 0xe3, 0xc3, 0xda, 0x2c, ++ 0x21, 0x22, 0x26, 0x21, 0x25, 0x24, 0x25, 0x21, 0x21, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x29, ++ 0x2b, 0x2c, 0x9b, 0xc5, 0xc3, 0xc1, 0xe2, 0xef, 0xed, 0x72, 0xf2, 0x92, 0x25, 0x24, 0x24, 0x24, ++ 0x21, 0x25, 0x24, 0x25, 0x21, 0x2a, 0x28, 0x28, 0x28, 0x28, 0x2a, 0x21, 0x29, 0x29, 0x25, 0x21, ++ 0x28, 0x3e, 0x27, 0x23, 0x21, 0x25, 0x24, 0x24, 0x21, 0x26, 0x25, 0x24, 0x29, 0x24, 0x21, 0x21, ++ 0x21, 0x25, 0x26, 0x2a, 0x2a, 0x2a, 0x28, 0x25, 0x97, 0x86, 0xf4, 0x5b, 0xda, 0xf5, 0x2b, 0x25, ++ 0x26, 0x26, 0x21, 0x25, 0x25, 0x25, 0x21, 0x21, 0x21, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0x24, ++ 0x29, 0x25, 0x2a, 0x21, 0xf0, 0xf6, 0xdd, 0xf7, 0xf7, 0xf8, 0xbe, 0x21, 0x21, 0x24, 0x29, 0x24, ++ 0x21, 0x26, 0x25, 0x21, 0x26, 0x2a, 0x2a, 0x2a, 0x28, 0x2a, 0x26, 0x29, 0x2b, 0x2b, 0x21, 0x26, ++ 0x2a, 0x27, 0x2a, 0x21, 0x25, 0x25, 0x25, 0x24, 0x25, 0x21, 0x25, 0x24, 0x29, 0x24, 0x21, 0x26, ++ 0x26, 0x21, 0x26, 0x26, 0x26, 0x26, 0x26, 0x21, 0x24, 0x92, 0x20, 0x20, 0x24, 0x21, 0x21, 0x21, ++ 0x21, 0x26, 0x25, 0x25, 0x21, 0x26, 0x26, 0x21, 0x21, 0x21, 0x24, 0x24, 0x24, 0x24, 0x25, 0x24, ++ 0x25, 0x26, 0x2a, 0x28, 0x22, 0x25, 0x2b, 0x2b, 0x2b, 0x24, 0x25, 0x21, 0x25, 0x24, 0x29, 0x24, ++ 0x25, 0x26, 0x26, 0x21, 0x26, 0x26, 0x26, 0x26, 0x26, 0x21, 0x29, 0x2b, 0x20, 0x29, 0x26, 0x23, ++ 0x26, 0x26, 0x26, 0x25, 0x25, 0x25, 0x25, 0x24, 0x24, 0x21, 0x25, 0x24, 0x24, 0x24, 0x25, 0x21, ++ 0x26, 0x21, 0x21, 0x25, 0x25, 0x25, 0x25, 0x24, 0x2b, 0x20, 0x2b, 0x25, 0x26, 0x26, 0x21, 0x21, ++ 0x23, 0x23, 0x26, 0x26, 0x23, 0x26, 0x26, 0x21, 0x21, 0x25, 0x25, 0x24, 0x24, 0x24, 0x25, 0x25, ++ 0x24, 0x21, 0x23, 0x23, 0x21, 0x21, 0x25, 0x25, 0x25, 0x24, 0x25, 0x25, 0x25, 0x24, 0x24, 0x25, ++ 0x25, 0x21, 0x26, 0x21, 0x21, 0x25, 0x25, 0x25, 0x25, 0x24, 0x2b, 0x20, 0x2b, 0x24, 0x26, 0x26, ++ 0x21, 0x21, 0x21, 0x21, 0x25, 0x25, 0x25, 0x25, 0x25, 0x21, 0x21, 0x21, 0x25, 0x25, 0x25, 0x21, ++ 0x26, 0x21, 0x25, 0x25, 0x24, 0x24, 0x29, 0x29, 0x2b, 0x2b, 0x24, 0x21, 0x23, 0x26, 0x21, 0x26, ++ 0x22, 0x2a, 0x23, 0x23, 0x22, 0x23, 0x21, 0x21, 0x25, 0x25, 0x24, 0x29, 0x24, 0x24, 0x24, 0x24, ++ 0x24, 0x24, 0x25, 0x21, 0x21, 0x25, 0x25, 0x25, 0x25, 0x24, 0x25, 0x21, 0x21, 0x21, 0x25, 0x25, ++ 0x25, 0x21, 0x26, 0x26, 0x25, 0x25, 0x24, 0x24, 0x29, 0x29, 0x2b, 0x2b, 0x24, 0x26, 0x23, 0x26 ++}; ++ ++#endif ++ ++#ifdef INCLUDE_LINUX_LOGO16 ++ ++unsigned char linux_logo16_red[] __initdata = { ++0x06, 0xab, 0xef, 0xcc, 0x56, 0xe1, 0x77, 0xfc, 0xc8, 0x34, 0xcd, 0xa6, 0x79, 0xad, 0x96, 0xf3 ++}; ++ ++unsigned char linux_logo16_green[] __initdata = { ++0x06, 0x87, 0xce, 0xa8, 0x52, 0xa8, 0x76, 0xfc, 0x92, 0x30, 0xcb, 0x72, 0x53, 0xad, 0x96, 0xbc ++}; ++ ++unsigned char linux_logo16_blue[] __initdata = { ++0x07, 0x23, 0x20, 0x39, 0x49, 0x0e, 0x72, 0xfa, 0x15, 0x28, 0xc4, 0x10, 0x0e, 0xab, 0x94, 0x10 ++}; ++ ++unsigned char linux_logo16[] __initdata = { ++0xae, 0xee, 0xed, 0xdd, 0xee, 0xee, 0xee, 0xde, 0xe6, 0x6d, 0xdd, 0xdd, 0xe6, 0x6d, 0xaa, 0xdd, 0xdd, 0xee, 0xdd, 0xee, 0xed, 0xdd, 0xaa, 0xaa, 0xaa, 0xae, 0xee, 0xed, 0xdd, 0xee, 0xee, 0xee, 0xde, 0xe6, 0x6d, 0xdd, 0xdd, 0xe6, 0x6d, 0xaa, ++0xe6, 0x66, 0xdd, 0xde, 0xee, 0xe6, 0xee, 0xee, 0x66, 0x6e, 0xad, 0xdd, 0xee, 0xed, 0xad, 0xdd, 0xde, 0xee, 0xee, 0xdd, 0xdd, 0xde, 0xdd, 0xdd, 0xdd, 0xe6, 0x66, 0xdd, 0xde, 0xee, 0xe6, 0xee, 0xee, 0x66, 0x6e, 0xad, 0xdd, 0xee, 0xdd, 0xdd, ++0xe6, 0x6e, 0xed, 0xde, 0xee, 0xee, 0xee, 0xe6, 0x6e, 0xed, 0xdd, 0xdd, 0xed, 0xdd, 0xdd, 0xdd, 0xee, 0xed, 0xdd, 0xde, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xe6, 0x6e, 0xed, 0xde, 0xee, 0xee, 0xee, 0xe6, 0x6e, 0xed, 0xdd, 0xdd, 0xee, 0xdd, 0xad, ++0x66, 0x6e, 0xdd, 0xde, 0xee, 0x6e, 0xee, 0xee, 0xee, 0xdd, 0xad, 0xdd, 0xee, 0xed, 0xdd, 0xde, 0xee, 0xd4, 0x00, 0x00, 0x00, 0x09, 0xdd, 0xdd, 0xee, 0x66, 0x6e, 0xdd, 0xde, 0xee, 0x6e, 0xee, 0xee, 0xee, 0xdd, 0xad, 0xdd, 0xde, 0xde, 0xdd, ++0x66, 0x6d, 0xdd, 0xdd, 0xee, 0xee, 0xee, 0xee, 0xed, 0xdd, 0xdd, 0xde, 0xee, 0xde, 0xee, 0xed, 0xd6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0xde, 0xee, 0x66, 0x6d, 0xdd, 0xdd, 0xee, 0xee, 0xee, 0xee, 0xed, 0xdd, 0xdd, 0xde, 0xee, 0xee, 0xee, ++0x6e, 0xed, 0xad, 0xde, 0xee, 0x6e, 0xee, 0xdd, 0xda, 0xdd, 0xdd, 0xee, 0xee, 0xee, 0xdd, 0xed, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90, 0x06, 0xee, 0x6e, 0xed, 0xad, 0xde, 0xee, 0x6e, 0xee, 0xdd, 0xda, 0xdd, 0xdd, 0xee, 0xee, 0xde, 0xdd, ++0xee, 0xed, 0xdd, 0xde, 0xe6, 0xee, 0xee, 0xdd, 0xdd, 0xdd, 0xde, 0xde, 0xdd, 0xdd, 0xed, 0xd4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x49, 0x00, 0x4d, 0xee, 0xed, 0xdd, 0xde, 0xe6, 0xee, 0xee, 0xdd, 0xdd, 0xdd, 0xde, 0xee, 0xed, 0xdd, 0xde, ++0xd6, 0xed, 0xdd, 0xee, 0x66, 0xee, 0xed, 0xdd, 0xed, 0xdd, 0xed, 0xee, 0xee, 0xee, 0xde, 0xd0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x64, 0x90, 0x06, 0xd6, 0xed, 0xdd, 0xee, 0x66, 0xee, 0xed, 0xdd, 0xde, 0xde, 0xde, 0xde, 0xed, 0xee, 0xed, ++0xee, 0xed, 0xdd, 0xde, 0x6e, 0xee, 0xdd, 0xdd, 0xde, 0xed, 0xde, 0xee, 0xee, 0xee, 0xee, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x44, 0x90, 0x00, 0xde, 0xee, 0xdd, 0xde, 0x6e, 0xee, 0xdd, 0xdd, 0xde, 0xed, 0xde, 0xde, 0xee, 0xee, 0xee, ++0xde, 0xed, 0xdd, 0xe6, 0x6e, 0xed, 0xdd, 0xde, 0xee, 0xee, 0xee, 0xee, 0xe6, 0xee, 0xed, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x6e, 0xdd, 0xad, 0xe6, 0x6e, 0xed, 0xdd, 0xde, 0xee, 0xee, 0xee, 0xe6, 0x6e, 0x6e, 0xee, ++0xdd, 0xda, 0xdd, 0xee, 0x6d, 0xdd, 0xdd, 0xde, 0xee, 0xee, 0xee, 0xee, 0xee, 0xde, 0xed, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0xdd, 0xdd, 0xee, 0x6d, 0xdd, 0xdd, 0xde, 0xee, 0xee, 0xee, 0xee, 0xee, 0xdd, 0xed, ++0xdd, 0xdd, 0xde, 0x66, 0xee, 0xdd, 0xde, 0xee, 0x6e, 0xee, 0xee, 0xed, 0xdd, 0xdd, 0xde, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0xdd, 0xde, 0x66, 0xee, 0xdd, 0xde, 0xee, 0x6e, 0xee, 0xee, 0xed, 0xdd, 0xdd, 0xdd, ++0xdd, 0xde, 0xde, 0xe6, 0xdd, 0xde, 0xe6, 0xee, 0xee, 0xee, 0xee, 0xdd, 0xda, 0xdd, 0xd6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90, 0x00, 0x00, 0x04, 0xde, 0xde, 0xe6, 0xdd, 0xde, 0xee, 0x6e, 0xee, 0xee, 0xee, 0xdd, 0xdd, 0xad, 0xdd, ++0xde, 0xee, 0xe6, 0xee, 0xde, 0xde, 0xe6, 0xee, 0xd6, 0xe6, 0xee, 0xdd, 0xdd, 0xdd, 0xd6, 0x00, 0x09, 0x09, 0x00, 0x00, 0x09, 0x64, 0x99, 0x00, 0x00, 0x04, 0xee, 0xe6, 0xee, 0xde, 0xde, 0x6e, 0xee, 0xee, 0xe6, 0xee, 0xdd, 0xdd, 0xed, 0xee, ++0xdd, 0xee, 0x6e, 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0xdd, 0xed, 0xed, 0xed, 0xee, 0x66, 0x69, 0x09, 0x00, 0x77, 0x77, 0x76, 0x00, 0x77, 0x77, 0x96, 0x77, 0x7a, 0x00, 0xd7, 0x77, 0x90, 0x67, 0x77, 0x60, 0x00, 0x00, 0x00, 0x00, 0x9e, 0x66, 0x66, 0x6e, 0xdd, 0xde, 0x6e, 0xdd, ++0xdd, 0xde, 0xdd, 0xdd, 0xdd, 0xee, 0xed, 0xee, 0x66, 0x60, 0x09, 0x04, 0x77, 0x77, 0x7d, 0x00, 0x77, 0x76, 0x0a, 0x77, 0x7d, 0x00, 0xa7, 0xa4, 0x09, 0xa7, 0x77, 0x60, 0x00, 0x90, 0x00, 0x00, 0x9e, 0x66, 0x6e, 0xee, 0xdd, 0xde, 0x6e, 0xdd, ++0xad, 0xee, 0xde, 0xdd, 0xee, 0xee, 0xee, 0xdd, 0xee, 0x90, 0x09, 0x06, 0x77, 0x77, 0x7a, 0x00, 0xd7, 0x70, 0x67, 0x77, 0x76, 0x00, 0x44, 0x04, 0xd7, 0x77, 0x77, 0xe0, 0x00, 0x90, 0x00, 0x00, 0x0d, 0xe6, 0x6e, 0xdd, 0xdd, 0xd6, 0x6e, 0xda, ++0xae, 0xee, 0xdd, 0xed, 0xed, 0xee, 0xee, 0xde, 0xe6, 0x00, 0x04, 0x06, 0x77, 0x77, 0x77, 0x00, 0xd7, 0xe0, 0x77, 0x77, 0x74, 0x09, 0xd4, 0x09, 0xa7, 0x77, 0x77, 0xe0, 0x00, 0x90, 0x00, 0x00, 0x0d, 0xe6, 0x6e, 0xdd, 0xad, 0xe6, 0xed, 0xad, ++0xe6, 0x66, 0xed, 0xde, 0xee, 0xe6, 0xee, 0xee, 0x64, 0x00, 0x04, 0x0e, 0x77, 0x77, 0x77, 0x00, 0x4a, 0x04, 0x77, 0x77, 0x79, 0x04, 0x77, 0x90, 0x97, 0x77, 0x77, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x66, 0xed, 0xdd, 0xde, 0xee, 0xed, 0xad, ++0xe6, 0x6e, 0xdd, 0xde, 0xee, 0x6e, 0xee, 0xe6, 0x64, 0x00, 0x00, 0x9e, 0x77, 0x77, 0x77, 0x40, 0x46, 0x97, 0x77, 0x77, 0x70, 0x0e, 0x77, 0xd0, 0x0a, 0x77, 0x77, 0x60, 0x09, 0x00, 0x00, 0x00, 0x0e, 0x66, 0xed, 0xad, 0xdd, 0xee, 0xdd, 0xdd, ++0x66, 0x6e, 0xdd, 0xde, 0xee, 0xee, 0xee, 0xee, 0xe6, 0x09, 0x40, 0x0e, 0x77, 0x77, 0x77, 0x60, 0x00, 0x67, 0x77, 0x77, 0xd0, 0x0d, 0x77, 0xa0, 0x06, 0x77, 0x77, 0x40, 0x90, 0x00, 0x09, 0x00, 0x4e, 0xee, 0xdd, 0xdd, 0xde, 0xde, 0xdd, 0xdd, ++0x66, 0x6d, 0xdd, 0xdd, 0xee, 0xee, 0xee, 0xee, 0xed, 0x1f, 0xf8, 0x04, 0x77, 0x77, 0x77, 0xd0, 0x09, 0x77, 0x77, 0x77, 0xe0, 0x07, 0x77, 0x79, 0x09, 0x77, 0x77, 0x90, 0x00, 0x00, 0x00, 0x40, 0x6e, 0xed, 0xdd, 0xad, 0xde, 0xee, 0xee, 0xee, ++0x6e, 0xed, 0xda, 0xde, 0xe6, 0xe6, 0xee, 0xdd, 0xa3, 0x5f, 0xf2, 0x10, 0x9a, 0x77, 0x77, 0xa0, 0x06, 0x77, 0x77, 0x74, 0x00, 0x04, 0xe7, 0x7a, 0x00, 0x94, 0xa2, 0x10, 0x00, 0x00, 0x00, 0x99, 0xed, 0xdd, 0xdd, 0xdd, 0xee, 0xee, 0xde, 0xdd, ++0xee, 0xed, 0xdd, 0xde, 0xe6, 0xee, 0xee, 0xda, 0xa5, 0x5f, 0xff, 0xf1, 0x09, 0xa7, 0x77, 0x7d, 0xd7, 0x77, 0x77, 0x7d, 0xdd, 0xdd, 0xa7, 0x77, 0xad, 0xdd, 0xf2, 0xb0, 0x00, 0x00, 0x00, 0x06, 0xf7, 0xdd, 0xdd, 0xde, 0xde, 0xed, 0xdd, 0xed, ++0xd6, 0xed, 0xdd, 0xee, 0x66, 0xda, 0xaa, 0xa3, 0x85, 0xff, 0x2f, 0xf2, 0xc0, 0x0d, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x52, 0xc0, 0x00, 0x00, 0x00, 0x95, 0x22, 0xad, 0xed, 0xde, 0xed, 0xee, 0xee, 0xde, ++0xd6, 0xed, 0xdd, 0xde, 0xee, 0xd8, 0x58, 0x55, 0x5f, 0xff, 0xff, 0xff, 0xf9, 0x00, 0xe7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0xf5, 0x10, 0x00, 0x00, 0x09, 0x8f, 0xf2, 0xae, 0xee, 0xde, 0xde, 0xee, 0xee, 0xee, ++0xde, 0xed, 0xdd, 0xe6, 0x6a, 0x85, 0xff, 0xf5, 0xff, 0xff, 0xff, 0xff, 0x21, 0x00, 0x06, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0xa8, 0xf5, 0x8b, 0x90, 0x09, 0xc1, 0x5f, 0xf3, 0xdd, 0xde, 0xee, 0x6e, 0x6e, 0x6e, 0xee, ++0xad, 0xda, 0xdd, 0xe6, 0xea, 0x85, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x2f, 0x40, 0x00, 0x47, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0xa5, 0x55, 0x88, 0xbb, 0xb1, 0x85, 0xff, 0xff, 0xae, 0xee, 0xee, 0xee, 0xed, 0xed, 0xdd, ++0xdd, 0xdd, 0xde, 0xe6, 0xea, 0x85, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x50, 0x00, 0x00, 0xa7, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x7a, 0xa8, 0xf5, 0x55, 0x88, 0x88, 0x5f, 0xff, 0xff, 0x2d, 0xee, 0xee, 0xdd, 0xdd, 0xdd, 0xdd, ++0xdd, 0xde, 0xde, 0x6e, 0xea, 0x85, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, 0x00, 0x00, 0x0a, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x7a, 0xd8, 0x5f, 0x55, 0x55, 0x55, 0xff, 0xff, 0xff, 0xfa, 0xad, 0xee, 0xdd, 0xdd, 0xdd, 0xdd, ++0xde, 0xee, 0x6e, 0x6e, 0xda, 0x85, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x2f, 0xc0, 0x00, 0x0d, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x7a, 0x68, 0x5f, 0xff, 0xff, 0x55, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xde, 0xed, 0xad, 0xdd, 0xee, ++0xde, 0xee, 0xee, 0xee, 0xda, 0x35, 0xff, 0xf2, 0xff, 0x2f, 0xff, 0xff, 0xff, 0xf2, 0x19, 0x00, 0x0e, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x76, 0x91, 0x5f, 0x5f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xad, 0xdd, 0xde, 0xee, 0xee, ++0xde, 0xe6, 0x66, 0xed, 0xdd, 0x35, 0xff, 0xff, 0xff, 0xff, 0x2f, 0xff, 0xff, 0xff, 0x25, 0x00, 0x67, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x40, 0x98, 0x5f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x2f, 0xff, 0x2a, 0xaa, 0xde, 0xee, 0xee, ++0xde, 0x6e, 0xee, 0xed, 0xdd, 0x35, 0xff, 0xff, 0xff, 0xff, 0xff, 0x2f, 0xff, 0xff, 0xf3, 0x37, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0xa9, 0x00, 0x98, 0x5f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xad, 0xde, 0xee, 0xee, ++0xee, 0x66, 0x6e, 0xdd, 0xea, 0x85, 0xff, 0xff, 0x2f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x1a, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x7e, 0x00, 0x00, 0xcb, 0x5f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0xf7, 0xde, 0x66, 0x66, 0xee, ++0xee, 0xe6, 0xee, 0xdd, 0xe3, 0x8f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf2, 0xff, 0x8c, 0xd7, 0x77, 0x77, 0x77, 0x77, 0x7e, 0x90, 0x00, 0x00, 0xcb, 0x5f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x3a, 0xaa, 0xe6, 0x66, 0x6e, 0xee, ++0x66, 0x66, 0x6e, 0xdd, 0xa3, 0x85, 0xff, 0xff, 0xf2, 0xff, 0x2f, 0xf2, 0xff, 0xff, 0xf5, 0x8b, 0x09, 0x6d, 0xad, 0xde, 0x69, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x5f, 0xff, 0xf2, 0xff, 0x2f, 0xff, 0xf3, 0x32, 0xaa, 0xde, 0x66, 0x66, 0x6e, 0xde, ++0x6e, 0xe6, 0xee, 0xdd, 0xa1, 0x85, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x8c, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xcb, 0x5f, 0xff, 0xff, 0xff, 0xff, 0x55, 0x8a, 0xaa, 0xdd, 0xe6, 0x64, 0x66, 0xee, 0xdd, ++0xee, 0xee, 0xee, 0xdd, 0xd3, 0x8b, 0x88, 0x85, 0x55, 0x5f, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xbb, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xcb, 0x8f, 0xff, 0xff, 0xff, 0x55, 0x88, 0xad, 0xda, 0xad, 0x66, 0x46, 0xee, 0xed, 0xdd, ++0xad, 0xee, 0xee, 0xdd, 0xea, 0xaa, 0x81, 0xbb, 0x18, 0x88, 0x85, 0x5f, 0xff, 0xff, 0x58, 0xbc, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xcb, 0x88, 0xff, 0xff, 0x55, 0x81, 0x3a, 0xdd, 0xdd, 0xae, 0x66, 0x66, 0xed, 0xdd, 0xdd, ++0xae, 0xee, 0xed, 0xdd, 0xed, 0xdd, 0xda, 0xa3, 0x1b, 0xbb, 0xbb, 0x88, 0x85, 0x58, 0x8b, 0xcc, 0x99, 0xee, 0xed, 0xed, 0xdd, 0xdd, 0xed, 0xee, 0x69, 0x9b, 0xb8, 0x58, 0x58, 0x8b, 0xba, 0xad, 0xee, 0xda, 0xde, 0x66, 0x6e, 0xee, 0xdd, 0xdd, ++0xa6, 0x6e, 0xed, 0xdd, 0xde, 0xdd, 0xad, 0xed, 0xda, 0xd8, 0xbc, 0xcb, 0xbb, 0xbb, 0xbc, 0xc9, 0xbd, 0xee, 0xed, 0xee, 0xed, 0xdd, 0xed, 0xdd, 0xda, 0xcc, 0xbb, 0xb8, 0xbb, 0xbb, 0xad, 0xdd, 0xdd, 0xdd, 0xee, 0x66, 0x66, 0xee, 0xdd, 0xdd, ++0xe6, 0x6e, 0xed, 0xdd, 0xee, 0xdd, 0xdd, 0xdd, 0xdd, 0xee, 0xed, 0xdb, 0xcc, 0xcc, 0xcc, 0x9a, 0xee, 0xee, 0xdd, 0xde, 0xee, 0xdd, 0xde, 0xdd, 0xaa, 0x39, 0xcc, 0xbb, 0xbc, 0xba, 0xdd, 0xdd, 0xed, 0xdd, 0xd6, 0x6e, 0x66, 0x6d, 0xdd, 0xde, ++0x64, 0x6e, 0xed, 0xdd, 0xee, 0xdd, 0xdd, 0xee, 0xed, 0xe6, 0xe6, 0x6d, 0xa1, 0xcc, 0x9b, 0xdd, 0xee, 0xed, 0xde, 0xde, 0xdd, 0xed, 0xde, 0xdd, 0xde, 0xee, 0x1c, 0xcc, 0xc1, 0xae, 0xed, 0xdd, 0xee, 0xde, 0xee, 0x6e, 0x6e, 0xed, 0xaa, 0xee, ++0xe6, 0x6e, 0xde, 0xdd, 0xde, 0xdd, 0xdd, 0xde, 0xee, 0xee, 0xee, 0xee, 0xda, 0xaa, 0xdd, 0xed, 0xee, 0xdd, 0xee, 0xed, 0xee, 0xdd, 0xdd, 0xdd, 0xde, 0xe6, 0xed, 0xda, 0xdd, 0xde, 0xdd, 0xdd, 0xde, 0xee, 0xee, 0xee, 0xee, 0xad, 0xad, 0xee, ++0xee, 0xed, 0xdd, 0xed, 0xde, 0xdd, 0xdd, 0xde, 0xed, 0xed, 0xdd, 0xdd, 0xda, 0xdd, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xdd, 0xdd, 0xdd, 0xde, 0xde, 0xee, 0xee, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xde, 0xee, 0xed, 0xde, 0xdd, 0xaa, 0xad, 0xee, ++0xde, 0xde, 0xed, 0xdd, 0xed, 0xee, 0xdd, 0xde, 0xee, 0xdd, 0xdd, 0xdd, 0xad, 0xde, 0xee, 0xee, 0xe6, 0xee, 0x6e, 0xee, 0xed, 0xdd, 0xdd, 0xdd, 0xdd, 0xde, 0xed, 0xed, 0xed, 0xde, 0xee, 0xde, 0xdd, 0xee, 0xdd, 0xdd, 0xdd, 0xdd, 0xde, 0xee ++}; ++ ++#endif ++ ++#ifdef INCLUDE_LINUX_LOGOBW ++ ++unsigned char linux_logo_bw[] __initdata = { ++0x20, 0xa9, 0x40, 0xa0, 0x22, 0x00, 0x08, 0x2a, 0x50, 0x28, ++0xb0, 0x95, 0x70, 0xa0, 0x28, 0x00, 0x2c, 0x25, 0x5c, 0x28, ++0x41, 0x52, 0x80, 0x00, 0xa1, 0x00, 0x28, 0x54, 0xa0, 0x00, ++0x70, 0x29, 0x40, 0x40, 0x9f, 0xf0, 0x54, 0x0a, 0x50, 0x10, ++0x80, 0xa4, 0x81, 0x55, 0x7f, 0xfd, 0x50, 0x29, 0x20, 0x55, ++0xa0, 0x54, 0x00, 0x90, 0xff, 0xff, 0x28, 0x15, 0x00, 0x90, ++0x41, 0x48, 0x05, 0x01, 0xff, 0xff, 0xa0, 0x52, 0x00, 0x40, ++0x20, 0xa8, 0x01, 0x55, 0xff, 0xf7, 0xd8, 0x2a, 0x11, 0x2a, ++0x41, 0x40, 0xa4, 0xab, 0xff, 0xff, 0xc0, 0x50, 0x08, 0xaa, ++0x22, 0xa0, 0x55, 0x53, 0xff, 0xff, 0xf0, 0xa8, 0x2a, 0xaa, ++0x02, 0x81, 0x24, 0x83, 0xff, 0xff, 0xe0, 0xa0, 0x54, 0x90, ++0x01, 0x45, 0x52, 0x03, 0xff, 0xff, 0xf0, 0x51, 0x52, 0x80, ++0x15, 0x15, 0x28, 0x07, 0xff, 0xff, 0xf5, 0x45, 0x54, 0x00, ++0x55, 0x15, 0x54, 0x03, 0xff, 0xef, 0xf5, 0x42, 0x8b, 0x02, ++0x2a, 0x48, 0x50, 0x37, 0x1f, 0x87, 0xf5, 0x15, 0x28, 0x14, ++0x2a, 0x54, 0x50, 0x13, 0x0f, 0x03, 0xfa, 0x85, 0x14, 0x12, ++0x54, 0x50, 0x80, 0xaa, 0x4e, 0x33, 0xf5, 0x12, 0x20, 0x14, ++0x54, 0x14, 0x40, 0xaa, 0xef, 0x7b, 0xf5, 0x09, 0x20, 0x2a, ++0x50, 0xa2, 0x82, 0xaa, 0xef, 0x79, 0xfa, 0x28, 0x80, 0xaa, ++0xac, 0x20, 0x05, 0xaa, 0xe0, 0x7b, 0xf5, 0x28, 0x01, 0x6a, ++0x50, 0x80, 0x0a, 0xa3, 0x40, 0x33, 0xf4, 0x10, 0x02, 0xa8, ++0x28, 0x40, 0x06, 0xa3, 0x40, 0x03, 0xf3, 0x10, 0x01, 0xa8, ++0x10, 0x81, 0x15, 0x03, 0x00, 0x03, 0xf4, 0x20, 0x45, 0x40, ++0x28, 0x40, 0x15, 0x43, 0x80, 0x0b, 0xfa, 0x10, 0x05, 0x50, ++0x50, 0x82, 0x15, 0x42, 0x00, 0x23, 0xf8, 0x20, 0x85, 0x51, ++0xa8, 0xa0, 0x2a, 0x83, 0x80, 0x4b, 0xfa, 0x10, 0x45, 0x50, ++0x50, 0x42, 0x95, 0x0b, 0x6a, 0x83, 0xdc, 0x28, 0x4a, 0xa2, ++0x50, 0x40, 0x55, 0x0b, 0x20, 0x41, 0xdc, 0x00, 0x2a, 0x82, ++0x40, 0x01, 0x00, 0x07, 0x1f, 0x01, 0xfe, 0x00, 0x80, 0x02, ++0x50, 0x21, 0x40, 0x17, 0x00, 0x00, 0xff, 0x08, 0x50, 0x02, ++0x22, 0x54, 0x80, 0x2e, 0x00, 0x00, 0xff, 0x14, 0xa0, 0x0a, ++0xa9, 0x12, 0xaa, 0xae, 0x00, 0x00, 0x7f, 0x82, 0x14, 0xaa, ++0x54, 0x49, 0x55, 0x5c, 0x00, 0x00, 0x7f, 0xa9, 0x55, 0x55, ++0xa5, 0x15, 0x52, 0xb8, 0x00, 0x00, 0x3f, 0xc5, 0x54, 0xaa, ++0x08, 0x12, 0x85, 0x78, 0x00, 0x00, 0x3f, 0xe9, 0x21, 0x55, ++0x05, 0x48, 0x41, 0x78, 0x00, 0x00, 0x3f, 0xf4, 0x90, 0x44, ++0x02, 0x25, 0x0a, 0xf0, 0x00, 0x00, 0x3f, 0xf9, 0x42, 0xaa, ++0x01, 0x11, 0x55, 0xf8, 0x00, 0x00, 0x1f, 0xf8, 0x2a, 0xaa, ++0x00, 0x0a, 0x15, 0xf0, 0x00, 0x00, 0x0f, 0xfe, 0x92, 0x51, ++0x00, 0x25, 0x43, 0xf0, 0x00, 0x00, 0x0f, 0xfd, 0x4a, 0x94, ++0x55, 0x52, 0x2b, 0xe0, 0x00, 0x00, 0x07, 0xfe, 0xa0, 0x4a, ++0x55, 0x00, 0x13, 0xc0, 0x00, 0x00, 0x07, 0xfe, 0x2a, 0x22, ++0x21, 0x50, 0x07, 0xc0, 0x00, 0x00, 0x03, 0xff, 0x04, 0x50, ++0x28, 0x20, 0x07, 0xcf, 0x8f, 0xff, 0xc3, 0xff, 0x00, 0x4a, ++0x40, 0x92, 0x17, 0x86, 0x02, 0x38, 0xe3, 0xff, 0x0a, 0xaa, ++0x50, 0x4a, 0xaf, 0x87, 0x06, 0x38, 0xe3, 0xff, 0xaa, 0xaa, ++0x28, 0xa1, 0x5f, 0x07, 0x0c, 0x38, 0xe3, 0xff, 0x55, 0x12, ++0x08, 0x15, 0x5f, 0x03, 0x0c, 0x30, 0xe1, 0xff, 0x95, 0x14, ++0x10, 0x21, 0x5f, 0x03, 0x18, 0x31, 0xc3, 0xff, 0xa8, 0x14, ++0x10, 0x94, 0xbf, 0x03, 0x18, 0x7f, 0x01, 0xff, 0x94, 0x14, ++0x50, 0xa9, 0x7e, 0x03, 0x10, 0x77, 0x03, 0xff, 0xa8, 0x28, ++0x28, 0x95, 0x7f, 0x03, 0xb0, 0x73, 0x81, 0xff, 0xa8, 0x28, ++0xd1, 0x52, 0xfe, 0x03, 0xa0, 0x61, 0x83, 0xff, 0xa8, 0x00, ++0x50, 0x2a, 0x3f, 0x01, 0xc0, 0x61, 0xc3, 0xff, 0xa0, 0x50, ++0xa0, 0xa5, 0x23, 0x01, 0xc0, 0xe1, 0xc3, 0xff, 0x40, 0x2a, ++0xa0, 0x54, 0x01, 0x81, 0xc1, 0xf0, 0xf1, 0xff, 0x80, 0x48, ++0x41, 0x48, 0x01, 0xc0, 0x00, 0x00, 0x03, 0xfe, 0x01, 0x20, ++0x21, 0x40, 0x80, 0xe0, 0x00, 0x00, 0x01, 0xfe, 0x08, 0xaa, ++0x41, 0x50, 0x00, 0x78, 0x00, 0x00, 0x03, 0xfc, 0x15, 0x2a, ++0x22, 0x80, 0x00, 0x3c, 0x00, 0x00, 0x00, 0xfc, 0x04, 0xaa, ++0x01, 0x20, 0x00, 0x3e, 0x00, 0x00, 0x01, 0x40, 0x12, 0x90, ++0x05, 0x20, 0x00, 0x1f, 0x00, 0x00, 0x10, 0x20, 0x09, 0x00, ++0x15, 0x00, 0x00, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x04, 0x00, ++0x55, 0x20, 0x00, 0x0f, 0x80, 0x00, 0x30, 0x00, 0x01, 0x02, ++0x2a, 0x00, 0x00, 0x07, 0xc0, 0x00, 0x60, 0x00, 0x00, 0x14, ++0x2a, 0x00, 0x00, 0x03, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x12, ++0x54, 0x00, 0x00, 0x00, 0x00, 0x01, 0xe0, 0x00, 0x00, 0x14, ++0x54, 0xa0, 0x00, 0x02, 0x00, 0x03, 0xf0, 0x00, 0x00, 0x2a, ++0x50, 0x00, 0x00, 0x01, 0x00, 0x0f, 0xe0, 0x00, 0x00, 0xaa, ++0xac, 0x00, 0x00, 0x01, 0xe0, 0xff, 0xf0, 0x00, 0x01, 0x6a, ++0x50, 0x40, 0x00, 0x02, 0xff, 0xff, 0xe0, 0x00, 0x82, 0xa8, ++0x94, 0x34, 0x00, 0x01, 0xff, 0xff, 0xf0, 0x00, 0x01, 0xa8, ++0x28, 0x85, 0xa0, 0x05, 0xff, 0xff, 0xe8, 0x08, 0x02, 0xa0, ++0x08, 0x40, 0x3d, 0x0b, 0xe0, 0x01, 0x74, 0x28, 0x45, 0x50, ++0x60, 0x82, 0x06, 0xef, 0x15, 0x08, 0x35, 0xa0, 0x0a, 0xa1, ++0x38, 0x40, 0x10, 0xfe, 0x50, 0x80, 0x1d, 0x60, 0x85, 0x50, ++0xc0, 0x82, 0xae, 0x38, 0x82, 0x00, 0x27, 0x88, 0x55, 0x42, ++0x50, 0x41, 0x21, 0x02, 0x49, 0x40, 0x50, 0x00, 0x25, 0x42, ++0x40, 0x00, 0x80, 0x09, 0x54, 0x80, 0x28, 0x00, 0x50, 0x02, ++0x50, 0x50, 0x40, 0x04, 0xaa, 0x00, 0x08, 0x14, 0x10, 0x02 ++}; ++ ++#endif ++ +diff -ruN linux-mips/include/asm-mips/mipsregs.h linux-vr/include/asm-mips/mipsregs.h +--- linux-mips/include/asm-mips/mipsregs.h Fri Nov 10 00:11:53 2000 ++++ linux-vr/include/asm-mips/mipsregs.h Thu Nov 23 15:03:49 2000 +@@ -76,9 +76,68 @@ + #define CP1_REVISION $0 + #define CP1_STATUS $31 + ++/* ++ kei ++*/ ++#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ ++#define FPU_CSR_COND 0x00800000 /* $fcc0 */ ++#define FPU_CSR_COND0 0x00800000 /* $fcc0 */ ++#define FPU_CSR_COND1 0x02000000 /* $fcc1 */ ++#define FPU_CSR_COND2 0x04000000 /* $fcc2 */ ++#define FPU_CSR_COND3 0x08000000 /* $fcc3 */ ++#define FPU_CSR_COND4 0x10000000 /* $fcc4 */ ++#define FPU_CSR_COND5 0x20000000 /* $fcc5 */ ++#define FPU_CSR_COND6 0x40000000 /* $fcc6 */ ++#define FPU_CSR_COND7 0x80000000 /* $fcc7 */ ++ ++/* ++ * X the exception cause indicator ++ * E the exception enable ++ * S the sticky/flag bit ++*/ ++#define FPU_CSR_ALL_X 0x0003f000 ++#define FPU_CSR_UNI_X 0x00020000 ++#define FPU_CSR_INV_X 0x00010000 ++#define FPU_CSR_DIV_X 0x00008000 ++#define FPU_CSR_OVF_X 0x00004000 ++#define FPU_CSR_UDF_X 0x00002000 ++#define FPU_CSR_INE_X 0x00001000 ++ ++#define FPU_CSR_ALL_E 0x00000f80 ++#define FPU_CSR_INV_E 0x00000800 ++#define FPU_CSR_DIV_E 0x00000400 ++#define FPU_CSR_OVF_E 0x00000200 ++#define FPU_CSR_UDF_E 0x00000100 ++#define FPU_CSR_INE_E 0x00000080 ++ ++#define FPU_CSR_ALL_S 0x0000007c ++#define FPU_CSR_INV_S 0x00000040 ++#define FPU_CSR_DIV_S 0x00000020 ++#define FPU_CSR_OVF_S 0x00000010 ++#define FPU_CSR_UDF_S 0x00000008 ++#define FPU_CSR_INE_S 0x00000004 ++ ++/* rounding mode */ ++#define FPU_CSR_RN 0x0 /* nearest */ ++#define FPU_CSR_RZ 0x1 /* towards zero */ ++#define FPU_CSR_RU 0x2 /* towards +Infinity */ ++#define FPU_CSR_RD 0x3 /* towards -Infinity */ ++/* -- kei -- */ ++ ++#ifdef __KERNEL__ ++/* Only use config.h if compiling kernel. ++ * Others will have to #define CONFIG_CPU_VR41XX if necessary. bdl */ ++#include ++#endif ++ + /* + * Values for PageMask register + */ ++#ifdef CONFIG_CPU_VR41XX ++#define PM_1K 0x00000000 ++#define PM_4K 0x00001800 ++#define PM_16K 0x00007800 ++#define PM_64K 0x0001f800 ++#define PM_256K 0x0007f800 ++#else + #define PM_4K 0x00000000 + #define PM_16K 0x00006000 + #define PM_64K 0x0001e000 +@@ -86,6 +145,8 @@ + #define PM_1M 0x001fe000 + #define PM_4M 0x007fe000 + #define PM_16M 0x01ffe000 ++#endif ++ + + /* + * Values used for computation of new tlb entries +@@ -179,6 +240,7 @@ + return res; \ + } + ++__BUILD_SET_CP0(conf,CP0_CONF) + __BUILD_SET_CP0(status,CP0_STATUS) + __BUILD_SET_CP0(cause,CP0_CAUSE) + __BUILD_SET_CP0(config,CP0_CONFIG) +@@ -284,6 +346,28 @@ + #define CAUSEF_CE (3 << 28) + #define CAUSEB_BD 31 + #define CAUSEF_BD (1 << 31) ++ ++/* ++ * Bits in the r39xx configuration register (register #3) ++ */ ++ ++#define CONFB_ICS 19 ++#define CONFF_ICS (7 << 19) ++#define CONFB_DCS 16 ++#define CONFF_DCS (7 << 16) ++#define CONFB_RF 10 ++#define CONFF_RF (3 << 10) ++#define CONFB_DOZE 9 ++#define CONFB_HALT 8 ++#define CONFB_LOCK 7 ++#define CONFB_DCBR 6 ++#define CONFB_ICE 5 ++#define CONFB_DCE 4 ++#define CONFB_IRSIZE 2 ++#define CONFF_IRSIZE (3 << 2) ++#define CONFB_DRSIZE 0 ++#define CONFF_DRSIZE (3 << 0) ++ + + /* + * Bits in the coprozessor 0 config register. +diff -ruN linux-mips/include/asm-mips/mmu_context.h linux-vr/include/asm-mips/mmu_context.h +--- linux-mips/include/asm-mips/mmu_context.h Mon Sep 11 23:53:14 2000 ++++ linux-vr/include/asm-mips/mmu_context.h Tue Sep 19 07:39:49 2000 +@@ -19,7 +19,7 @@ + extern unsigned long asid_cache; + extern pgd_t *current_pgd; + +-#if defined(CONFIG_CPU_R3000) ++#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_R39XX) + + #define ASID_INC 0x40 + #define ASID_MASK 0xfc0 +diff -ruN linux-mips/include/asm-mips/pci.h linux-vr/include/asm-mips/pci.h +--- linux-mips/include/asm-mips/pci.h Fri Nov 10 00:11:55 2000 ++++ linux-vr/include/asm-mips/pci.h Thu Nov 23 15:05:44 2000 +@@ -201,6 +201,16 @@ + #endif + } + ++/* Return whether the given PCI device DMA address mask can ++ * be supported properly. For example, if your device can ++ * only drive the low 24-bits during PCI bus mastering, then ++ * you would pass 0x00ffffff as the mask to this function. ++ */ ++extern inline int pci_dma_supported(struct pci_dev *hwdev, dma_addr_t mask) ++{ ++ return 1; ++} ++ + /* + * These macros should be used after a pci_map_sg call has been done + * to get bus addresses of each of the SG entries and their lengths. +diff -ruN linux-mips/include/asm-mips/pgtable.h linux-vr/include/asm-mips/pgtable.h +--- linux-mips/include/asm-mips/pgtable.h Fri Nov 10 00:11:57 2000 ++++ linux-vr/include/asm-mips/pgtable.h Thu Nov 23 15:03:49 2000 +@@ -116,7 +116,7 @@ + #define _PAGE_ACCESSED (1<<3) /* implemented in software */ + #define _PAGE_MODIFIED (1<<4) /* implemented in software */ + +-#if defined(CONFIG_CPU_R3000) ++#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_R39XX) + + #define _PAGE_GLOBAL (1<<8) + #define _PAGE_VALID (1<<9) +@@ -305,7 +305,11 @@ + * is simple. + */ + #define page_address(page) ((page)->virtual) ++#ifdef CONFIG_CPU_VR41XX ++#define pte_page(x) (mem_map+(unsigned long)((pte_val(x) >> (PAGE_SHIFT + 2)))) ++#else + #define pte_page(x) (mem_map+(unsigned long)((pte_val(x) >> PAGE_SHIFT))) ++#endif + + /* + * The following only work if pte_present() is true. +@@ -376,6 +380,17 @@ + * Conversion functions: convert a page and protection to a page entry, + * and a page entry and page directory to the page they refer to. + */ ++#ifdef CONFIG_CPU_VR41XX ++#define mk_pte(page, pgprot) \ ++({ \ ++ pte_t __pte; \ ++ \ ++ pte_val(__pte) = ((unsigned long)(page - mem_map) << (PAGE_SHIFT + 2)) | \ ++ pgprot_val(pgprot); \ ++ \ ++ __pte; \ ++}) ++#else + #define mk_pte(page, pgprot) \ + ({ \ + pte_t __pte; \ +@@ -385,10 +400,15 @@ + \ + __pte; \ + }) ++#endif + + extern inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) + { ++#ifdef CONFIG_CPU_VR41XX ++ return __pte((physpage << 2) | pgprot_val(pgprot)); ++#else + return __pte(physpage | pgprot_val(pgprot)); ++#endif + } + + extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot) +diff -ruN linux-mips/include/asm-mips/power.h linux-vr/include/asm-mips/power.h +--- linux-mips/include/asm-mips/power.h Wed Dec 31 16:00:00 1969 ++++ linux-vr/include/asm-mips/power.h Sun Mar 26 23:24:39 2000 +@@ -0,0 +1,24 @@ ++/* ++ * power.h - Common power management defines ++ * ++ * Copyright (C) 2000 Michael Klar ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ */ ++ ++#ifndef __ASM_POWER_H ++#define __ASM_POWER_H ++ ++#ifndef _LANGUAGE_ASSEMBLY ++extern unsigned int powerevent_queued; ++extern unsigned int hibernation_state; ++#endif ++ ++#define LOAD_MAGIC (('L'<<24) | ('O'<<16) | ('A'<<8) | 'D') ++#define HIB_MAGIC ((' '<<24) | ('H'<<16) | ('I'<<8) | 'B') ++#define RUN_MAGIC ((' '<<24) | ('R'<<16) | ('U'<<8) | 'N') ++ ++#endif /* __ASM_POWER_H */ +diff -ruN linux-mips/include/asm-mips/processor.h linux-vr/include/asm-mips/processor.h +--- linux-mips/include/asm-mips/processor.h Mon Sep 11 23:53:15 2000 ++++ linux-vr/include/asm-mips/processor.h Thu Nov 23 15:03:49 2000 +@@ -102,11 +102,15 @@ + unsigned int control; + } __attribute__((aligned(8))); + ++ ++typedef unsigned long long fpureg_t; ++ + /* + * FIXME: no fpu emulator yet (but who cares anyway?) + */ + struct mips_fpu_soft_struct { +- long dummy; ++ fpureg_t regs[NUM_FPU_REGS]; ++ unsigned int sr; + }; + + union mips_fpu_union { +@@ -148,6 +152,24 @@ + mm_segment_t current_ds; + unsigned long irix_trampoline; /* Wheee... */ + unsigned long irix_oldctx; ++ ++ /* ++ * These are really only needed if the full FPU emulator ++ * is configured. Would be made conditional on ++ * MIPS_FPU_EMULATOR if it weren't for the fact that ++ * having offset.h rebuilt differently for different ++ * config options would be asking for trouble. ++ */ ++ ++ /* ++ * Saved EPC during delay-slot emulation (see math-emu/cp1emu.c) ++ */ ++ unsigned long dsemul_epc; ++ ++ /* ++ * Pointer to instruction used to induce address error ++ */ ++ unsigned long dsemul_aerpc; + }; + + #endif /* !defined (_LANGUAGE_ASSEMBLY) */ +@@ -177,6 +199,11 @@ + * For now the default is to fix address errors \ + */ \ + MF_FIXADE, { 0 }, 0, 0 \ ++ /* \ ++ * dsemul_epc and dsemul_aerpc should never be used uninitialized, ++ * but... \ ++ */ \ ++ , 0, 0 \ + } + + #ifdef __KERNEL__ +diff -ruN linux-mips/include/asm-mips/r39xx.h linux-vr/include/asm-mips/r39xx.h +--- linux-mips/include/asm-mips/r39xx.h Wed Dec 31 16:00:00 1969 ++++ linux-vr/include/asm-mips/r39xx.h Thu Nov 23 15:11:59 2000 +@@ -0,0 +1,721 @@ ++/* $Id: r39xx.h,v 1.17 2000/11/17 21:57:18 pavel Exp $ ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ */ ++ ++#ifndef __R39XX_H__ ++#define __R39XX_H__ ++ ++#include ++ ++/****************************************************************************** ++* ++* 01 General macro definitions ++* ++******************************************************************************/ ++ ++#define REGISTER_BASE 0xb0c00000 ++ ++#ifndef _LANGUAGE_ASSEMBLY ++ ++ #define REG_AT(x) (*((volatile unsigned long *)(REGISTER_BASE + x))) ++ ++#else ++ ++ #define REG_AT(x) (REGISTER_BASE + x) ++ ++#endif ++ ++#define BIT(x) (1 << x) ++ ++/****************************************************************************** ++* ++* 02 Bus Interface Unit ++* ++******************************************************************************/ ++ ++#define MemConfig0 REG_AT(0x000) ++#define MemConfig1 REG_AT(0x004) ++#define MemConfig2 REG_AT(0x008) ++#define MemConfig3 REG_AT(0x00c) ++#define MemConfig4 REG_AT(0x010) ++#define MemConfig5 REG_AT(0x014) ++#define MemConfig6 REG_AT(0x018) ++#define MemConfig7 REG_AT(0x01c) ++#define MemConfig8 REG_AT(0x020) ++ ++/* Memory config register 1 */ ++ ++#define MEM1_ENCS1USER BIT(21) ++ ++/* Memory config register 3 */ ++ ++#define MEM3_CARD1ACCVAL_MASK (BIT(24) | BIT(25) | BIT(26) | BIT(27)) ++#define MEM3_CARD1IOEN BIT(4) ++ ++/* Memory config register 4 */ ++ ++#define MEM4_ARBITRATIONEN BIT(29) ++#define MEM4_MEMPOWERDOWN BIT(16) ++#define MEM4_ENREFRESH1 BIT(15) ++#define MEM4_ENREFRESH0 BIT(14) ++ ++#define MEM4_ENWATCH BIT(24) ++#define MEM4_WATCHTIMEVAL_MASK (0xf) ++#define MEM4_WATCHTIMEVAL_SHIFT (20) ++ ++#define MEM4_WATCHTIME_VALUE (0xf) ++ ++ ++/****************************************************************************** ++* ++* 06 Clock module ++* ++******************************************************************************/ ++ ++#define ClockControl REG_AT(0x1C0) ++ ++#define CLK_CHICLKDIV_MASK 0xff000000 ++#define CLK_CHICLKDIV_SHIFT 24 ++#define CLK_ENCLKTEST BIT(23) ++#define CLK_CLKTESTSELSIB BIT(22) ++#define CLK_CHIMCLKSEL BIT(21) ++#define CLK_CHICLKDIR BIT(20) ++#define CLK_ENCHIMCLK BIT(19) ++#define CLK_ENVIDCLK BIT(18) ++#define CLK_ENMBUSCLK BIT(17) ++#define CLK_ENSPICLK BIT(16) ++#define CLK_ENTIMERCLK BIT(15) ++#define CLK_ENFASTTIMERCLK BIT(14) ++#define CLK_SIBMCLKDIR BIT(13) ++#define CLK_ENSIBMCLK BIT(11) ++#define CLK_SIBMCLKDIV_MASK (BIT(10) | BIT(9) | BIT(8)) ++#define CLK_SIBMCLKDIV_SHIFT 8 ++#define CLK_CSERSEL BIT(7) ++#define CLK_CSERDIV_MASK (BIT(6) | BIT(5) | BIT(4)) ++#define CLK_CSERDIV_SHIFT 4 ++#define CLK_ENCSERCLK BIT(3) ++#define CLK_ENIRCLK BIT(2) ++#define CLK_EN_UART_A BIT(1) ++#define CLK_EN_UART_B BIT(0) ++ ++ ++/****************************************************************************** ++* ++* 07 CHI module ++* ++******************************************************************************/ ++ ++#define CHIControl REG_AT(0x1D8) ++#define CHIPointerEnable REG_AT(0x1DC) ++#define CHIReceivePtrA REG_AT(0x1E0) ++#define CHIReceivePtrB REG_AT(0x1E4) ++#define CHITransmitPtrA REG_AT(0x1E8) ++#define CHITransmitPtrB REG_AT(0x1EC) ++#define CHISize REG_AT(0x1F0) ++#define CHIReceiveStart REG_AT(0x1F4) ++#define CHITransmitStart REG_AT(0x1F8) ++#define CHIHoldingReg REG_AT(0x1FC) ++ ++/* CHI Control Register */ ++/* */ ++#define CHI_RXEN BIT(2) ++#define CHI_TXEN BIT(1) ++#define CHI_ENCHI BIT(0) ++ ++ ++/****************************************************************************** ++* ++* 08 Interrupt module ++* ++******************************************************************************/ ++ ++/* Register locations */ ++ ++#define IntStatus1 REG_AT(0x100) ++#define IntStatus2 REG_AT(0x104) ++#define IntStatus3 REG_AT(0x108) ++#define IntStatus4 REG_AT(0x10c) ++#define IntStatus5 REG_AT(0x110) ++#define IntStatus6 REG_AT(0x114) ++ ++#define IntClear1 REG_AT(0x100) ++#define IntClear2 REG_AT(0x104) ++#define IntClear3 REG_AT(0x108) ++#define IntClear4 REG_AT(0x10c) ++#define IntClear5 REG_AT(0x110) ++#define IntClear6 REG_AT(0x114) ++ ++#define IntEnable1 REG_AT(0x118) ++#define IntEnable2 REG_AT(0x11c) ++#define IntEnable3 REG_AT(0x120) ++#define IntEnable4 REG_AT(0x124) ++#define IntEnable5 REG_AT(0x128) ++#define IntEnable6 REG_AT(0x12c) ++ ++/* Interrupt Status Register 1 at offset 100 */ ++#define INT1_LCDINT BIT(31) ++#define INT1_DFINT BIT(30) ++#define INT1_CHIDMAHALF BIT(29) ++#define INT1_CHIDMAFULL BIT(28) ++#define INT1_CHIDMACNTINT BIT(27) ++#define INT1_CHIRXAINT BIT(26) ++#define INT1_CHIRXBINT BIT(25) ++#define INT1_CHIACTINT BIT(24) ++#define INT1_CHIERRINT BIT(23) ++#define INT1_SND0_5INT BIT(22) ++#define INT1_SND1_0INT BIT(21) ++#define INT1_TEL0_5INT BIT(20) ++#define INT1_TEL1_0INT BIT(19) ++#define INT1_SNDDMACNTINT BIT(18) ++#define INT1_TELDMACNTINT BIT(17) ++#define INT1_LSNDCLIPINT BIT(16) ++#define INT1_RSNDCLIPINT BIT(15) ++#define INT1_VALSNDPOSINT BIT(14) ++#define INT1_VALSNDNEGINT BIT(13) ++#define INT1_VALTELPOSINT BIT(12) ++#define INT1_VALTELNEGINT BIT(11) ++#define INT1_SNDININT BIT(10) ++#define INT1_TELININT BIT(9) ++#define INT1_SIBSF0INT BIT(8) ++#define INT1_SIBSF1INT BIT(7) ++#define INT1_SIBIRQPOSINT BIT(6) ++#define INT1_SIBIRQNEGINT BIT(5) ++ ++/* Interrupt Status Register 2 at offset 104 */ ++#define INT2_UARTARXINT BIT(31) ++#define INT2_UARTARXOVERRUN BIT(30) ++#define INT2_UARTAFRAMEINT BIT(29) ++#define INT2_UARTABREAKINT BIT(28) ++#define INT2_UARTATXINT BIT(26) ++#define INT2_UARTATXOVERRUN BIT(25) ++#define INT2_UARTAEMPTY BIT(24) ++ ++#define INT2_UARTBRXINT BIT(21) ++#define INT2_UARTBRXOVERRUN BIT(20) ++#define INT2_UARTBFRAMEINT BIT(29) ++#define INT2_UARTBBREAKINT BIT(18) ++#define INT2_UARTBTXINT BIT(16) ++#define INT2_UARTBTXOVERRUN BIT(15) ++#define INT2_UARTBEMPTY BIT(14) ++ ++#define INT2_UARTA_RX (BIT(31) | BIT(30) | BIT(29) | BIT(28) | BIT(27)) ++#define INT2_UARTA_TX (BIT(26) | BIT(25) | BIT(24)) ++#define INT2_UARTA_DMA (BIT(23) | BIT(22)) ++ ++#define INT2_UARTB_RX (BIT(21) | BIT(20) | BIT(19) | BIT(18) | BIT(17)) ++#define INT2_UARTB_TX (BIT(16) | BIT(15) | BIT(14)) ++#define INT2_UARTB_DMA (BIT(13) | BIT(12)) ++ ++/* Interrupt Status Register 5 */ ++#define INT5_RTCINT BIT(31) ++#define INT5_ALARMINT BIT(30) ++#define INT5_PERIODICINT BIT(29) ++#define INT5_POSPWRINT BIT(27) ++#define INT5_NEGPWRINT BIT(26) ++#define INT5_POSPWROKINT BIT(25) ++#define INT5_NEGPWROKINT BIT(24) ++#define INT5_POSONBUTINT BIT(23) ++#define INT5_NEGONBUTINT BIT(22) ++#define INT5_SPIAVAILINT BIT(21) ++#define INT5_SPIRCVINT BIT(19) ++#define INT5_SPIEMPTYINT BIT(18) ++#define INT5_IOPOSINT6 BIT(13) ++#define INT5_IOPOSINT5 BIT(12) ++#define INT5_IOPOSINT4 BIT(11) ++#define INT5_IOPOSINT3 BIT(10) ++#define INT5_IOPOSINT2 BIT(9) ++#define INT5_IOPOSINT1 BIT(8) ++#define INT5_IOPOSINT0 BIT(7) ++#define INT5_IONEGINT6 BIT(6) ++#define INT5_IONEGINT5 BIT(5) ++#define INT5_IONEGINT4 BIT(4) ++#define INT5_IONEGINT3 BIT(3) ++#define INT5_IONEGINT2 BIT(2) ++#define INT5_IONEGINT1 BIT(1) ++#define INT5_IONEGINT0 BIT(0) ++ ++#define INT5_IONEGINT_SHIFT 0 ++#define INT5_IONEGINT_MASK (0x7F< + #include + #include ++#include + + /* + * This assumes you have a 1.8432 MHz clock for your UART. +@@ -29,6 +30,8 @@ + #define JAZZ_BASE_BAUD BASE_BAUD + #endif + ++#define VR41XX_BASE_BAUD 1152000 ++ + /* Standard COM flags (except for COM4, because of the 8514 problem) */ + #ifdef CONFIG_SERIAL_DETECT_IRQ + #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ) +@@ -76,6 +79,50 @@ + #define JAZZ_SERIAL_PORT_DEFNS + #endif + ++#ifdef CONFIG_CPU_VR41XX ++/* note: serial driver misbehaves if port == 0, even if port not used */ ++#define _VR41XX_SERIAL_INIT(base, irqno) \ ++ { type: PORT_16550A, \ ++ baud_base: VR41XX_BASE_BAUD, \ ++ port: (unsigned long)base, \ ++ irq: irqno, \ ++ flags: STD_COM_FLAGS, \ ++ iomem_base: (unsigned char *)base, \ ++ io_type: SERIAL_VADDR } ++ ++#ifdef CONFIG_CPU_VR4122 ++#define VR41XX_SERIAL_PORT_DEFNS \ ++ _VR41XX_SERIAL_INIT(VR41XX_SIURB, VR41XX_IRQ_SIU), /* ttyS0 */ \ ++ _VR41XX_SERIAL_INIT(VR41XX_SIURB, VR41XX_IRQ_SIU), /* ttyS1 (IrDA) */ ++#define MAX_VR_PORT 1 ++#define SHARED_RS232_LINE 0 ++#define SHARED_IRDA_LINE 1 ++#else ++#ifdef CONFIG_CPU_VR4181 ++ ++#define VR41XX_SERIAL_PORT_DEFNS \ ++ _VR41XX_SERIAL_INIT(VR41XX_SIURB, VR41XX_IRQ_SIU), /* ttyS0 */ \ ++ _VR41XX_SERIAL_INIT(VR41XX_SIURB_2, VR41XX_IRQ_SIU), /* ttyS1 (IrDA) */ \ ++ _VR41XX_SERIAL_INIT(VR41XX_SIURB_2, VR41XX_IRQ_SIU), /* ttyS2 */ ++#define MAX_VR_PORT 2 ++#define SHARED_RS232_LINE 2 ++#define SHARED_IRDA_LINE 1 ++ ++#else /* VR4121 and similar */ ++ ++#define VR41XX_SERIAL_PORT_DEFNS \ ++ _VR41XX_SERIAL_INIT(VR41XX_SIURB, VR41XX_IRQ_SIU), /* ttyS0 */ \ ++ _VR41XX_SERIAL_INIT(VR41XX_SIURB, VR41XX_IRQ_SIU), /* ttyS1 (IrDA) */ ++#define MAX_VR_PORT 1 ++#define SHARED_RS232_LINE 0 ++#define SHARED_IRDA_LINE 1 ++#endif /* CONFIG_CPU_VR4181 */ ++#endif /* CONFIG_CPU_VR4122 */ ++ ++#else /* non-VR41xx */ ++#define VR41XX_SERIAL_PORT_DEFNS ++#endif ++ + #ifdef CONFIG_MIPS_EV96100 + #include + #include +@@ -163,9 +210,19 @@ + #define MCA_SERIAL_PORT_DFNS + #endif + ++#ifdef CONFIG_NEC_HARRIER ++#define NEC_HARRIER_SERIAL_PORT_DFNS \ ++ { 0, VR41XX_BASE_BAUD, (unsigned long)NEC_HARRIER_SIO1, VR41XX_IRQ_SIO, STD_COM_FLAGS }, /* ttyS1 */ \ ++ { 0, VR41XX_BASE_BAUD, (unsigned long)NEC_HARRIER_SIO2, VR41XX_IRQ_SIO, STD_COM_FLAGS }, /* ttyS2 */ ++#else ++#define NEC_HARRIER_SERIAL_PORT_DFNS ++#endif ++ + #define SERIAL_PORT_DFNS \ ++ VR41XX_SERIAL_PORT_DEFNS \ + EV96100_SERIAL_PORT_DEFNS \ + JAZZ_SERIAL_PORT_DEFNS \ + STD_SERIAL_PORT_DEFNS \ + EXTRA_SERIAL_PORT_DEFNS \ +- HUB6_SERIAL_PORT_DFNS ++ HUB6_SERIAL_PORT_DFNS \ ++ NEC_HARRIER_SERIAL_PORT_DFNS +diff -ruN linux-mips/include/asm-mips/stackframe.h linux-vr/include/asm-mips/stackframe.h +--- linux-mips/include/asm-mips/stackframe.h Fri Nov 10 00:12:08 2000 ++++ linux-vr/include/asm-mips/stackframe.h Thu Nov 23 15:11:38 2000 +@@ -144,7 +144,7 @@ + lw $23, PT_R23(sp); \ + lw $30, PT_R30(sp) + +-#if defined(CONFIG_CPU_R3000) ++#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_R39XX) + + #define RESTORE_SOME \ + .set push; \ +diff -ruN linux-mips/include/asm-mips/unaligned.h linux-vr/include/asm-mips/unaligned.h +--- linux-mips/include/asm-mips/unaligned.h Fri Nov 10 00:12:11 2000 ++++ linux-vr/include/asm-mips/unaligned.h Sun Nov 12 12:33:10 2000 +@@ -9,6 +9,8 @@ + #ifndef _ASM_UNALIGNED_H + #define _ASM_UNALIGNED_H + ++#include ++ + extern void __get_unaligned_bad_length(void); + extern void __put_unaligned_bad_length(void); + +diff -ruN linux-mips/include/asm-mips/vr4121.h linux-vr/include/asm-mips/vr4121.h +--- linux-mips/include/asm-mips/vr4121.h Wed Dec 31 16:00:00 1969 ++++ linux-vr/include/asm-mips/vr4121.h Wed Sep 13 08:25:13 2000 +@@ -0,0 +1,478 @@ ++/* $Id: vr4121.h,v 1.1 2000/06/05 01:30:57 brad Exp $ ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 1999 by Michael Klar ++ */ ++#ifndef __ASM_MIPS_VR4121_H ++#define __ASM_MIPS_VR4121_H ++ ++#include ++ ++// CPU interrupts ++#define VR41XX_IRQ_SW1 0 // IP0 - Software interrupt ++#define VR41XX_IRQ_SW2 1 // IP1 - Software interrupt ++#define VR41XX_IRQ_INT0 2 // IP2 - All but battery, high speed modem, and real time clock ++#define VR41XX_IRQ_INT1 3 // IP3 - RTC Long1 (system timer) ++#define VR41XX_IRQ_INT2 4 // IP4 - RTC Long2 ++#define VR41XX_IRQ_INT3 5 // IP5 - High Speed Modem ++#define VR41XX_IRQ_INT4 6 // IP6 - Unused ++#define VR41XX_IRQ_TIMER 7 // IP7 - Timer interrupt from CPO_COMPARE (Note: RTC Long1 is the system timer.) ++ ++// Cascaded from VR41XX_IRQ_INT0 (ICU mapped interrupts) ++#define VR41XX_IRQ_BATTERY 8 ++#define VR41XX_IRQ_POWER 9 ++#define VR41XX_IRQ_RTCL1 10 // Use VR41XX_IRQ_INT1 instead. ++#define VR41XX_IRQ_ETIMER 11 ++#define VR41XX_IRQ_RFU12 12 ++#define VR41XX_IRQ_PIU 13 ++#define VR41XX_IRQ_AIU 14 ++#define VR41XX_IRQ_KIU 15 ++#define VR41XX_IRQ_GIU 16 // This is a cascade to IRQs 40-71. Do not use. ++#define VR41XX_IRQ_SIU 17 ++#define VR41XX_IRQ_WRBERR 18 ++#define VR41XX_IRQ_SOFT 19 ++#define VR41XX_IRQ_RFU20 20 ++#define VR41XX_IRQ_DOZEPIU 21 ++#define VR41XX_IRQ_RFU22 22 ++#define VR41XX_IRQ_RFU23 23 ++#define VR41XX_IRQ_RTCL2 24 // Use VR41XX_IRQ_INT2 instead. ++#define VR41XX_IRQ_LED 25 ++#define VR41XX_IRQ_HSP 26 // Use VR41XX_IRQ_INT3 instead. ++#define VR41XX_IRQ_TCLK 27 ++#define VR41XX_IRQ_FIR 28 ++#define VR41XX_IRQ_DSIU 29 ++#define VR41XX_IRQ_RFU30 30 ++#define VR41XX_IRQ_RFU31 31 ++#define VR41XX_IRQ_RFU32 32 ++#define VR41XX_IRQ_RFU33 33 ++#define VR41XX_IRQ_RFU34 34 ++#define VR41XX_IRQ_RFU35 35 ++#define VR41XX_IRQ_RFU36 36 ++#define VR41XX_IRQ_RFU37 37 ++#define VR41XX_IRQ_RFU38 38 ++#define VR41XX_IRQ_RFU39 39 ++ ++// Cascaded from VR41XX_IRQ_GIU ++#define VR41XX_IRQ_GPIO0 40 ++#define VR41XX_IRQ_GPIO1 41 ++#define VR41XX_IRQ_GPIO2 42 ++#define VR41XX_IRQ_GPIO3 43 ++#define VR41XX_IRQ_GPIO4 44 ++#define VR41XX_IRQ_GPIO5 45 ++#define VR41XX_IRQ_GPIO6 46 ++#define VR41XX_IRQ_GPIO7 47 ++#define VR41XX_IRQ_GPIO8 48 ++#define VR41XX_IRQ_GPIO9 49 ++#define VR41XX_IRQ_GPIO10 50 ++#define VR41XX_IRQ_GPIO11 51 ++#define VR41XX_IRQ_GPIO12 52 ++#define VR41XX_IRQ_GPIO13 53 ++#define VR41XX_IRQ_GPIO14 54 ++#define VR41XX_IRQ_GPIO15 55 ++#define VR41XX_IRQ_GPIO16 56 ++#define VR41XX_IRQ_GPIO17 57 ++#define VR41XX_IRQ_GPIO18 58 ++#define VR41XX_IRQ_GPIO19 59 ++#define VR41XX_IRQ_GPIO20 60 ++#define VR41XX_IRQ_GPIO21 61 ++#define VR41XX_IRQ_GPIO22 62 ++#define VR41XX_IRQ_GPIO23 63 ++#define VR41XX_IRQ_GPIO24 64 ++#define VR41XX_IRQ_GPIO25 65 ++#define VR41XX_IRQ_GPIO26 66 ++#define VR41XX_IRQ_GPIO27 67 ++#define VR41XX_IRQ_GPIO28 68 ++#define VR41XX_IRQ_GPIO29 69 ++#define VR41XX_IRQ_GPIO30 70 ++#define VR41XX_IRQ_GPIO31 71 ++ ++// Alternative to above GPIO IRQ defines ++#define VR41XX_IRQ_GPIO(pin) ((VR41XX_IRQ_GPIO0) + (pin)) ++ ++#define VR41XX_IRQ_MAX 71 ++ ++#ifndef _LANGUAGE_ASSEMBLY ++#define __preg8 (volatile unsigned char*) ++#define __preg16 (volatile unsigned short*) ++#define __preg32 (volatile unsigned int*) ++#else ++#define __preg8 ++#define __preg16 ++#define __preg32 ++#endif ++ ++// Embedded CPU peripheral registers ++ ++// Bus Control Unit (BCU) ++#define VR41XX_BCUCNTREG1 __preg16(KSEG1 + 0x0B000000) /* BCU Control Register 1 (R/W) */ ++#define VR41XX_BCUCNTREG2 __preg16(KSEG1 + 0x0B000002) /* BCU Control Register 2 (R/W) */ ++#define VR41XX_ROMSIZEREG __preg16(KSEG1 + 0x0B000004) /* ROM Size Register (R/W) */ ++#define VR41XX_RAMSIZEREG __preg16(KSEG1 + 0x0B000006) /* DRAM Size Register (R/W) */ ++#define VR41XX_BCUSPEEDREG __preg16(KSEG1 + 0x0B00000A) /* BCU Access Cycle Change Register (R/W) */ ++#define VR41XX_BCUERRSTREG __preg16(KSEG1 + 0x0B00000C) /* BCU BUS ERROR Status Register (R/W) */ ++#define VR41XX_BCURFCNTREG __preg16(KSEG1 + 0x0B00000E) /* BCU Refresh Control Register (R/W) */ ++#define VR41XX_REVIDREG __preg16(KSEG1 + 0x0B000010) /* Revision ID Register (R) */ ++#define VR41XX_BCURFCOUNTREG __preg16(KSEG1 + 0x0B000012) /* BCU Refresh Count Register (R/W) */ ++#define VR41XX_CLKSPEEDREG __preg16(KSEG1 + 0x0B000014) /* Clock Speed Register (R) */ ++#define VR41XX_BCUCNTREG3 __preg16(KSEG1 + 0x0B000016) /* BCU Control Register 3 (R/W) */ ++#define VR41XX_SDRAMMODEREG __preg16(KSEG1 + 0x0B00001A) /* SDRAM Mode Register */ ++#define VR41XX_SROMMODEREG __preg16(KSEG1 + 0x0B00001C) /* SROM Mode Register */ ++#define VR41XX_SDRAMCNTREG __preg16(KSEG1 + 0x0B00001E) /* SDRAM Control Register */ ++#define VR41XX_BCUTOUTCNTREG __preg16(KSEG1 + 0x0B000300) /* BCU Timeout Control Register */ ++#define VR41XX_BCUTOUTCOUNTREG __preg16(KSEG1 + 0x0B000302) /* BCU Timeout Count Register */ ++ ++// DMA Address Unit (DMAAU) ++#define VR41XX_AIUIBALREG __preg16(KSEG1 + 0x0B000020) /* AIU IN DMA Base Address Register Low (R/W) */ ++#define VR41XX_AIUIBAHREG __preg16(KSEG1 + 0x0B000022) /* AIU IN DMA Base Address Register High (R/W) */ ++#define VR41XX_AIUIALREG __preg16(KSEG1 + 0x0B000024) /* AIU IN DMA Address Register Low (R/W) */ ++#define VR41XX_AIUIAHREG __preg16(KSEG1 + 0x0B000026) /* AIU IN DMA Address Register High (R/W) */ ++#define VR41XX_AIUOBALREG __preg16(KSEG1 + 0x0B000028) /* AIU OUT DMA Base Address Register Low (R/W) */ ++#define VR41XX_AIUOBAHREG __preg16(KSEG1 + 0x0B00002A) /* AIU OUT DMA Base Address Register High (R/W) */ ++#define VR41XX_AIUOALREG __preg16(KSEG1 + 0x0B00002C) /* AIU OUT DMA Address Register Low (R/W) */ ++#define VR41XX_AIUOAHREG __preg16(KSEG1 + 0x0B00002E) /* AIU OUT DMA Address Register High (R/W) */ ++#define VR41XX_FIRBALREG __preg16(KSEG1 + 0x0B000030) /* FIR DMA Base Address Register Low (R/W) */ ++#define VR41XX_FIRBAHREG __preg16(KSEG1 + 0x0B000032) /* FIR DMA Base Address Register High (R/W) */ ++#define VR41XX_FIRALREG __preg16(KSEG1 + 0x0B000034) /* FIR DMA Address Register Low (R/W) */ ++#define VR41XX_FIRAHREG __preg16(KSEG1 + 0x0B000036) /* FIR DMA Address Register High (R/W) */ ++ ++// DMA Control Unit (DCU) ++#define VR41XX_DMARSTREG __preg16(KSEG1 + 0x0B000040) /* DMA Reset Register (R/W) */ ++#define VR41XX_DMAIDLEREG __preg16(KSEG1 + 0x0B000042) /* DMA Idle Register (R) */ ++#define VR41XX_DMASENREG __preg16(KSEG1 + 0x0B000044) /* DMA Sequencer Enable Register (R/W) */ ++#define VR41XX_DMAMSKREG __preg16(KSEG1 + 0x0B000046) /* DMA Mask Register (R/W) */ ++#define VR41XX_DMAREQREG __preg16(KSEG1 + 0x0B000048) /* DMA Request Register (R) */ ++#define VR41XX_TDREG __preg16(KSEG1 + 0x0B00004A) /* Transfer Direction Register (R/W) */ ++ ++// Clock Mask Unit (CMU) ++#define VR41XX_CMUCLKMSK __preg16(KSEG1 + 0x0B000060) /* CMU Clock Mask Register (R/W) */ ++#define VR41XX_CMUCLKMSK_MSKPIUPCLK 0x0001 ++#define VR41XX_CMUCLKMSK_MSKSIU 0x0102 ++ ++// Interrupt Control Unit (ICU) ++#define VR41XX_SYSINT1REG __preg16(KSEG1 + 0x0B000080) /* Level 1 System interrupt register 1 (R) */ ++#define VR41XX_PIUINTREGro __preg16(KSEG1 + 0x0B000082) /* Level 2 PIU interrupt register (R) */ ++#define VR41XX_AIUINTREG __preg16(KSEG1 + 0x0B000084) /* Level 2 AIU interrupt register (R) */ ++#define VR41XX_KIUINTREG __preg16(KSEG1 + 0x0B000086) /* Level 2 KIU interrupt register (R) */ ++#define VR41XX_GIUINTLREG __preg16(KSEG1 + 0x0B000088) /* Level 2 GIU interrupt register Low (R) */ ++#define VR41XX_DSIUINTREG __preg16(KSEG1 + 0x0B00008A) /* Level 2 DSIU interrupt register (R) */ ++#define VR41XX_MSYSINT1REG __preg16(KSEG1 + 0x0B00008C) /* Level 1 mask system interrupt register 1 (R/W) */ ++#define VR41XX_MPIUINTREG __preg16(KSEG1 + 0x0B00008E) /* Level 2 mask PIU interrupt register (R/W) */ ++#define VR41XX_MAIUINTREG __preg16(KSEG1 + 0x0B000090) /* Level 2 mask AIU interrupt register (R/W) */ ++#define VR41XX_MKIUINTREG __preg16(KSEG1 + 0x0B000092) /* Level 2 mask KIU interrupt register (R/W) */ ++#define VR41XX_MGIUINTLREG __preg16(KSEG1 + 0x0B000094) /* Level 2 mask GIU interrupt register Low (R/W) */ ++#define VR41XX_MDSIUINTREG __preg16(KSEG1 + 0x0B000096) /* Level 2 mask DSIU interrupt register (R/W) */ ++#define VR41XX_NMIREG __preg16(KSEG1 + 0x0B000098) /* NMI register (R/W) */ ++#define VR41XX_SOFTINTREG __preg16(KSEG1 + 0x0B00009A) /* Software interrupt register (R/W) */ ++#define VR41XX_SYSINT2REG __preg16(KSEG1 + 0x0B000200) /* Level 1 System interrupt register 2 (R) */ ++#define VR41XX_GIUINTHREG __preg16(KSEG1 + 0x0B000202) /* Level 2 GIU interrupt register High (R) */ ++#define VR41XX_FIRINTREG __preg16(KSEG1 + 0x0B000204) /* Level 2 FIR interrupt register (R) */ ++#define VR41XX_MSYSINT2REG __preg16(KSEG1 + 0x0B000206) /* Level 1 mask system interrupt register 2 (R/W) */ ++#define VR41XX_MGIUINTHREG __preg16(KSEG1 + 0x0B000208) /* Level 2 mask GIU interrupt register High (R/W) */ ++#define VR41XX_MFIRINTREG __preg16(KSEG1 + 0x0B00020A) /* Level 2 mask FIR interrupt register (R/W) */ ++ ++// Power Management Unit (PMU) ++#define VR41XX_PMUINTREG __preg16(KSEG1 + 0x0B0000A0) /* PMU Status Register (R/W) */ ++#define VR41XX_PMUINT_POWERSW 0x1 /* Power switch */ ++#define VR41XX_PMUINT_BATT 0x2 /* Low batt during normal operation */ ++#define VR41XX_PMUINT_DEADMAN 0x4 /* Deadman's switch */ ++#define VR41XX_PMUINT_RESET 0x8 /* Reset switch */ ++#define VR41XX_PMUINT_RTCRESET 0x10 /* RTC Reset */ ++#define VR41XX_PMUINT_TIMEOUT 0x20 /* HAL Timer Reset */ ++#define VR41XX_PMUINT_BATTLOW 0x100 /* Battery low */ ++#define VR41XX_PMUINT_RTC 0x200 /* RTC Alarm */ ++#define VR41XX_PMUINT_DCD 0x400 /* DCD# */ ++#define VR41XX_PMUINT_GPIO0 0x1000 /* GPIO0 */ ++#define VR41XX_PMUINT_GPIO1 0x2000 /* GPIO1 */ ++#define VR41XX_PMUINT_GPIO2 0x4000 /* GPIO2 */ ++#define VR41XX_PMUINT_GPIO3 0x8000 /* GPIO3 */ ++ ++#define VR41XX_PMUCNTREG __preg16(KSEG1 + 0x0B0000A2) /* PMU Control Register (R/W) */ ++#define VR41XX_PMUWAITREG __preg16(KSEG1 + 0x0B0000A8) /* PMU Wait Counter Register (R/W) */ ++#define VR41XX_PMUINT2REG __preg16(KSEG1 + 0x0B0000A4) /* PMU Interrupt/Status 2 Register (R/W) */ ++#define VR41XX_PMUCNT2REG __preg16(KSEG1 + 0x0B0000A6) /* PMU Control 2 Resister (R/W) */ ++ ++// Real Time Clock Unit (RTC) ++#define VR41XX_ETIMELREG __preg16(KSEG1 + 0x0B0000C0) /* Elapsed Time L Register (R/W) */ ++#define VR41XX_ETIMEMREG __preg16(KSEG1 + 0x0B0000C2) /* Elapsed Time M Register (R/W) */ ++#define VR41XX_ETIMEHREG __preg16(KSEG1 + 0x0B0000C4) /* Elapsed Time H Register (R/W) */ ++#define VR41XX_ECMPLREG __preg16(KSEG1 + 0x0B0000C8) /* Elapsed Compare L Register (R/W) */ ++#define VR41XX_ECMPMREG __preg16(KSEG1 + 0x0B0000CA) /* Elapsed Compare M Register (R/W) */ ++#define VR41XX_ECMPHREG __preg16(KSEG1 + 0x0B0000CC) /* Elapsed Compare H Register (R/W) */ ++#define VR41XX_RTCL1LREG __preg16(KSEG1 + 0x0B0000D0) /* RTC Long 1 L Register (R/W) */ ++#define VR41XX_RTCL1HREG __preg16(KSEG1 + 0x0B0000D2) /* RTC Long 1 H Register (R/W) */ ++#define VR41XX_RTCL1CNTLREG __preg16(KSEG1 + 0x0B0000D4) /* RTC Long 1 Count L Register (R) */ ++#define VR41XX_RTCL1CNTHREG __preg16(KSEG1 + 0x0B0000D6) /* RTC Long 1 Count H Register (R) */ ++#define VR41XX_RTCL2LREG __preg16(KSEG1 + 0x0B0000D8) /* RTC Long 2 L Register (R/W) */ ++#define VR41XX_RTCL2HREG __preg16(KSEG1 + 0x0B0000DA) /* RTC Long 2 H Register (R/W) */ ++#define VR41XX_RTCL2CNTLREG __preg16(KSEG1 + 0x0B0000DC) /* RTC Long 2 Count L Register (R) */ ++#define VR41XX_RTCL2CNTHREG __preg16(KSEG1 + 0x0B0000DE) /* RTC Long 2 Count H Register (R) */ ++#define VR41XX_RTCINTREG __preg16(KSEG1 + 0x0B0001DE) /* RTC Interrupt Register (R/W) */ ++#define VR41XX_TCLKLREG __preg16(KSEG1 + 0x0B0001C0) /* TCLK L Register (R/W) */ ++#define VR41XX_TCLKHREG __preg16(KSEG1 + 0x0B0001C2) /* TCLK H Register (R/W) */ ++#define VR41XX_TCLKCNTLREG __preg16(KSEG1 + 0x0B0001C4) /* TCLK Count L Register (R) */ ++#define VR41XX_TCLKCNTHREG __preg16(KSEG1 + 0x0B0001C6) /* TCLK Count H Register (R) */ ++ ++// Deadman's Switch Unit (DSU) ++#define VR41XX_DSUCNTREG __preg16(KSEG1 + 0x0B0000E0) /* DSU Control Register (R/W) */ ++#define VR41XX_DSUSETREG __preg16(KSEG1 + 0x0B0000E2) /* DSU Dead Time Set Register (R/W) */ ++#define VR41XX_DSUCLRREG __preg16(KSEG1 + 0x0B0000E4) /* DSU Clear Register (W) */ ++#define VR41XX_DSUTIMREG __preg16(KSEG1 + 0x0B0000E6) /* DSU Elapsed Time Register (R/W) */ ++ ++// General Purpose I/O Unit (GIU) ++#define VR41XX_GIUIOSELL __preg16(KSEG1 + 0x0B000100) /* GPIO Input/Output Select Register L (R/W) */ ++#define VR41XX_GIUIOSELH __preg16(KSEG1 + 0x0B000102) /* GPIO Input/Output Select Register H (R/W) */ ++#define VR41XX_GIUPIODL __preg16(KSEG1 + 0x0B000104) /* GPIO Port Input/Output Data Register L (R/W) */ ++#define VR41XX_GIUPIODL_GPIO15 0x8000 ++#define VR41XX_GIUPIODL_GPIO14 0x4000 ++#define VR41XX_GIUPIODL_GPIO13 0x2000 ++#define VR41XX_GIUPIODL_GPIO12 0x1000 ++#define VR41XX_GIUPIODL_GPIO11 0x0800 ++#define VR41XX_GIUPIODL_GPIO10 0x0400 ++#define VR41XX_GIUPIODL_GPIO9 0x0200 ++#define VR41XX_GIUPIODL_GPIO8 0x0100 ++#define VR41XX_GIUPIODL_GPIO7 0x0080 ++#define VR41XX_GIUPIODL_GPIO6 0x0040 ++#define VR41XX_GIUPIODL_GPIO5 0x0020 ++#define VR41XX_GIUPIODL_GPIO4 0x0010 ++#define VR41XX_GIUPIODL_GPIO3 0x0008 ++#define VR41XX_GIUPIODL_GPIO2 0x0004 ++#define VR41XX_GIUPIODL_GPIO1 0x0002 ++#define VR41XX_GIUPIODL_GPIO0 0x0001 ++#define VR41XX_GIUPIODH __preg16(KSEG1 + 0x0B000106) /* GPIO Port Input/Output Data Register H (R/W) */ ++#define VR41XX_GIUPIODH_GPIO31 0x8000 ++#define VR41XX_GIUPIODH_GPIO30 0x4000 ++#define VR41XX_GIUPIODH_GPIO29 0x2000 ++#define VR41XX_GIUPIODH_GPIO28 0x1000 ++#define VR41XX_GIUPIODH_GPIO27 0x0800 ++#define VR41XX_GIUPIODH_GPIO26 0x0400 ++#define VR41XX_GIUPIODH_GPIO25 0x0200 ++#define VR41XX_GIUPIODH_GPIO24 0x0100 ++#define VR41XX_GIUPIODH_GPIO23 0x0080 ++#define VR41XX_GIUPIODH_GPIO22 0x0040 ++#define VR41XX_GIUPIODH_GPIO21 0x0020 ++#define VR41XX_GIUPIODH_GPIO20 0x0010 ++#define VR41XX_GIUPIODH_GPIO19 0x0008 ++#define VR41XX_GIUPIODH_GPIO18 0x0004 ++#define VR41XX_GIUPIODH_GPIO17 0x0002 ++#define VR41XX_GIUPIODH_GPIO16 0x0001 ++#define VR41XX_GIUINTSTATL __preg16(KSEG1 + 0x0B000108) /* GPIO Interrupt Status Register L (R/W) */ ++#define VR41XX_GIUINTSTATH __preg16(KSEG1 + 0x0B00010A) /* GPIO Interrupt Status Register H (R/W) */ ++#define VR41XX_GIUINTENL __preg16(KSEG1 + 0x0B00010C) /* GPIO Interrupt Enable Register L (R/W) */ ++#define VR41XX_GIUINTENH __preg16(KSEG1 + 0x0B00010E) /* GPIO Interrupt Enable Register H (R/W) */ ++#define VR41XX_GIUINTTYPL __preg16(KSEG1 + 0x0B000110) /* GPIO Interrupt Type (Edge or Level) Select Register (R/W) */ ++#define VR41XX_GIUINTTYPH __preg16(KSEG1 + 0x0B000112) /* GPIO Interrupt Type (Edge or Level) Select Register (R/W) */ ++#define VR41XX_GIUINTALSELL __preg16(KSEG1 + 0x0B000114) /* GPIO Interrupt Active Level Select Register L (R/W) */ ++#define VR41XX_GIUINTALSELH __preg16(KSEG1 + 0x0B000116) /* GPIO Interrupt Active Level Select Register H (R/W) */ ++#define VR41XX_GIUINTHTSELL __preg16(KSEG1 + 0x0B000118) /* GPIO Interrupt Hold/Through Select Register L (R/W) */ ++#define VR41XX_GIUINTHTSELH __preg16(KSEG1 + 0x0B00011A) /* GPIO Interrupt Hold/Through Select Register H (R/W) */ ++ ++#define VR41XX_GIUPODATL __preg16(KSEG1 + 0x0B00011C) /* GPIO Port Output Data Register L (R/W) */ ++#define VR41XX_GIUPODATL_GPIO47 0x8000 ++#define VR41XX_GIUPODATL_GPIO46 0x4000 ++#define VR41XX_GIUPODATL_GPIO45 0x2000 ++#define VR41XX_GIUPODATL_GPIO44 0x1000 ++#define VR41XX_GIUPODATL_GPIO43 0x0800 ++#define VR41XX_GIUPODATL_GPIO42 0x0400 ++#define VR41XX_GIUPODATL_GPIO41 0x0200 ++#define VR41XX_GIUPODATL_GPIO40 0x0100 ++#define VR41XX_GIUPODATL_GPIO39 0x0080 ++#define VR41XX_GIUPODATL_GPIO38 0x0040 ++#define VR41XX_GIUPODATL_GPIO37 0x0020 ++#define VR41XX_GIUPODATL_GPIO36 0x0010 ++#define VR41XX_GIUPODATL_GPIO35 0x0008 ++#define VR41XX_GIUPODATL_GPIO34 0x0004 ++#define VR41XX_GIUPODATL_GPIO33 0x0002 ++#define VR41XX_GIUPODATL_GPIO32 0x0001 ++#define VR41XX_GIUPODATL_PODAT15 0x8000 ++#define VR41XX_GIUPODATL_PODAT14 0x4000 ++#define VR41XX_GIUPODATL_PODAT13 0x2000 ++#define VR41XX_GIUPODATL_PODAT12 0x1000 ++#define VR41XX_GIUPODATL_PODAT11 0x0800 ++#define VR41XX_GIUPODATL_PODAT10 0x0400 ++#define VR41XX_GIUPODATL_PODAT9 0x0200 ++#define VR41XX_GIUPODATL_PODAT8 0x0100 ++#define VR41XX_GIUPODATL_PODAT7 0x0080 ++#define VR41XX_GIUPODATL_PODAT6 0x0040 ++#define VR41XX_GIUPODATL_PODAT5 0x0020 ++#define VR41XX_GIUPODATL_PODAT4 0x0010 ++#define VR41XX_GIUPODATL_PODAT3 0x0008 ++#define VR41XX_GIUPODATL_PODAT2 0x0004 ++#define VR41XX_GIUPODATL_PODAT1 0x0002 ++#define VR41XX_GIUPODATL_PODAT0 0x0001 ++#define VR41XX_GIUPODATH __preg16(KSEG1 + 0x0B00011E) /* GPIO Port Output Data Register H (R/W) */ ++#define VR41XX_GIUPODATH_GPIO51 0x0008 ++#define VR41XX_GIUPODATH_GPIO50 0x0004 ++#define VR41XX_GIUPODATH_GPIO49 0x0002 ++#define VR41XX_GIUPODATH_GPIO48 0x0001 ++#define VR41XX_GIUPODATH_PODAT3 0x0008 ++#define VR41XX_GIUPODATH_PODAT2 0x0004 ++#define VR41XX_GIUPODATH_PODAT1 0x0002 ++#define VR41XX_GIUPODATH_PODAT0 0x0001 ++#define VR41XX_GIUUSEUPDN __preg16(KSEG1 + 0x0B0002E0) /* GPIO Pullup/Down User Register (R/W) */ ++#define VR41XX_GIUTERMUPDN __preg16(KSEG1 + 0x0B0002E2) /* GPIO Terminal Pullup/Down Register (R/W) */ ++#define VR41XX_SECIRQMASKL VR41XX_GIUINTENL ++#define VR41XX_SECIRQMASKH VR41XX_GIUINTENH ++ ++// Touch Panel Interface Unit (PIU) ++#define VR41XX_PIUCNTREG __preg16(KSEG1 + 0x0B000122) /* PIU Control register (R/W) */ ++#define VR41XX_PIUCNTREG_PIUSEQEN 0x0004 ++#define VR41XX_PIUCNTREG_PIUPWR 0x0002 ++#define VR41XX_PIUCNTREG_PADRST 0x0001 ++ ++#define VR41XX_PIUINTREG __preg16(KSEG1 + 0x0B000124) /* PIU Interrupt cause register (R/W) */ ++#define VR41XX_PIUINTREG_OVP 0x8000 ++#define VR41XX_PIUINTREG_PADCMD 0x0040 ++#define VR41XX_PIUINTREG_PADADP 0x0020 ++#define VR41XX_PIUINTREG_PADPAGE1 0x0010 ++#define VR41XX_PIUINTREG_PADPAGE0 0x0008 ++#define VR41XX_PIUINTREG_PADDLOST 0x0004 ++#define VR41XX_PIUINTREG_PENCHG 0x0001 ++ ++#define VR41XX_PIUSIVLREG __preg16(KSEG1 + 0x0B000126) /* PIU Data sampling interval register (R/W) */ ++#define VR41XX_PIUSTBLREG __preg16(KSEG1 + 0x0B000128) /* PIU A/D converter start delay register (R/W) */ ++#define VR41XX_PIUCMDREG __preg16(KSEG1 + 0x0B00012A) /* PIU A/D command register (R/W) */ ++#define VR41XX_PIUASCNREG __preg16(KSEG1 + 0x0B000130) /* PIU A/D port scan register (R/W) */ ++#define VR41XX_PIUAMSKREG __preg16(KSEG1 + 0x0B000132) /* PIU A/D scan mask register (R/W) */ ++#define VR41XX_PIUCIVLREG __preg16(KSEG1 + 0x0B00013E) /* PIU Check interval register (R) */ ++#define VR41XX_PIUPB00REG __preg16(KSEG1 + 0x0B0002A0) /* PIU Page 0 Buffer 0 register (R/W) */ ++#define VR41XX_PIUPB01REG __preg16(KSEG1 + 0x0B0002A2) /* PIU Page 0 Buffer 1 register (R/W) */ ++#define VR41XX_PIUPB02REG __preg16(KSEG1 + 0x0B0002A4) /* PIU Page 0 Buffer 2 register (R/W) */ ++#define VR41XX_PIUPB03REG __preg16(KSEG1 + 0x0B0002A6) /* PIU Page 0 Buffer 3 register (R/W) */ ++#define VR41XX_PIUPB10REG __preg16(KSEG1 + 0x0B0002A8) /* PIU Page 1 Buffer 0 register (R/W) */ ++#define VR41XX_PIUPB11REG __preg16(KSEG1 + 0x0B0002AA) /* PIU Page 1 Buffer 1 register (R/W) */ ++#define VR41XX_PIUPB12REG __preg16(KSEG1 + 0x0B0002AC) /* PIU Page 1 Buffer 2 register (R/W) */ ++#define VR41XX_PIUPB13REG __preg16(KSEG1 + 0x0B0002AE) /* PIU Page 1 Buffer 3 register (R/W) */ ++#define VR41XX_PIUAB0REG __preg16(KSEG1 + 0x0B0002B0) /* PIU A/D scan Buffer 0 register (R/W) */ ++#define VR41XX_PIUAB1REG __preg16(KSEG1 + 0x0B0002B2) /* PIU A/D scan Buffer 1 register (R/W) */ ++#define VR41XX_PIUAB2REG __preg16(KSEG1 + 0x0B0002B4) /* PIU A/D scan Buffer 2 register (R/W) */ ++#define VR41XX_PIUAB3REG __preg16(KSEG1 + 0x0B0002B6) /* PIU A/D scan Buffer 3 register (R/W) */ ++#define VR41XX_PIUPB04REG __preg16(KSEG1 + 0x0B0002BC) /* PIU Page 0 Buffer 4 register (R/W) */ ++#define VR41XX_PIUPB14REG __preg16(KSEG1 + 0x0B0002BE) /* PIU Page 1 Buffer 4 register (R/W) */ ++ ++// Audio Interface Unit (AIU) ++#define VR41XX_SODATREG __preg16(KSEG1 + 0x0B000166) /* Speaker Output Data Register (R/W) */ ++#define VR41XX_SCNTREG __preg16(KSEG1 + 0x0B000168) /* Speaker Output Control Register (R/W) */ ++#define VR41XX_MIDATREG __preg16(KSEG1 + 0x0B000170) /* Mike Input Data Register (R/W) */ ++#define VR41XX_MCNTREG __preg16(KSEG1 + 0x0B000172) /* Mike Input Control Register (R/W) */ ++#define VR41XX_DVALIDREG __preg16(KSEG1 + 0x0B000178) /* Data Valid Register (R/W) */ ++#define VR41XX_SEQREG __preg16(KSEG1 + 0x0B00017A) /* Sequential Register (R/W) */ ++#define VR41XX_INTREG __preg16(KSEG1 + 0x0B00017C) /* Interrupt Register (R/W) */ ++#define VR41XX_MDMADATREG __preg16(KSEG1 + 0x0B000160) /* Mike DMA Data Register (R/W) */ ++#define VR41XX_SDMADATREG __preg16(KSEG1 + 0x0B000162) /* Speaker DMA Data Register (R/W) */ ++#define VR41XX_SCNVRREG __preg16(KSEG1 + 0x0B00016A) /* Speaker Conversion Rate Register (R/W) */ ++#define VR41XX_MCNVRREG __preg16(KSEG1 + 0x0B000174) /* Mike Conversion Rate Register (R/W) */ ++ ++// Keyboard Interface Unit (KIU) ++#define VR41XX_KIUDAT0 __preg16(KSEG1 + 0x0B000180) /* KIU Data0 Register (R/W) */ ++#define VR41XX_KIUDAT1 __preg16(KSEG1 + 0x0B000182) /* KIU Data1 Register (R/W) */ ++#define VR41XX_KIUDAT2 __preg16(KSEG1 + 0x0B000184) /* KIU Data2 Register (R/W) */ ++#define VR41XX_KIUDAT3 __preg16(KSEG1 + 0x0B000186) /* KIU Data3 Register (R/W) */ ++#define VR41XX_KIUDAT4 __preg16(KSEG1 + 0x0B000188) /* KIU Data4 Register (R/W) */ ++#define VR41XX_KIUDAT5 __preg16(KSEG1 + 0x0B00018A) /* KIU Data5 Register (R/W) */ ++#define VR41XX_KIUSCANREP __preg16(KSEG1 + 0x0B000190) /* KIU Scan/Repeat Register (R/W) */ ++#define VR41XX_KIUSCANREP_KEYEN 0x8000 ++#define VR41XX_KIUSCANREP_SCANSTP 0x0008 ++#define VR41XX_KIUSCANREP_SCANSTART 0x0004 ++#define VR41XX_KIUSCANREP_ATSTP 0x0002 ++#define VR41XX_KIUSCANREP_ATSCAN 0x0001 ++#define VR41XX_KIUSCANS __preg16(KSEG1 + 0x0B000192) /* KIU Scan Status Register (R) */ ++#define VR41XX_KIUWKS __preg16(KSEG1 + 0x0B000194) /* KIU Wait Keyscan Stable Register (R/W) */ ++#define VR41XX_KIUWKI __preg16(KSEG1 + 0x0B000196) /* KIU Wait Keyscan Interval Register (R/W) */ ++#define VR41XX_KIUINT __preg16(KSEG1 + 0x0B000198) /* KIU Interrupt Register (R/W) */ ++#define VR41XX_KIUINT_KDATLOST 0x0004 ++#define VR41XX_KIUINT_KDATRDY 0x0002 ++#define VR41XX_KIUINT_SCANINT 0x0001 ++#define VR41XX_KIURST __preg16(KSEG1 + 0x0B00019A) /* KIU Reset Register (W) */ ++#define VR41XX_KIUGPEN __preg16(KSEG1 + 0x0B00019C) /* KIU General Purpose Output Enable (R/W) */ ++#define VR41XX_SCANLINE __preg16(KSEG1 + 0x0B00019E) /* KIU Scan Line Register (R/W) */ ++ ++// Debug Serial Interface Unit (DSIU) ++#define VR41XX_PORTREG __preg16(KSEG1 + 0x0B0001A0) /* Port Change Register (R/W) */ ++#define VR41XX_MODEMREG __preg16(KSEG1 + 0x0B0001A2) /* Modem Control Register (R) */ ++#define VR41XX_ASIM00REG __preg16(KSEG1 + 0x0B0001A4) /* Asynchronous Mode 0 Register (R/W) */ ++#define VR41XX_ASIM01REG __preg16(KSEG1 + 0x0B0001A6) /* Asynchronous Mode 1 Register (R/W) */ ++#define VR41XX_RXB0RREG __preg16(KSEG1 + 0x0B0001A8) /* Receive Buffer Register (Extended) (R) */ ++#define VR41XX_RXB0LREG __preg16(KSEG1 + 0x0B0001AA) /* Receive Buffer Register (R) */ ++#define VR41XX_TXS0RREG __preg16(KSEG1 + 0x0B0001AC) /* Transmit Data Register (Extended) (R/W) */ ++#define VR41XX_TXS0LREG __preg16(KSEG1 + 0x0B0001AE) /* Transmit Data Register (R/W) */ ++#define VR41XX_ASIS0REG __preg16(KSEG1 + 0x0B0001B0) /* Status Register (R) */ ++#define VR41XX_INTR0REG __preg16(KSEG1 + 0x0B0001B2) /* Debug SIU Interrupt Register (R/W) */ ++#define VR41XX_BPRM0REG __preg16(KSEG1 + 0x0B0001B6) /* Baud rate Generator Prescaler Mode Register (R/W) */ ++#define VR41XX_DSIURESETREG __preg16(KSEG1 + 0x0B0001B8) /* Debug SIU Reset Register (R/W) */ ++ ++// LED Control Unit (LED) ++#define VR41XX_LEDHTSREG __preg16(KSEG1 + 0x0B000240) /* LED H Time Set register (R/W) */ ++#define VR41XX_LEDLTSREG __preg16(KSEG1 + 0x0B000242) /* LED L Time Set register (R/W) */ ++#define VR41XX_LEDCNTREG __preg16(KSEG1 + 0x0B000248) /* LED Control register (R/W) */ ++#define VR41XX_LEDASTCREG __preg16(KSEG1 + 0x0B00024A) /* LED Auto Stop Time Count register (R/W) */ ++#define VR41XX_LEDINTREG __preg16(KSEG1 + 0x0B00024C) /* LED Interrupt register (R/W) */ ++ ++// Serial Interface Unit (SIU / SIU1 and SIU2) ++#define VR41XX_SIURB __preg8(KSEG1 + 0x0C000000) /* Receiver Buffer Register (Read) DLAB = 0 (R) */ ++#define VR41XX_SIUTH __preg8(KSEG1 + 0x0C000000) /* Transmitter Holding Register (Write) DLAB = 0 (W) */ ++#define VR41XX_SIUDLL __preg8(KSEG1 + 0x0C000000) /* Divisor Latch (Least Significant Byte) DLAB = 1 (R/W) */ ++#define VR41XX_SIUIE __preg8(KSEG1 + 0x0C000001) /* Interrupt Enable DLAB = 0 (R/W) */ ++#define VR41XX_SIUDLM __preg8(KSEG1 + 0x0C000001) /* Divisor Latch (Most Significant Byte) DLAB = 1 (R/W) */ ++#define VR41XX_SIUIID __preg8(KSEG1 + 0x0C000002) /* Interrupt Identification Register (Read) (R) */ ++#define VR41XX_SIUFC __preg8(KSEG1 + 0x0C000002) /* FIFO Control Register (Write) (W) */ ++#define VR41XX_SIULC __preg8(KSEG1 + 0x0C000003) /* Line Control Register (R/W) */ ++#define VR41XX_SIUMC __preg8(KSEG1 + 0x0C000004) /* MODEM Control Register (R/W) */ ++#define VR41XX_SIULS __preg8(KSEG1 + 0x0C000005) /* Line Status Register (R/W) */ ++#define VR41XX_SIUMS __preg8(KSEG1 + 0x0C000006) /* MODEM Status Register (R/W) */ ++#define VR41XX_SIUSC __preg8(KSEG1 + 0x0C000007) /* Scratch Register (R/W) */ ++#define VR41XX_SIUIRSEL __preg8(KSEG1 + 0x0C000008) /* SIU/FIR IrDA Selector (R/W) */ ++#define VR41XX_SIURESET __preg8(KSEG1 + 0x0C000009) /* SIU Reset Register (R/W) */ ++#define VR41XX_SIUCSEL __preg8(KSEG1 + 0x0C00000A) /* SIU Echo-Back Control Register (R/W) */ ++ ++// Modem Interface Unit (HSP) ++// Not sure if some of these are right type, some may be 16 bit regs: ++#define VR41XX_HSPINIT __preg8(KSEG1 + 0x0C000020) /* HSP Initialize Register (R/W) */ ++#define VR41XX_HSPDATAL __preg8(KSEG1 + 0x0C000022) /* HSP Data Register L (R/W) */ ++#define VR41XX_HSPDATAH __preg8(KSEG1 + 0x0C000023) /* HSP Data Register H (R/W) */ ++#define VR41XX_HSPINDEX __preg8(KSEG1 + 0x0C000024) /* HSP Index Register (W) */ ++#define VR41XX_HSPID __preg8(KSEG1 + 0x0C000028) /* HSP ID Register (R) */ ++#define VR41XX_HSPPCS __preg8(KSEG1 + 0x0C000029) /* HSP I/O Address Program Confirmation Register (R) */ ++#define VR41XX_HSPPCTEL __preg8(KSEG1 + 0x0C000029) /* HSP Signature Checking Port (W) */ ++ ++// Fast IrDA Interface Unit (FIR) ++#define VR41XX_FRSTR __preg16(KSEG1 + 0x0C000040) /* FIR Reset register (R/W) */ ++#define VR41XX_DPINTR __preg16(KSEG1 + 0x0C000042) /* DMA Page Interrupt register (R/W) */ ++#define VR41XX_DPCNTR __preg16(KSEG1 + 0x0C000044) /* DMA Control register (R/W) */ ++#define VR41XX_TDR __preg16(KSEG1 + 0x0C000050) /* Transmit Data register (W) */ ++#define VR41XX_RDR __preg16(KSEG1 + 0x0C000052) /* Receive Data register (R) */ ++#define VR41XX_IMR __preg16(KSEG1 + 0x0C000054) /* Interrupt Mask register (R/W) */ ++#define VR41XX_FSR __preg16(KSEG1 + 0x0C000056) /* FIFO Setup register (R/W) */ ++#define VR41XX_IRSR1 __preg16(KSEG1 + 0x0C000058) /* Infrared Setup register 1 (R/W) */ ++#define VR41XX_CRCSR __preg16(KSEG1 + 0x0C00005C) /* CRC Setup register (R/W) */ ++#define VR41XX_FIRCR __preg16(KSEG1 + 0x0C00005E) /* FIR Control register (R/W) */ ++#define VR41XX_MIRCR __preg16(KSEG1 + 0x0C000060) /* MIR Control register (R/W) */ ++#define VR41XX_DMACR __preg16(KSEG1 + 0x0C000062) /* DMA Control register (R/W) */ ++#define VR41XX_DMAER __preg16(KSEG1 + 0x0C000064) /* DMA Enable register (R/W) */ ++#define VR41XX_TXIR __preg16(KSEG1 + 0x0C000066) /* Transmit Indication register (R) */ ++#define VR41XX_RXIR __preg16(KSEG1 + 0x0C000068) /* Receive Indication register (R) */ ++#define VR41XX_IFR __preg16(KSEG1 + 0x0C00006A) /* Interrupt Flag register (R) */ ++#define VR41XX_RXSTS __preg16(KSEG1 + 0x0C00006C) /* Receive Status (R) */ ++#define VR41XX_TXFL __preg16(KSEG1 + 0x0C00006E) /* Transmit Frame Length (R/W) */ ++#define VR41XX_MRXF __preg16(KSEG1 + 0x0C000070) /* Maximum Receive Frame Length (R/W) */ ++#define VR41XX_RXFL __preg16(KSEG1 + 0x0C000074) /* Receive Frame Length (R) */ ++ ++// physical address spaces ++#define VR41XX_LCD 0x0a000000 ++#define VR41XX_INTERNAL_IO_2 0x0b000000 ++#define VR41XX_INTERNAL_IO_1 0x0c000000 ++#define VR41XX_ISA_MEM 0x10000000 ++#define VR41XX_ISA_IO 0x14000000 ++#define VR41XX_ROM 0x18000000 ++ ++// This is the base address for IO port decoding to which the 16 bit IO port address ++// is added. Defining it to 0 will usually cause a kernel oops any time port IO is ++// attempted, which can be handy for turning up parts of the kernel that make ++// incorrect architecture assumptions (by assuming that everything acts like a PC), ++// but we need it correctly defined to use the PCMCIA/CF controller: ++#define VR41XX_PORT_BASE (KSEG1 + VR41XX_ISA_IO) ++#define VR41XX_ISAMEM_BASE (KSEG1 + VR41XX_ISA_MEM) ++ ++#endif /* __ASM_MIPS_VR4121_H */ +diff -ruN linux-mips/include/asm-mips/vr4122.h linux-vr/include/asm-mips/vr4122.h +--- linux-mips/include/asm-mips/vr4122.h Wed Dec 31 16:00:00 1969 ++++ linux-vr/include/asm-mips/vr4122.h Wed Nov 15 12:09:27 2000 +@@ -0,0 +1,472 @@ ++/* $Id: vr4122.h,v 1.1 2000/11/15 20:09:27 mikemac Exp $ ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 1999 by Michael Klar ++ * Copyright (C) 2000 by Michael R. McDonald ++ */ ++#ifndef __ASM_MIPS_VR4122_H ++#define __ASM_MIPS_VR4122_H ++ ++#include ++ ++/* CPU interrupts */ ++#define VR41XX_IRQ_SW1 0 /* IP0 - Software interrupt */ ++#define VR41XX_IRQ_SW2 1 /* IP1 - Software interrupt */ ++#define VR41XX_IRQ_INT0 2 /* IP2 - All but battery, high speed modem, and real time clock */ ++#define VR41XX_IRQ_INT1 3 /* IP3 - RTC Long1 (system timer) */ ++#define VR41XX_IRQ_INT2 4 /* IP4 - RTC Long2 */ ++#define VR41XX_IRQ_INT3 5 /* IP5 - High Speed Modem */ ++#define VR41XX_IRQ_INT4 6 /* IP6 - Unused */ ++#define VR41XX_IRQ_TIMER 7 /* IP7 - Timer interrupt from CPO_COMPARE (Note: RTC Long1 is the system timer.) */ ++ ++/* Cascaded from VR41XX_IRQ_INT0 (ICU mapped interrupts) */ ++#define VR41XX_IRQ_BATTERY 8 ++#define VR41XX_IRQ_POWER 9 ++#define VR41XX_IRQ_RTCL1 10 /* Use VR41XX_IRQ_INT1 instead. */ ++#define VR41XX_IRQ_ETIMER 11 ++#define VR41XX_IRQ_RFU12 12 ++#define VR41XX_IRQ_RFU13 13 ++#define VR41XX_IRQ_RFU14 14 ++#define VR41XX_IRQ_RFU15 15 ++#define VR41XX_IRQ_GIU 16 /* This is a cascade to IRQs 40-71. Do not use. */ ++#define VR41XX_IRQ_SIU 17 ++#define VR41XX_IRQ_WRBERR 18 ++#define VR41XX_IRQ_SOFT 19 ++#define VR41XX_IRQ_RFU20 20 ++#define VR41XX_IRQ_DOZEPIU 21 ++#define VR41XX_IRQ_RFU22 22 ++#define VR41XX_IRQ_RFU23 23 ++#define VR41XX_IRQ_RTCL2 24 /* Use VR41XX_IRQ_INT2 instead. */ ++#define VR41XX_IRQ_LED 25 ++#define VR41XX_IRQ_HSP 26 /* Use VR41XX_IRQ_INT3 instead. */ ++#define VR41XX_IRQ_TCLK 27 ++#define VR41XX_IRQ_FIR 28 ++#define VR41XX_IRQ_DSIU 29 ++#define VR41XX_IRQ_PCIU 30 ++#define VR41XX_IRQ_RFU31 31 ++#define VR41XX_IRQ_RFU32 32 ++#define VR41XX_IRQ_RFU33 33 ++#define VR41XX_IRQ_RFU34 34 ++#define VR41XX_IRQ_RFU35 35 ++#define VR41XX_IRQ_RFU36 36 ++#define VR41XX_IRQ_RFU37 37 ++#define VR41XX_IRQ_RFU38 38 ++#define VR41XX_IRQ_RFU39 39 ++ ++/* Cascaded from VR41XX_IRQ_GIU */ ++#define VR41XX_IRQ_GPIO0 40 ++#define VR41XX_IRQ_GPIO1 41 ++#define VR41XX_IRQ_GPIO2 42 ++#define VR41XX_IRQ_GPIO3 43 ++#define VR41XX_IRQ_GPIO4 44 ++#define VR41XX_IRQ_GPIO5 45 ++#define VR41XX_IRQ_GPIO6 46 ++#define VR41XX_IRQ_GPIO7 47 ++#define VR41XX_IRQ_GPIO8 48 ++#define VR41XX_IRQ_GPIO9 49 ++#define VR41XX_IRQ_GPIO10 50 ++#define VR41XX_IRQ_GPIO11 51 ++#define VR41XX_IRQ_GPIO12 52 ++#define VR41XX_IRQ_GPIO13 53 ++#define VR41XX_IRQ_GPIO14 54 ++#define VR41XX_IRQ_GPIO15 55 ++#define VR41XX_IRQ_GPIO16 56 ++#define VR41XX_IRQ_GPIO17 57 ++#define VR41XX_IRQ_GPIO18 58 ++#define VR41XX_IRQ_GPIO19 59 ++#define VR41XX_IRQ_GPIO20 60 ++#define VR41XX_IRQ_GPIO21 61 ++#define VR41XX_IRQ_GPIO22 62 ++#define VR41XX_IRQ_GPIO23 63 ++#define VR41XX_IRQ_GPIO24 64 ++#define VR41XX_IRQ_GPIO25 65 ++#define VR41XX_IRQ_GPIO26 66 ++#define VR41XX_IRQ_GPIO27 67 ++#define VR41XX_IRQ_GPIO28 68 ++#define VR41XX_IRQ_GPIO29 69 ++#define VR41XX_IRQ_GPIO30 70 ++#define VR41XX_IRQ_GPIO31 71 ++ ++#ifdef CONFIG_NEC_HARRIER ++#define VR41XX_IRQ_4173 VR41XX_IRQ_GPIO1 ++#define VR41XX_IRQ_MQ200 VR41XX_IRQ_GPIO4 ++#define VR41XX_IRQ_PCI VR41XX_IRQ_GPIO5 ++#define VR41XX_IRQ_SIO VR41XX_IRQ_GPIO8 ++#endif ++ ++/* Alternative to above GPIO IRQ defines */ ++#define VR41XX_IRQ_GPIO(pin) ((VR41XX_IRQ_GPIO0) + (pin)) ++ ++#define VR41XX_IRQ_MAX 71 ++ ++#ifndef _LANGUAGE_ASSEMBLY ++#define __preg8 (volatile unsigned char*) ++#define __preg16 (volatile unsigned short*) ++#define __preg32 (volatile unsigned int*) ++#else ++#define __preg8 ++#define __preg16 ++#define __preg32 ++#endif ++ ++/* Embedded CPU peripheral registers */ ++ ++/* Bus Control Unit (BCU) */ ++#define VR41XX_BCUCNTREG1 __preg16(KSEG1 + 0x0F000000) /* BCU Control Register 1 */ ++#define VR41XX_ROMSIZEREG __preg16(KSEG1 + 0x0F000004) /* ROM Size Register */ ++#define VR41XX_ROMSPEEDREG __preg16(KSEG1 + 0x0F000006) /* BCU Access Cycle Change Register */ ++#define VR41XX_BCUSPEEDREG VR41XX_ROMSPEEDREG /* BCU Access Cycle Change Register */ ++#define VR41XX_IO0SPEEDREG __preg16(KSEG1 + 0x0F000008) /* I/O Access Cycle Change Register 0 */ ++#define VR41XX_IO1SPEEDREG __preg16(KSEG1 + 0x0F00000A) /* I/O Access Cycle Change Register 1 */ ++#define VR41XX_REVIDREG __preg16(KSEG1 + 0x0F000010) /* Revision ID Register */ ++#define VR41XX_CLKSPEEDREG __preg16(KSEG1 + 0x0F000014) /* Clock Speed Register */ ++#define VR41XX_BCUCNTREG3 __preg16(KSEG1 + 0x0F000016) /* BCU Control Register 3 */ ++#define VR41XX_BCUCACHECNTREG __preg16(KSEG1 + 0x0F000018) /* BCU Cache Control Register */ ++ ++/* DMA Address Unit (DMAAU) */ ++#define VR41XX_CSIIBALREG __preg16(KSEG1 + 0x0F000020) /* CSI reception DMA base address register low */ ++#define VR41XX_CSIIBAHREG __preg16(KSEG1 + 0x0F000022) /* CSI reception DMA base address register high */ ++#define VR41XX_CSIIALREG __preg16(KSEG1 + 0x0F000024) /* CSI reception DMA address register low */ ++#define VR41XX_CSIIAHREG __preg16(KSEG1 + 0x0F000026) /* CSI reception DMA address register high */ ++#define VR41XX_CSIOBALREG __preg16(KSEG1 + 0x0F000028) /* CSI transmission DMA base address register low */ ++#define VR41XX_CSIOBAHREG __preg16(KSEG1 + 0x0F00002A) /* CSI transmission DMA base address register high */ ++#define VR41XX_CSIOALREG __preg16(KSEG1 + 0x0F00002C) /* CSI transmission DMA address register low */ ++#define VR41XX_CSIOAHREG __preg16(KSEG1 + 0x0F00002E) /* CSI transmission DMA address register high */ ++#define VR41XX_FIRBALREG __preg16(KSEG1 + 0x0F000030) /* FIR DMA Base Address Register Low */ ++#define VR41XX_FIRBAHREG __preg16(KSEG1 + 0x0F000032) /* FIR DMA Base Address Register High */ ++#define VR41XX_FIRALREG __preg16(KSEG1 + 0x0F000034) /* FIR DMA Address Register Low */ ++#define VR41XX_FIRAHREG __preg16(KSEG1 + 0x0F000036) /* FIR DMA Address Register High */ ++#define VR41XX_RAMBALREG __preg16(KSEG1 + 0x0F0001E0) /* RAM base address lower address between IO space and RAM */ ++#define VR41XX_RAMBAHREG __preg16(KSEG1 + 0x0F0001E2) /* RAM base address higher address between IO space and RAM */ ++#define VR41XX_RAMALREG __preg16(KSEG1 + 0x0F0001E4) /* RAM address lower address between IO space and RAM */ ++#define VR41XX_RAMAHREG __preg16(KSEG1 + 0x0F0001E6) /* RAM address higher address between IO space and RAM */ ++#define VR41XX_IOBALREG __preg16(KSEG1 + 0x0F0001E8) /* IO base address lower address between IO space and RAM */ ++#define VR41XX_IOBAHREG __preg16(KSEG1 + 0x0F0001EA) /* IO base address higher address between IO space and RAM */ ++#define VR41XX_IOALREG __preg16(KSEG1 + 0x0F0001EC) /* IO address lower address between IO space and RAM */ ++#define VR41XX_IOAHREG __preg16(KSEG1 + 0x0F0001EE) /* IO address higher address between IO space and RAM */ ++ ++/* DMA Control Unit (DCU) */ ++#define VR41XX_DMARSTREG __preg16(KSEG1 + 0x0F000040) /* DMA Reset Register */ ++#define VR41XX_DMAIDLEREG __preg16(KSEG1 + 0x0F000042) /* DMA Idle Register */ ++#define VR41XX_DMASENREG __preg16(KSEG1 + 0x0F000044) /* DMA Sequencer Enable Register */ ++#define VR41XX_DMAMSKREG __preg16(KSEG1 + 0x0F000046) /* DMA Mask Register */ ++#define VR41XX_DMAREQREG __preg16(KSEG1 + 0x0F000048) /* DMA Request Register */ ++#define VR41XX_TDREG __preg16(KSEG1 + 0x0F00004A) /* Transfer Direction Register */ ++#define VR41XX_DMAABITREG __preg16(KSEG1 + 0x0F00004C) /* DMA arbitration protocol selection register */ ++#define VR41XX_CONTROLREG __preg16(KSEG1 + 0x0F00004E) /* DMA control register */ ++#define VR41XX_BASSCNTLREG __preg16(KSEG1 + 0x0F000050) /* DMA transfer byte size register low */ ++#define VR41XX_BASSCNTHREG __preg16(KSEG1 + 0x0F000052) /* DMA transfer byte size register high */ ++#define VR41XX_CURRENTCNTLREG __preg16(KSEG1 + 0x0F000054) /* DMA remaining transfer byte size register low */ ++#define VR41XX_CURRENTCNTHREG __preg16(KSEG1 + 0x0F000056) /* DMA remaining transfer byte size register high */ ++#define VR41XX_TCINTR __preg16(KSEG1 + 0x0F000058) /* Terminal count interrupt request */ ++ ++/* Clock Mask Unit (CMU) */ ++#define VR41XX_CMUCLKMSK __preg16(KSEG1 + 0x0F000060) /* CMU Clock Mask Register */ ++#define VR41XX_CMUCLKMSK_MSKPIUPCLK 0x0001 ++#define VR41XX_CMUCLKMSK_MSKSIU 0x0102 ++ ++/* Interrupt Control Unit (ICU) */ ++#define VR41XX_SYSINT1REG __preg16(KSEG1 + 0x0F000080) /* Level 1 System interrupt register 1 */ ++#define VR41XX_GIUINTLREG __preg16(KSEG1 + 0x0F000088) /* Level 2 GIU interrupt register Low */ ++#define VR41XX_DSIUINTREG __preg16(KSEG1 + 0x0F00008A) /* Level 2 DSIU interrupt register */ ++#define VR41XX_MSYSINT1REG __preg16(KSEG1 + 0x0F00008C) /* Level 1 mask system interrupt register 1 */ ++#define VR41XX_MGIUINTLREG __preg16(KSEG1 + 0x0F000094) /* Level 2 mask GIU interrupt register Low */ ++#define VR41XX_MDSIUINTREG __preg16(KSEG1 + 0x0F000096) /* Level 2 mask DSIU interrupt register */ ++#define VR41XX_NMIREG __preg16(KSEG1 + 0x0F000098) /* NMI register */ ++#define VR41XX_SOFTINTREG __preg16(KSEG1 + 0x0F00009A) /* Software interrupt register */ ++#define VR41XX_SYSINT2REG __preg16(KSEG1 + 0x0F0000A0) /* Level 1 System interrupt register 2 */ ++#define VR41XX_GIUINTHREG __preg16(KSEG1 + 0x0F0000A2) /* Level 2 GIU interrupt register High */ ++#define VR41XX_FIRINTREG __preg16(KSEG1 + 0x0F0000A4) /* Level 2 FIR interrupt register */ ++#define VR41XX_MSYSINT2REG __preg16(KSEG1 + 0x0F0000A6) /* Level 1 mask system interrupt register 2 */ ++#define VR41XX_MGIUINTHREG __preg16(KSEG1 + 0x0F0000A8) /* Level 2 mask GIU interrupt register High */ ++#define VR41XX_MFIRINTREG __preg16(KSEG1 + 0x0F0000AA) /* Level 2 mask FIR interrupt register */ ++#define VR41XX_PCIINTREG __preg16(KSEG1 + 0x0F0000AC) /* Level 2 PCI interrupt register */ ++#define VR41XX_SCUINTREG __preg16(KSEG1 + 0x0F0000AE) /* Level 2 SCU interrupt register */ ++#define VR41XX_CSIINTREG __preg16(KSEG1 + 0x0F0000B0) /* Level 2 CSI interrupt register */ ++#define VR41XX_MPCIINTREG __preg16(KSEG1 + 0x0F0000B2) /* Level 2 mask PCI interrupt register */ ++#define VR41XX_MSCUINTREG __preg16(KSEG1 + 0x0F0000B4) /* Level 2 mask SCU interrupt register */ ++#define VR41XX_MCSIINTREG __preg16(KSEG1 + 0x0F0000B6) /* Level 2 mask CSI interrupt register */ ++ ++/* Power Management Unit (PMU) */ ++#define VR41XX_PMUINTREG __preg16(KSEG1 + 0x0F0000C0) /* PMU Status Register */ ++#define VR41XX_PMUINT_POWERSW 0x1 /* Power switch */ ++#define VR41XX_PMUINT_BATT 0x2 /* Low batt during normal operation */ ++#define VR41XX_PMUINT_DEADMAN 0x4 /* Deadman's switch */ ++#define VR41XX_PMUINT_RESET 0x8 /* Reset switch */ ++#define VR41XX_PMUINT_RTCRESET 0x10 /* RTC Reset */ ++#define VR41XX_PMUINT_TIMEOUT 0x20 /* HAL Timer Reset */ ++#define VR41XX_PMUINT_BATTLOW 0x100 /* Battery low */ ++#define VR41XX_PMUINT_RTC 0x200 /* RTC Alarm */ ++#define VR41XX_PMUINT_DCD 0x400 /* DCD# */ ++#define VR41XX_PMUINT_GPIO0 0x1000 /* GPIO0 */ ++#define VR41XX_PMUINT_GPIO1 0x2000 /* GPIO1 */ ++#define VR41XX_PMUINT_GPIO2 0x4000 /* GPIO2 */ ++#define VR41XX_PMUINT_GPIO3 0x8000 /* GPIO3 */ ++ ++#define VR41XX_PMUCNTREG __preg16(KSEG1 + 0x0F0000C2) /* PMU Control Register */ ++#define VR41XX_PMUINT2REG __preg16(KSEG1 + 0x0F0000C4) /* PMU Interrupt/Status 2 Register */ ++#define VR41XX_PMUCNT2REG __preg16(KSEG1 + 0x0F0000C6) /* PMU Control 2 Resister */ ++#define VR41XX_PMUWAITREG __preg16(KSEG1 + 0x0F0000C8) /* PMU Wait Counter Register */ ++#define VR41XX_PMUTCLKDIVREG __preg16(KSEG1 + 0x0F0000CC) /* PMU Tclk Div mode register */ ++#define VR41XX_PMUINTRCLKDIVREG __preg16(KSEG1 + 0x0F0000CE) /* PMU INT clock Div mode register */ ++#define VR41XX_PMUCLKRUNREG __preg16(KSEG1 + 0x0F0000D6) /* PMU CLKRUN control register */ ++ ++ ++/* Real Time Clock Unit (RTC) */ ++#define VR41XX_ETIMELREG __preg16(KSEG1 + 0x0F000100) /* Elapsed Time L Register */ ++#define VR41XX_ETIMEMREG __preg16(KSEG1 + 0x0F000102) /* Elapsed Time M Register */ ++#define VR41XX_ETIMEHREG __preg16(KSEG1 + 0x0F000104) /* Elapsed Time H Register */ ++#define VR41XX_ECMPLREG __preg16(KSEG1 + 0x0F000108) /* Elapsed Compare L Register */ ++#define VR41XX_ECMPMREG __preg16(KSEG1 + 0x0F00010A) /* Elapsed Compare M Register */ ++#define VR41XX_ECMPHREG __preg16(KSEG1 + 0x0F00010C) /* Elapsed Compare H Register */ ++#define VR41XX_RTCL1LREG __preg16(KSEG1 + 0x0F000110) /* RTC Long 1 L Register */ ++#define VR41XX_RTCL1HREG __preg16(KSEG1 + 0x0F000112) /* RTC Long 1 H Register */ ++#define VR41XX_RTCL1CNTLREG __preg16(KSEG1 + 0x0F000114) /* RTC Long 1 Count L Register */ ++#define VR41XX_RTCL1CNTHREG __preg16(KSEG1 + 0x0F000116) /* RTC Long 1 Count H Register */ ++#define VR41XX_RTCL2LREG __preg16(KSEG1 + 0x0F000118) /* RTC Long 2 L Register */ ++#define VR41XX_RTCL2HREG __preg16(KSEG1 + 0x0F00011A) /* RTC Long 2 H Register */ ++#define VR41XX_RTCL2CNTLREG __preg16(KSEG1 + 0x0F00011C) /* RTC Long 2 Count L Register */ ++#define VR41XX_RTCL2CNTHREG __preg16(KSEG1 + 0x0F00011E) /* RTC Long 2 Count H Register */ ++#define VR41XX_TCLKLREG __preg16(KSEG1 + 0x0F000120) /* TCLK L Register */ ++#define VR41XX_TCLKHREG __preg16(KSEG1 + 0x0F000122) /* TCLK H Register */ ++#define VR41XX_TCLKCNTLREG __preg16(KSEG1 + 0x0F000124) /* TCLK Count L Register */ ++#define VR41XX_TCLKCNTHREG __preg16(KSEG1 + 0x0F000126) /* TCLK Count H Register */ ++#define VR41XX_RTCINTREG __preg16(KSEG1 + 0x0F00013E) /* RTC Interrupt Register */ ++ ++/* Deadman's Switch Unit (DSU) */ ++#define VR41XX_DSUCNTREG __preg16(KSEG1 + 0x0F0000E0) /* DSU Control Register */ ++#define VR41XX_DSUSETREG __preg16(KSEG1 + 0x0F0000E2) /* DSU Dead Time Set Register */ ++#define VR41XX_DSUCLRREG __preg16(KSEG1 + 0x0F0000E4) /* DSU Clear Register */ ++#define VR41XX_DSUTIMREG __preg16(KSEG1 + 0x0F0000E6) /* DSU Elapsed Time Register */ ++ ++/* General Purpose I/O Unit (GIU) */ ++#define VR41XX_GIUIOSELL __preg16(KSEG1 + 0x0F000140) /* GPIO Input/Output Select Register L */ ++#define VR41XX_GIUIOSELH __preg16(KSEG1 + 0x0F000142) /* GPIO Input/Output Select Register H */ ++#define VR41XX_GIUPIODL __preg16(KSEG1 + 0x0F000144) /* GPIO Port Input/Output Data Register L */ ++#define VR41XX_GIUPIODL_GPIO15 0x8000 ++#define VR41XX_GIUPIODL_GPIO14 0x4000 ++#define VR41XX_GIUPIODL_GPIO13 0x2000 ++#define VR41XX_GIUPIODL_GPIO12 0x1000 ++#define VR41XX_GIUPIODL_GPIO11 0x0800 ++#define VR41XX_GIUPIODL_GPIO10 0x0400 ++#define VR41XX_GIUPIODL_GPIO9 0x0200 ++#define VR41XX_GIUPIODL_GPIO8 0x0100 ++#define VR41XX_GIUPIODL_GPIO7 0x0080 ++#define VR41XX_GIUPIODL_GPIO6 0x0040 ++#define VR41XX_GIUPIODL_GPIO5 0x0020 ++#define VR41XX_GIUPIODL_GPIO4 0x0010 ++#define VR41XX_GIUPIODL_GPIO3 0x0008 ++#define VR41XX_GIUPIODL_GPIO2 0x0004 ++#define VR41XX_GIUPIODL_GPIO1 0x0002 ++#define VR41XX_GIUPIODL_GPIO0 0x0001 ++#define VR41XX_GIUPIODH __preg16(KSEG1 + 0x0F000146) /* GPIO Port Input/Output Data Register H */ ++#define VR41XX_GIUPIODH_GPIO31 0x8000 ++#define VR41XX_GIUPIODH_GPIO30 0x4000 ++#define VR41XX_GIUPIODH_GPIO29 0x2000 ++#define VR41XX_GIUPIODH_GPIO28 0x1000 ++#define VR41XX_GIUPIODH_GPIO27 0x0800 ++#define VR41XX_GIUPIODH_GPIO26 0x0400 ++#define VR41XX_GIUPIODH_GPIO25 0x0200 ++#define VR41XX_GIUPIODH_GPIO24 0x0100 ++#define VR41XX_GIUPIODH_GPIO23 0x0080 ++#define VR41XX_GIUPIODH_GPIO22 0x0040 ++#define VR41XX_GIUPIODH_GPIO21 0x0020 ++#define VR41XX_GIUPIODH_GPIO20 0x0010 ++#define VR41XX_GIUPIODH_GPIO19 0x0008 ++#define VR41XX_GIUPIODH_GPIO18 0x0004 ++#define VR41XX_GIUPIODH_GPIO17 0x0002 ++#define VR41XX_GIUPIODH_GPIO16 0x0001 ++#define VR41XX_GIUINTSTATL __preg16(KSEG1 + 0x0F000148) /* GPIO Interrupt Status Register L */ ++#define VR41XX_GIUINTSTATH __preg16(KSEG1 + 0x0F00014A) /* GPIO Interrupt Status Register H */ ++#define VR41XX_GIUINTENL __preg16(KSEG1 + 0x0F00014C) /* GPIO Interrupt Enable Register L */ ++#define VR41XX_GIUINTENH __preg16(KSEG1 + 0x0F00014E) /* GPIO Interrupt Enable Register H */ ++#define VR41XX_GIUINTTYPL __preg16(KSEG1 + 0x0F000150) /* GPIO Interrupt Type (Edge or Level) Select Register */ ++#define VR41XX_GIUINTTYPH __preg16(KSEG1 + 0x0F000152) /* GPIO Interrupt Type (Edge or Level) Select Register */ ++#define VR41XX_GIUINTALSELL __preg16(KSEG1 + 0x0F000154) /* GPIO Interrupt Active Level Select Register L */ ++#define VR41XX_GIUINTALSELH __preg16(KSEG1 + 0x0F000156) /* GPIO Interrupt Active Level Select Register H */ ++#define VR41XX_GIUINTHTSELL __preg16(KSEG1 + 0x0F000158) /* GPIO Interrupt Hold/Through Select Register L */ ++#define VR41XX_GIUINTHTSELH __preg16(KSEG1 + 0x0F00015A) /* GPIO Interrupt Hold/Through Select Register H */ ++ ++#define VR41XX_GIUPODATEN __preg16(KSEG1 + 0x0F00015C) /* GPIO Port Output Data Enable Register */ ++#define VR41XX_GIUPODATL __preg16(KSEG1 + 0x0F00015E) /* GPIO Port Output Data Register L */ ++#define VR41XX_GIUPODATL_GPIO47 0x8000 ++#define VR41XX_GIUPODATL_GPIO46 0x4000 ++#define VR41XX_GIUPODATL_GPIO45 0x2000 ++#define VR41XX_GIUPODATL_GPIO44 0x1000 ++#define VR41XX_GIUPODATL_GPIO43 0x0800 ++#define VR41XX_GIUPODATL_GPIO42 0x0400 ++#define VR41XX_GIUPODATL_GPIO41 0x0200 ++#define VR41XX_GIUPODATL_GPIO40 0x0100 ++#define VR41XX_GIUPODATL_GPIO39 0x0080 ++#define VR41XX_GIUPODATL_GPIO38 0x0040 ++#define VR41XX_GIUPODATL_GPIO37 0x0020 ++#define VR41XX_GIUPODATL_GPIO36 0x0010 ++#define VR41XX_GIUPODATL_GPIO35 0x0008 ++#define VR41XX_GIUPODATL_GPIO34 0x0004 ++#define VR41XX_GIUPODATL_GPIO33 0x0002 ++#define VR41XX_GIUPODATL_GPIO32 0x0001 ++#define VR41XX_GIUPODATL_PODAT15 0x8000 ++#define VR41XX_GIUPODATL_PODAT14 0x4000 ++#define VR41XX_GIUPODATL_PODAT13 0x2000 ++#define VR41XX_GIUPODATL_PODAT12 0x1000 ++#define VR41XX_GIUPODATL_PODAT11 0x0800 ++#define VR41XX_GIUPODATL_PODAT10 0x0400 ++#define VR41XX_GIUPODATL_PODAT9 0x0200 ++#define VR41XX_GIUPODATL_PODAT8 0x0100 ++#define VR41XX_GIUPODATL_PODAT7 0x0080 ++#define VR41XX_GIUPODATL_PODAT6 0x0040 ++#define VR41XX_GIUPODATL_PODAT5 0x0020 ++#define VR41XX_GIUPODATL_PODAT4 0x0010 ++#define VR41XX_GIUPODATL_PODAT3 0x0008 ++#define VR41XX_GIUPODATL_PODAT2 0x0004 ++#define VR41XX_GIUPODATL_PODAT1 0x0002 ++#define VR41XX_GIUPODATL_PODAT0 0x0001 ++#define VR41XX_SECIRQMASKL VR41XX_GIUINTENL ++#define VR41XX_SECIRQMASKH VR41XX_GIUINTENH ++ ++/* SDRAM Control Unit (SDRAMU) */ ++#define VR41XX_SDRAMMODEREG __preg16(KSEG1 + 0x0F000400) /* SDRAM mode register */ ++#define VR41XX_SDRAMCNTREG __preg16(KSEG1 + 0x0F000402) /* SDRAM control register */ ++#define VR41XX_BCURFCNTREG __preg16(KSEG1 + 0x0F000404) /* BCU refresh control register */ ++#define VR41XX_BCURFCOUNTREG __preg16(KSEG1 + 0x0F000406) /* BCU refresh cycle count register */ ++#define VR41XX_RAMSIZEREG __preg16(KSEG1 + 0x0F000408) /* DRAM size register */ ++ ++/* Debug Serial Interface Unit (DSIU) */ ++#define VR41XX_PORTREG __preg16(KSEG1 + 0x0F000820) /* Port Change Register */ ++#define VR41XX_MODEMREG __preg16(KSEG1 + 0x0F000822) /* Modem Control Register */ ++#define VR41XX_ASIM00REG __preg16(KSEG1 + 0x0F000824) /* Asynchronous Mode 0 Register */ ++#define VR41XX_ASIM01REG __preg16(KSEG1 + 0x0F000826) /* Asynchronous Mode 1 Register */ ++#define VR41XX_RXB0RREG __preg16(KSEG1 + 0x0F000828) /* Receive Buffer Register (Extended) */ ++#define VR41XX_RXB0LREG __preg16(KSEG1 + 0x0F00082A) /* Receive Buffer Register */ ++#define VR41XX_TXS0RREG __preg16(KSEG1 + 0x0F00082C) /* Transmit Data Register (Extended) */ ++#define VR41XX_TXS0LREG __preg16(KSEG1 + 0x0F00082E) /* Transmit Data Register */ ++#define VR41XX_ASIS0REG __preg16(KSEG1 + 0x0F000830) /* Status Register */ ++#define VR41XX_INTR0REG __preg16(KSEG1 + 0x0F000832) /* Debug SIU Interrupt Register */ ++#define VR41XX_BPRM0REG __preg16(KSEG1 + 0x0F000836) /* Baud rate Generator Prescaler Mode Register */ ++#define VR41XX_DSIURESETREG __preg16(KSEG1 + 0x0F000838) /* Debug SIU Reset Register */ ++ ++/* LED Control Unit (LED) */ ++#define VR41XX_LEDHTSREG __preg16(KSEG1 + 0x0F000180) /* LED H Time Set register */ ++#define VR41XX_LEDLTSREG __preg16(KSEG1 + 0x0F000182) /* LED L Time Set register */ ++#define VR41XX_LEDCNTREG __preg16(KSEG1 + 0x0F000188) /* LED Control register */ ++#define VR41XX_LEDASTCREG __preg16(KSEG1 + 0x0F00018A) /* LED Auto Stop Time Count register */ ++#define VR41XX_LEDINTREG __preg16(KSEG1 + 0x0F00018C) /* LED Interrupt register */ ++ ++/* Serial Interface Unit (SIU / SIU1 and SIU2) */ ++#define VR41XX_SIURB __preg8(KSEG1 + 0x0F000800) /* Receiver Buffer Register (Read) DLAB = 0 */ ++#define VR41XX_SIUTH __preg8(KSEG1 + 0x0F000800) /* Transmitter Holding Register (Write) DLAB = 0 */ ++#define VR41XX_SIUDLL __preg8(KSEG1 + 0x0F000800) /* Divisor Latch (Least Significant Byte) DLAB = 1 */ ++#define VR41XX_SIUIE __preg8(KSEG1 + 0x0F000801) /* Interrupt Enable DLAB = 0 */ ++#define VR41XX_SIUDLM __preg8(KSEG1 + 0x0F000801) /* Divisor Latch (Most Significant Byte) DLAB = 1 */ ++#define VR41XX_SIUIID __preg8(KSEG1 + 0x0F000802) /* Interrupt Identification Register (Read) */ ++#define VR41XX_SIUFC __preg8(KSEG1 + 0x0F000802) /* FIFO Control Register (Write) */ ++#define VR41XX_SIULC __preg8(KSEG1 + 0x0F000803) /* Line Control Register */ ++#define VR41XX_SIUMC __preg8(KSEG1 + 0x0F000804) /* MODEM Control Register */ ++#define VR41XX_SIULS __preg8(KSEG1 + 0x0F000805) /* Line Status Register */ ++#define VR41XX_SIUMS __preg8(KSEG1 + 0x0F000806) /* MODEM Status Register */ ++#define VR41XX_SIUSC __preg8(KSEG1 + 0x0F000807) /* Scratch Register */ ++#define VR41XX_SIUIRSEL __preg8(KSEG1 + 0x0F000808) /* SIU/FIR IrDA Selector */ ++#define VR41XX_SIURESET __preg8(KSEG1 + 0x0F000809) /* SIU Reset Register */ ++#define VR41XX_SIUCSEL __preg8(KSEG1 + 0x0F00080A) /* SIU Echo-Back Control Register */ ++ ++/* Fast IrDA Interface Unit (FIR) */ ++#define VR41XX_FRSTR __preg16(KSEG1 + 0x0F000840) /* FIR Reset register */ ++#define VR41XX_DPINTR __preg16(KSEG1 + 0x0F000842) /* DMA Page Interrupt register */ ++#define VR41XX_DPCNTR __preg16(KSEG1 + 0x0F000844) /* DMA Control register */ ++#define VR41XX_TDR __preg16(KSEG1 + 0x0F000850) /* Transmit Data register */ ++#define VR41XX_RDR __preg16(KSEG1 + 0x0F000852) /* Receive Data register */ ++#define VR41XX_IMR __preg16(KSEG1 + 0x0F000854) /* Interrupt Mask register */ ++#define VR41XX_FSR __preg16(KSEG1 + 0x0F000856) /* FIFO Setup register */ ++#define VR41XX_IRSR1 __preg16(KSEG1 + 0x0F000858) /* Infrared Setup register 1 */ ++#define VR41XX_CRCSR __preg16(KSEG1 + 0x0F00085C) /* CRC Setup register */ ++#define VR41XX_FIRCR __preg16(KSEG1 + 0x0F00085E) /* FIR Control register */ ++#define VR41XX_MIRCR __preg16(KSEG1 + 0x0F000860) /* MIR Control register */ ++#define VR41XX_DMACR __preg16(KSEG1 + 0x0F000862) /* DMA Control register */ ++#define VR41XX_DMAER __preg16(KSEG1 + 0x0F000864) /* DMA Enable register */ ++#define VR41XX_TXIR __preg16(KSEG1 + 0x0F000866) /* Transmit Indication register */ ++#define VR41XX_RXIR __preg16(KSEG1 + 0x0F000868) /* Receive Indication register */ ++#define VR41XX_IFR __preg16(KSEG1 + 0x0F00086A) /* Interrupt Flag register */ ++#define VR41XX_RXSTS __preg16(KSEG1 + 0x0F00086C) /* Receive Status */ ++#define VR41XX_TXFL __preg16(KSEG1 + 0x0F00086E) /* Transmit Frame Length */ ++#define VR41XX_MRXF __preg16(KSEG1 + 0x0F000870) /* Maximum Receive Frame Length */ ++#define VR41XX_RXFL __preg16(KSEG1 + 0x0F000874) /* Receive Frame Length */ ++ ++/* PCI Interface Unit (PCIU) */ ++#define VR41XX_PCIMMAW1REG __preg32(KSEG1 + 0x0F000C00) ++#define VR41XX_PCIMMAW2REG __preg32(KSEG1 + 0x0F000C04) ++#define VR41XX_PCITAW1REG __preg32(KSEG1 + 0x0F000C08) ++#define VR41XX_PCITAW2REG __preg32(KSEG1 + 0x0F000C0C) ++#define VR41XX_PCIMIOAWREG __preg32(KSEG1 + 0x0F000C10) ++#define VR41XX_PCICONFDREG __preg32(KSEG1 + 0x0F000C14) ++#define VR41XX_PCICONFAREG __preg32(KSEG1 + 0x0F000C18) ++#define VR41XX_PCIMAILREG __preg32(KSEG1 + 0x0F000C1C) ++#define VR41XX_BUSERRADREG __preg32(KSEG1 + 0x0F000C24) ++#define VR41XX_INTCNTSTAREG __preg32(KSEG1 + 0x0F000C28) ++#define VR41XX_PCIEXACCREG __preg32(KSEG1 + 0x0F000C2C) ++#define VR41XX_PCIRECONTREG __preg32(KSEG1 + 0x0F000C30) ++#define VR41XX_PCIENREG __preg32(KSEG1 + 0x0F000C34) ++#define VR41XX_PCICLKSELREG __preg32(KSEG1 + 0x0F000C38) ++#define VR41XX_PCITRDYVREG __preg32(KSEG1 + 0x0F000C3C) ++#define VR41XX_PCICLKRUNREG __preg16(KSEG1 + 0x0F000C60) ++ ++#define VR41XX_PCIVENDORIDREG __preg16(KSEG1 + 0x0F000D00) ++#define VR41XX_PCIDEVICEIDREG __preg16(KSEG1 + 0x0F000D02) ++#define VR41XX_PCICOMMABDREG __preg32(KSEG1 + 0x0F000D04) ++#define VR41XX_PCIREVREG __preg32(KSEG1 + 0x0F000D08) ++#define VR41XX_PCICACHELSREG __preg32(KSEG1 + 0x0F000D0C) ++#define VR41XX_PCIMAILBAREG __preg32(KSEG1 + 0x0F000D10) ++#define VR41XX_PCIMBA1REG __preg32(KSEG1 + 0x0F000D14) ++#define VR41XX_PCIMBA2REG __preg32(KSEG1 + 0x0F000D18) ++#define VR41XX_PCIINTLINEREG __preg32(KSEG1 + 0x0F000D3C) ++#define VR41XX_PCIRETVALREG __preg32(KSEG1 + 0x0F000D40) ++ ++#ifdef CONFIG_NEC_HARRIER ++ ++/* physical address spaces */ ++#define VR41XX_LCD 0x0a000000 ++#define VR41XX_INTERNAL_IO_2 0x0b000000 ++#define VR41XX_INTERNAL_IO_1 0x0c000000 ++#define VR41XX_ISA_MEM 0x10000000 ++#define VR41XX_ISA_IO 0x16000000 ++#define VR41XX_ROM 0x18000000 ++ ++#define NEC_HARRIER_SIO1 __preg16(KSEG1 + 0x0A000000) ++#define NEC_HARRIER_SIO2 __preg16(KSEG1 + 0x0A000010) ++ ++#define NEC_HARRIER_FLSHCNTREG __preg8(KSEG1 + 0x0DFFFFA0) ++#define NEC_HARRIER_FLSHBANKREG __preg8(KSEG1 + 0x0DFFFFA4) ++#define NEC_HARRIER_SWSETREG __preg8(KSEG1 + 0x0DFFFFA8) ++#define NEC_HARRIER_LED1REG __preg8(KSEG1 + 0x0DFFFFC0) ++#define NEC_HARRIER_LED2REG __preg8(KSEG1 + 0x0DFFFFC4) ++#define NEC_HARRIER_SDBINTREG __preg8(KSEG1 + 0x0DFFFFD0) ++#define NEC_HARRIER_SDBINTMASK __preg8(KSEG1 + 0x0DFFFFD4) ++#define NEC_HARRIER_RSTREG __preg8(KSEG1 + 0x0DFFFFD8) ++#define NEC_HARRIER_PCIINTREG __preg8(KSEG1 + 0x0DFFFFDC) ++#define NEC_HARRIER_PCIINTMASK __preg8(KSEG1 + 0x0DFFFFE0) ++#define NEC_HARRIER_PCICLKREG __preg32(KSEG1 + 0x0DFFFFE4) ++ ++#define NEC_HARRIER_DISPLAY_LEDS(x) \ ++ do { \ ++ *NEC_HARRIER_LED1REG = (unsigned char) ((x) & 0xff); \ ++ *NEC_HARRIER_LED2REG = (unsigned char)(((x) >> 8) & 0xff); \ ++ } while (0) ++ ++ ++/* This is the base address for IO port decoding to which the 16 bit IO port address */ ++/* is added. Defining it to 0 will usually cause a kernel oops any time port IO is */ ++/* attempted, which can be handy for turning up parts of the kernel that make */ ++/* incorrect architecture assumptions (by assuming that everything acts like a PC), */ ++/* but we need it correctly defined to use the PCMCIA/CF controller: */ ++#define VR41XX_PORT_BASE (KSEG1 + VR41XX_ISA_IO) ++#define VR41XX_ISAMEM_BASE (KSEG1 + VR41XX_ISA_MEM) ++ ++#else /* CONFIG_NEC_HARRIER */ ++ ++#define NEC_HARRIER_DISPLAY_LEDS(x) {} ++ ++#endif /* CONFIG_NEC_HARRIER */ ++ ++#endif /* __ASM_MIPS_VR4122_H */ +diff -ruN linux-mips/include/asm-mips/vr4181.h linux-vr/include/asm-mips/vr4181.h +--- linux-mips/include/asm-mips/vr4181.h Wed Dec 31 16:00:00 1969 ++++ linux-vr/include/asm-mips/vr4181.h Tue Oct 31 21:49:24 2000 +@@ -0,0 +1,476 @@ ++/* $Id: vr4181.h,v 1.2 2000/10/30 04:53:03 brad Exp $ ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 1999 by Michael Klar ++ */ ++#ifndef __ASM_MIPS_VR4181_H ++#define __ASM_MIPS_VR4181_H ++ ++#include ++ ++// CPU interrupts ++#define VR41XX_IRQ_SW1 0 // IP0 - Software interrupt ++#define VR41XX_IRQ_SW2 1 // IP1 - Software interrupt ++#define VR41XX_IRQ_INT0 2 // IP2 - All but battery, high speed modem, and real time clock ++#define VR41XX_IRQ_INT1 3 // IP3 - RTC Long1 (system timer) ++#define VR41XX_IRQ_INT2 4 // IP4 - RTC Long2 ++#define VR41XX_IRQ_INT3 5 // IP5 - High Speed Modem (unused on VR4181) ++#define VR41XX_IRQ_INT4 6 // IP6 - Unused ++#define VR41XX_IRQ_TIMER 7 // IP7 - Timer interrupt from CPO_COMPARE (Note: RTC Long1 is the system timer.) ++ ++// Cascaded from VR41XX_IRQ_INT0 (ICU mapped interrupts) ++#define VR41XX_IRQ_BATTERY 8 ++#define VR41XX_IRQ_POWER 9 ++#define VR41XX_IRQ_RTCL1 10 // Use VR41XX_IRQ_INT1 instead. ++#define VR41XX_IRQ_ETIMER 11 ++#define VR41XX_IRQ_RFU12 12 ++#define VR41XX_IRQ_PIU 13 ++#define VR41XX_IRQ_AIU 14 ++#define VR41XX_IRQ_KIU 15 ++#define VR41XX_IRQ_GIU 16 // This is a cascade to IRQs 40-71. Do not use. ++#define VR41XX_IRQ_SIU 17 ++#define VR41XX_IRQ_RFU18 18 ++#define VR41XX_IRQ_SOFT 19 ++#define VR41XX_IRQ_RFU20 20 ++#define VR41XX_IRQ_DOZEPIU 21 ++#define VR41XX_IRQ_RFU22 22 ++#define VR41XX_IRQ_RFU23 23 ++#define VR41XX_IRQ_RTCL2 24 // Use VR41XX_IRQ_INT2 instead. ++#define VR41XX_IRQ_LED 25 ++#define VR41XX_IRQ_ECU 26 // (CompactFlash) ++#define VR41XX_IRQ_CSU 27 ++#define VR41XX_IRQ_USB 28 ++#define VR41XX_IRQ_DMA 29 ++#define VR41XX_IRQ_LCD 30 ++#define VR41XX_IRQ_RFU31 31 ++#define VR41XX_IRQ_RFU32 32 ++#define VR41XX_IRQ_RFU33 33 ++#define VR41XX_IRQ_RFU34 34 ++#define VR41XX_IRQ_RFU35 35 ++#define VR41XX_IRQ_RFU36 36 ++#define VR41XX_IRQ_RFU37 37 ++#define VR41XX_IRQ_RFU38 38 ++#define VR41XX_IRQ_RFU39 39 ++// Note: Still need to do the extra VR4181 IRQ definitions ++ ++// Cascaded from VR41XX_IRQ_GIU ++#define VR41XX_IRQ_GPIO0 40 ++#define VR41XX_IRQ_GPIO1 41 ++#define VR41XX_IRQ_GPIO2 42 ++#define VR41XX_IRQ_GPIO3 43 ++#define VR41XX_IRQ_GPIO4 44 ++#define VR41XX_IRQ_GPIO5 45 ++#define VR41XX_IRQ_GPIO6 46 ++#define VR41XX_IRQ_GPIO7 47 ++#define VR41XX_IRQ_GPIO8 48 ++#define VR41XX_IRQ_GPIO9 49 ++#define VR41XX_IRQ_GPIO10 50 ++#define VR41XX_IRQ_GPIO11 51 ++#define VR41XX_IRQ_GPIO12 52 ++#define VR41XX_IRQ_GPIO13 53 ++#define VR41XX_IRQ_GPIO14 54 ++#define VR41XX_IRQ_GPIO15 55 ++ ++// Alternative to above GPIO IRQ defines ++#define VR41XX_IRQ_GPIO(pin) ((VR41XX_IRQ_GPIO0) + (pin)) ++ ++#define VR41XX_IRQ_MAX 55 ++ ++#ifndef _LANGUAGE_ASSEMBLY ++#define __preg8 (volatile unsigned char*) ++#define __preg16 (volatile unsigned short*) ++#define __preg32 (volatile unsigned int*) ++#else ++#define __preg8 ++#define __preg16 ++#define __preg32 ++#endif ++ ++// Embedded CPU peripheral registers ++// Note that many of the registers have different physical address for VR4181 ++ ++// Bus Control Unit (BCU) ++#define VR41XX_BCUCNTREG1 __preg16(KSEG1 + 0x0A000000) /* BCU control register 1 (R/W) */ ++#define VR41XX_CMUCLKMSK __preg16(KSEG1 + 0x0A000004) /* Clock mask register (R/W) */ ++#define VR41XX_CMUCLKMSK_MSKCSUPCLK 0x0040 ++#define VR41XX_CMUCLKMSK_MSKAIUPCLK 0x0020 ++#define VR41XX_CMUCLKMSK_MSKPIUPCLK 0x0010 ++#define VR41XX_CMUCLKMSK_MSKADUPCLK 0x0008 ++#define VR41XX_CMUCLKMSK_MSKSIU18M 0x0004 ++#define VR41XX_CMUCLKMSK_MSKADU18M 0x0002 ++#define VR41XX_CMUCLKMSK_MSKUSB 0x0001 ++#define VR41XX_CMUCLKMSK_MSKSIU VR41XX_CMUCLKMSK_MSKSIU18M ++#define VR41XX_BCUSPEEDREG __preg16(KSEG1 + 0x0A00000C) /* BCU access time parameter (R/W) */ ++#define VR41XX_BCURFCNTREG __preg16(KSEG1 + 0x0A000010) /* BCU refresh control register (R/W) */ ++#define VR41XX_REVIDREG __preg16(KSEG1 + 0x0A000014) /* Revision ID register (R) */ ++#define VR41XX_CLKSPEEDREG __preg16(KSEG1 + 0x0A000018) /* Clock speed register (R) */ ++#define VR41XX_EDOMCYTREG __preg16(KSEG1 + 0x0A000300) /* Memory cycle timing register (R/W) */ ++#define VR41XX_MEMCFG_REG __preg16(KSEG1 + 0x0A000304) /* Memory configuration register (R/W) */ ++#define VR41XX_MODE_REG __preg16(KSEG1 + 0x0A000308) /* SDRAM mode register (R/W) */ ++#define VR41XX_SDTIMINGREG __preg16(KSEG1 + 0x0A00030C) /* SDRAM timing register (R/W) */ ++ ++// DMA Control Unit (DCU) ++#define VR41XX_MICDEST1REG1 __preg16(KSEG1 + 0x0A000020) /* Microphone destination 1 address register 1 (R/W) */ ++#define VR41XX_MICDEST1REG2 __preg16(KSEG1 + 0x0A000022) /* Microphone destination 1 address register 2 (R/W) */ ++#define VR41XX_MICDEST2REG1 __preg16(KSEG1 + 0x0A000024) /* Microphone destination 2 address register 1 (R/W) */ ++#define VR41XX_MICDEST2REG2 __preg16(KSEG1 + 0x0A000026) /* Microphone destination 2 address register 2 (R/W) */ ++#define VR41XX_SPKRRC1REG1 __preg16(KSEG1 + 0x0A000028) /* Speaker Source 1 address register 1 (R/W) */ ++#define VR41XX_SPKRRC1REG2 __preg16(KSEG1 + 0x0A00002A) /* Speaker Source 1 address register 2 (R/W) */ ++#define VR41XX_SPKRRC2REG1 __preg16(KSEG1 + 0x0A00002C) /* Speaker Source 2 address register 1 (R/W) */ ++#define VR41XX_SPKRRC2REG2 __preg16(KSEG1 + 0x0A00002E) /* Speaker Source 2 address register 2 (R/W) */ ++#define VR41XX_DMARSTREG __preg16(KSEG1 + 0x0A000040) /* DMA Reset register (R/W) */ ++#define VR41XX_AIUDMAMSKREG __preg16(KSEG1 + 0x0A000046) /* Audio DMA mask register (R/W) */ ++#define VR41XX_USBDMAMSKREG __preg16(KSEG1 + 0x0A000600) /* USB DMA Mask register (R/W) */ ++#define VR41XX_USBRXS1AREG1 __preg16(KSEG1 + 0x0A000602) /* USB Rx source 1 address register 1 (R/W) */ ++#define VR41XX_USBRXS1AREG2 __preg16(KSEG1 + 0x0A000604) /* USB Rx source 1 address register 2 (R/W) */ ++#define VR41XX_USBRXS2AREG1 __preg16(KSEG1 + 0x0A000606) /* USB Rx source 2 address register 1 (R/W) */ ++#define VR41XX_USBRXS2AREG2 __preg16(KSEG1 + 0x0A000608) /* USB Rx source 2 address register 2 (R/W) */ ++#define VR41XX_USBTXS1AREG1 __preg16(KSEG1 + 0x0A00060A) /* USB Tx source 1 address register 1 (R/W) */ ++#define VR41XX_USBTXS1AREG2 __preg16(KSEG1 + 0x0A00060C) /* USB Tx source 1 address register 2 (R/W) */ ++#define VR41XX_USBTXS2AREG1 __preg16(KSEG1 + 0x0A00060E) /* USB Tx source 2 address register 1 (R/W) */ ++#define VR41XX_USBTXS2AREG2 __preg16(KSEG1 + 0x0A000610) /* USB Tx source 2 address register 2 (R/W) */ ++#define VR41XX_USBRXD1AREG1 __preg16(KSEG1 + 0x0A00062A) /* USB Rx destination 1 address register 1 (R/W) */ ++#define VR41XX_USBRXD1AREG2 __preg16(KSEG1 + 0x0A00062C) /* USB Rx destination 1 address register 2 (R/W) */ ++#define VR41XX_USBRXD2AREG1 __preg16(KSEG1 + 0x0A00062E) /* USB Rx destination 2 address register 1 (R/W) */ ++#define VR41XX_USBRXD2AREG2 __preg16(KSEG1 + 0x0A000630) /* USB Rx destination 2 address register 2 (R/W) */ ++#define VR41XX_USBTXD1AREG1 __preg16(KSEG1 + 0x0A000632) /* USB Tx destination 1 address register 1 (R/W) */ ++#define VR41XX_USBTXD1AREG2 __preg16(KSEG1 + 0x0A000634) /* USB Tx destination 1 address register 2 (R/W) */ ++#define VR41XX_USBTXD2AREG1 __preg16(KSEG1 + 0x0A000636) /* USB Tx destination 2 address register 1 (R/W) */ ++#define VR41XX_USBTXD2AREG2 __preg16(KSEG1 + 0x0A000638) /* USB Tx destination 2 address register 2 (R/W) */ ++#define VR41XX_RxRCLENREG __preg16(KSEG1 + 0x0A000652) /* USB Rx record length register (R/W) */ ++#define VR41XX_TxRCLENREG __preg16(KSEG1 + 0x0A000654) /* USB Tx record length register (R/W) */ ++#define VR41XX_MICRCLENREG __preg16(KSEG1 + 0x0A000658) /* Microphone record length register (R/W) */ ++#define VR41XX_SPKRCLENREG __preg16(KSEG1 + 0x0A00065A) /* Speaker record length register (R/W) */ ++#define VR41XX_USBCFGREG __preg16(KSEG1 + 0x0A00065C) /* USB configuration register (R/W) */ ++#define VR41XX_MICDMACFGREG __preg16(KSEG1 + 0x0A00065E) /* Microphone DMA configuration register (R/W) */ ++#define VR41XX_SPKDMACFGREG __preg16(KSEG1 + 0x0A000660) /* Speaker DMA configuration register (R/W) */ ++#define VR41XX_DMAITRQREG __preg16(KSEG1 + 0x0A000662) /* DMA interrupt request register (R/W) */ ++#define VR41XX_DMACLTREG __preg16(KSEG1 + 0x0A000664) /* DMA control register (R/W) */ ++#define VR41XX_DMAITMKREG __preg16(KSEG1 + 0x0A000666) /* DMA interrupt mask register (R/W) */ ++ ++// ISA Bridge ++#define VR41XX_ISABRGCTL __preg16(KSEG1 + 0x0B0002C0) /* ISA Bridge Control Register (R/W) */ ++#define VR41XX_ISABRGSTS __preg16(KSEG1 + 0x0B0002C2) /* ISA Bridge Status Register (R/W) */ ++#define VR41XX_XISACTL __preg16(KSEG1 + 0x0B0002C4) /* External ISA Control Register (R/W) */ ++ ++// Clocked Serial Interface (CSI) ++#define VR41XX_CSIMODE __preg16(KSEG1 + 0x0B000900) /* CSI Mode Register (R/W) */ ++#define VR41XX_CSIRXDATA __preg16(KSEG1 + 0x0B000902) /* CSI Receive Data Register (R) */ ++#define VR41XX_CSITXDATA __preg16(KSEG1 + 0x0B000904) /* CSI Transmit Data Register (R/W) */ ++#define VR41XX_CSILSTAT __preg16(KSEG1 + 0x0B000906) /* CSI Line Status Register (R/W) */ ++#define VR41XX_CSIINTMSK __preg16(KSEG1 + 0x0B000908) /* CSI Interrupt Mask Register (R/W) */ ++#define VR41XX_CSIINTSTAT __preg16(KSEG1 + 0x0B00090a) /* CSI Interrupt Status Register (R/W) */ ++#define VR41XX_CSITXBLEN __preg16(KSEG1 + 0x0B00090c) /* CSI Transmit Burst Length Register (R/W) */ ++#define VR41XX_CSIRXBLEN __preg16(KSEG1 + 0x0B00090e) /* CSI Receive Burst Length Register (R/W) */ ++ ++// Interrupt Control Unit (ICU) ++#define VR41XX_SYSINT1REG __preg16(KSEG1 + 0x0A000080) /* Level 1 System interrupt register 1 (R) */ ++#define VR41XX_MSYSINT1REG __preg16(KSEG1 + 0x0A00008C) /* Level 1 mask system interrupt register 1 (R/W) */ ++#define VR41XX_NMIREG __preg16(KSEG1 + 0x0A000098) /* NMI register (R/W) */ ++#define VR41XX_SOFTINTREG __preg16(KSEG1 + 0x0A00009A) /* Software interrupt register (R/W) */ ++#define VR41XX_SYSINT2REG __preg16(KSEG1 + 0x0A000200) /* Level 1 System interrupt register 2 (R) */ ++#define VR41XX_MSYSINT2REG __preg16(KSEG1 + 0x0A000206) /* Level 1 mask system interrupt register 2 (R/W) */ ++#define VR41XX_PIUINTREGro __preg16(KSEG1 + 0x0B000082) /* Level 2 PIU interrupt register (R) */ ++#define VR41XX_AIUINTREG __preg16(KSEG1 + 0x0B000084) /* Level 2 AIU interrupt register (R) */ ++#define VR41XX_MPIUINTREG __preg16(KSEG1 + 0x0B00008E) /* Level 2 mask PIU interrupt register (R/W) */ ++#define VR41XX_MAIUINTREG __preg16(KSEG1 + 0x0B000090) /* Level 2 mask AIU interrupt register (R/W) */ ++#define VR41XX_MKIUINTREG __preg16(KSEG1 + 0x0B000092) /* Level 2 mask KIU interrupt register (R/W) */ ++#define VR41XX_KIUINTREG __preg16(KSEG1 + 0x0B000198) /* Level 2 KIU interrupt register (R) */ ++ ++// Power Management Unit (PMU) ++#define VR41XX_PMUINTREG __preg16(KSEG1 + 0x0B0000A0) /* PMU Status Register (R/W) */ ++#define VR41XX_PMUINT_POWERSW 0x1 /* Power switch */ ++#define VR41XX_PMUINT_BATT 0x2 /* Low batt during normal operation */ ++#define VR41XX_PMUINT_DEADMAN 0x4 /* Deadman's switch */ ++#define VR41XX_PMUINT_RESET 0x8 /* Reset switch */ ++#define VR41XX_PMUINT_RTCRESET 0x10 /* RTC Reset */ ++#define VR41XX_PMUINT_TIMEOUT 0x20 /* HAL Timer Reset */ ++#define VR41XX_PMUINT_BATTLOW 0x100 /* Battery low */ ++#define VR41XX_PMUINT_RTC 0x200 /* RTC Alarm */ ++#define VR41XX_PMUINT_DCD 0x400 /* DCD# */ ++#define VR41XX_PMUINT_GPIO0 0x1000 /* GPIO0 */ ++#define VR41XX_PMUINT_GPIO1 0x2000 /* GPIO1 */ ++#define VR41XX_PMUINT_GPIO2 0x4000 /* GPIO2 */ ++#define VR41XX_PMUINT_GPIO3 0x8000 /* GPIO3 */ ++ ++#define VR41XX_PMUCNTREG __preg16(KSEG1 + 0x0B0000A2) /* PMU Control Register (R/W) */ ++#define VR41XX_PMUWAITREG __preg16(KSEG1 + 0x0B0000A8) /* PMU Wait Counter Register (R/W) */ ++#define VR41XX_PMUDIVREG __preg16(KSEG1 + 0x0B0000AC) /* PMU Divide Mode Register (R/W) */ ++#define VR41XX_DRAMHIBCTL __preg16(KSEG1 + 0x0B0000B2) /* DRAM Hibernate Control Register (R/W) */ ++ ++// Real Time Clock Unit (RTC) ++#define VR41XX_ETIMELREG __preg16(KSEG1 + 0x0B0000C0) /* Elapsed Time L Register (R/W) */ ++#define VR41XX_ETIMEMREG __preg16(KSEG1 + 0x0B0000C2) /* Elapsed Time M Register (R/W) */ ++#define VR41XX_ETIMEHREG __preg16(KSEG1 + 0x0B0000C4) /* Elapsed Time H Register (R/W) */ ++#define VR41XX_ECMPLREG __preg16(KSEG1 + 0x0B0000C8) /* Elapsed Compare L Register (R/W) */ ++#define VR41XX_ECMPMREG __preg16(KSEG1 + 0x0B0000CA) /* Elapsed Compare M Register (R/W) */ ++#define VR41XX_ECMPHREG __preg16(KSEG1 + 0x0B0000CC) /* Elapsed Compare H Register (R/W) */ ++#define VR41XX_RTCL1LREG __preg16(KSEG1 + 0x0B0000D0) /* RTC Long 1 L Register (R/W) */ ++#define VR41XX_RTCL1HREG __preg16(KSEG1 + 0x0B0000D2) /* RTC Long 1 H Register (R/W) */ ++#define VR41XX_RTCL1CNTLREG __preg16(KSEG1 + 0x0B0000D4) /* RTC Long 1 Count L Register (R) */ ++#define VR41XX_RTCL1CNTHREG __preg16(KSEG1 + 0x0B0000D6) /* RTC Long 1 Count H Register (R) */ ++#define VR41XX_RTCL2LREG __preg16(KSEG1 + 0x0B0000D8) /* RTC Long 2 L Register (R/W) */ ++#define VR41XX_RTCL2HREG __preg16(KSEG1 + 0x0B0000DA) /* RTC Long 2 H Register (R/W) */ ++#define VR41XX_RTCL2CNTLREG __preg16(KSEG1 + 0x0B0000DC) /* RTC Long 2 Count L Register (R) */ ++#define VR41XX_RTCL2CNTHREG __preg16(KSEG1 + 0x0B0000DE) /* RTC Long 2 Count H Register (R) */ ++#define VR41XX_RTCINTREG __preg16(KSEG1 + 0x0B0001DE) /* RTC Interrupt Register (R/W) */ ++ ++// Deadman's Switch Unit (DSU) ++#define VR41XX_DSUCNTREG __preg16(KSEG1 + 0x0B0000E0) /* DSU Control Register (R/W) */ ++#define VR41XX_DSUSETREG __preg16(KSEG1 + 0x0B0000E2) /* DSU Dead Time Set Register (R/W) */ ++#define VR41XX_DSUCLRREG __preg16(KSEG1 + 0x0B0000E4) /* DSU Clear Register (W) */ ++#define VR41XX_DSUTIMREG __preg16(KSEG1 + 0x0B0000E6) /* DSU Elapsed Time Register (R/W) */ ++ ++// General Purpose I/O Unit (GIU) ++#define VR41XX_GPMD0REG __preg16(KSEG1 + 0x0B000300) /* GPIO Mode 0 Register (R/W) */ ++#define VR41XX_GPMD1REG __preg16(KSEG1 + 0x0B000302) /* GPIO Mode 1 Register (R/W) */ ++#define VR41XX_GPMD2REG __preg16(KSEG1 + 0x0B000304) /* GPIO Mode 2 Register (R/W) */ ++#define VR41XX_GPMD3REG __preg16(KSEG1 + 0x0B000306) /* GPIO Mode 3 Register (R/W) */ ++#define VR41XX_GPDATHREG __preg16(KSEG1 + 0x0B000308) /* GPIO Data High Register (R/W) */ ++#define VR41XX_GPDATHREG_GPIO16 0x0001 ++#define VR41XX_GPDATHREG_GPIO17 0x0002 ++#define VR41XX_GPDATHREG_GPIO18 0x0004 ++#define VR41XX_GPDATHREG_GPIO19 0x0008 ++#define VR41XX_GPDATHREG_GPIO20 0x0010 ++#define VR41XX_GPDATHREG_GPIO21 0x0020 ++#define VR41XX_GPDATHREG_GPIO22 0x0040 ++#define VR41XX_GPDATHREG_GPIO23 0x0080 ++#define VR41XX_GPDATHREG_GPIO24 0x0100 ++#define VR41XX_GPDATHREG_GPIO25 0x0200 ++#define VR41XX_GPDATHREG_GPIO26 0x0400 ++#define VR41XX_GPDATHREG_GPIO27 0x0800 ++#define VR41XX_GPDATHREG_GPIO28 0x1000 ++#define VR41XX_GPDATHREG_GPIO29 0x2000 ++#define VR41XX_GPDATHREG_GPIO30 0x4000 ++#define VR41XX_GPDATHREG_GPIO31 0x8000 ++#define VR41XX_GPDATLREG __preg16(KSEG1 + 0x0B00030A) /* GPIO Data Low Register (R/W) */ ++#define VR41XX_GPDATLREG_GPIO0 0x0001 ++#define VR41XX_GPDATLREG_GPIO1 0x0002 ++#define VR41XX_GPDATLREG_GPIO2 0x0004 ++#define VR41XX_GPDATLREG_GPIO3 0x0008 ++#define VR41XX_GPDATLREG_GPIO4 0x0010 ++#define VR41XX_GPDATLREG_GPIO5 0x0020 ++#define VR41XX_GPDATLREG_GPIO6 0x0040 ++#define VR41XX_GPDATLREG_GPIO7 0x0080 ++#define VR41XX_GPDATLREG_GPIO8 0x0100 ++#define VR41XX_GPDATLREG_GPIO9 0x0200 ++#define VR41XX_GPDATLREG_GPIO10 0x0400 ++#define VR41XX_GPDATLREG_GPIO11 0x0800 ++#define VR41XX_GPDATLREG_GPIO12 0x1000 ++#define VR41XX_GPDATLREG_GPIO13 0x2000 ++#define VR41XX_GPDATLREG_GPIO14 0x4000 ++#define VR41XX_GPDATLREG_GPIO15 0x8000 ++#define VR41XX_GPINTEN __preg16(KSEG1 + 0x0B00030C) /* GPIO Interrupt Enable Register (R/W) */ ++#define VR41XX_GPINTMSK __preg16(KSEG1 + 0x0B00030E) /* GPIO Interrupt Mask Register (R/W) */ ++#define VR41XX_GPINTTYPH __preg16(KSEG1 + 0x0B000310) /* GPIO Interrupt Type High Register (R/W) */ ++#define VR41XX_GPINTTYPL __preg16(KSEG1 + 0x0B000312) /* GPIO Interrupt Type Low Register (R/W) */ ++#define VR41XX_GPINTSTAT __preg16(KSEG1 + 0x0B000314) /* GPIO Interrupt Status Register (R/W) */ ++#define VR41XX_GPHIBSTH __preg16(KSEG1 + 0x0B000316) /* GPIO Hibernate Pin State High Register (R/W) */ ++#define VR41XX_GPHIBSTL __preg16(KSEG1 + 0x0B000318) /* GPIO Hibernate Pin State Low Register (R/W) */ ++#define VR41XX_GPSICTL __preg16(KSEG1 + 0x0B00031A) /* GPIO Serial Interface Control Register (R/W) */ ++#define VR41XX_KEYEN __preg16(KSEG1 + 0x0B00031C) /* Keyboard Scan Pin Enable Register (R/W) */ ++#define VR41XX_PCS0STRA __preg16(KSEG1 + 0x0B000320) /* Programmable Chip Select [0] Start Address Register (R/W) */ ++#define VR41XX_PCS0STPA __preg16(KSEG1 + 0x0B000322) /* Programmable Chip Select [0] Stop Address Register (R/W) */ ++#define VR41XX_PCS0HIA __preg16(KSEG1 + 0x0B000324) /* Programmable Chip Select [0] High Address Register (R/W) */ ++#define VR41XX_PCS1STRA __preg16(KSEG1 + 0x0B000326) /* Programmable Chip Select [1] Start Address Register (R/W) */ ++#define VR41XX_PCS1STPA __preg16(KSEG1 + 0x0B000328) /* Programmable Chip Select [1] Stop Address Register (R/W) */ ++#define VR41XX_PCS1HIA __preg16(KSEG1 + 0x0B00032A) /* Programmable Chip Select [1] High Address Register (R/W) */ ++#define VR41XX_PCSMODE __preg16(KSEG1 + 0x0B00032C) /* Programmable Chip Select Mode Register (R/W) */ ++#define VR41XX_LCDGPMODE __preg16(KSEG1 + 0x0B00032E) /* LCD General Purpose Mode Register (R/W) */ ++#define VR41XX_MISCREG0 __preg16(KSEG1 + 0x0B000330) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ ++#define VR41XX_MISCREG1 __preg16(KSEG1 + 0x0B000332) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ ++#define VR41XX_MISCREG2 __preg16(KSEG1 + 0x0B000334) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ ++#define VR41XX_MISCREG3 __preg16(KSEG1 + 0x0B000336) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ ++#define VR41XX_MISCREG4 __preg16(KSEG1 + 0x0B000338) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ ++#define VR41XX_MISCREG5 __preg16(KSEG1 + 0x0B00033A) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ ++#define VR41XX_MISCREG6 __preg16(KSEG1 + 0x0B00033C) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ ++#define VR41XX_MISCREG7 __preg16(KSEG1 + 0x0B00033D) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ ++#define VR41XX_MISCREG8 __preg16(KSEG1 + 0x0B000340) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ ++#define VR41XX_MISCREG9 __preg16(KSEG1 + 0x0B000342) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ ++#define VR41XX_MISCREG10 __preg16(KSEG1 + 0x0B000344) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ ++#define VR41XX_MISCREG11 __preg16(KSEG1 + 0x0B000346) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ ++#define VR41XX_MISCREG12 __preg16(KSEG1 + 0x0B000348) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ ++#define VR41XX_MISCREG13 __preg16(KSEG1 + 0x0B00034A) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ ++#define VR41XX_MISCREG14 __preg16(KSEG1 + 0x0B00034C) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ ++#define VR41XX_MISCREG15 __preg16(KSEG1 + 0x0B00034E) /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */ ++#define VR41XX_SECIRQMASKL VR41XX_GPINTEN ++// No SECIRQMASKH for VR4181 ++ ++// Touch Panel Interface Unit (PIU) ++#define VR41XX_PIUCNTREG __preg16(KSEG1 + 0x0B000122) /* PIU Control register (R/W) */ ++#define VR41XX_PIUCNTREG_PIUSEQEN 0x0004 ++#define VR41XX_PIUCNTREG_PIUPWR 0x0002 ++#define VR41XX_PIUCNTREG_PADRST 0x0001 ++ ++#define VR41XX_PIUINTREG __preg16(KSEG1 + 0x0B000124) /* PIU Interrupt cause register (R/W) */ ++#define VR41XX_PIUINTREG_OVP 0x8000 ++#define VR41XX_PIUINTREG_PADCMD 0x0040 ++#define VR41XX_PIUINTREG_PADADP 0x0020 ++#define VR41XX_PIUINTREG_PADPAGE1 0x0010 ++#define VR41XX_PIUINTREG_PADPAGE0 0x0008 ++#define VR41XX_PIUINTREG_PADDLOST 0x0004 ++#define VR41XX_PIUINTREG_PENCHG 0x0001 ++ ++#define VR41XX_PIUSIVLREG __preg16(KSEG1 + 0x0B000126) /* PIU Data sampling interval register (R/W) */ ++#define VR41XX_PIUSTBLREG __preg16(KSEG1 + 0x0B000128) /* PIU A/D converter start delay register (R/W) */ ++#define VR41XX_PIUCMDREG __preg16(KSEG1 + 0x0B00012A) /* PIU A/D command register (R/W) */ ++#define VR41XX_PIUASCNREG __preg16(KSEG1 + 0x0B000130) /* PIU A/D port scan register (R/W) */ ++#define VR41XX_PIUAMSKREG __preg16(KSEG1 + 0x0B000132) /* PIU A/D scan mask register (R/W) */ ++#define VR41XX_PIUCIVLREG __preg16(KSEG1 + 0x0B00013E) /* PIU Check interval register (R) */ ++#define VR41XX_PIUPB00REG __preg16(KSEG1 + 0x0B0002A0) /* PIU Page 0 Buffer 0 register (R/W) */ ++#define VR41XX_PIUPB01REG __preg16(KSEG1 + 0x0B0002A2) /* PIU Page 0 Buffer 1 register (R/W) */ ++#define VR41XX_PIUPB02REG __preg16(KSEG1 + 0x0B0002A4) /* PIU Page 0 Buffer 2 register (R/W) */ ++#define VR41XX_PIUPB03REG __preg16(KSEG1 + 0x0B0002A6) /* PIU Page 0 Buffer 3 register (R/W) */ ++#define VR41XX_PIUPB10REG __preg16(KSEG1 + 0x0B0002A8) /* PIU Page 1 Buffer 0 register (R/W) */ ++#define VR41XX_PIUPB11REG __preg16(KSEG1 + 0x0B0002AA) /* PIU Page 1 Buffer 1 register (R/W) */ ++#define VR41XX_PIUPB12REG __preg16(KSEG1 + 0x0B0002AC) /* PIU Page 1 Buffer 2 register (R/W) */ ++#define VR41XX_PIUPB13REG __preg16(KSEG1 + 0x0B0002AE) /* PIU Page 1 Buffer 3 register (R/W) */ ++#define VR41XX_PIUAB0REG __preg16(KSEG1 + 0x0B0002B0) /* PIU A/D scan Buffer 0 register (R/W) */ ++#define VR41XX_PIUAB1REG __preg16(KSEG1 + 0x0B0002B2) /* PIU A/D scan Buffer 1 register (R/W) */ ++#define VR41XX_PIUAB2REG __preg16(KSEG1 + 0x0B0002B4) /* PIU A/D scan Buffer 2 register (R/W) */ ++#define VR41XX_PIUAB3REG __preg16(KSEG1 + 0x0B0002B6) /* PIU A/D scan Buffer 3 register (R/W) */ ++#define VR41XX_PIUPB04REG __preg16(KSEG1 + 0x0B0002BC) /* PIU Page 0 Buffer 4 register (R/W) */ ++#define VR41XX_PIUPB14REG __preg16(KSEG1 + 0x0B0002BE) /* PIU Page 1 Buffer 4 register (R/W) */ ++ ++// Audio Interface Unit (AIU) ++#define VR41XX_SODATREG __preg16(KSEG1 + 0x0B000166) /* Speaker Output Data Register (R/W) */ ++#define VR41XX_SCNTREG __preg16(KSEG1 + 0x0B000168) /* Speaker Output Control Register (R/W) */ ++#define VR41XX_MIDATREG __preg16(KSEG1 + 0x0B000170) /* Mike Input Data Register (R/W) */ ++#define VR41XX_MCNTREG __preg16(KSEG1 + 0x0B000172) /* Mike Input Control Register (R/W) */ ++#define VR41XX_DVALIDREG __preg16(KSEG1 + 0x0B000178) /* Data Valid Register (R/W) */ ++#define VR41XX_SEQREG __preg16(KSEG1 + 0x0B00017A) /* Sequential Register (R/W) */ ++#define VR41XX_INTREG __preg16(KSEG1 + 0x0B00017C) /* Interrupt Register (R/W) */ ++#define VR41XX_SDMADATREG __preg16(KSEG1 + 0x0B000160) /* Speaker DMA Data Register (R/W) */ ++#define VR41XX_MDMADATREG __preg16(KSEG1 + 0x0B000162) /* Microphone DMA Data Register (R/W) */ ++#define VR41XX_DAVREF_SETUP __preg16(KSEG1 + 0x0B000164) /* DAC Vref setup register (R/W) */ ++#define VR41XX_SCNVC_END __preg16(KSEG1 + 0x0B00016E) /* Speaker sample rate control (R/W) */ ++#define VR41XX_MIDATREG __preg16(KSEG1 + 0x0B000170) /* Microphone Input Data Register (R/W) */ ++#define VR41XX_MCNTREG __preg16(KSEG1 + 0x0B000172) /* Microphone Input Control Register (R/W) */ ++#define VR41XX_MCNVC_END __preg16(KSEG1 + 0x0B00017E) /* Microphone sample rate control (R/W) */ ++ ++// Keyboard Interface Unit (KIU) ++#define VR41XX_KIUDAT0 __preg16(KSEG1 + 0x0B000180) /* KIU Data0 Register (R/W) */ ++#define VR41XX_KIUDAT1 __preg16(KSEG1 + 0x0B000182) /* KIU Data1 Register (R/W) */ ++#define VR41XX_KIUDAT2 __preg16(KSEG1 + 0x0B000184) /* KIU Data2 Register (R/W) */ ++#define VR41XX_KIUDAT3 __preg16(KSEG1 + 0x0B000186) /* KIU Data3 Register (R/W) */ ++#define VR41XX_KIUDAT4 __preg16(KSEG1 + 0x0B000188) /* KIU Data4 Register (R/W) */ ++#define VR41XX_KIUDAT5 __preg16(KSEG1 + 0x0B00018A) /* KIU Data5 Register (R/W) */ ++#define VR41XX_KIUSCANREP __preg16(KSEG1 + 0x0B000190) /* KIU Scan/Repeat Register (R/W) */ ++#define VR41XX_KIUSCANREP_KEYEN 0x8000 ++#define VR41XX_KIUSCANREP_SCANSTP 0x0008 ++#define VR41XX_KIUSCANREP_SCANSTART 0x0004 ++#define VR41XX_KIUSCANREP_ATSTP 0x0002 ++#define VR41XX_KIUSCANREP_ATSCAN 0x0001 ++#define VR41XX_KIUSCANS __preg16(KSEG1 + 0x0B000192) /* KIU Scan Status Register (R) */ ++#define VR41XX_KIUWKS __preg16(KSEG1 + 0x0B000194) /* KIU Wait Keyscan Stable Register (R/W) */ ++#define VR41XX_KIUWKI __preg16(KSEG1 + 0x0B000196) /* KIU Wait Keyscan Interval Register (R/W) */ ++#define VR41XX_KIUINT __preg16(KSEG1 + 0x0B000198) /* KIU Interrupt Register (R/W) */ ++#define VR41XX_KIUINT_KDATLOST 0x0004 ++#define VR41XX_KIUINT_KDATRDY 0x0002 ++#define VR41XX_KIUINT_SCANINT 0x0001 ++#define VR41XX_KIUDAT6 __preg16(KSEG1 + 0x0B00018C) /* Scan Line 6 Key Data Register (R) */ ++#define VR41XX_KIUDAT7 __preg16(KSEG1 + 0x0B00018E) /* Scan Line 7 Key Data Register (R) */ ++ ++// CompactFlash Controller ++#define VR41XX_PCCARDINDEX __preg8(KSEG1 + 0x0B0008E0) /* PC Card Controller Index Register */ ++#define VR41XX_PCCARDDATA __preg8(KSEG1 + 0x0B0008E1) /* PC Card Controller Data Register */ ++#define VR41XX_INTSTATREG __preg16(KSEG1 + 0x0B0008F8) /* Interrupt Status Register (R/W) */ ++#define VR41XX_INTMSKREG __preg16(KSEG1 + 0x0B0008FA) /* Interrupt Mask Register (R/W) */ ++#define VR41XX_CFG_REG_1 __preg16(KSEG1 + 0x0B0008FE) /* Configuration Register 1 */ ++ ++// LED Control Unit (LED) ++#define VR41XX_LEDHTSREG __preg16(KSEG1 + 0x0B000240) /* LED H Time Set register (R/W) */ ++#define VR41XX_LEDLTSREG __preg16(KSEG1 + 0x0B000242) /* LED L Time Set register (R/W) */ ++#define VR41XX_LEDCNTREG __preg16(KSEG1 + 0x0B000248) /* LED Control register (R/W) */ ++#define VR41XX_LEDASTCREG __preg16(KSEG1 + 0x0B00024A) /* LED Auto Stop Time Count register (R/W) */ ++#define VR41XX_LEDINTREG __preg16(KSEG1 + 0x0B00024C) /* LED Interrupt register (R/W) */ ++ ++// Serial Interface Unit (SIU / SIU1 and SIU2) ++#define VR41XX_SIURB __preg8(KSEG1 + 0x0C000010) /* Receiver Buffer Register (Read) DLAB = 0 (R) */ ++#define VR41XX_SIUTH __preg8(KSEG1 + 0x0C000010) /* Transmitter Holding Register (Write) DLAB = 0 (W) */ ++#define VR41XX_SIUDLL __preg8(KSEG1 + 0x0C000010) /* Divisor Latch (Least Significant Byte) DLAB = 1 (R/W) */ ++#define VR41XX_SIUIE __preg8(KSEG1 + 0x0C000011) /* Interrupt Enable DLAB = 0 (R/W) */ ++#define VR41XX_SIUDLM __preg8(KSEG1 + 0x0C000011) /* Divisor Latch (Most Significant Byte) DLAB = 1 (R/W) */ ++#define VR41XX_SIUIID __preg8(KSEG1 + 0x0C000012) /* Interrupt Identification Register (Read) (R) */ ++#define VR41XX_SIUFC __preg8(KSEG1 + 0x0C000012) /* FIFO Control Register (Write) (W) */ ++#define VR41XX_SIULC __preg8(KSEG1 + 0x0C000013) /* Line Control Register (R/W) */ ++#define VR41XX_SIUMC __preg8(KSEG1 + 0x0C000014) /* MODEM Control Register (R/W) */ ++#define VR41XX_SIULS __preg8(KSEG1 + 0x0C000015) /* Line Status Register (R/W) */ ++#define VR41XX_SIUMS __preg8(KSEG1 + 0x0C000016) /* MODEM Status Register (R/W) */ ++#define VR41XX_SIUSC __preg8(KSEG1 + 0x0C000017) /* Scratch Register (R/W) */ ++#define VR41XX_SIURESET __preg8(KSEG1 + 0x0C000019) /* SIU Reset Register (R/W) */ ++#define VR41XX_SIUACTMSK __preg8(KSEG1 + 0x0C00001C) /* SIU Activity Mask (R/W) */ ++#define VR41XX_SIUACTTMR __preg8(KSEG1 + 0x0C00001E) /* SIU Activity Timer (R/W) */ ++#define VR41XX_SIURB_2 __preg8(KSEG1 + 0x0C000000) /* Receive Buffer Register (Read) (R) */ ++#define VR41XX_SIUTH_2 __preg8(KSEG1 + 0x0C000000) /* Transmitter Holding Register (Write) (W) */ ++#define VR41XX_SIUDLL_2 __preg8(KSEG1 + 0x0C000000) /* Divisor Latch (Least Significant Byte) (R/W) */ ++#define VR41XX_SIUIE_2 __preg8(KSEG1 + 0x0C000001) /* Interrupt Enable (DLAB = 0) (R/W) */ ++#define VR41XX_SIUDLM_2 __preg8(KSEG1 + 0x0C000001) /* Divisor Latch (Most Significant Byte) (DLAB = 1) (R/W) */ ++#define VR41XX_SIUIID_2 __preg8(KSEG1 + 0x0C000002) /* Interrupt Identification Register (Read) (R) */ ++#define VR41XX_SIUFC_2 __preg8(KSEG1 + 0x0C000002) /* FIFO Control Register (Write) (W) */ ++#define VR41XX_SIULC_2 __preg8(KSEG1 + 0x0C000003) /* Line Control Register (R/W) */ ++#define VR41XX_SIUMC_2 __preg8(KSEG1 + 0x0C000004) /* Modem Control Register (R/W) */ ++#define VR41XX_SIULS_2 __preg8(KSEG1 + 0x0C000005) /* Line Status Register (R/W) */ ++#define VR41XX_SIUMS_2 __preg8(KSEG1 + 0x0C000006) /* Modem Status Register (R/W) */ ++#define VR41XX_SIUSC_2 __preg8(KSEG1 + 0x0C000007) /* Scratch Register (R/W) */ ++#define VR41XX_SIUIRSEL_2 __preg8(KSEG1 + 0x0C000008) /* SIU IrDA Selectot (R/W) */ ++#define VR41XX_SIURESET_2 __preg8(KSEG1 + 0x0C000009) /* SIU Reset Register (R/W) */ ++#define VR41XX_SIUCSEL_2 __preg8(KSEG1 + 0x0C00000A) /* IrDA Echo-back Control (R/W) */ ++#define VR41XX_SIUACTMSK_2 __preg8(KSEG1 + 0x0C00000C) /* SIU Activity Mask Register (R/W) */ ++#define VR41XX_SIUACTTMR_2 __preg8(KSEG1 + 0x0C00000E) /* SIU Activity Timer Register (R/W) */ ++ ++ ++// USB Module ++#define VR41XX_USBINFIFO __preg16(KSEG1 + 0x0B000780) /* USB Bulk Input FIFO (Bulk In End Point) (W) */ ++#define VR41XX_USBOUTFIFO __preg16(KSEG1 + 0x0B000782) /* USB Bulk Output FIFO (Bulk Out End Point) (R) */ ++#define VR41XX_USBCTLFIFO __preg16(KSEG1 + 0x0B000784) /* USB Control FIFO (Control End Point) (W) */ ++#define VR41XX_USBSTAT __preg16(KSEG1 + 0x0B000786) /* Interrupt Status Register (R/W) */ ++#define VR41XX_USBINTMSK __preg16(KSEG1 + 0x0B000788) /* Interrupt Mask Register (R/W) */ ++#define VR41XX_USBCTLREG __preg16(KSEG1 + 0x0B00078A) /* Control Register (R/W) */ ++#define VR41XX_USBSTPREG __preg16(KSEG1 + 0x0B00078C) /* USB Transfer Stop Register (R/W) */ ++ ++// LCD Controller ++#define VR41XX_HRTOTALREG __preg16(KSEG1 + 0x0A000400) /* Horizontal total Register (R/W) */ ++#define VR41XX_HRVISIBREG __preg16(KSEG1 + 0x0A000402) /* Horizontal Visible Register (R/W) */ ++#define VR41XX_LDCLKSTREG __preg16(KSEG1 + 0x0A000404) /* Load clock start Register (R/W) */ ++#define VR41XX_LDCLKNDREG __preg16(KSEG1 + 0x0A000406) /* Load clock end Register (R/W) */ ++#define VR41XX_VRTOTALREG __preg16(KSEG1 + 0x0A000408) /* Vertical Total Register (R/W) */ ++#define VR41XX_VRVISIBREG __preg16(KSEG1 + 0x0A00040A) /* Vertical Visible Register (R/W) */ ++#define VR41XX_FVSTARTREG __preg16(KSEG1 + 0x0A00040C) /* FLM vertical start Register (R/W) */ ++#define VR41XX_FVENDREG __preg16(KSEG1 + 0x0A00040E) /* FLM vertical end Register (R/W) */ ++#define VR41XX_LCDCTRLREG __preg16(KSEG1 + 0x0A000410) /* LCD control Register (R/W) */ ++#define VR41XX_LCDINRQREG __preg16(KSEG1 + 0x0A000412) /* LCD Interrupt request Register (R/W) */ ++#define VR41XX_LCDCFGREG0 __preg16(KSEG1 + 0x0A000414) /* LCD Configuration Register 0 (R/W) */ ++#define VR41XX_LCDCFGREG1 __preg16(KSEG1 + 0x0A000416) /* LCD Configuration Register 1 (R/W) */ ++#define VR41XX_FBSTAD1REG __preg16(KSEG1 + 0x0A000418) /* Frame Buffer Start Address 1 Register (R/W) */ ++#define VR41XX_FBSTAD2REG __preg16(KSEG1 + 0x0A00041A) /* Frame Buffer Start Address 2 Register (R/W) */ ++#define VR41XX_FBNDAD1REG __preg16(KSEG1 + 0x0A000420) /* Frame Buffer End Address 1 Register (R/W) */ ++#define VR41XX_FBNDAD2REG __preg16(KSEG1 + 0x0A000422) /* Frame Buffer End Address 2 register (R/W) */ ++#define VR41XX_FHSTARTREG __preg16(KSEG1 + 0x0A000424) /* FLM horizontal Start Register (R/W) */ ++#define VR41XX_FHENDREG __preg16(KSEG1 + 0x0A000426) /* FLM horizontal End Register (R/W) */ ++#define VR41XX_PWRCONREG1 __preg16(KSEG1 + 0x0A000430) /* Power Control register 1 (R/W) */ ++#define VR41XX_PWRCONREG2 __preg16(KSEG1 + 0x0A000432) /* Power Control register 2 (R/W) */ ++#define VR41XX_LCDIMSKREG __preg16(KSEG1 + 0x0A000434) /* LCD Interrupt Mask register (R/W) */ ++#define VR41XX_CPINDCTREG __preg16(KSEG1 + 0x0A00047E) /* Color palette Index and control Register (R/W) */ ++#define VR41XX_CPALDATREG __preg32(KSEG1 + 0x0A000480) /* Color palette data register (32bits Register) (R/W) */ ++ ++// physical address spaces ++#define VR41XX_LCD 0x0a000000 ++#define VR41XX_INTERNAL_IO_2 0x0b000000 ++#define VR41XX_INTERNAL_IO_1 0x0c000000 ++#define VR41XX_ISA_MEM 0x10000000 ++#define VR41XX_ISA_IO 0x14000000 ++#define VR41XX_ROM 0x18000000 ++ ++// This is the base address for IO port decoding to which the 16 bit IO port address ++// is added. Defining it to 0 will usually cause a kernel oops any time port IO is ++// attempted, which can be handy for turning up parts of the kernel that make ++// incorrect architecture assumptions (by assuming that everything acts like a PC), ++// but we need it correctly defined to use the PCMCIA/CF controller: ++#define VR41XX_PORT_BASE (KSEG1 + VR41XX_ISA_IO) ++#define VR41XX_ISAMEM_BASE (KSEG1 + VR41XX_ISA_MEM) ++ ++#endif /* __ASM_MIPS_VR4181_H */ +diff -ruN linux-mips/include/asm-mips/vr41xx-platdep.h linux-vr/include/asm-mips/vr41xx-platdep.h +--- linux-mips/include/asm-mips/vr41xx-platdep.h Wed Dec 31 16:00:00 1969 ++++ linux-vr/include/asm-mips/vr41xx-platdep.h Thu Nov 23 15:05:41 2000 +@@ -0,0 +1,655 @@ ++/* $Id: vr41xx-platdep.h,v 1.35 2000/11/21 14:18:08 yuasa Exp $ ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 1999 by Michael Klar ++ */ ++#ifndef __ASM_MIPS_VR41XX_PLATDEP_H ++#define __ASM_MIPS_VR41XX_PLATDEP_H ++ ++/* ++ * This file contains the device-specific defines for VR41xx CPU-based ++ * platforms. Anything CPU-specific should go in vr41xx.h instead. ++ * Eventually, most, if not all, dependancies on CONFIG_[device_name] ++ * should be moved in here, which should make it easier to add new ++ * device support. ++ */ ++ ++#include ++#include ++ ++/* ++ * Here are the macros defined in this file and what they mean. If not ++ * defined for a platform, reasonable defaults are used. ++ * ++ * DEVICE_IRQ_MASKL IRQ mask for GPIO ints, to disable some IRQs for ++ * autodetect. A bitmask corresponding to IRQ #s ++ * 40 through 55. A 0 bit means disabled, a 1 bit ++ * will enable for autodetect only if the line is ++ * configured as input at boot. ++ * DEVICE_IRQ_MASKH Same for IRQ #s 56 through 71. Note that a VR4111 ++ * or VR4121-based device that uses 32-bit data bus ++ * should probably set DEVICE_IRQ_MASKH to 0. ++ * ADJUSTED_PORT_BASE Some devices have ISA IO ports at a different ++ * offset than the standard. In particular, ++ * VRC4171 PCMCIA controller needs an extra offset. ++ * This value is the virtual address corresponding ++ * to ISA IO port 0. ++ * For VIDEORAM_* ad FB_*, see drivers/video/sfb.c for description, those ++ * are not used unless Simple Frame Buffer (or maybe one of its ++ * derivatives) is used. ++ * GPIO_BTN_MAP Default map of GPIO lines to button definition. ++ * GPIO_BTN_PRESS_LOW Define this if GPIO level 0 corresponds to a ++ * button press. Leave undefined if 1 correspods ++ * to button press. ++ * KBD_SCANLINES For devices with keyboards, the number of KIU ++ * scanlines to use. Default is all 12. ++ * ++ * (more to come...) ++ */ ++ ++#ifdef CONFIG_CASIO_E10 ++#define VIDEORAM_BASE (KSEG1 + 0x0a000000) ++#define FB_X_RES 240 ++#define FB_X_VIRTUAL_RES 1024 ++#define FB_Y_RES 320 ++#define FB_BPP 2 ++#define FB_IS_GREY 1 ++#endif ++ ++#ifdef CONFIG_CASIO_E15 ++#define VIDEORAM_BASE (KSEG1 + 0x0a000000) ++#define VIDEORAM_SIZE (256 * 1024) /* ??? */ ++#define FB_X_RES 240 ++#define FB_X_VIRTUAL_RES 512 ++#define FB_Y_RES 320 ++#define FB_BPP 4 ++#define FB_IS_GREY 1 ++#define FB_IS_INVERSE 1 ++#endif ++ ++#ifdef CONFIG_CASIO_E105 ++#define VIDEORAM_BASE (KSEG1 + 0x0a200000) ++#define FB_X_RES 240 ++#define FB_X_VIRTUAL_RES 256 ++#define FB_Y_RES 320 ++#define FB_BPP 16 ++#endif ++ ++#ifdef CONFIG_COMPAQ_AERO_15XX ++#define VIDEORAM_BASE (KSEG1 + 0x0a000000) ++#define ADJUSTED_PORT_BASE (VR41XX_PORT_BASE + 0x01000000) ++#define FB_X_RES 320 ++#define FB_Y_RES 240 ++#define FB_BPP 4 ++#define FB_IS_GREY 1 ++#define FB_IS_INVERSE 1 ++#define GPIO_BTN_MAP { 0, BTN_AP5, 0, 0, 0, 0, 0, \ ++ BTN_EXIT, BTN_POWER, BTN_AP4, BTN_AP3, BTN_AP2, BTN_AP1, 0, \ ++ 0, 0, BTN_UP, BTN_DOWN, BTN_ACTION, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } ++#define VR41XX_ENABLE_SPEAKER() \ ++ { \ ++ unsigned long flags; \ ++ save_and_cli(flags); \ ++ *VR41XX_GIUPODATL |= (VR41XX_GIUPODATL_GPIO33 | \ ++ VR41XX_GIUPODATL_GPIO34); \ ++ restore_flags(flags); \ ++ } ++#define VR41XX_DISABLE_SPEAKER() \ ++ { \ ++ unsigned long flags; \ ++ save_and_cli(flags); \ ++ *VR41XX_GIUPODATL &= ~(VR41XX_GIUPODATL_GPIO33 | \ ++ VR41XX_GIUPODATL_GPIO34); \ ++ restore_flags(flags); \ ++ } ++#define VR41XX_ENABLE_SERIAL(x) \ ++ *VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO15; ++#define VR41XX_DISABLE_SERIAL(x) \ ++ *VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO15; ++#endif ++ ++#ifdef CONFIG_COMPAQ_AERO_21XX ++#define VIDEORAM_BASE (KSEG1 + 0x0a000000) ++#define FB_X_RES 320 ++#define FB_Y_RES 240 ++#define FB_BPP 8 ++#endif ++ ++#ifdef CONFIG_EVEREX_FREESTYLE ++#define DEVICE_IRQ_MASKL 0xfffb ++#define DEVICE_IRQ_MASKH 0xffff ++#define ADJUSTED_PORT_BASE (VR41XX_PORT_BASE + 0x01000000) ++#define VIDEORAM_SIZE (256 * 1024) ++#define FB_X_RES 320 ++#define FB_Y_RES 240 ++#define FB_BPP 4 ++#define FB_IS_GREY 1 ++#define FB_IS_INVERSE 1 ++#define GPIO_BTN_MAP { 0, BTN_AP5, 0, 0, BTN_UP, BTN_DOWN, BTN_ACTION, \ ++ BTN_EXIT, BTN_CONTRAST, BTN_AP1, BTN_AP2, BTN_AP3, BTN_AP4, 0, \ ++ 0, 0, 0, 0, 0, 0, BTN_BACKLIGHT, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } ++#define GPIO_BTN_PRESS_LOW ++#define VR41XX_ENABLE_SERIAL(x) \ ++ *VR41XX_GIUPODATH |= VR41XX_GIUPODATH_GPIO48; ++#define VR41XX_DISABLE_SERIAL(x) \ ++ *VR41XX_GIUPODATH &= ~VR41XX_GIUPODATH_GPIO48; ++ ++#define VR41XX_ENABLE_SPEAKER() \ ++ { \ ++ unsigned long flags; \ ++ save_and_cli(flags); \ ++ *VR41XX_GIUPODATL |= VR41XX_GIUPODATL_GPIO44; \ ++ restore_flags(flags); \ ++ } ++#define VR41XX_DISABLE_SPEAKER() \ ++ { \ ++ unsigned long flags; \ ++ save_and_cli(flags); \ ++ *VR41XX_GIUPODATL &= ~VR41XX_GIUPODATL_GPIO44; \ ++ restore_flags(flags); \ ++ } ++#endif ++ ++#ifdef CONFIG_IBM_WORKPAD ++#define DEVICE_IRQ_MASKL 0xffff ++#define DEVICE_IRQ_MASKH 0x0000 ++#define ADJUSTED_PORT_BASE (VR41XX_PORT_BASE + 0x01000000) ++#define VIDEORAM_BASE (KSEG1 + 0x0a000000) ++#define FB_X_RES 640 ++#define FB_Y_RES 480 ++#define FB_BPP 16 ++#define GPIO_BTN_MAP { 0, BTN_AP5, BTN_NOTIFICATION, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } ++#define GPIO_BTN_PRESS_LOW ++#define VR41XX_ENABLE_SPEAKER() \ ++ { \ ++ unsigned long flags; \ ++ save_and_cli(flags); \ ++ *VR41XX_GIUPODATH |= VR41XX_GIUPODATH_GPIO49; \ ++ restore_flags(flags); \ ++ } ++#define VR41XX_DISABLE_SPEAKER() \ ++ { \ ++ unsigned long flags; \ ++ save_and_cli(flags); \ ++ *VR41XX_GIUPODATH &= ~VR41XX_GIUPODATH_GPIO49; \ ++ restore_flags(flags); \ ++ } ++#endif ++ ++#ifdef CONFIG_AGENDA_VR3 ++#define GPIO_BTN_MAP { \ ++ 0, 0, 0, 0, 0, 0, 0, BTN_AP2, \ ++ BTN_SYNC, BTN_AP1, 0, 0, 0, 0, 0, 0 \ ++} ++#undef GPIO_BTN_PRESS_LOW ++#define VR41XX_ENABLE_IRDA() irda_power(1); ++#define VR41XX_DISABLE_IRDA() irda_power(0); ++#endif ++ ++#ifdef CONFIG_NEC_MOBILEPRO_700 ++#define VIDEORAM_BASE (KSEG1 + 0x0a000000) ++#define VIDEORAM_SIZE (64 * 1024) ++#define FB_X_VIRTUAL_RES 1024 ++#define FB_X_RES 640 ++#define FB_Y_RES 240 ++#define FB_BPP 2 ++#define FB_IS_GREY 1 ++// GPIO[12] is speaker power on/off bit ++#define VR41XX_ENABLE_SPEAKER() \ ++ { \ ++ unsigned long flags; \ ++ save_and_cli(flags); \ ++ *VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO12; \ ++ restore_flags(flags); \ ++ } ++#define VR41XX_DISABLE_SPEAKER() \ ++ { \ ++ unsigned long flags; \ ++ save_and_cli(flags); \ ++ *VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO12; \ ++ restore_flags(flags); \ ++ } ++#endif ++ ++#ifdef CONFIG_NEC_MOBILEPRO_750C ++#define VIDEORAM_BASE (KSEG1 + 0x13000000) ++#define FB_X_VIRTUAL_RES 1024 ++#define FB_X_RES 640 ++#define FB_Y_RES 240 ++#define FB_BPP 8 ++// GPIO[12] is speaker power on/off bit ++#define VR41XX_ENABLE_SPEAKER() \ ++ { \ ++ unsigned long flags; \ ++ save_and_cli(flags); \ ++ *VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO12; \ ++ restore_flags(flags); \ ++ } ++#define VR41XX_DISABLE_SPEAKER() \ ++ { \ ++ unsigned long flags; \ ++ save_and_cli(flags); \ ++ *VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO12; \ ++ restore_flags(flags); \ ++ } ++#endif ++ ++#ifdef CONFIG_NEC_MOBILEPRO_770 ++// Tested by Jean-Nicolas, thanks! ++#define VIDEORAM_BASE (KSEG1 + 0x0a000000) ++#define VIDEORAM_SIZE (640 * 240 * 8) ++#define FB_X_VIRTUAL_RES 800 ++#define FB_X_RES 640 ++#define FB_Y_RES 240 ++#define FB_BPP 16 ++// GIUPODAT[12] is speaker power on/off bit confirmed by Checkstuff.exe ++#define VR41XX_ENABLE_SPEAKER() \ ++ { \ ++ unsigned long flags; \ ++ save_and_cli(flags); \ ++ *VR41XX_GIUPODATL |= VR41XX_GIUPODATL_GPIO44; \ ++ restore_flags(flags); \ ++ } ++#define VR41XX_DISABLE_SPEAKER() \ ++ { \ ++ unsigned long flags; \ ++ save_and_cli(flags); \ ++ *VR41XX_GIUPODATL &= ~VR41XX_GIUPODATL_GPIO44; \ ++ restore_flags(flags); \ ++ } ++#endif ++ ++#ifdef CONFIG_NEC_MOBILEPRO_800 ++#define VIDEORAM_BASE (KSEG1 + 0x0a000000) ++#define FB_X_RES 800 ++#define FB_Y_RES 600 ++#define FB_BPP 16 ++// GPIO[12] is speaker power on/off bit ++#define VR41XX_ENABLE_SPEAKER() \ ++ { \ ++ unsigned long flags; \ ++ save_and_cli(flags); \ ++ *VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO12; \ ++ restore_flags(flags); \ ++ } ++#define VR41XX_DISABLE_SPEAKER() \ ++ { \ ++ unsigned long flags; \ ++ save_and_cli(flags); \ ++ *VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO12; \ ++ restore_flags(flags); \ ++ } ++#endif ++ ++#ifdef CONFIG_NEC_OSPREY ++// AP4 did strange things, Backlight button GPIO currently used for IOCS16, ++// AP2 used for debug board Ethernet controller, AP3 just doesn't work ++#define GPIO_BTN_MAP { BTN_CONTRAST, BTN_UP, BTN_DOWN, 0, BTN_AP1, BTN_EXIT, 0, \ ++ 0, BTN_ACTION, 0, 0, 0, 0, 0, 0, 0 } ++#undef GPIO_BTN_PRESS_LOW ++#endif ++ ++#ifdef CONFIG_NEC_UEB30 ++#define VIDEORAM_BASE (KSEG1 + 0x0a000000) ++#define FB_X_RES 640 ++#define FB_Y_RES 480 ++#define FB_BPP 8 ++#endif ++ ++#ifdef CONFIG_VADEM_CLIO_1000 ++#define VR41XX_ENABLE_SERIAL(x) \ ++ *VR41XX_GIUPODATL |= VR41XX_GIUPODATL_GPIO42; ++#define VR41XX_DISABLE_SERIAL(x) \ ++ *VR41XX_GIUPODATL &= ~VR41XX_GIUPODATL_GPIO42; ++#define KBD_SCANLINES 8 ++#endif ++ ++#ifdef CONFIG_VADEM_CLIO_1050 ++#define KBD_SCANLINES 8 ++#define VIDEORAM_BASE (KSEG1 + 0x0a200000) ++#define FB_X_RES 640 ++#define FB_Y_RES 480 ++#define FB_BPP 16 ++#endif ++ ++#ifdef CONFIG_NEC_MOBILEGEAR2_R300 ++#define VIDEORAM_BASE (KSEG1 + 0x0a000000) ++#define VIDEORAM_SIZE (64 * 1024) ++#define FB_X_VIRTUAL_RES 1024 ++#define FB_X_RES 640 ++#define FB_Y_RES 240 ++#define FB_BPP 2 ++#define FB_IS_GREY 1 ++// GPIO[12] is speaker power on/off bit ++#define VR41XX_ENABLE_SPEAKER() \ ++ { \ ++ unsigned long flags; \ ++ save_and_cli(flags); \ ++ *VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO12; \ ++ restore_flags(flags); \ ++ } ++#define VR41XX_DISABLE_SPEAKER() \ ++ { \ ++ unsigned long flags; \ ++ save_and_cli(flags); \ ++ *VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO12; \ ++ restore_flags(flags); \ ++ } ++// GPIO[14] is serial power on/off bit ++#define VR41XX_ENABLE_SERIAL(x) \ ++ *VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO14; ++#define VR41XX_DISABLE_SERIAL(x) \ ++ *VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO14; ++#endif ++ ++#ifdef CONFIG_NEC_MOBILEGEAR2_R320 ++#define VIDEORAM_BASE (KSEG1 + 0x0a000000) ++#define VIDEORAM_SIZE (64 * 1024) ++#define FB_X_VIRTUAL_RES 640 ++#define FB_X_RES 640 ++#define FB_Y_RES 240 ++#define FB_BPP 2 ++#define FB_IS_GREY 1 ++// GPIO[12] is speaker power on/off bit ++#define VR41XX_ENABLE_SPEAKER() \ ++ { \ ++ unsigned long flags; \ ++ save_and_cli(flags); \ ++ *VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO12; \ ++ restore_flags(flags); \ ++ } ++#define VR41XX_DISABLE_SPEAKER() \ ++ { \ ++ unsigned long flags; \ ++ save_and_cli(flags); \ ++ *VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO12; \ ++ restore_flags(flags); \ ++ } ++// GPIO[14] is serial power on/off bit ++#define VR41XX_ENABLE_SERIAL(x) \ ++ *VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO14; ++#define VR41XX_DISABLE_SERIAL(x) \ ++ *VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO14; ++#endif ++ ++#ifdef CONFIG_NEC_MOBILEGEAR2_R430 ++#define DEVICE_IRQ_MASKL 0xffff ++#define DEVICE_IRQ_MASKH 0x0000 ++#define VIDEORAM_BASE (KSEG1 + 0x0a180100) ++#define VIDEORAM_SIZE (640 * 240 * 8) ++#define FB_X_VIRTUAL_RES 640 ++#define FB_X_RES 640 ++#define FB_Y_RES 240 ++#define FB_BPP 16 ++// GIUPODAT[12] is speaker power on/off bit confirmed by Checkstuff.exe ++#define VR41XX_ENABLE_SPEAKER() \ ++ { \ ++ unsigned long flags; \ ++ save_and_cli(flags); \ ++ *VR41XX_GIUPODATL |= VR41XX_GIUPODATL_GPIO44; \ ++ restore_flags(flags); \ ++ } ++#define VR41XX_DISABLE_SPEAKER() \ ++ { \ ++ unsigned long flags; \ ++ save_and_cli(flags); \ ++ *VR41XX_GIUPODATL &= ~VR41XX_GIUPODATL_GPIO44; \ ++ restore_flags(flags); \ ++ } ++// GPIO[14] is serial power on/off bit ++#define VR41XX_ENABLE_SERIAL(x) \ ++ *VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO14; ++#define VR41XX_DISABLE_SERIAL(x) \ ++ *VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO14; ++#endif ++ ++ ++#ifdef CONFIG_NEC_MOBILEGEAR2_R500 ++#define VIDEORAM_BASE (KSEG1 + 0x13000000) ++#define VIDEORAM_SIZE (640 * 240 * 8) ++#define FB_X_VIRTUAL_RES 1024 ++#define FB_X_RES 640 ++#define FB_Y_RES 240 ++#define FB_BPP 8 ++// #define FB_IS_GRAY 1 ++// GPIO[12] is speaker power on/off bit ++#define VR41XX_ENABLE_SPEAKER() \ ++ { \ ++ unsigned long flags; \ ++ save_and_cli(flags); \ ++ *VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO12; \ ++ restore_flags(flags); \ ++ } ++#define VR41XX_DISABLE_SPEAKER() \ ++ { \ ++ unsigned long flags; \ ++ save_and_cli(flags); \ ++ *VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO12; \ ++ restore_flags(flags); \ ++ } ++// GPIO[14] is serial power on/off bit ++#define VR41XX_ENABLE_SERIAL(x) \ ++ *VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO14; ++#define VR41XX_DISABLE_SERIAL(x) \ ++ *VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO14; ++#endif ++ ++#ifdef CONFIG_NEC_MOBILEGEAR2_R510 ++// Not tested yet ++#define VIDEORAM_BASE (KSEG1 + 0x0a000000) ++#define VIDEORAM_SIZE (640 * 240 * 8) ++#define FB_X_VIRTUAL_RES 1024 ++#define FB_X_RES 640 ++#define FB_Y_RES 240 ++#define FB_BPP 8 ++// GIUPODAT[12] is speaker power on/off bit confirmed by Checkstuff.exe ++#define VR41XX_ENABLE_SPEAKER() \ ++ { \ ++ unsigned long flags; \ ++ save_and_cli(flags); \ ++ *VR41XX_GIUPODATL |= VR41XX_GIUPODATL_GPIO44; \ ++ restore_flags(flags); \ ++ } ++#define VR41XX_DISABLE_SPEAKER() \ ++ { \ ++ unsigned long flags; \ ++ save_and_cli(flags); \ ++ *VR41XX_GIUPODATL &= ~VR41XX_GIUPODATL_GPIO44; \ ++ restore_flags(flags); \ ++ } ++// GPIO[14] is serial power on/off bit ++#define VR41XX_ENABLE_SERIAL(x) \ ++ *VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO14; ++#define VR41XX_DISABLE_SERIAL(x) \ ++ *VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO14; ++#endif ++ ++#ifdef CONFIG_NEC_MOBILEGEAR2_R520 ++#define VIDEORAM_BASE (KSEG1 + 0x0a000000) ++#define VIDEORAM_SIZE (640 * 240 * 8) ++#define FB_X_VIRTUAL_RES 800 ++#define FB_X_RES 640 ++#define FB_Y_RES 240 ++#define FB_BPP 16 ++// GIUPODAT[12] is speaker power on/off bit confirmed by Checkstuff.exe ++#define VR41XX_ENABLE_SPEAKER() \ ++ { \ ++ unsigned long flags; \ ++ save_and_cli(flags); \ ++ *VR41XX_GIUPODATL |= VR41XX_GIUPODATL_GPIO44; \ ++ restore_flags(flags); \ ++ } ++#define VR41XX_DISABLE_SPEAKER() \ ++ { \ ++ unsigned long flags; \ ++ save_and_cli(flags); \ ++ *VR41XX_GIUPODATL &= ~VR41XX_GIUPODATL_GPIO44; \ ++ restore_flags(flags); \ ++ } ++// GPIO[14] is serial power on/off bit ++#define VR41XX_ENABLE_SERIAL(x) \ ++ *VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO14; ++#define VR41XX_DISABLE_SERIAL(x) \ ++ *VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO14; ++#endif ++ ++#ifdef CONFIG_NEC_MOBILEGEAR2_R530 ++#define DEVICE_IRQ_MASKL 0xffff ++#define DEVICE_IRQ_MASKH 0x0000 ++#define VIDEORAM_BASE (KSEG1 + 0x0a180100) ++#define VIDEORAM_SIZE (640 * 240 * 8) ++#define FB_X_VIRTUAL_RES 640 ++#define FB_X_RES 640 ++#define FB_Y_RES 240 ++#define FB_BPP 16 ++// GIUPODAT[12] is speaker power on/off bit confirmed by Checkstuff.exe ++#define VR41XX_ENABLE_SPEAKER() \ ++ { \ ++ unsigned long flags; \ ++ save_and_cli(flags); \ ++ *VR41XX_GIUPODATL |= VR41XX_GIUPODATL_GPIO44; \ ++ restore_flags(flags); \ ++ } ++#define VR41XX_DISABLE_SPEAKER() \ ++ { \ ++ unsigned long flags; \ ++ save_and_cli(flags); \ ++ *VR41XX_GIUPODATL &= ~VR41XX_GIUPODATL_GPIO44; \ ++ restore_flags(flags); \ ++ } ++// GPIO[14] is serial power on/off bit ++#define VR41XX_ENABLE_SERIAL(x) \ ++ *VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO14; ++#define VR41XX_DISABLE_SERIAL(x) \ ++ *VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO14; ++#endif ++ ++#ifdef CONFIG_DOCOMO_SIGMARION ++#define VIDEORAM_BASE (KSEG1 + 0x0a000000) ++#define VIDEORAM_SIZE (640 * 240 * 8) ++#define FB_X_VIRTUAL_RES 640 ++#define FB_X_RES 640 ++#define FB_Y_RES 240 ++#define FB_BPP 16 ++// GIUPODAT[12] is speaker power on/off bit confirmed by Checkstuff.exe ++#define VR41XX_ENABLE_SPEAKER() \ ++ { \ ++ unsigned long flags; \ ++ save_and_cli(flags); \ ++ *VR41XX_GIUPODATL |= VR41XX_GIUPODATL_GPIO44; \ ++ restore_flags(flags); \ ++ } ++#define VR41XX_DISABLE_SPEAKER() \ ++ { \ ++ unsigned long flags; \ ++ save_and_cli(flags); \ ++ *VR41XX_GIUPODATL &= ~VR41XX_GIUPODATL_GPIO44; \ ++ restore_flags(flags); \ ++ } ++// GPIO[14] is serial power on/off bit ++#define VR41XX_ENABLE_SERIAL(x) \ ++ *VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO14; ++#define VR41XX_DISABLE_SERIAL(x) \ ++ *VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO14; ++#endif ++ ++#ifdef CONFIG_NEC_MOBILEGEAR2_R700 ++// Not tested yet ++#define VIDEORAM_BASE (KSEG1 + 0x0a000000) ++#define VIDEORAM_SIZE (640 * 240 * 8) ++#define FB_X_VIRTUAL_RES 800 ++#define FB_X_RES 800 ++#define FB_Y_RES 600 ++#define FB_BPP 16 ++// GPIO[12] is speaker power on/off bit ++#define VR41XX_ENABLE_SPEAKER() \ ++ { \ ++ unsigned long flags; \ ++ save_and_cli(flags); \ ++ *VR41XX_GIUPIODL |= VR41XX_GIUPIODL_GPIO12; \ ++ restore_flags(flags); \ ++ } ++#define VR41XX_DISABLE_SPEAKER() \ ++ { \ ++ unsigned long flags; \ ++ save_and_cli(flags); \ ++ *VR41XX_GIUPIODL &= ~VR41XX_GIUPIODL_GPIO12; \ ++ restore_flags(flags); \ ++ } ++// PODAT[14](GPIO[46]) is serial power on/off bit ++#define VR41XX_ENABLE_SERIAL(x) \ ++ *VR41XX_GIUPODATL |= VR41XX_GIUPODATL_GPIO46; ++#define VR41XX_DISABLE_SERIAL(x) \ ++ *VR41XX_GIUPODATL &= ~VR41XX_GIUPODATL_GPIO46; ++#endif ++ ++#ifdef CONFIG_NEC_HARRIER ++#define VIDEORAMBASE (KSEG1 + 0x10400000) ++#define FB_X_RES 800 ++#define FB_Y_RES 600 ++#define FB_BPP 8 ++#define VIDEORAM_SIZE (FB_X_RES * FB_Y_RES * FB_BPP / 8) ++#define KBD_SCANLINES 8 ++#define GPIO_BTN_MAP { \ ++ BTN_AP1, 0, 0, BTN_AP2, \ ++ 0, 0, 0, BTN_BACKLIGHT, \ ++ 0, BTN_AP3, 0, 0, \ ++ BTN_AP4, 0, 0, 0, \ ++ 0, 0, 0, 0, \ ++ 0, 0, 0, 0, \ ++ 0, 0, 0, 0, \ ++ 0, 0, 0, 0, \ ++ 0, 0, 0, 0, \ ++ 0, 0, 0, 0, \ ++ BTN_AP25, BTN_AP26, BTN_AP27, BTN_AP28, \ ++ BTN_AP29, BTN_AP30, BTN_AP31, BTN_AP32, \ ++ BTN_AP33, BTN_AP34, BTN_AP35, BTN_AP36 \ ++ } ++#endif ++ ++// Some reasonable defaults ++ ++#ifndef DEVICE_IRQ_MASKL ++#define DEVICE_IRQ_MASKL 0xffff ++#endif ++ ++#ifndef DEVICE_IRQ_MASKH ++#ifndef CONFIG_CPU_VR4181 ++#define DEVICE_IRQ_MASKH 0xffff ++#endif ++#endif ++ ++#ifndef ADJUSTED_PORT_BASE ++#define ADJUSTED_PORT_BASE VR41XX_PORT_BASE ++#endif ++ ++#ifndef VR41XX_ENABLE_SPEAKER ++#define VR41XX_ENABLE_SPEAKER() do { } while (0) ++#endif ++#ifndef VR41XX_DISABLE_SPEAKER ++#define VR41XX_DISABLE_SPEAKER() do { } while (0) ++#endif ++ ++#ifndef VR41XX_ENABLE_SERIAL ++#define VR41XX_ENABLE_SERIAL(x) do { } while (0) ++#endif ++#ifndef VR41XX_DISABLE_SERIAL ++#define VR41XX_DISABLE_SERIAL(x) do { } while (0) ++#endif ++ ++#ifndef VR41XX_ENABLE_IRDA ++#define VR41XX_ENABLE_IRDA() do { } while (0) ++#endif ++#ifndef VR41XX_DISABLE_IRDA ++#define VR41XX_DISABLE_IRDA() do { } while (0) ++#endif ++ ++#ifndef KBD_SCANLINES ++#define KBD_SCANLINES 12 ++#endif ++ ++#endif /* __ASM_MIPS_VR41XX_PLATDEP_H */ +diff -ruN linux-mips/include/asm-mips/vr41xx.h linux-vr/include/asm-mips/vr41xx.h +--- linux-mips/include/asm-mips/vr41xx.h Wed Dec 31 16:00:00 1969 ++++ linux-vr/include/asm-mips/vr41xx.h Thu Nov 23 11:57:43 2000 +@@ -0,0 +1,28 @@ ++/* $Id: vr41xx.h,v 1.14 2000/11/15 20:04:24 mikemac Exp $ ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 1999 by Michael Klar ++ */ ++#ifndef __ASM_MIPS_VR41XX_H ++#define __ASM_MIPS_VR41XX_H ++ ++#ifdef __KERNEL__ ++ ++#include ++ ++#ifdef CONFIG_CPU_VR4181 ++#include ++#else ++#ifdef CONFIG_CPU_VR4122 ++#include ++#else ++#include ++#endif ++#endif ++ ++#endif /* __KERNEL__ */ ++ ++#endif +diff -ruN linux-mips/include/asm-mips/vrc4171.h linux-vr/include/asm-mips/vrc4171.h +--- linux-mips/include/asm-mips/vrc4171.h Wed Dec 31 16:00:00 1969 ++++ linux-vr/include/asm-mips/vrc4171.h Sun Sep 10 13:29:18 2000 +@@ -0,0 +1,457 @@ ++/* ++ * linux/include/asm-mips/vrc4171.h ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 1999 by Steve K. Longerbeam ++ * Copyright (C) 2000 Michael Klar ++ */ ++ ++#ifndef __ASM_MIPS_VRC4171_H_ ++#define __ASM_MIPS_VRC4171_H_ ++ ++#include ++ ++// ++// LCD display and PCMCIA controller base addresses ++// ++#define VRC4171_LCD_BASE (KSEG1 + VR41XX_LCD) ++#define VRC4171_LCDMEM_BASE VRC4171_LCD_BASE ++#define VRC4171_LCDREG_BASE (VRC4171_LCD_BASE + 0x00800000) ++#define VRC4171_PCMCIA_BASE (KSEG1 + VR41XX_ISA_IO + 0x01000000) ++ ++#define VRC4171_Config1 __preg16(VRC4171_PCMCIA_BASE + 0x05fe) ++#define VRC4171_Config2 __preg16(VRC4171_PCMCIA_BASE + 0x05fc) ++#define VRC4171_IntrStat __preg16(VRC4171_PCMCIA_BASE + 0x05fa) ++#define VRC4171_GPIOControlData __preg16(VRC4171_PCMCIA_BASE + 0x05ee) ++ ++// NOTE: These reg defs are unconfirmed by documentation. In fact, I'm ++// not real sure where they came from. This may be a VRC4171 vs VRC4171A ++// issue, since the only documentation available is for VRC4171A. MFK ++#define VRC4171_PCS0UpperStrtStp __preg16(VRC4171_PCMCIA_BASE + 0x05ec) ++#define VRC4171_PCS0LowerStart __preg16(VRC4171_PCMCIA_BASE + 0x05ea) ++#define VRC4171_PCS0LowerStop __preg16(VRC4171_PCMCIA_BASE + 0x05e8) ++#define VRC4171_PCS1UpperStrtStp __preg16(VRC4171_PCMCIA_BASE + 0x05e6) ++#define VRC4171_PCS1LowerStart __preg16(VRC4171_PCMCIA_BASE + 0x05e4) ++#define VRC4171_PCS1LowerStop __preg16(VRC4171_PCMCIA_BASE + 0x05e2) ++ ++// These reg defs are per the VRC4171A documentation: ++#define VRC4171A_PCS0UpperStart __preg16(VRC4171_PCMCIA_BASE + 0x05ec) ++#define VRC4171A_PCS0LowerStart __preg16(VRC4171_PCMCIA_BASE + 0x05ea) ++#define VRC4171A_PCS0UpperStop __preg16(VRC4171_PCMCIA_BASE + 0x05e8) ++#define VRC4171A_PCS0LowerStop __preg16(VRC4171_PCMCIA_BASE + 0x05e6) ++#define VRC4171A_PCS1UpperStart __preg16(VRC4171_PCMCIA_BASE + 0x05e4) ++#define VRC4171A_PCS1LowerStart __preg16(VRC4171_PCMCIA_BASE + 0x05e2) ++#define VRC4171A_PCS1UpperStop __preg16(VRC4171_PCMCIA_BASE + 0x05de) ++#define VRC4171A_PCS1LowerStop __preg16(VRC4171_PCMCIA_BASE + 0x05dc) ++ ++// The PCIC Index and Data registers ++#define VRC4171_PCICINDEX __preg8(VRC4171_PCMCIA_BASE + 0x03e0) ++#define VRC4171_PCICDATA __preg8(VRC4171_PCMCIA_BASE + 0x03e1) ++ ++// The LCD registers ++#define VRC4171_PanelSelect __preg16(VRC4171_LCDREG_BASE + 0x0000) ++#define VRC4171_LCDPanelCtl __preg16(VRC4171_LCDREG_BASE + 0x0002) ++#define VRC4171_PowerModeCtl __preg16(VRC4171_LCDREG_BASE + 0x0004) ++#define VRC4171_MCLKEnable __preg16(VRC4171_LCDREG_BASE + 0x0006) ++#define VRC4171_VCLKEnable __preg16(VRC4171_LCDREG_BASE + 0x0008) ++#define VRC4171_VidFIFOMemIntCtl __preg16(VRC4171_LCDREG_BASE + 0x000A) ++#define VRC4171_PixelAdjVertHalf __preg16(VRC4171_LCDREG_BASE + 0x000C) ++#define VRC4171_HorzDisplayCtl __preg16(VRC4171_LCDREG_BASE + 0x0010) ++#define VRC4171_HorzRetrCtl __preg16(VRC4171_LCDREG_BASE + 0x0012) ++#define VRC4171_VertDispEndCtl __preg16(VRC4171_LCDREG_BASE + 0x0014) ++#define VRC4171_VertDispCtl __preg16(VRC4171_LCDREG_BASE + 0x0016) ++#define VRC4171_VertRetrStartCtl __preg16(VRC4171_LCDREG_BASE + 0x0018) ++#define VRC4171_VertRetrEndCtl __preg16(VRC4171_LCDREG_BASE + 0x001A) ++#define VRC4171_StartingAddress __preg16(VRC4171_LCDREG_BASE + 0x001C) ++#define VRC4171_Offset __preg16(VRC4171_LCDREG_BASE + 0x001E) ++#define VRC4171_HardwareCurCtl __preg16(VRC4171_LCDREG_BASE + 0x0020) ++#define VRC4171_HardwareCurXPos __preg16(VRC4171_LCDREG_BASE + 0x0022) ++#define VRC4171_HardwareCurYPos __preg16(VRC4171_LCDREG_BASE + 0x0024) ++#define VRC4171_HardwareCurClr0A __preg16(VRC4171_LCDREG_BASE + 0x0026) ++#define VRC4171_HardwareCurClr0B __preg16(VRC4171_LCDREG_BASE + 0x0028) ++#define VRC4171_HardwareCurClr1A __preg16(VRC4171_LCDREG_BASE + 0x002A) ++#define VRC4171_HardwareCurClr1B __preg16(VRC4171_LCDREG_BASE + 0x002C) ++#define VRC4171_HardwareCurOrign __preg16(VRC4171_LCDREG_BASE + 0x002E) ++#define VRC4171_RAMWriteAddress __preg16(VRC4171_LCDREG_BASE + 0x0040) ++#define VRC4171_RAMWritePort0 __preg16(VRC4171_LCDREG_BASE + 0x0042) ++#define VRC4171_RAMWritePort1 __preg16(VRC4171_LCDREG_BASE + 0x0044) ++// Note: RAMRead doesn't seem to work on VRC4171, maybe another VRC4171A diff ++#define VRC4171_RAMReadAddress __preg16(VRC4171_LCDREG_BASE + 0x0046) ++#define VRC4171_RAMReadPort0 __preg16(VRC4171_LCDREG_BASE + 0x0048) ++#define VRC4171_RAMReadPort1 __preg16(VRC4171_LCDREG_BASE + 0x004A) ++#define VRC4171_ScratchPadReg0 __preg16(VRC4171_LCDREG_BASE + 0x0050) ++#define VRC4171_ScratchPadReg1 __preg16(VRC4171_LCDREG_BASE + 0x0052) ++ ++//----------------------------------------------------------- ++// Configuration I Register (VRC4171_Config1) Bit Definitions ++//----------------------------------------------------------- ++ ++#define SLOT_B_NONE 0x0000 ++#define SLOT_B_PCMCIA 0x4000 ++#define SLOT_B_COMP_FLASH 0x8000 ++#define SLOT_B_MINI 0xc000 ++#define SLOT_B_MASK 0xc000 ++#define EN_OR 0x2000 ++#define EN_VCLK 0x1000 ++#define EN_BUSCLK 0x0800 ++#define IO_UADEC 0x0200 ++#define VMCLK_DIV8 0x01c0 ++#define VMCLK_DIV7 0x0180 ++#define VMCLK_DIV6 0x0140 ++#define VMCLK_DIV5 0x0100 ++#define VMCLK_DIV4 0x00c0 ++#define VMCLK_DIV3 0x0080 ++#define VMCLK_DIV2 0x0040 ++#define VMCLK_DIV1 0x0000 ++#define VCLK_DIV8 0x0038 ++#define VCLK_DIV7 0x0030 ++#define VCLK_DIV6 0x0028 ++#define VCLK_DIV5 0x0020 ++#define VCLK_DIV4 0x0018 ++#define VCLK_DIV3 0x0010 ++#define VCLK_DIV2 0x0008 ++#define VCLK_DIV1 0x0000 ++ ++//------------------------------------------------------------ ++// Configuration II Register (VRC4171_Config2) Bit Definitions ++//------------------------------------------------------------ ++#define SIL_REV_MASK 0xf000 ++#define REV_VRC4171A 0x2000 ++#define REV_VRC4171 0x1000 ++#define MCLK_EN 0x0400 ++#define READ_HOLD_DELAY_NONE 0x0000 ++#define READ_HOLD_DELAY_7 0x0004 ++#define READ_HOLD_DELAY_X1 0x0008 ++#define READ_HOLD_DELAY_14 0x000c ++#define IOCH_R1 0x0002 ++ ++ ++ ++//--------------------------------------------------------// ++// Register Index Values ++//--------------------------------------------------------// ++typedef enum { ++ IndexChipRevision = 0, // 0x00 ++ IndexInterfaceStatus, // 0x01 ++ IndexPowerControl, // 0x02 ++ IndexIntrAndGeneralControl, // 0x03 ++ IndexCardStatusChange, // 0x04 ++ IndexCardStatusIntrConfig, // 0x05 ++ IndexMappingEnable, // 0x06 ++ IndexIoWindowControl, // 0x07 ++ IndexIomap0StartAddrLow, // 0x08 ++ IndexIomap0StartAddrHi, // 0x09 ++ IndexIomap0EndAddrLow, // 0x0a ++ IndexIomap0EndAddrHi, // 0x0b ++ IndexIomap1StartAddrLow, // 0x0c ++ IndexIomap1StartAddrHi, // 0x0d ++ IndexIomap1EndAddrLow, // 0x0e ++ IndexIomap1EndAddrHi, // 0x0f ++ IndexMemmap0StartAddrLow, // 0x10 ++ IndexMemmap0StartAddrHi, // 0x11 ++ IndexMemmap0EndAddrLow, // 0x12 ++ IndexMemmap0EndAddrHi, // 0x13 ++ IndexMemmap0AddrOffsetLow, // 0x14 ++ IndexMemmap0AddrOffsetHi, // 0x15 ++ IndexMiscControl, // 0x16 ++ IndexFifoControl, // 0x17 ++ IndexMemmap1StartAddrLow, // 0x18 ++ IndexMemmap1StartAddrHi, // 0x19 ++ IndexMemmap1EndAddrLow, // 0x1a ++ IndexMemmap1EndAddrHi, // 0x1b ++ IndexMemmap1AddrOffsetLow, // 0x1c ++ IndexMemmap1AddrOffsetHi, // 0x1d ++ IndexGlobalControl, // 0x1e ++ IndexVoltageSense, // 0x1f ++ IndexMemmap2StartAddrLow, // 0x20 ++ IndexMemmap2StartAddrHi, // 0x21 ++ IndexMemmap2EndAddrLow, // 0x22 ++ IndexMemmap2EndAddrHi, // 0x23 ++ IndexMemmap2AddrOffsetLow, // 0x24 ++ IndexMemmap2AddrOffsetHi, // 0x25 ++ IndexAtaControl, // 0x26 ++ IndexReserved0, // 0x27 ++ IndexMemmap3StartAddrLow, // 0x28 ++ IndexMemmap3StartAddrHi, // 0x29 ++ IndexMemmap3EndAddrLow, // 0x2a ++ IndexMemmap3EndAddrHi, // 0x2b ++ IndexMemmap3AddrOffsetLow, // 0x2c ++ IndexMemmap3AddrOffsetHi, // 0x2d ++ IndexReserved1, // 0x2e ++ IndexVoltageSelect, // 0x2f ++ IndexMemmap4StartAddrLow, // 0x30 ++ IndexMemmap4StartAddrHi, // 0x31 ++ IndexMemmap4EndAddrLow, // 0x32 ++ IndexMemmap4EndAddrHi, // 0x33 ++ IndexMemmap4AddrOffsetLow, // 0x34 ++ IndexMemmap4AddrOffsetHi, // 0x35 ++ IndexIomap0AddrOffsetLow, // 0x36 ++ IndexIomap0AddrOffsetHi, // 0x37 ++ IndexIomap1AddrOffsetLow, // 0x38 ++ IndexIomap1AddrOffsetHi, // 0x39 ++ IndexSetupTiming0, // 0x3a ++ IndexCommandTiming0, // 0x3b ++ IndexRecoveryTiming0, // 0x3c ++ IndexSetupTiming1, // 0x3d ++ IndexCommandTiming1, // 0x3e ++ IndexRecoveryTiming1 // 0x3f ++} vrc4171pcm_index_t; ++ ++ ++// To access Slot B PCIC data registers, add the following ++// to the index values above. ++#define SLOT_B_INDEX_OFFSET 0x40 ++ ++//--------------------------------------------------------// ++// SOCKET // ++// Data Register // ++ ++//--------------------------------------------------------// ++// REGISTER INDEX No.00 Bit Definitions ++//--------------------------------------------------------// ++#define SLOT_REV_MASK 0x0f ++#define IF_TYPE_MASK 0xc0 ++#define IF_TYPE_IO_MEM 0x80 ++ ++//--------------------------------------------------------// ++// REGISTER INDEX No.01 Bit Definitions ++//--------------------------------------------------------// ++#define CARD_POWER_ON (1<<6) ++#define READY_BUSY (1<<5) ++#define WRITE_PROTECT (1<<4) ++#define CARD_DETECT_CD2 (1<<3) ++#define CARD_DETECT_CD1 (1<<2) ++#define BATTERY_VOLTAGE_DETECT_BVD2 (1<<1) ++#define BATTERY_VOLTAGE_DETECT_BVD1 (1<<0) ++ ++//--------------------------------------------------------// ++// REGISTER INDEX No.02 Bit Definitions ++//--------------------------------------------------------// ++#define OUTPUT_ENABLE 0x80 ++#define POWER_ENABLE 0x10 ++#define VPP_SELECT_MASK 0x03 ++ ++//--------------------------------------------------------// ++// REGISTER INDEX No.03 Bit Definitions ++//--------------------------------------------------------// ++ ++#define RING_INDICATE_ENABLE 0x80 // ++#define CARD_RESET 0x40 // ++#define CARD_IS_IO 0x20 // ++#define ENABLE_MANAGE_INT 0x10 // ++#define IO_IRQ_BIT_OFFSET 0 ++ ++//--------------------------------------------------------// ++// REGISTER INDEX No.04 Bit Definitions ++//--------------------------------------------------------// ++#define DETECT_CHANGE 0x08 // ++#define READY_CHANGE 0x04 // ++#define BATTERY_WARNING 0x02 // ++#define BATTERY_DEAD_OR_STS_CHG 0x01 // ++ ++//--------------------------------------------------------// ++// REGISTER INDEX No.05 Bit Definitions ++//--------------------------------------------------------// ++ ++#define CSC_IRQ_BIT_OFFSET 4 ++#define CARD_DETECT_ENABLE 0x08 // ++#define READY_ENABLE 0x04 // ++#define BATTERY_WARNING_ENABLE 0x02 // ++#define BATTERY_DEAD_STSCHG_ENABLE 0x01 // ++ ++//--------------------------------------------------------// ++// REGISTER INDEX No.06 Bit Definitions ++//--------------------------------------------------------// ++ ++#define IOMAP1_ENABLE 0x80 // ++#define IOMAP0_ENABLE 0x40 // ++#define MEMCS16_DECODE 0x20 // ++#define MEMMAP4_ENABLE 0x10 // ++#define MEMMAP3_ENABLE 0x08 // ++#define MEMMAP2_ENABLE 0x04 // ++#define MEMMAP1_ENABLE 0x02 // ++#define MEMMAP0_ENABLE 0x01 // ++ ++//--------------------------------------------------------// ++// REGISTER INDEX No.07 Bit Definitions ++//--------------------------------------------------------// ++ ++#define TIMING_REGISTER_SELECT1 0x80 // ++// 0x40 // ++#define AUTO_SIZE_IO_WINDOW1 0x20 // ++#define IO_WINDOW1_SIZE 0x10 // ++#define TIMING_REGISTER_SELECT0 0x08 // ++// 0x04 // ++#define AUTO_SIZE_IO_WINDOW0 0x02 // ++#define IO_WINDOW0_SIZE 0x01 // ++ ++#define IO_WINDOW0_WS 0x04 ++#define IO_WINDOW1_WS 0x40 ++ ++//--------------------------------------------------------// ++// REGISTER INDEX No.08 ,0C Bit Definitions ++// // ++// I/O MAP0,1 START ADDRESS LOW : START ADDRESS Bit 7-0 // ++//--------------------------------------------------------// ++ ++//--------------------------------------------------------// ++// REGISTER INDEX No.09 ,0D Bit Definitions ++// // ++// I/O MAP0,1 START ADDRESS HIGH : START ADDRESS Bit 15-8 // ++//--------------------------------------------------------// ++ ++//--------------------------------------------------------// ++// REGISTER INDEX No.0A ,0E Bit Definitions ++// // ++// I/O MAP0,1 END ADDRESS LOW : END ADDRESS Bit 7-0 // ++//--------------------------------------------------------// ++ ++//--------------------------------------------------------// ++// REGISTER INDEX No.0B ,0F Bit Definitions ++// // ++// I/O MAP0,1 END ADDRESS HIGH : END ADDRESS Bit 15-8 // ++//--------------------------------------------------------// ++ ++//--------------------------------------------------------// ++// REGISTER INDEX No.10,18,20,28,30 Bit Definitions ++// // ++// MEMORY MAP0,1,2,3,4 START ADDRESS LOW // ++// : START ADDRESS Bit 19-12// ++//--------------------------------------------------------// ++ ++//--------------------------------------------------------// ++// REGISTER INDEX No.11,19,21,29,31 Bit Definitions ++// // ++// MEMORY MAP0,1,2,3,4 START ADDRESS HIGH // ++// : START ADDRESS Bit 23-20// ++//--------------------------------------------------------// ++ ++#define WINDOW_DATA_SIZE 0x80 // ++ ++//--------------------------------------------------------// ++// REGISTER INDEX No.12,1A,22,2A,32 Bit Definitions ++// // ++// MEMORY MAP0,1,2,3,4 END ADDRESS LOW // ++// : END ADDRESS Bit 19-12 // ++//--------------------------------------------------------// ++ ++//--------------------------------------------------------// ++// REGISTER INDEX No.13,1B,23,2B,33 Bit Definitions ++// // ++// MEMORY MAP0,1,2,3,4 END ADDRESS HIGH // ++// : END ADDRESS Bit 23-20 // ++//--------------------------------------------------------// ++ ++#define CARD_TIMER_SELECT_HI 0x80 // ++#define CARD_TIMER_SELECT_LOW 0x40 // ++ ++//--------------------------------------------------------// ++// REGISTER INDEX No.14,1C,24,2C,34 Bit Definitions ++// // ++// MEMORY MAP0,1,2,3,4 ADDRESS OFFSET LOW // ++// : OFFSET ADDRESS Bit 19-12 // ++//--------------------------------------------------------// ++ ++//--------------------------------------------------------// ++// REGISTER INDEX No.15,1D,25,2D,35 Bit Definitions ++// // ++// MEMORY MAP0,1,2,3,4 ADDRESS OFFSET HIGH // ++// : OFFSET ADDRESS Bit 25-20 // ++//--------------------------------------------------------// ++ ++#define WINDOW_WRITE_PROTECT 0x80 // ++#define REG_SETTING 0x40 // ++ ++//--------------------------------------------------------// ++// REGISTER INDEX No.16 Bit Definitions ++//--------------------------------------------------------// ++ ++#define INPACK_ENABLE 0x80 // ++// 0x40 // ++// 0x20 // ++#define SPEAKER_ENABLE 0x10 // ++#define PULSE_SYSTEM_IRQ 0x08 // ++#define PLUSE_MANAGEMENT_INTERUPT 0x04 // ++#define VCC3_3 0x02 // ++#define DETECT_5V 0x01 // ++#define DLY16INH 0x01 ++ ++//--------------------------------------------------------// ++// REGISTER INDEX No.17 Bit Definitions ++//--------------------------------------------------------// ++ ++#define EMPTY_WRITE_FIFO 0x80 // ++// 0x40 // ++// 0x20 // ++// 0x10 // ++// 0x08 // ++// 0x04 // ++// 0x02 // ++// 0x01 // ++ ++//--------------------------------------------------------// ++// REGISTER INDEX No.1E Bit Definitions ++//--------------------------------------------------------// ++#define CLRPMIRQ 0x10 ++#define IRQPM_EN 0x08 ++#define EXWRBK 0x04 ++ ++//--------------------------------------------------------// ++// REGISTER INDEX No.1F Bit Definitions ++//--------------------------------------------------------// ++ ++#define CHIP_IDENTIFICATION_HI 0x80 // ++#define CHIP_IDENTIFICATION_LOW 0x40 // ++#define DUAL_SIGLE_SLOT 0x20 // ++#define CL_PD67_REV_LEVEL_BIT2 0x10 // ++#define CL_PD67_REV_LEVEL_BIT1 0x08 // ++#define CL_PD67_REV_LEVEL_BIT0 0x04 // ++#define VS2 0x02 ++#define VS1 0x01 ++#define VOLTAGE_SENSE_B_SHIFT 2 ++ ++//--------------------------------------------------------// ++// REGISTER INDEX No.26 Bit Definitions ++//--------------------------------------------------------// ++ ++#define A25_CSEL 0x80 // ++#define A24_M_S 0x40 // ++#define A23_VU 0x20 // ++#define A22 0x10 // ++#define A21 0x08 // ++// 0x04 // ++#define SPEAKER_IS_LED_INPUT 0x02 // ++#define ATA_MORD 0x01 // ++ ++//--------------------------------------------------------// ++// REGISTER INDEX No.2F Bit Definitions ++//--------------------------------------------------------// ++#define VCC_SELECT_MASK 0x03 ++ ++// ++// Mode Control Register 2 ++// ++#define DIRECT_VOLTAGE_SWITCH_ENABLE (1<<3) ++#define INPUT_ACKNOWLIEDGE_ENABLE (1<<2) ++#define IREQ_SENSE_SELECTION (1<<1) ++#define VOLTAGE_SELECTION (1<<0) ++#define VSELECT2 (1<<1) ++#define VSELECT1 (1<<0) ++#define VOLTAGE_LIMIT_SHIFT 2 ++#define VOLTAGE_SELECT_MASK 0x3 ++ ++//--------------------------------------------------------// ++// REGISTER INDEX No.3c Bit Definitions ++//--------------------------------------------------------// ++#define INTERNAL_VOLTAGE_SENSE 0x4 ++ ++//--------------------------------------------------------// ++// REGISTER INDEX No.3b & 7b Bit Definitions ++//--------------------------------------------------------// ++#define GP_OUTPUT 0x30 ++ ++ ++#endif // __ASM_MIPS_VRC4171_H_ +diff -ruN linux-mips/include/asm-mips/vrc4173.h linux-vr/include/asm-mips/vrc4173.h +--- linux-mips/include/asm-mips/vrc4173.h Wed Dec 31 16:00:00 1969 ++++ linux-vr/include/asm-mips/vrc4173.h Wed Nov 15 12:09:44 2000 +@@ -0,0 +1,214 @@ ++/* $Id: vrc4173.h,v 1.1 2000/11/15 20:09:44 mikemac Exp $ ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2000 by Michael R. McDonald ++ */ ++#ifndef __ASM_MIPS_VRC4173_H ++#define __ASM_MIPS_VRC4173_H ++ ++#include ++ ++#define VRC4173_IO_EXTENT 4096 ++#define VRC4173_SYSINT_MASK 0x0179 /* No doze, AC97, PCMCIA, nor KIU */ ++#define VRC4173_SELECTREG_MASK 0x7 /* Enable touch panel, PS2 1&2, and GPIO[0-15] */ ++ ++/* VRC4173 subfunction devices */ ++#define USB_DEV 0 ++#define PCMCIA2_DEV 1 ++#define PCMCIA1_DEV 2 ++#define PS2AUX_DEV 3 ++#define PS2KBD_DEV 4 ++#define PIU_DEV 5 ++#define AIU_DEV 6 ++#define KIU_DEV 7 ++#define GIU_DEV 8 ++#define AC97_DEV 9 ++ ++/* DMA Address Unit (DMAAU) */ ++#define VRC4173_AIUIBALREG 0x000 /* AIU IN DMA Base Address Register Low (R/W) */ ++#define VRC4173_AIUIBAHREG 0x002 /* AIU IN DMA Base Address Register High (R/W) */ ++#define VRC4173_AIUIALREG 0x004 /* AIU IN DMA Address Register Low (R/W) */ ++#define VRC4173_AIUIAHREG 0x006 /* AIU IN DMA Address Register High (R/W) */ ++#define VRC4173_AIUOBALREG 0x008 /* AIU OUT DMA Base Address Register Low (R/W) */ ++#define VRC4173_AIUOBAHREG 0x00A /* AIU OUT DMA Base Address Register High (R/W) */ ++#define VRC4173_AIUOALREG 0x00C /* AIU OUT DMA Address Register Low (R/W) */ ++#define VRC4173_AIUOAHREG 0x00E /* AIU OUT DMA Address Register High (R/W) */ ++#define VRC4173_FIRBALREG 0x010 /* FIR DMA Base Address Register Low (R/W) */ ++#define VRC4173_FIRBAHREG 0x012 /* FIR DMA Base Address Register High (R/W) */ ++#define VRC4173_FIRALREG 0x014 /* FIR DMA Address Register Low (R/W) */ ++#define VRC4173_FIRAHREG 0x016 /* FIR DMA Address Register High (R/W) */ ++ ++/* DMA Control Unit (DCU) */ ++#define VRC4173_DMARSTREG 0x020 /* DMA Reset Register */ ++#define VRC4173_DMAIDLEREG 0x022 /* DMA Sequencer Status Register */ ++#define VRC4173_DMASENREG 0x024 /* DMA Sequencer Enable Register */ ++#define VRC4173_DMAMSKREG 0x026 /* DMA Mask Register */ ++#define VRC4173_DMAREQREG 0x028 /* DMA Request Register */ ++ ++/* Clock Mask Unit (CMU) */ ++#define VRC4173_CMUCLKMSK 0x040 /* 4173 CMU Clock Mask Register */ ++#define VRC4173_CMUSRST 0x042 /* 4173 CMU Soft Reset Register */ ++ ++/* Interrupt Control Unit (ICU) */ ++#define VRC4173_SYSINT1REG 0x060 /* Level 1 System interrupt register 1 */ ++#define VRC4173_PIUINTREG_RO 0x062 /* Level 2 PIU interrupt register */ ++#define VRC4173_AIUINTREG 0x064 /* Level 2 AIU interrupt register */ ++#define VRC4173_KIUINTREG 0x066 /* Level 2 KIU interrupt register */ ++#define VRC4173_GIULINTREG 0x068 /* Level 2 GIU interrupt register Low */ ++#define VRC4173_GIUHINTREG 0x06A /* Level 2 GIU interrupt register High */ ++#define VRC4173_MSYSINT1REG 0x06C /* Level 1 mask system interrupt register 1 */ ++#define VRC4173_MPIUINTREG 0x06E /* Level 2 mask PIU interrupt register */ ++#define VRC4173_MAIUINTREG 0x070 /* Level 2 mask AIU interrupt register */ ++#define VRC4173_MKIUINTREG 0x072 /* Level 2 mask KIU interrupt register */ ++#define VRC4173_MGIULINTREG 0x074 /* Level 2 mask GIU interrupt register Low */ ++#define VRC4173_MGIUHINTREG 0x076 /* Level 2 mask GIU interrupt register High */ ++ ++/* General Purpose I/O Unit (GIU) */ ++#define VRC4173_GIUDIRL 0x080 /* GPIO Input/Output Select Register L */ ++#define VRC4173_GIUDIRH 0x082 /* GPIO Input/Output Select Register H */ ++#define VRC4173_GIUPIODL 0x084 /* GPIO Port Input/Output Data Register L */ ++#define VRC4173_GIUPIODH 0x086 /* GPIO Port Input/Output Data Register H */ ++#define VRC4173_GIUINTSTATL 0x088 /* GPIO Interrupt Status Register L */ ++#define VRC4173_GIUINTSTATH 0x08A /* GPIO Interrupt Status Register H */ ++#define VRC4173_GIUINTENL 0x08C /* GPIO Interrupt Enable Register L */ ++#define VRC4173_GIUINTENH 0x08E /* GPIO Interrupt Enable Register H */ ++#define VRC4173_GIUINTTYPL 0x090 /* GPIO Interrupt Type (Edge/Level) Select Register */ ++#define VRC4173_GIUINTTYPH 0x092 /* GPIO Interrupt Type (Edge/Level) Select Register */ ++#define VRC4173_GIUINTALSELL 0x094 /* GPIO Interrupt Active Level Select Register L */ ++#define VRC4173_GIUINTALSELH 0x096 /* GPIO Interrupt Active Level Select Register H */ ++#define VRC4173_GIUINTHTSELL 0x098 /* GPIO Interrupt Hold/Through Select Register L */ ++#define VRC4173_GIUINTHTSELH 0x09A /* GPIO Interrupt Hold/Through Select Register H */ ++#define VRC4173_SELECTREG 0x09E /* GPIO Port Output Data Enable Register */ ++ ++#define VRC4173_SELECT_GPIO_L 1 ++#define VRC4173_SELECT_PS2_2 2 ++#define VRC4173_SELECT_PS2_1 4 ++#define VRC4173_SELECT_GPIO_H 8 ++ ++#define VRC4173_GIUPIODH_GPIO20 0x0010 ++#define VRC4173_GIUPIODH_GPIO19 0x0008 ++#define VRC4173_GIUPIODH_GPIO18 0x0004 ++#define VRC4173_GIUPIODH_GPIO17 0x0002 ++#define VRC4173_GIUPIODH_GPIO16 0x0001 ++#define VRC4173_GIUPIODL_GPIO15 0x8000 ++#define VRC4173_GIUPIODL_GPIO14 0x4000 ++#define VRC4173_GIUPIODL_GPIO13 0x2000 ++#define VRC4173_GIUPIODL_GPIO12 0x1000 ++#define VRC4173_GIUPIODL_GPIO11 0x0800 ++#define VRC4173_GIUPIODL_GPIO10 0x0400 ++#define VRC4173_GIUPIODL_GPIO9 0x0200 ++#define VRC4173_GIUPIODL_GPIO8 0x0100 ++#define VRC4173_GIUPIODL_GPIO7 0x0080 ++#define VRC4173_GIUPIODL_GPIO6 0x0040 ++#define VRC4173_GIUPIODL_GPIO5 0x0020 ++#define VRC4173_GIUPIODL_GPIO4 0x0010 ++#define VRC4173_GIUPIODL_GPIO3 0x0008 ++#define VRC4173_GIUPIODL_GPIO2 0x0004 ++#define VRC4173_GIUPIODL_GPIO1 0x0002 ++#define VRC4173_GIUPIODL_GPIO0 0x0001 ++ ++/* Touch Panel Interface Unit (PIU) */ ++#define VRC4173_PIUCNTREG 0x0A2 /* PIU Control register (R/W) */ ++#define VRC4173_PIUCNTREG_PIUSEQEN 0x0004 ++#define VRC4173_PIUCNTREG_PIUPWR 0x0002 ++#define VRC4173_PIUCNTREG_PADRST 0x0001 ++#define VRC4173_PIUCNTREG_STATE_DISABLE 0 ++#define VRC4173_PIUCNTREG_STATE_STANDBY 1 ++#define VRC4173_PIUCNTREG_STATE_PORTSCAN 2 ++#define VRC4173_PIUCNTREG_STATE_WAITPEN 4 ++#define VRC4173_PIUCNTREG_STATE_PENSCAN 5 ++#define VRC4173_PIUCNTREG_STATE_NEXTSCAN 6 ++#define VRC4173_PIUCNTREG_STATE_CMDSCAN 7 ++ ++#define VRC4173_PIUINTREG 0x0A4 /* PIU Interrupt cause register (R/W) */ ++#define VRC4173_PIUINTREG_OVP 0x8000 ++#define VRC4173_PIUINTREG_PADCMD 0x0040 ++#define VRC4173_PIUINTREG_PADADP 0x0020 ++#define VRC4173_PIUINTREG_PADPAGE1 0x0010 ++#define VRC4173_PIUINTREG_PADPAGE0 0x0008 ++#define VRC4173_PIUINTREG_PADDLOST 0x0004 ++#define VRC4173_PIUINTREG_PENCHG 0x0001 ++ ++#define VRC4173_PIUSIVLREG 0x0A6 /* PIU Data sampling interval register (R/W) */ ++#define VRC4173_PIUSTBLREG 0x0A8 /* PIU A/D converter start delay register (R/W) */ ++#define VRC4173_PIUCMDREG 0x0AA /* PIU A/D command register (R/W) */ ++#define VRC4173_PIUASCNREG 0x0B0 /* PIU A/D port scan register (R/W) */ ++#define VRC4173_PIUAMSKREG 0x0B2 /* PIU A/D scan mask register (R/W) */ ++#define VRC4173_PIUCIVLREG 0x0BE /* PIU Check interval register (R) */ ++#define VRC4173_PIUPB00REG 0x0C0 /* PIU Page 0 Buffer 0 register (R/W) */ ++#define VRC4173_PIUPB01REG 0x0C2 /* PIU Page 0 Buffer 1 register (R/W) */ ++#define VRC4173_PIUPB02REG 0x0C4 /* PIU Page 0 Buffer 2 register (R/W) */ ++#define VRC4173_PIUPB03REG 0x0C6 /* PIU Page 0 Buffer 3 register (R/W) */ ++#define VRC4173_PIUPB10REG 0x0C8 /* PIU Page 1 Buffer 0 register (R/W) */ ++#define VRC4173_PIUPB11REG 0x0CA /* PIU Page 1 Buffer 1 register (R/W) */ ++#define VRC4173_PIUPB12REG 0x0CC /* PIU Page 1 Buffer 2 register (R/W) */ ++#define VRC4173_PIUPB13REG 0x0CE /* PIU Page 1 Buffer 3 register (R/W) */ ++#define VRC4173_PIUAB0REG 0x0D0 /* PIU A/D scan Buffer 0 register (R/W) */ ++#define VRC4173_PIUAB1REG 0x0D2 /* PIU A/D scan Buffer 1 register (R/W) */ ++#define VRC4173_PIUPB04REG 0x0DC /* PIU Page 0 Buffer 4 register (R/W) */ ++#define VRC4173_PIUPB14REG 0x0DE /* PIU Page 1 Buffer 4 register (R/W) */ ++ ++/* Audio Interface Unit (AIU) */ ++#define VRC4173_MDMADATREG 0x0E0 /* Mike DMA Data Register (R/W) */ ++#define VRC4173_SDMADATREG 0x0E2 /* Speaker DMA Data Register (R/W) */ ++#define VRC4173_SODATREG 0x0E6 /* Speaker Output Data Register (R/W) */ ++#define VRC4173_SCNTREG 0x0E8 /* Speaker Output Control Register (R/W) */ ++#define VRC4173_SCNVRREG 0x0EA /* Speaker Conversion Rate Register (R/W) */ ++#define VRC4173_MIDATREG 0x0F0 /* Mike Input Data Register (R/W) */ ++#define VRC4173_MCNTREG 0x0F2 /* Mike Input Control Register (R/W) */ ++#define VRC4173_MCNVRREG 0x0F4 /* Mike Conversion Rate Register (R/W) */ ++#define VRC4173_DVALIDREG 0x0F8 /* Data Valid Register (R/W) */ ++#define VRC4173_SEQREG 0x0FA /* Sequential Register (R/W) */ ++#define VRC4173_INTREG 0x0FC /* Interrupt Register (R/W) */ ++ ++/* Keyboard Interface Unit (KIU) of the VRC4173 */ ++#define VRC4173_KIUDAT0 0x100 /* KIU Data0 Register (R/W) */ ++#define VRC4173_KIUDAT1 0x102 /* KIU Data1 Register (R/W) */ ++#define VRC4173_KIUDAT2 0x104 /* KIU Data2 Register (R/W) */ ++#define VRC4173_KIUDAT3 0x106 /* KIU Data3 Register (R/W) */ ++#define VRC4173_KIUDAT4 0x108 /* KIU Data4 Register (R/W) */ ++#define VRC4173_KIUDAT5 0x10A /* KIU Data5 Register (R/W) */ ++#define VRC4173_KIUSCANREP 0x110 /* KIU Scan/Repeat Register (R/W) */ ++#define VRC4173_KIUSCANREP_KEYEN 0x8000 ++#define VRC4173_KIUSCANREP_SCANSTP 0x0008 ++#define VRC4173_KIUSCANREP_SCANSTART 0x0004 ++#define VRC4173_KIUSCANREP_ATSTP 0x0002 ++#define VRC4173_KIUSCANREP_ATSCAN 0x0001 ++#define VRC4173_KIUSCANS 0x112 /* KIU Scan Status Register (R) */ ++#define VRC4173_KIUWKS 0x114 /* KIU Wait Keyscan Stable Register (R/W) */ ++#define VRC4173_KIUWKI 0x116 /* KIU Wait Keyscan Interval Register (R/W) */ ++#define VRC4173_KIUINT 0x118 /* KIU Interrupt Register (R/W) */ ++#define VRC4173_KIUINT_KDATLOST 0x0004 ++#define VRC4173_KIUINT_KDATRDY 0x0002 ++#define VRC4173_KIUINT_SCANINT 0x0001 ++#define VRC4173_KIURST 0x11A /* KIU Reset Register (W) */ ++#define VRC4173_KIUGPEN 0x11C /* KIU General Purpose Output Enable (R/W) */ ++#define VRC4173_SCANLINE 0x11E /* KIU Scan Line Register (R/W) */ ++ ++// PS2 Interface Unit (PSIU) of the VRC4173 ++#define VRC4173_PS2CH1DATA 0x120 /* PS2 Channel 1 Data Register (R/W) */ ++#define VRC4173_PS2CH1CTRL 0x122 /* PS2 Channel 1 Control Register (R/W) */ ++#define VRC4173_PS2CH1RST 0x124 /* PS2 Channel 1 Reset Register (R/W) */ ++ ++#define VRC4173_PS2CH2DATA 0x140 /* PS2 Channel 2 Data Register (R/W) */ ++#define VRC4173_PS2CH2CTRL 0x142 /* PS2 Channel 2 Control Register (R/W) */ ++#define VRC4173_PS2CH2RST 0x144 /* PS2 Channel 2 Reset Register (R/W) */ ++ ++/* AC97 Unit (AC97U) */ ++#define VRC4173_AC97_INT_STATUS 0x000 /* Interrupt Clear/Status Register */ ++#define VRC4173_AC97_CODEC_WR 0x004 /* Codec Write Register */ ++#define VRC4173_AC97_CODEC_RD 0x008 /* Codec Read Register */ ++#define VRC4173_AC97_ACLINK_CTRL 0x01C /* ACLINK Control Register */ ++ ++#define VRC4173_AC97_CODEC_WR_RWC (1<<23) /* sets read/write command */ ++#define VRC4173_AC97_CODEC_WR_WRDY (1<<31) /* write ready */ ++ ++#define VRC4173_AC97_CODEC_RD_RDRDY (1<<30) /* Read Data Ready */ ++#define VRC4173_AC97_CODEC_RD_DMASK 0xffff /* Read Data Mask */ ++ ++#define VRC4173_AC97_ACLINK_CTRL_SYNC_ON (1<<30) /* Codec sync bit */ ++ ++#endif /* __ASM_MIPS_VRC4173_H */ +diff -ruN linux-mips/include/linux/buttons.h linux-vr/include/linux/buttons.h +--- linux-mips/include/linux/buttons.h Wed Dec 31 16:00:00 1969 ++++ linux-vr/include/linux/buttons.h Thu Nov 23 11:57:44 2000 +@@ -0,0 +1,89 @@ ++/* $Id: buttons.h,v 1.3 2000/11/15 20:03:07 mikemac Exp $ ++ * ++ * Data defines for button input ++ * ++ * This was created for the NEC VR41xx GPIO button driver, but should be ++ * general enough that it applies to other platforms as well. ++ * ++ * Copyright (c) 2000 Michael Klar ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ */ ++ ++#ifndef _LINUX_BUTTONS_H ++#define _LINUX_BUTTONS_H ++ ++ ++#define BTN_PRESS 0x8000 ++#define BTN_RELEASE 0 ++ ++#define BTN_STATE_MASK 0x8000 ++#define BTN_DATA_MASK 0x0fff ++ ++/* ++ * The button definitions: ++ * ++ * Feel free to add more. With 4096 potential vlaues, we're not going to ++ * run out any time soon. Note that the application types listed for the ++ * BTN_AP buttons are only suggestions for which AP buttons to assign to ++ * which physical button based on button icon, and may not be applicable ++ * to platforms that are not productivity-oriented. ++ */ ++ ++#define BTN_POWER 0 ++#define BTN_ACTION 1 ++#define BTN_EXIT 2 ++#define BTN_UP 3 ++#define BTN_DOWN 4 ++#define BTN_CONTRAST 5 ++#define BTN_BACKLIGHT 6 ++#define BTN_NORTH 7 ++#define BTN_SOUTH 8 ++#define BTN_EAST 9 ++#define BTN_WEST 10 ++#define BTN_NOTIFICATION 11 ++#define BTN_SYNC 12 ++ ++#define BTN_AP1 256 // Task list ++#define BTN_AP2 257 // Address book ++#define BTN_AP3 258 // Notepad ++#define BTN_AP4 259 // Calendar ++#define BTN_AP5 260 // Voice recorder ++#define BTN_AP6 261 ++#define BTN_AP7 262 ++#define BTN_AP8 263 ++#define BTN_AP9 264 ++#define BTN_AP10 265 ++#define BTN_AP11 266 ++#define BTN_AP12 267 ++#define BTN_AP13 268 ++#define BTN_AP14 269 ++#define BTN_AP15 270 ++#define BTN_AP16 271 ++ ++#define BTN_AP17 272 ++#define BTN_AP18 273 ++#define BTN_AP19 274 ++#define BTN_AP20 275 ++#define BTN_AP21 276 ++#define BTN_AP22 277 ++#define BTN_AP23 278 ++#define BTN_AP24 279 ++#define BTN_AP25 280 ++#define BTN_AP26 281 ++#define BTN_AP27 282 ++#define BTN_AP28 283 ++#define BTN_AP29 284 ++#define BTN_AP30 285 ++#define BTN_AP31 286 ++#define BTN_AP32 287 ++ ++#define BTN_AP33 288 ++#define BTN_AP34 289 ++#define BTN_AP35 290 ++#define BTN_AP36 291 ++#define BTN_AP37 292 ++ ++#endif /* _LINUX_BUTTONS_H */ +diff -ruN linux-mips/include/linux/fb.h linux-vr/include/linux/fb.h +--- linux-mips/include/linux/fb.h Mon Sep 11 23:53:49 2000 ++++ linux-vr/include/linux/fb.h Thu Nov 23 15:05:26 2000 +@@ -30,6 +30,19 @@ + #define FBIOGET_GLYPH 0x4615 + #define FBIOGET_HWCINFO 0x4616 + ++/* For Linux VR */ ++#define FBIOGET_BACKLIGHT 0x4620 ++#define FBIOPUT_BACKLIGHT 0x4621 ++#define FBIOGET_CONTRAST 0x4622 ++#define FBIOPUT_CONTRAST 0x4623 ++#define FBIO_POWER 0x4624 ++ ++int display_get_backlight(void); ++int display_set_backlight(int n); ++int display_get_contrast(void); ++int display_set_contrast(int n); ++int display_power(int n); ++ + #define FB_TYPE_PACKED_PIXELS 0 /* Packed Pixels */ + #define FB_TYPE_PLANES 1 /* Non interleaved planes */ + #define FB_TYPE_INTERLEAVED_PLANES 2 /* Interleaved planes */ +diff -ruN linux-mips/include/linux/if.h linux-vr/include/linux/if.h +--- linux-mips/include/linux/if.h Sun Feb 20 13:53:54 2000 ++++ linux-vr/include/linux/if.h Sat Jul 15 08:17:02 2000 +@@ -59,7 +59,7 @@ + { + unsigned long mem_start; + unsigned long mem_end; +- unsigned short base_addr; ++ unsigned long base_addr; + unsigned char irq; + unsigned char dma; + unsigned char port; +diff -ruN linux-mips/include/linux/linkage.h linux-vr/include/linux/linkage.h +--- linux-mips/include/linux/linkage.h Sat Jun 24 22:46:58 2000 ++++ linux-vr/include/linux/linkage.h Sat Jul 1 11:32:42 2000 +@@ -1,7 +1,11 @@ + #ifndef _LINUX_LINKAGE_H + #define _LINUX_LINKAGE_H + ++#ifdef __KERNEL__ ++// Only use config.h if compiling kernel. ++// Others will have to #define CONFIG_X86_ALIGNMENT_16 if necessary. bdl + #include ++#endif + + #ifdef __cplusplus + #define CPP_ASMLINKAGE extern "C" +diff -ruN linux-mips/include/linux/miscdevice.h linux-vr/include/linux/miscdevice.h +--- linux-mips/include/linux/miscdevice.h Fri Nov 10 00:17:06 2000 ++++ linux-vr/include/linux/miscdevice.h Thu Nov 23 15:04:40 2000 +@@ -13,6 +13,8 @@ + #define APOLLO_MOUSE_MINOR 7 + #define PC110PAD_MINOR 9 + #define ADB_MOUSE_MINOR 10 ++#define VR41XX_TPANEL_MINOR 11 ++#define R39XX_TPANEL_MINOR 12 /* FIXME: Not OK'd with hpa yet */ + #define WATCHDOG_MINOR 130 /* Watchdog timer */ + #define TEMP_MINOR 131 /* Temperature Sensor */ + #define RTC_MINOR 135 +@@ -20,6 +22,7 @@ + #define SUN_OPENPROM_MINOR 139 + #define NVRAM_MINOR 144 + #define I2O_MINOR 166 ++#define VR41XX_BUTTONS_MINOR 180 + #define MICROCODE_MINOR 184 + #define MISC_DYNAMIC_MINOR 255 + +diff -ruN linux-mips/include/linux/pci_ids.h linux-vr/include/linux/pci_ids.h +--- linux-mips/include/linux/pci_ids.h Fri Nov 10 00:17:29 2000 ++++ linux-vr/include/linux/pci_ids.h Thu Nov 23 11:57:44 2000 +@@ -316,9 +316,14 @@ + #define PCI_DEVICE_ID_MIRO_36050 0x5601 + + #define PCI_VENDOR_ID_NEC 0x1033 ++#define PCI_DEVICE_ID_NEC_VRC4173_USB 0x0035 ++#define PCI_DEVICE_ID_NEC_NAPCCARD 0x003e + #define PCI_DEVICE_ID_NEC_PCX2 0x0046 + #define PCI_DEVICE_ID_NEC_NILE4 0x005a + #define PCI_DEVICE_ID_NEC_VRC5476 0x009b ++#define PCI_DEVICE_ID_NEC_VRC4173 0x00a5 ++#define PCI_DEVICE_ID_NEC_VRC4173_AC97 0x00a6 ++#define PCI_DEVICE_ID_NEC_VR4122 0x00be + + #define PCI_VENDOR_ID_FD 0x1036 + #define PCI_DEVICE_ID_FD_36C70 0x0000 +@@ -1140,6 +1145,9 @@ + + #define PCI_VENDOR_ID_NETVIN 0x4a14 + #define PCI_DEVICE_ID_NETVIN_NV5000SC 0x5000 ++ ++#define PCI_VENDOR_ID_MEDIAQ 0x4d51 ++#define PCI_DEVICE_ID_MEDIAQ_MQ200 0x0200 + + #define PCI_VENDOR_ID_S3 0x5333 + #define PCI_DEVICE_ID_S3_PLATO_PXS 0x0551 +diff -ruN linux-mips/include/linux/sched.h linux-vr/include/linux/sched.h +--- linux-mips/include/linux/sched.h Fri Nov 10 00:17:40 2000 ++++ linux-vr/include/linux/sched.h Thu Nov 23 15:03:49 2000 +@@ -552,7 +552,9 @@ + extern int in_group_p(gid_t); + extern int in_egroup_p(gid_t); + ++#if 0 // removed for VR41xx PCMCIA support + extern void release(struct task_struct * p); ++#endif + + extern void proc_caches_init(void); + extern void flush_signals(struct task_struct *); +diff -ruN linux-mips/include/linux/serial.h linux-vr/include/linux/serial.h +--- linux-mips/include/linux/serial.h Mon Sep 11 23:54:01 2000 ++++ linux-vr/include/linux/serial.h Wed Sep 13 08:16:40 2000 +@@ -81,6 +81,7 @@ + #define SERIAL_IO_HUB6 1 + #define SERIAL_IO_MEM 2 + #define SERIAL_IO_GSC 3 ++#define SERIAL_VADDR 4 + + struct serial_uart_config { + char *name; +diff -ruN linux-mips/include/linux/tpanel.h linux-vr/include/linux/tpanel.h +--- linux-mips/include/linux/tpanel.h Wed Dec 31 16:00:00 1969 ++++ linux-vr/include/linux/tpanel.h Mon Dec 27 12:12:30 1999 +@@ -0,0 +1,31 @@ ++/* $Id: tpanel.h,v 1.3 1999/12/27 20:12:30 brad Exp $ ++ * ++ * Touch Panel Data Structures ++ * by Michael Klar, wyldfier@iname.com ++ * ++ * Created for the touch panel interface built into the NEC VR41xx family of ++ * CPUs, but should be applicable to other touch panel hardware ++ */ ++ ++#ifndef _LINUX_TPANEL_H ++#define _LINUX_TPANEL_H ++ ++#include ++ ++/* ++ * The scan interval and settling time can be set via IOCTL, but the defualt ++ * of .01 sec and 480us should suffice for most applications. The argument to ++ * these IOCTL calls is a struct of the values in microseconds, but note that ++ * the hardware may have a less precise interval. If so, the value will be ++ * rounded and the actual value returned back. ++ */ ++ ++struct scanparam { ++ unsigned int interval; ++ unsigned int settletime; ++}; ++ ++#define TPGETSCANPARM _IOR( 0xB0, 0x00, struct scanparam ) ++#define TPSETSCANPARM _IOW( 0xB0, 0x01, struct scanparam ) ++ ++#endif /* _LINUX_TPANEL_H */ diff --git a/devel/mipsel-linux-kernel-headers/files/patch-cc-mips-lv-built b/devel/mipsel-linux-kernel-headers/files/patch-cc-mips-lv-built new file mode 100644 index 000000000000..e7509399ee64 --- /dev/null +++ b/devel/mipsel-linux-kernel-headers/files/patch-cc-mips-lv-built @@ -0,0 +1,477 @@ +diff -ruN linux-vr/include/asm-mips/offset.h linux-vr-built/include/asm-mips/offset.h +--- linux-vr/include/asm-mips/offset.h Wed Dec 31 16:00:00 1969 ++++ linux-vr-built/include/asm-mips/offset.h Thu Nov 23 15:34:50 2000 +@@ -0,0 +1,100 @@ ++/* DO NOT TOUCH, AUTOGENERATED BY OFFSET.C */ ++ ++#ifndef _MIPS_OFFSET_H ++#define _MIPS_OFFSET_H ++ ++/* MIPS pt_regs offsets. */ ++#define PT_R0 24 ++#define PT_R1 28 ++#define PT_R2 32 ++#define PT_R3 36 ++#define PT_R4 40 ++#define PT_R5 44 ++#define PT_R6 48 ++#define PT_R7 52 ++#define PT_R8 56 ++#define PT_R9 60 ++#define PT_R10 64 ++#define PT_R11 68 ++#define PT_R12 72 ++#define PT_R13 76 ++#define PT_R14 80 ++#define PT_R15 84 ++#define PT_R16 88 ++#define PT_R17 92 ++#define PT_R18 96 ++#define PT_R19 100 ++#define PT_R20 104 ++#define PT_R21 108 ++#define PT_R22 112 ++#define PT_R23 116 ++#define PT_R24 120 ++#define PT_R25 124 ++#define PT_R26 128 ++#define PT_R27 132 ++#define PT_R28 136 ++#define PT_R29 140 ++#define PT_R30 144 ++#define PT_R31 148 ++#define PT_LO 152 ++#define PT_HI 156 ++#define PT_EPC 160 ++#define PT_BVADDR 164 ++#define PT_STATUS 168 ++#define PT_CAUSE 172 ++#define PT_SIZE 176 ++ ++/* MIPS task_struct offsets. */ ++#define TASK_STATE 0 ++#define TASK_FLAGS 4 ++#define TASK_SIGPENDING 8 ++#define TASK_NEED_RESCHED 20 ++#define TASK_PTRACE 24 ++#define TASK_COUNTER 32 ++#define TASK_NICE 36 ++#define TASK_MM 44 ++#define TASK_PID 108 ++#define TASK_STRUCT_SIZE 1040 ++ ++/* MIPS specific thread_struct offsets. */ ++#define THREAD_REG16 600 ++#define THREAD_REG17 604 ++#define THREAD_REG18 608 ++#define THREAD_REG19 612 ++#define THREAD_REG20 616 ++#define THREAD_REG21 620 ++#define THREAD_REG22 624 ++#define THREAD_REG23 628 ++#define THREAD_REG29 632 ++#define THREAD_REG30 636 ++#define THREAD_REG31 640 ++#define THREAD_STATUS 644 ++#define THREAD_FPU 648 ++#define THREAD_BVADDR 912 ++#define THREAD_BUADDR 916 ++#define THREAD_ECODE 920 ++#define THREAD_TRAPNO 924 ++#define THREAD_MFLAGS 928 ++#define THREAD_CURDS 932 ++#define THREAD_TRAMP 936 ++#define THREAD_OLDCTX 940 ++ ++/* Linux mm_struct offsets. */ ++#define MM_USERS 16 ++#define MM_PGD 12 ++#define MM_CONTEXT 60 ++ ++/* Linux sigcontext offsets. */ ++#define SC_REGS 16 ++#define SC_FPREGS 272 ++#define SC_MDHI 544 ++#define SC_MDLO 552 ++#define SC_PC 8 ++#define SC_STATUS 4 ++#define SC_OWNEDFP 528 ++#define SC_FPC_CSR 532 ++#define SC_FPC_EIR 536 ++#define SC_CAUSE 560 ++#define SC_BADVADDR 564 ++ ++#endif /* !(_MIPS_OFFSET_H) */ +diff -ruN linux-vr/include/linux/autoconf.h linux-vr-built/include/linux/autoconf.h +--- linux-vr/include/linux/autoconf.h Wed Dec 31 16:00:00 1969 ++++ linux-vr-built/include/linux/autoconf.h Thu Nov 23 15:32:16 2000 +@@ -0,0 +1,352 @@ ++/* ++ * Automatically generated C config: don't edit ++ */ ++#define AUTOCONF_INCLUDED ++ ++/* ++ * Code maturity level options ++ */ ++#define CONFIG_EXPERIMENTAL 1 ++ ++/* ++ * Machine selection ++ */ ++#undef CONFIG_CLASS_DESKTOP ++#define CONFIG_CLASS_PDA 1 ++#undef CONFIG_SGI_IP22 ++#undef CONFIG_DECSTATION ++#undef CONFIG_AGENDA_VR3 ++#undef CONFIG_CASIO_E10 ++#undef CONFIG_CASIO_E15 ++#undef CONFIG_CASIO_E105 ++#undef CONFIG_CASIO_E125 ++#undef CONFIG_COMPAQ_8XX_201X ++#undef CONFIG_COMPAQ_AERO_15XX ++#undef CONFIG_COMPAQ_AERO_21XX ++#undef CONFIG_EVEREX_FREESTYLE ++#define CONFIG_IBM_WORKPAD 1 ++#undef CONFIG_NEC_MOBILEPRO_700 ++#undef CONFIG_NEC_MOBILEPRO_750C ++#undef CONFIG_NEC_MOBILEPRO_770 ++#undef CONFIG_NEC_MOBILEPRO_800 ++#undef CONFIG_NEC_MOBILEGEAR2_R300 ++#undef CONFIG_NEC_MOBILEGEAR2_R320 ++#undef CONFIG_NEC_MOBILEGEAR2_R430 ++#undef CONFIG_NEC_MOBILEGEAR2_R500 ++#undef CONFIG_NEC_MOBILEGEAR2_R510 ++#undef CONFIG_NEC_MOBILEGEAR2_R520 ++#undef CONFIG_NEC_MOBILEGEAR2_R530 ++#undef CONFIG_NEC_MOBILEGEAR2_R700 ++#undef CONFIG_DOCOMO_SIGMARION ++#undef CONFIG_NEC_OSPREY ++#undef CONFIG_NEC_UEB30 ++#undef CONFIG_PHILIPS_NINO ++#undef CONFIG_PHILIPS_VELO ++#undef CONFIG_SHARP_MOBILON ++#undef CONFIG_VTECH_HELIO ++#undef CONFIG_VADEM_CLIO_1000 ++#undef CONFIG_VADEM_CLIO_1050 ++#define CONFIG_CPU_VR41XX 1 ++#undef CONFIG_VTECH_HELIO_EMULATOR ++#undef CONFIG_CPU_HAS_LLSC ++#undef CONFIG_CPU_HAS_WB ++#define CONFIG_CPU_NO_FPU 1 ++#define CONFIG_ISA 1 ++#define CONFIG_KEYBOARD 1 ++#undef CONFIG_PCI ++#undef CONFIG_I8259 ++ ++/* ++ * Loadable module support ++ */ ++#undef CONFIG_MODULES ++ ++/* ++ * General setup ++ */ ++#define CONFIG_CPU_LITTLE_ENDIAN 1 ++#define CONFIG_KCORE_ELF 1 ++#define CONFIG_ELF_KERNEL 1 ++#undef CONFIG_BINFMT_AOUT ++#define CONFIG_BINFMT_ELF 1 ++#undef CONFIG_BINFMT_MISC ++#undef CONFIG_MIPS_FPU_EMULATOR ++#define CONFIG_NET 1 ++#undef CONFIG_HOTPLUG ++#undef CONFIG_PCMCIA ++#undef CONFIG_SYSVIPC ++#undef CONFIG_BSD_PROCESS_ACCT ++#define CONFIG_SYSCTL 1 ++#undef CONFIG_XIP_ROM ++#undef CONFIG_LINK_OVERRIDE ++ ++/* ++ * Parallel port support ++ */ ++#undef CONFIG_PARPORT ++#undef CONFIG_PM ++ ++/* ++ * Plug and Play configuration ++ */ ++#undef CONFIG_PNP ++#undef CONFIG_ISAPNP ++ ++/* ++ * Memory Technology Devices (MTD) ++ */ ++#undef CONFIG_MTD ++ ++/* ++ * Block devices ++ */ ++#undef CONFIG_BLK_DEV_FD ++#undef CONFIG_BLK_DEV_XD ++#undef CONFIG_PARIDE ++#undef CONFIG_BLK_CPQ_DA ++#undef CONFIG_BLK_CPQ_CISS_DA ++#undef CONFIG_BLK_DEV_DAC960 ++#undef CONFIG_BLK_DEV_LOOP ++#undef CONFIG_BLK_DEV_NBD ++#define CONFIG_BLK_DEV_RAM 1 ++#define CONFIG_BLK_DEV_RAM_SIZE (4096) ++#undef CONFIG_BLK_DEV_INITRD ++ ++/* ++ * Multi-device support (RAID and LVM) ++ */ ++#undef CONFIG_MD ++#undef CONFIG_BLK_DEV_MD ++#undef CONFIG_MD_LINEAR ++#undef CONFIG_MD_RAID0 ++#undef CONFIG_MD_RAID1 ++#undef CONFIG_MD_RAID5 ++#undef CONFIG_BLK_DEV_LVM ++#undef CONFIG_LVM_PROC_FS ++ ++/* ++ * Networking options ++ */ ++#undef CONFIG_PACKET ++#undef CONFIG_NETLINK ++#undef CONFIG_NETFILTER ++#undef CONFIG_FILTER ++#define CONFIG_UNIX 1 ++#define CONFIG_INET 1 ++#undef CONFIG_IP_MULTICAST ++#undef CONFIG_IP_ADVANCED_ROUTER ++#undef CONFIG_IP_PNP ++#undef CONFIG_NET_IPIP ++#undef CONFIG_NET_IPGRE ++#undef CONFIG_INET_ECN ++#undef CONFIG_SYN_COOKIES ++#undef CONFIG_IPV6 ++#undef CONFIG_KHTTPD ++#undef CONFIG_ATM ++ ++/* ++ * ++ */ ++#undef CONFIG_IPX ++#undef CONFIG_ATALK ++#undef CONFIG_DECNET ++#undef CONFIG_BRIDGE ++#undef CONFIG_X25 ++#undef CONFIG_LAPB ++#undef CONFIG_LLC ++#undef CONFIG_ECONET ++#undef CONFIG_WAN_ROUTER ++#undef CONFIG_NET_FASTROUTE ++#undef CONFIG_NET_HW_FLOWCONTROL ++ ++/* ++ * QoS and/or fair queueing ++ */ ++#undef CONFIG_NET_SCHED ++ ++/* ++ * ATA/IDE/MFM/RLL support ++ */ ++#define CONFIG_IDE 1 ++ ++/* ++ * IDE, ATA and ATAPI Block devices ++ */ ++#define CONFIG_BLK_DEV_IDE 1 ++ ++/* ++ * Please see Documentation/ide.txt for help/info on IDE drives ++ */ ++#undef CONFIG_BLK_DEV_HD_IDE ++#undef CONFIG_BLK_DEV_HD ++#define CONFIG_BLK_DEV_IDEDISK 1 ++#undef CONFIG_IDEDISK_MULTI_MODE ++#undef CONFIG_BLK_DEV_IDEDISK_VENDOR ++#undef CONFIG_BLK_DEV_IDEDISK_FUJITSU ++#undef CONFIG_BLK_DEV_IDEDISK_IBM ++#undef CONFIG_BLK_DEV_IDEDISK_MAXTOR ++#undef CONFIG_BLK_DEV_IDEDISK_QUANTUM ++#undef CONFIG_BLK_DEV_IDEDISK_SEAGATE ++#undef CONFIG_BLK_DEV_IDEDISK_WD ++#undef CONFIG_BLK_DEV_COMMERIAL ++#undef CONFIG_BLK_DEV_TIVO ++#undef CONFIG_BLK_DEV_IDECS ++#undef CONFIG_BLK_DEV_IDECD ++#undef CONFIG_BLK_DEV_IDETAPE ++#undef CONFIG_BLK_DEV_IDEFLOPPY ++#undef CONFIG_BLK_DEV_IDESCSI ++ ++/* ++ * IDE chipset support/bugfixes ++ */ ++#undef CONFIG_BLK_DEV_CMD640 ++#undef CONFIG_BLK_DEV_CMD640_ENHANCED ++#undef CONFIG_BLK_DEV_ISAPNP ++#undef CONFIG_IDE_CHIPSETS ++#undef CONFIG_IDEDMA_AUTO ++#undef CONFIG_DMA_NONPCI ++#undef CONFIG_BLK_DEV_IDE_MODES ++ ++/* ++ * Network device support ++ */ ++#undef CONFIG_NETDEVICES ++ ++/* ++ * IrDA (infrared) support ++ */ ++#undef CONFIG_IRDA ++ ++/* ++ * Character devices ++ */ ++#define CONFIG_VT 1 ++#define CONFIG_VT_CONSOLE 1 ++#define CONFIG_SERIAL 1 ++#undef CONFIG_SERIAL_CONSOLE ++#define CONFIG_TOUCH_PANEL 1 ++#define CONFIG_BUTTONS 1 ++#define CONFIG_BUTTONS_GPIO 1 ++#define CONFIG_BUTTONS_DIRECT_POWEROFF 1 ++#define CONFIG_RTC 1 ++#undef CONFIG_UNIX98_PTYS ++ ++/* ++ * File systems ++ */ ++#undef CONFIG_QUOTA ++#undef CONFIG_AUTOFS_FS ++#undef CONFIG_AUTOFS4_FS ++#undef CONFIG_ADFS_FS ++#undef CONFIG_ADFS_FS_RW ++#undef CONFIG_AFFS_FS ++#undef CONFIG_HFS_FS ++#undef CONFIG_BFS_FS ++#undef CONFIG_FAT_FS ++#undef CONFIG_MSDOS_FS ++#undef CONFIG_UMSDOS_FS ++#undef CONFIG_VFAT_FS ++#undef CONFIG_EFS_FS ++#undef CONFIG_JFFS_FS ++#undef CONFIG_CRAMFS ++#undef CONFIG_RAMFS ++#undef CONFIG_ISO9660_FS ++#undef CONFIG_JOLIET ++#undef CONFIG_MINIX_FS ++#undef CONFIG_NTFS_FS ++#undef CONFIG_NTFS_RW ++#undef CONFIG_HPFS_FS ++#define CONFIG_PROC_FS 1 ++#undef CONFIG_DEVFS_FS ++#undef CONFIG_DEVFS_MOUNT ++#undef CONFIG_DEVFS_DEBUG ++#undef CONFIG_DEVPTS_FS ++#undef CONFIG_QNX4FS_FS ++#undef CONFIG_QNX4FS_RW ++#undef CONFIG_ROMFS_FS ++#define CONFIG_EXT2_FS 1 ++#undef CONFIG_SYSV_FS ++#undef CONFIG_SYSV_FS_WRITE ++#undef CONFIG_UDF_FS ++#undef CONFIG_UDF_RW ++#undef CONFIG_UFS_FS ++#undef CONFIG_UFS_FS_WRITE ++ ++/* ++ * Network File Systems ++ */ ++#undef CONFIG_CODA_FS ++#define CONFIG_NFS_FS 1 ++#undef CONFIG_NFS_V3 ++#undef CONFIG_ROOT_NFS ++#undef CONFIG_NFSD ++#undef CONFIG_NFSD_V3 ++#define CONFIG_SUNRPC 1 ++#define CONFIG_LOCKD 1 ++#undef CONFIG_SMB_FS ++#undef CONFIG_NCP_FS ++#undef CONFIG_NCPFS_PACKET_SIGNING ++#undef CONFIG_NCPFS_IOCTL_LOCKING ++#undef CONFIG_NCPFS_STRONG ++#undef CONFIG_NCPFS_NFS_NS ++#undef CONFIG_NCPFS_OS2_NS ++#undef CONFIG_NCPFS_SMALLDOS ++#undef CONFIG_NCPFS_MOUNT_SUBDIR ++#undef CONFIG_NCPFS_NDS_DOMAINS ++#undef CONFIG_NCPFS_NLS ++#undef CONFIG_NCPFS_EXTRAS ++ ++/* ++ * Partition Types ++ */ ++#undef CONFIG_PARTITION_ADVANCED ++#define CONFIG_MSDOS_PARTITION 1 ++#undef CONFIG_NLS ++ ++/* ++ * Console drivers ++ */ ++ ++/* ++ * Frame-buffer support ++ */ ++#define CONFIG_FB 1 ++#define CONFIG_DUMMY_CONSOLE 1 ++#undef CONFIG_FB_CYBER2000 ++#undef CONFIG_FB_VIRTUAL ++#define CONFIG_FB_SIMPLE 1 ++#undef CONFIG_FB_HPCSFB ++#undef CONFIG_FB_SED1354 ++#undef CONFIG_FB_VR4181 ++#undef CONFIG_FB_R3912 ++#undef CONFIG_FB_VRC4171 ++#undef CONFIG_FBCON_ADVANCED ++#define CONFIG_FBCON_CFB16 1 ++#undef CONFIG_FBCON_FONTWIDTH8_ONLY ++#undef CONFIG_FBCON_FONTS ++#define CONFIG_FONT_8x8 1 ++#define CONFIG_FONT_8x16 1 ++#undef CONFIG_FBCON_DISABLE_LOGO ++ ++/* ++ * Sound ++ */ ++#undef CONFIG_SOUND ++ ++/* ++ * USB support ++ */ ++#undef CONFIG_USB ++ ++/* ++ * Input core support ++ */ ++#undef CONFIG_INPUT ++ ++/* ++ * Kernel hacking ++ */ ++#define CONFIG_CROSSCOMPILE 1 ++#undef CONFIG_REMOTE_DEBUG ++#undef CONFIG_MAGIC_SYSRQ ++#undef CONFIG_PROC_GIUINFO +diff -ruN linux-vr/include/linux/compile.h linux-vr-built/include/linux/compile.h +--- linux-vr/include/linux/compile.h Wed Dec 31 16:00:00 1969 ++++ linux-vr-built/include/linux/compile.h Thu Nov 23 15:34:48 2000 +@@ -0,0 +1,6 @@ ++#define UTS_VERSION "#1 Thu Nov 23 15:34:48 PST 2000" ++#define LINUX_COMPILE_TIME "15:34:48" ++#define LINUX_COMPILE_BY "mfklar" ++#define LINUX_COMPILE_HOST "ppan1" ++#define LINUX_COMPILE_DOMAIN "localdomain" ++#define LINUX_COMPILER "gcc version egcs-2.91.66 19990314 (egcs-1.1.2 release)" +diff -ruN linux-vr/include/linux/version.h linux-vr-built/include/linux/version.h +--- linux-vr/include/linux/version.h Wed Dec 31 16:00:00 1969 ++++ linux-vr-built/include/linux/version.h Thu Nov 23 15:32:20 2000 +@@ -0,0 +1,3 @@ ++#define UTS_RELEASE "2.4.0-test9" ++#define LINUX_VERSION_CODE 132096 ++#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c)) diff --git a/devel/mipsel-linux-kernel-headers/pkg-comment b/devel/mipsel-linux-kernel-headers/pkg-comment new file mode 100644 index 000000000000..6212ca8ed64a --- /dev/null +++ b/devel/mipsel-linux-kernel-headers/pkg-comment @@ -0,0 +1 @@ +Kernel headers for linux 2.4.0-pre9 for development for mipsel-linux diff --git a/devel/mipsel-linux-kernel-headers/pkg-descr b/devel/mipsel-linux-kernel-headers/pkg-descr new file mode 100644 index 000000000000..e4c6b12e2fc0 --- /dev/null +++ b/devel/mipsel-linux-kernel-headers/pkg-descr @@ -0,0 +1,7 @@ + Kernel headers from linux kernel 2.4.0-pre9 for cross development with + mipsel-linux as target. + + This port was hacked from SRPM for RedHat cross-development toolchain + for Linux VR. + +WWW: http://www.linux-vr.org/ diff --git a/devel/mipsel-linux-kernel-headers/pkg-plist b/devel/mipsel-linux-kernel-headers/pkg-plist new file mode 100644 index 000000000000..f3f5593027c9 --- /dev/null +++ b/devel/mipsel-linux-kernel-headers/pkg-plist @@ -0,0 +1,757 @@ +mipsel-linux/include/asm +mipsel-linux/include/asm-mips/a.out.h +mipsel-linux/include/asm-mips/addrspace.h +mipsel-linux/include/asm-mips/arc/types.h +mipsel-linux/include/asm-mips/asm.h +mipsel-linux/include/asm-mips/asmmacro.h +mipsel-linux/include/asm-mips/atomic.h +mipsel-linux/include/asm-mips/baget/baget.h +mipsel-linux/include/asm-mips/baget/vac.h +mipsel-linux/include/asm-mips/baget/vic.h +mipsel-linux/include/asm-mips/bcache.h +mipsel-linux/include/asm-mips/betty.h +mipsel-linux/include/asm-mips/bitops.h +mipsel-linux/include/asm-mips/bootinfo.h +mipsel-linux/include/asm-mips/branch.h +mipsel-linux/include/asm-mips/bugs.h +mipsel-linux/include/asm-mips/byteorder.h +mipsel-linux/include/asm-mips/cache.h +mipsel-linux/include/asm-mips/cachectl.h +mipsel-linux/include/asm-mips/cacheops.h +mipsel-linux/include/asm-mips/checksum.h +mipsel-linux/include/asm-mips/cpu.h +mipsel-linux/include/asm-mips/current.h +mipsel-linux/include/asm-mips/ddb5074.h +mipsel-linux/include/asm-mips/dec/interrupts.h +mipsel-linux/include/asm-mips/dec/ioasic.h +mipsel-linux/include/asm-mips/dec/ioasic_addrs.h +mipsel-linux/include/asm-mips/dec/ioasic_ints.h +mipsel-linux/include/asm-mips/dec/kn01.h +mipsel-linux/include/asm-mips/dec/kn02.h +mipsel-linux/include/asm-mips/dec/kn02xa.h +mipsel-linux/include/asm-mips/dec/kn03.h +mipsel-linux/include/asm-mips/dec/machtype.h +mipsel-linux/include/asm-mips/dec/tc.h +mipsel-linux/include/asm-mips/dec/tcinfo.h +mipsel-linux/include/asm-mips/dec/tcmodule.h +mipsel-linux/include/asm-mips/delay.h +mipsel-linux/include/asm-mips/div64.h +mipsel-linux/include/asm-mips/dma.h +mipsel-linux/include/asm-mips/ds1286.h +mipsel-linux/include/asm-mips/elf.h +mipsel-linux/include/asm-mips/errno.h +mipsel-linux/include/asm-mips/fcntl.h +mipsel-linux/include/asm-mips/floppy.h +mipsel-linux/include/asm-mips/fp.h +mipsel-linux/include/asm-mips/fpregdef.h +mipsel-linux/include/asm-mips/fpu_emulator.h +mipsel-linux/include/asm-mips/galileo-boards/ev96100.h +mipsel-linux/include/asm-mips/galileo-boards/ev96100int.h +mipsel-linux/include/asm-mips/galileo-boards/gt64120.h +mipsel-linux/include/asm-mips/galileo-boards/gt96100.h +mipsel-linux/include/asm-mips/gdb-stub.h +mipsel-linux/include/asm-mips/gfx.h +mipsel-linux/include/asm-mips/hardirq.h +mipsel-linux/include/asm-mips/hdreg.h +mipsel-linux/include/asm-mips/hw_irq.h +mipsel-linux/include/asm-mips/ide.h +mipsel-linux/include/asm-mips/init.h +mipsel-linux/include/asm-mips/inst.h +mipsel-linux/include/asm-mips/inventory.h +mipsel-linux/include/asm-mips/io.h +mipsel-linux/include/asm-mips/ioctl.h +mipsel-linux/include/asm-mips/ioctls.h +mipsel-linux/include/asm-mips/ipc.h +mipsel-linux/include/asm-mips/ipcbuf.h +mipsel-linux/include/asm-mips/irq.h +mipsel-linux/include/asm-mips/isadep.h +mipsel-linux/include/asm-mips/jazz.h +mipsel-linux/include/asm-mips/jazzdma.h +mipsel-linux/include/asm-mips/keyboard.h +mipsel-linux/include/asm-mips/linux_logo.h +mipsel-linux/include/asm-mips/linux_logo_sgi.h +mipsel-linux/include/asm-mips/linux_logo_vr.h +mipsel-linux/include/asm-mips/mc146818rtc.h +mipsel-linux/include/asm-mips/mips-boards/atlas.h +mipsel-linux/include/asm-mips/mips-boards/atlasint.h +mipsel-linux/include/asm-mips/mips-boards/generic.h +mipsel-linux/include/asm-mips/mips-boards/gt64120.h +mipsel-linux/include/asm-mips/mips-boards/malta.h +mipsel-linux/include/asm-mips/mips-boards/maltaint.h +mipsel-linux/include/asm-mips/mips-boards/piix4.h +mipsel-linux/include/asm-mips/mips-boards/prom.h +mipsel-linux/include/asm-mips/mipsprom.h +mipsel-linux/include/asm-mips/mipsregs.h +mipsel-linux/include/asm-mips/mman.h +mipsel-linux/include/asm-mips/mmu_context.h +mipsel-linux/include/asm-mips/msgbuf.h +mipsel-linux/include/asm-mips/namei.h +mipsel-linux/include/asm-mips/ng1.h +mipsel-linux/include/asm-mips/ng1hw.h +mipsel-linux/include/asm-mips/nile4.h +mipsel-linux/include/asm-mips/offset.h +mipsel-linux/include/asm-mips/orion.h +mipsel-linux/include/asm-mips/paccess.h +mipsel-linux/include/asm-mips/page.h +mipsel-linux/include/asm-mips/param.h +mipsel-linux/include/asm-mips/parport.h +mipsel-linux/include/asm-mips/pci.h +mipsel-linux/include/asm-mips/pgalloc.h +mipsel-linux/include/asm-mips/pgtable.h +mipsel-linux/include/asm-mips/poll.h +mipsel-linux/include/asm-mips/posix_types.h +mipsel-linux/include/asm-mips/power.h +mipsel-linux/include/asm-mips/prctl.h +mipsel-linux/include/asm-mips/processor.h +mipsel-linux/include/asm-mips/ptrace.h +mipsel-linux/include/asm-mips/r39xx.h +mipsel-linux/include/asm-mips/r4kcache.h +mipsel-linux/include/asm-mips/reboot.h +mipsel-linux/include/asm-mips/reg.h +mipsel-linux/include/asm-mips/regdef.h +mipsel-linux/include/asm-mips/resource.h +mipsel-linux/include/asm-mips/riscos-syscall.h +mipsel-linux/include/asm-mips/rrm.h +mipsel-linux/include/asm-mips/scatterlist.h +mipsel-linux/include/asm-mips/segment.h +mipsel-linux/include/asm-mips/semaphore-helper.h +mipsel-linux/include/asm-mips/semaphore.h +mipsel-linux/include/asm-mips/sembuf.h +mipsel-linux/include/asm-mips/serial.h +mipsel-linux/include/asm-mips/sfp-machine.h +mipsel-linux/include/asm-mips/sgi/sgi.h +mipsel-linux/include/asm-mips/sgi/sgihpc.h +mipsel-linux/include/asm-mips/sgi/sgimc.h +mipsel-linux/include/asm-mips/sgi/sgint23.h +mipsel-linux/include/asm-mips/sgialib.h +mipsel-linux/include/asm-mips/sgiarcs.h +mipsel-linux/include/asm-mips/sgidefs.h +mipsel-linux/include/asm-mips/shmbuf.h +mipsel-linux/include/asm-mips/shmiq.h +mipsel-linux/include/asm-mips/shmparam.h +mipsel-linux/include/asm-mips/sigcontext.h +mipsel-linux/include/asm-mips/siginfo.h +mipsel-linux/include/asm-mips/signal.h +mipsel-linux/include/asm-mips/smp.h +mipsel-linux/include/asm-mips/smplock.h +mipsel-linux/include/asm-mips/sni.h +mipsel-linux/include/asm-mips/socket.h +mipsel-linux/include/asm-mips/sockios.h +mipsel-linux/include/asm-mips/softirq.h +mipsel-linux/include/asm-mips/spinlock.h +mipsel-linux/include/asm-mips/stackframe.h +mipsel-linux/include/asm-mips/stat.h +mipsel-linux/include/asm-mips/statfs.h +mipsel-linux/include/asm-mips/string.h +mipsel-linux/include/asm-mips/sysmips.h +mipsel-linux/include/asm-mips/system.h +mipsel-linux/include/asm-mips/termbits.h +mipsel-linux/include/asm-mips/termios.h +mipsel-linux/include/asm-mips/timex.h +mipsel-linux/include/asm-mips/types.h +mipsel-linux/include/asm-mips/uaccess.h +mipsel-linux/include/asm-mips/ucontext.h +mipsel-linux/include/asm-mips/umap.h +mipsel-linux/include/asm-mips/unaligned.h +mipsel-linux/include/asm-mips/unistd.h +mipsel-linux/include/asm-mips/user.h +mipsel-linux/include/asm-mips/usioctl.h +mipsel-linux/include/asm-mips/vga.h +mipsel-linux/include/asm-mips/vr4121.h +mipsel-linux/include/asm-mips/vr4122.h +mipsel-linux/include/asm-mips/vr4181.h +mipsel-linux/include/asm-mips/vr41xx-platdep.h +mipsel-linux/include/asm-mips/vr41xx.h +mipsel-linux/include/asm-mips/vrc4171.h +mipsel-linux/include/asm-mips/vrc4173.h +mipsel-linux/include/asm-mips/watch.h +mipsel-linux/include/asm-mips/wbflush.h +mipsel-linux/include/asm-mips/xxx +mipsel-linux/include/linux/802_11.h +mipsel-linux/include/linux/a.out.h +mipsel-linux/include/linux/ac97_codec.h +mipsel-linux/include/linux/acct.h +mipsel-linux/include/linux/acpi.h +mipsel-linux/include/linux/adb.h +mipsel-linux/include/linux/adb_mouse.h +mipsel-linux/include/linux/adfs_fs.h +mipsel-linux/include/linux/adfs_fs_i.h +mipsel-linux/include/linux/adfs_fs_sb.h +mipsel-linux/include/linux/affs_fs.h +mipsel-linux/include/linux/affs_fs_i.h +mipsel-linux/include/linux/affs_fs_sb.h +mipsel-linux/include/linux/affs_hardblocks.h +mipsel-linux/include/linux/agp_backend.h +mipsel-linux/include/linux/agpgart.h +mipsel-linux/include/linux/amifd.h +mipsel-linux/include/linux/amifdreg.h +mipsel-linux/include/linux/amigaffs.h +mipsel-linux/include/linux/apm_bios.h +mipsel-linux/include/linux/arcdevice.h +mipsel-linux/include/linux/atalk.h +mipsel-linux/include/linux/atari_rootsec.h +mipsel-linux/include/linux/atm.h +mipsel-linux/include/linux/atm_eni.h +mipsel-linux/include/linux/atm_idt77105.h +mipsel-linux/include/linux/atm_nicstar.h +mipsel-linux/include/linux/atm_suni.h +mipsel-linux/include/linux/atm_tcp.h +mipsel-linux/include/linux/atm_zatm.h +mipsel-linux/include/linux/atmapi.h +mipsel-linux/include/linux/atmarp.h +mipsel-linux/include/linux/atmclip.h +mipsel-linux/include/linux/atmdev.h +mipsel-linux/include/linux/atmioc.h +mipsel-linux/include/linux/atmlec.h +mipsel-linux/include/linux/atmmpc.h +mipsel-linux/include/linux/atmsap.h +mipsel-linux/include/linux/atmsvc.h +mipsel-linux/include/linux/auto_fs.h +mipsel-linux/include/linux/auto_fs4.h +mipsel-linux/include/linux/autoconf.h +mipsel-linux/include/linux/awe_voice.h +mipsel-linux/include/linux/ax25.h +mipsel-linux/include/linux/b1lli.h +mipsel-linux/include/linux/b1pcmcia.h +mipsel-linux/include/linux/baycom.h +mipsel-linux/include/linux/bfs_fs.h +mipsel-linux/include/linux/bfs_fs_i.h +mipsel-linux/include/linux/bfs_fs_sb.h +mipsel-linux/include/linux/binfmts.h +mipsel-linux/include/linux/bitops.h +mipsel-linux/include/linux/blk.h +mipsel-linux/include/linux/blkdev.h +mipsel-linux/include/linux/blkpg.h +mipsel-linux/include/linux/bootmem.h +mipsel-linux/include/linux/bpqether.h +mipsel-linux/include/linux/brlock.h +mipsel-linux/include/linux/buttons.h +mipsel-linux/include/linux/byteorder/big_endian.h +mipsel-linux/include/linux/byteorder/generic.h +mipsel-linux/include/linux/byteorder/little_endian.h +mipsel-linux/include/linux/byteorder/pdp_endian.h +mipsel-linux/include/linux/byteorder/swab.h +mipsel-linux/include/linux/byteorder/swabb.h +mipsel-linux/include/linux/cache.h +mipsel-linux/include/linux/capability.h +mipsel-linux/include/linux/capi.h +mipsel-linux/include/linux/cciss_ioctl.h +mipsel-linux/include/linux/cd1400.h +mipsel-linux/include/linux/cdk.h +mipsel-linux/include/linux/cdrom.h +mipsel-linux/include/linux/circ_buf.h +mipsel-linux/include/linux/coda.h +mipsel-linux/include/linux/coda_cache.h +mipsel-linux/include/linux/coda_fs_i.h +mipsel-linux/include/linux/coda_linux.h +mipsel-linux/include/linux/coda_proc.h +mipsel-linux/include/linux/coda_psdev.h +mipsel-linux/include/linux/coff.h +mipsel-linux/include/linux/com20020.h +mipsel-linux/include/linux/compatmac.h +mipsel-linux/include/linux/compile.h +mipsel-linux/include/linux/comstats.h +mipsel-linux/include/linux/concap.h +mipsel-linux/include/linux/config.h +mipsel-linux/include/linux/console.h +mipsel-linux/include/linux/console_struct.h +mipsel-linux/include/linux/consolemap.h +mipsel-linux/include/linux/ctype.h +mipsel-linux/include/linux/cuda.h +mipsel-linux/include/linux/cyclades.h +mipsel-linux/include/linux/cyclomx.h +mipsel-linux/include/linux/cycx_cfm.h +mipsel-linux/include/linux/cycx_drv.h +mipsel-linux/include/linux/cycx_x25.h +mipsel-linux/include/linux/dasd.h +mipsel-linux/include/linux/dcache.h +mipsel-linux/include/linux/delay.h +mipsel-linux/include/linux/devfs_fs.h +mipsel-linux/include/linux/devfs_fs_kernel.h +mipsel-linux/include/linux/devpts_fs.h +mipsel-linux/include/linux/dio.h +mipsel-linux/include/linux/dirent.h +mipsel-linux/include/linux/dn.h +mipsel-linux/include/linux/dnotify.h +mipsel-linux/include/linux/dtlk.h +mipsel-linux/include/linux/efs_dir.h +mipsel-linux/include/linux/efs_fs.h +mipsel-linux/include/linux/efs_fs_i.h +mipsel-linux/include/linux/efs_fs_sb.h +mipsel-linux/include/linux/efs_vh.h +mipsel-linux/include/linux/elevator.h +mipsel-linux/include/linux/elf.h +mipsel-linux/include/linux/elfcore.h +mipsel-linux/include/linux/errno.h +mipsel-linux/include/linux/errqueue.h +mipsel-linux/include/linux/etherdevice.h +mipsel-linux/include/linux/ext2_fs.h +mipsel-linux/include/linux/ext2_fs_i.h +mipsel-linux/include/linux/ext2_fs_sb.h +mipsel-linux/include/linux/fat_cvf.h +mipsel-linux/include/linux/fb.h +mipsel-linux/include/linux/fcdevice.h +mipsel-linux/include/linux/fcntl.h +mipsel-linux/include/linux/fd.h +mipsel-linux/include/linux/fd1772.h +mipsel-linux/include/linux/fddidevice.h +mipsel-linux/include/linux/fdreg.h +mipsel-linux/include/linux/file.h +mipsel-linux/include/linux/filter.h +mipsel-linux/include/linux/fs.h +mipsel-linux/include/linux/fs_struct.h +mipsel-linux/include/linux/ftape-header-segment.h +mipsel-linux/include/linux/ftape-vendors.h +mipsel-linux/include/linux/ftape.h +mipsel-linux/include/linux/gameport.h +mipsel-linux/include/linux/generic_serial.h +mipsel-linux/include/linux/genhd.h +mipsel-linux/include/linux/ghash.h +mipsel-linux/include/linux/hayesesp.h +mipsel-linux/include/linux/hdlcdrv.h +mipsel-linux/include/linux/hdreg.h +mipsel-linux/include/linux/hdsmart.h +mipsel-linux/include/linux/hfs_fs.h +mipsel-linux/include/linux/hfs_fs_i.h +mipsel-linux/include/linux/hfs_fs_sb.h +mipsel-linux/include/linux/hfs_sysdep.h +mipsel-linux/include/linux/highmem.h +mipsel-linux/include/linux/highuid.h +mipsel-linux/include/linux/hippidevice.h +mipsel-linux/include/linux/hpfs_fs.h +mipsel-linux/include/linux/hpfs_fs_i.h +mipsel-linux/include/linux/hpfs_fs_sb.h +mipsel-linux/include/linux/hysdn_if.h +mipsel-linux/include/linux/i2c-algo-bit.h +mipsel-linux/include/linux/i2c-algo-pcf.h +mipsel-linux/include/linux/i2c-dev.h +mipsel-linux/include/linux/i2c-elektor.h +mipsel-linux/include/linux/i2c-id.h +mipsel-linux/include/linux/i2c-old.h +mipsel-linux/include/linux/i2c.h +mipsel-linux/include/linux/i2o-dev.h +mipsel-linux/include/linux/i2o.h +mipsel-linux/include/linux/ibmtr.h +mipsel-linux/include/linux/icmp.h +mipsel-linux/include/linux/icmpv6.h +mipsel-linux/include/linux/ide.h +mipsel-linux/include/linux/if.h +mipsel-linux/include/linux/if_arcnet.h +mipsel-linux/include/linux/if_arp.h +mipsel-linux/include/linux/if_bonding.h +mipsel-linux/include/linux/if_bridge.h +mipsel-linux/include/linux/if_cablemodem.h +mipsel-linux/include/linux/if_ec.h +mipsel-linux/include/linux/if_eql.h +mipsel-linux/include/linux/if_ether.h +mipsel-linux/include/linux/if_fc.h +mipsel-linux/include/linux/if_fddi.h +mipsel-linux/include/linux/if_frad.h +mipsel-linux/include/linux/if_hippi.h +mipsel-linux/include/linux/if_ltalk.h +mipsel-linux/include/linux/if_packet.h +mipsel-linux/include/linux/if_plip.h +mipsel-linux/include/linux/if_ppp.h +mipsel-linux/include/linux/if_pppox.h +mipsel-linux/include/linux/if_pppvar.h +mipsel-linux/include/linux/if_shaper.h +mipsel-linux/include/linux/if_slip.h +mipsel-linux/include/linux/if_strip.h +mipsel-linux/include/linux/if_tr.h +mipsel-linux/include/linux/if_tun.h +mipsel-linux/include/linux/if_tunnel.h +mipsel-linux/include/linux/igmp.h +mipsel-linux/include/linux/in.h +mipsel-linux/include/linux/in6.h +mipsel-linux/include/linux/in_route.h +mipsel-linux/include/linux/in_systm.h +mipsel-linux/include/linux/inet.h +mipsel-linux/include/linux/inetdevice.h +mipsel-linux/include/linux/init.h +mipsel-linux/include/linux/input.h +mipsel-linux/include/linux/interrupt.h +mipsel-linux/include/linux/iobuf.h +mipsel-linux/include/linux/ioctl.h +mipsel-linux/include/linux/ioport.h +mipsel-linux/include/linux/ip.h +mipsel-linux/include/linux/ipc.h +mipsel-linux/include/linux/ipsec.h +mipsel-linux/include/linux/ipv6.h +mipsel-linux/include/linux/ipv6_route.h +mipsel-linux/include/linux/ipx.h +mipsel-linux/include/linux/irda.h +mipsel-linux/include/linux/irq.h +mipsel-linux/include/linux/irq_cpustat.h +mipsel-linux/include/linux/isapnp.h +mipsel-linux/include/linux/isdn.h +mipsel-linux/include/linux/isdn_divertif.h +mipsel-linux/include/linux/isdn_lzscomp.h +mipsel-linux/include/linux/isdn_ppp.h +mipsel-linux/include/linux/isdnif.h +mipsel-linux/include/linux/isicom.h +mipsel-linux/include/linux/iso_fs.h +mipsel-linux/include/linux/iso_fs_i.h +mipsel-linux/include/linux/iso_fs_sb.h +mipsel-linux/include/linux/istallion.h +mipsel-linux/include/linux/ixjuser.h +mipsel-linux/include/linux/jffs.h +mipsel-linux/include/linux/joystick.h +mipsel-linux/include/linux/kbd_diacr.h +mipsel-linux/include/linux/kbd_kern.h +mipsel-linux/include/linux/kbd_ll.h +mipsel-linux/include/linux/kd.h +mipsel-linux/include/linux/kdev_t.h +mipsel-linux/include/linux/kernel.h +mipsel-linux/include/linux/kernel_stat.h +mipsel-linux/include/linux/kernelcapi.h +mipsel-linux/include/linux/keyboard.h +mipsel-linux/include/linux/kmod.h +mipsel-linux/include/linux/lapb.h +mipsel-linux/include/linux/limits.h +mipsel-linux/include/linux/linkage.h +mipsel-linux/include/linux/linux_logo.h +mipsel-linux/include/linux/list.h +mipsel-linux/include/linux/lockd/bind.h +mipsel-linux/include/linux/lockd/debug.h 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+mipsel-linux/include/linux/vt_kern.h +mipsel-linux/include/linux/wait.h +mipsel-linux/include/linux/wanpipe.h +mipsel-linux/include/linux/wanrouter.h +mipsel-linux/include/linux/watchdog.h +mipsel-linux/include/linux/wavefront.h +mipsel-linux/include/linux/wireless.h +mipsel-linux/include/linux/wrapper.h +mipsel-linux/include/linux/x25.h +mipsel-linux/include/linux/yam.h +mipsel-linux/include/linux/zftape.h +mipsel-linux/include/linux/zorro.h +@unexec rm -f mipsel-linux/include/asm +@dirrm mipsel-linux/include/asm-mips/arc +@dirrm mipsel-linux/include/asm-mips/baget +@dirrm mipsel-linux/include/asm-mips/dec +@dirrm mipsel-linux/include/asm-mips/galileo-boards +@dirrm mipsel-linux/include/asm-mips/mips-boards +@dirrm mipsel-linux/include/asm-mips/sgi +@dirrm mipsel-linux/include/asm-mips +@dirrm mipsel-linux/include/linux/byteorder +@dirrm mipsel-linux/include/linux/lockd +@dirrm mipsel-linux/include/linux/mtd +@dirrm mipsel-linux/include/linux/netfilter_ipv4 +@dirrm mipsel-linux/include/linux/netfilter_ipv6 +@dirrm mipsel-linux/include/linux/nfsd +@dirrm mipsel-linux/include/linux/raid +@dirrm mipsel-linux/include/linux/sunrpc +@dirrm mipsel-linux/include/linux +@dirrm mipsel-linux/include +@dirrm mipsel-linux