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Cheng-Lung Sung 2006-08-03 03:26:38 +00:00
parent 621b506e07
commit 3f4bff3a6e
Notes: svn2git 2021-03-31 03:12:20 +00:00 
svn path=/head/; revision=169529
1 changed files with 1 additions and 1 deletions
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cad/gplcver/Makefile
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@ -12,7 +12,7 @@ CATEGORIES= cad
MASTER_SITES= http://www.pragmatic-c.com/gpl-cver/downloads/
DISTNAME= ${PORTNAME}-${PORTVERSION:R}${PORTVERSION:E}.src
MAINTAINER= ijliao@csie.nctu.edu.tw
MAINTAINER= ijliao@FreeBSD.org
COMMENT= A Verilog HDL simulator
USE_BZIP2= yes