databases/py-pglast: fix build on powerpc* by removing outdated patch
While here, also enable on armv6, armv7 and aarch64.
This commit is contained in:
Piotr Kubaj
parent
f00cad86d8
commit
57ca7ff78b
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@ -11,8 +11,6 @@ WWW= https://github.com/lelit/pglast
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LICENSE= GPLv3+
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BROKEN_riscv64= fails to build: PostgreSQL does not have native spinlock support on this platform
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NOT_FOR_ARCHS= aarch64 armv6 armv7
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NOT_FOR_ARCHS_REASON= port/atomics/arch-<arch>.h: No such file or directory
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USES= gmake python
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USE_PYTHON= autoplist distutils
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@ -1,257 +0,0 @@
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--- libpg_query/src/postgres/include/port/atomics/arch-ppc.h.orig 2020-12-28 19:58:43 UTC
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+++ libpg_query/src/postgres/include/port/atomics/arch-ppc.h
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@@ -0,0 +1,254 @@
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+/*-------------------------------------------------------------------------
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+ *
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+ * arch-ppc.h
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+ * Atomic operations considerations specific to PowerPC
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+ *
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+ * Portions Copyright (c) 1996-2020, PostgreSQL Global Development Group
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+ * Portions Copyright (c) 1994, Regents of the University of California
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+ *
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+ * NOTES:
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+ *
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+ * src/include/port/atomics/arch-ppc.h
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+ *
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+ *-------------------------------------------------------------------------
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+ */
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+
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+#if defined(__GNUC__)
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+
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+/*
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+ * lwsync orders loads with respect to each other, and similarly with stores.
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+ * But a load can be performed before a subsequent store, so sync must be used
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+ * for a full memory barrier.
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+ */
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+#define pg_memory_barrier_impl() __asm__ __volatile__ ("sync" : : : "memory")
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+#define pg_read_barrier_impl() __asm__ __volatile__ ("lwsync" : : : "memory")
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+#define pg_write_barrier_impl() __asm__ __volatile__ ("lwsync" : : : "memory")
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+#endif
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+
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+#define PG_HAVE_ATOMIC_U32_SUPPORT
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+typedef struct pg_atomic_uint32
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+{
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+ volatile uint32 value;
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+} pg_atomic_uint32;
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+
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+/* 64bit atomics are only supported in 64bit mode */
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+#if SIZEOF_VOID_P >= 8
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+#define PG_HAVE_ATOMIC_U64_SUPPORT
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+typedef struct pg_atomic_uint64
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+{
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+ volatile uint64 value pg_attribute_aligned(8);
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+} pg_atomic_uint64;
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+
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+#endif
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+
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+/*
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+ * This mimics gcc __atomic_compare_exchange_n(..., __ATOMIC_SEQ_CST), but
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+ * code generation differs at the end. __atomic_compare_exchange_n():
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+ * 100: isync
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+ * 104: mfcr r3
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+ * 108: rlwinm r3,r3,3,31,31
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+ * 10c: bne 120 <.eb+0x10>
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+ * 110: clrldi r3,r3,63
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+ * 114: addi r1,r1,112
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+ * 118: blr
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+ * 11c: nop
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+ * 120: clrldi r3,r3,63
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+ * 124: stw r9,0(r4)
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+ * 128: addi r1,r1,112
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+ * 12c: blr
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+ *
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+ * This:
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+ * f0: isync
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+ * f4: mfcr r9
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+ * f8: rldicl. r3,r9,35,63
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+ * fc: bne 104 <.eb>
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+ * 100: stw r10,0(r4)
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+ * 104: addi r1,r1,112
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+ * 108: blr
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+ *
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+ * This implementation may or may not have materially different performance.
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+ * It's not exploiting the fact that cr0 still holds the relevant comparison
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+ * bits, set during the __asm__. One could fix that by moving more code into
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+ * the __asm__. (That would remove the freedom to eliminate dead stores when
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+ * the caller ignores "expected", but few callers do.)
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+ *
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+ * Recognizing constant "newval" would be superfluous, because there's no
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+ * immediate-operand version of stwcx.
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+ */
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+#define PG_HAVE_ATOMIC_COMPARE_EXCHANGE_U32
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+static inline bool
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+pg_atomic_compare_exchange_u32_impl(volatile pg_atomic_uint32 *ptr,
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+ uint32 *expected, uint32 newval)
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+{
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+ uint32 found;
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+ uint32 condition_register;
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+ bool ret;
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+
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+#ifdef HAVE_I_CONSTRAINT__BUILTIN_CONSTANT_P
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+ if (__builtin_constant_p(*expected) &&
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+ (int32) *expected <= PG_INT16_MAX &&
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+ (int32) *expected >= PG_INT16_MIN)
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+ __asm__ __volatile__(
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+ " sync \n"
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+ " lwarx %0,0,%5 \n"
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+ " cmpwi %0,%3 \n"
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+ " bne $+12 \n" /* branch to isync */
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+ " stwcx. %4,0,%5 \n"
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+ " bne $-16 \n" /* branch to lwarx */
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+ " isync \n"
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+ " mfcr %1 \n"
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+: "=&r"(found), "=r"(condition_register), "+m"(ptr->value)
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+: "i"(*expected), "r"(newval), "r"(&ptr->value)
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+: "memory", "cc");
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+ else
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+#endif
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+ __asm__ __volatile__(
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+ " sync \n"
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+ " lwarx %0,0,%5 \n"
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+ " cmpw %0,%3 \n"
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+ " bne $+12 \n" /* branch to isync */
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+ " stwcx. %4,0,%5 \n"
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+ " bne $-16 \n" /* branch to lwarx */
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+ " isync \n"
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+ " mfcr %1 \n"
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+: "=&r"(found), "=r"(condition_register), "+m"(ptr->value)
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+: "r"(*expected), "r"(newval), "r"(&ptr->value)
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+: "memory", "cc");
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+
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+ ret = (condition_register >> 29) & 1; /* test eq bit of cr0 */
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+ if (!ret)
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+ *expected = found;
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+ return ret;
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+}
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+
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+/*
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+ * This mirrors gcc __sync_fetch_and_add().
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+ *
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+ * Like tas(), use constraint "=&b" to avoid allocating r0.
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+ */
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+#define PG_HAVE_ATOMIC_FETCH_ADD_U32
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+static inline uint32
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+pg_atomic_fetch_add_u32_impl(volatile pg_atomic_uint32 *ptr, int32 add_)
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+{
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+ uint32 _t;
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+ uint32 res;
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+
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+#ifdef HAVE_I_CONSTRAINT__BUILTIN_CONSTANT_P
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+ if (__builtin_constant_p(add_) &&
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+ add_ <= PG_INT16_MAX && add_ >= PG_INT16_MIN)
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+ __asm__ __volatile__(
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+ " sync \n"
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+ " lwarx %1,0,%4 \n"
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+ " addi %0,%1,%3 \n"
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+ " stwcx. %0,0,%4 \n"
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+ " bne $-12 \n" /* branch to lwarx */
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+ " isync \n"
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+: "=&r"(_t), "=&b"(res), "+m"(ptr->value)
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+: "i"(add_), "r"(&ptr->value)
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+: "memory", "cc");
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+ else
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+#endif
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+ __asm__ __volatile__(
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+ " sync \n"
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+ " lwarx %1,0,%4 \n"
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+ " add %0,%1,%3 \n"
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+ " stwcx. %0,0,%4 \n"
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+ " bne $-12 \n" /* branch to lwarx */
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+ " isync \n"
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+: "=&r"(_t), "=&r"(res), "+m"(ptr->value)
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+: "r"(add_), "r"(&ptr->value)
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+: "memory", "cc");
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+
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+ return res;
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+}
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+
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+#ifdef PG_HAVE_ATOMIC_U64_SUPPORT
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+
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+#define PG_HAVE_ATOMIC_COMPARE_EXCHANGE_U64
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+static inline bool
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+pg_atomic_compare_exchange_u64_impl(volatile pg_atomic_uint64 *ptr,
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+ uint64 *expected, uint64 newval)
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+{
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+ uint64 found;
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+ uint32 condition_register;
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+ bool ret;
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+
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+ /* Like u32, but s/lwarx/ldarx/; s/stwcx/stdcx/; s/cmpw/cmpd/ */
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+#ifdef HAVE_I_CONSTRAINT__BUILTIN_CONSTANT_P
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+ if (__builtin_constant_p(*expected) &&
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+ (int64) *expected <= PG_INT16_MAX &&
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+ (int64) *expected >= PG_INT16_MIN)
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+ __asm__ __volatile__(
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+ " sync \n"
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+ " ldarx %0,0,%5 \n"
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+ " cmpdi %0,%3 \n"
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+ " bne $+12 \n" /* branch to isync */
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+ " stdcx. %4,0,%5 \n"
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+ " bne $-16 \n" /* branch to ldarx */
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+ " isync \n"
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+ " mfcr %1 \n"
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+: "=&r"(found), "=r"(condition_register), "+m"(ptr->value)
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+: "i"(*expected), "r"(newval), "r"(&ptr->value)
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+: "memory", "cc");
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+ else
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+#endif
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+ __asm__ __volatile__(
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+ " sync \n"
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+ " ldarx %0,0,%5 \n"
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+ " cmpd %0,%3 \n"
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+ " bne $+12 \n" /* branch to isync */
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+ " stdcx. %4,0,%5 \n"
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+ " bne $-16 \n" /* branch to ldarx */
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+ " isync \n"
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+ " mfcr %1 \n"
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+: "=&r"(found), "=r"(condition_register), "+m"(ptr->value)
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+: "r"(*expected), "r"(newval), "r"(&ptr->value)
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+: "memory", "cc");
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+
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+ ret = (condition_register >> 29) & 1; /* test eq bit of cr0 */
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+ if (!ret)
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+ *expected = found;
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+ return ret;
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+}
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+
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+#define PG_HAVE_ATOMIC_FETCH_ADD_U64
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+static inline uint64
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+pg_atomic_fetch_add_u64_impl(volatile pg_atomic_uint64 *ptr, int64 add_)
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+{
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+ uint64 _t;
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+ uint64 res;
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+
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+ /* Like u32, but s/lwarx/ldarx/; s/stwcx/stdcx/ */
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+#ifdef HAVE_I_CONSTRAINT__BUILTIN_CONSTANT_P
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+ if (__builtin_constant_p(add_) &&
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+ add_ <= PG_INT16_MAX && add_ >= PG_INT16_MIN)
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+ __asm__ __volatile__(
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+ " sync \n"
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+ " ldarx %1,0,%4 \n"
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+ " addi %0,%1,%3 \n"
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+ " stdcx. %0,0,%4 \n"
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+ " bne $-12 \n" /* branch to ldarx */
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+ " isync \n"
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+: "=&r"(_t), "=&b"(res), "+m"(ptr->value)
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+: "i"(add_), "r"(&ptr->value)
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+: "memory", "cc");
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+ else
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+#endif
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+ __asm__ __volatile__(
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+ " sync \n"
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+ " ldarx %1,0,%4 \n"
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+ " add %0,%1,%3 \n"
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+ " stdcx. %0,0,%4 \n"
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+ " bne $-12 \n" /* branch to ldarx */
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+ " isync \n"
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+: "=&r"(_t), "=&r"(res), "+m"(ptr->value)
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+: "r"(add_), "r"(&ptr->value)
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+: "memory", "cc");
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+
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+ return res;
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+}
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+
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+#endif /* PG_HAVE_ATOMIC_U64_SUPPORT */
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+
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+/* per architecture manual doubleword accesses have single copy atomicity */
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+#define PG_HAVE_8BYTE_SINGLE_COPY_ATOMICITY
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