Fix compile on -CURRENT. Linker is still broken due to broken *mk.
This commit is contained in:
Joe Marcus Clarke
parent
fea9346f1d
commit
6d374500ba
Notes:
svn2git
2021-03-31 03:12:20 +00:00
svn path=/head/; revision=85179
1 changed files with 636 additions and 0 deletions
636
math/libgmp-freebsd/files/patch-contrib_longlong.h
Normal file
636
math/libgmp-freebsd/files/patch-contrib_longlong.h
Normal file
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@ -0,0 +1,636 @@
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--- contrib/longlong.h.orig Sat Jul 19 02:31:07 2003
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+++ contrib/longlong.h Sat Jul 19 02:31:09 2003
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@@ -106,8 +106,8 @@
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#if (defined (__a29k__) || defined (_AM29K)) && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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- __asm__ ("add %1,%4,%5
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- addc %0,%2,%3" \
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+ __asm__ ("add %1,%4,%5 \n\t" \
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+ "addc %0,%2,%3" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "%r" ((USItype)(ah)), \
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@@ -115,8 +115,8 @@
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"%r" ((USItype)(al)), \
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"rI" ((USItype)(bl)))
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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- __asm__ ("sub %1,%4,%5
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- subc %0,%2,%3" \
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+ __asm__ ("sub %1,%4,%5 \n\t" \
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+ "subc %0,%2,%3" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "r" ((USItype)(ah)), \
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@@ -173,8 +173,8 @@
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#if defined (__arm__) && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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- __asm__ ("adds %1, %4, %5
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- adc %0, %2, %3" \
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+ __asm__ ("adds %1, %4, %5 \n\t" \
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+ "adc %0, %2, %3" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "%r" ((USItype)(ah)), \
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@@ -182,8 +182,8 @@
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"%r" ((USItype)(al)), \
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"rI" ((USItype)(bl)))
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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- __asm__ ("subs %1, %4, %5
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- sbc %0, %2, %3" \
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+ __asm__ ("subs %1, %4, %5 \n\t" \
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+ "sbc %0, %2, %3" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "r" ((USItype)(ah)), \
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@@ -191,19 +191,19 @@
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"r" ((USItype)(al)), \
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"rI" ((USItype)(bl)))
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#define umul_ppmm(xh, xl, a, b) \
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- __asm__ ("%@ Inlined umul_ppmm
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- mov %|r0, %2, lsr #16
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- mov %|r2, %3, lsr #16
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- bic %|r1, %2, %|r0, lsl #16
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- bic %|r2, %3, %|r2, lsl #16
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- mul %1, %|r1, %|r2
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- mul %|r2, %|r0, %|r2
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- mul %|r1, %0, %|r1
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- mul %0, %|r0, %0
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- adds %|r1, %|r2, %|r1
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- addcs %0, %0, #65536
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- adds %1, %1, %|r1, lsl #16
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- adc %0, %0, %|r1, lsr #16" \
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+ __asm__ ("%@ Inlined umul_ppmm \n\t" \
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+ "mov %|r0, %2, lsr #16 \n\t" \
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+ "mov %|r2, %3, lsr #16 \n\t" \
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+ "bic %|r1, %2, %|r0, lsl #16 \n\t" \
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+ "bic %|r2, %3, %|r2, lsl #16 \n\t" \
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+ "mul %1, %|r1, %|r2 \n\t" \
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+ "mul %|r2, %|r0, %|r2 \n\t" \
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+ "mul %|r1, %0, %|r1 \n\t" \
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+ "mul %0, %|r0, %0 \n\t" \
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+ "adds %|r1, %|r2, %|r1 \n\t" \
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+ "addcs %0, %0, #65536 \n\t" \
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+ "adds %1, %1, %|r1, lsl #16 \n\t" \
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+ "adc %0, %0, %|r1, lsr #16 \n\t" \
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: "=&r" ((USItype)(xh)), \
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"=r" ((USItype)(xl)) \
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: "r" ((USItype)(a)), \
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@@ -243,8 +243,8 @@
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#if defined (__gmicro__) && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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- __asm__ ("add.w %5,%1
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- addx %3,%0" \
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+ __asm__ ("add.w %5,%1 \n\t" \
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+ "addx %3,%0" \
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: "=g" ((USItype)(sh)), \
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"=&g" ((USItype)(sl)) \
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: "%0" ((USItype)(ah)), \
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@@ -252,8 +252,8 @@
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"%1" ((USItype)(al)), \
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"g" ((USItype)(bl)))
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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- __asm__ ("sub.w %5,%1
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- subx %3,%0" \
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+ __asm__ ("sub.w %5,%1 \n\t" \
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+ "subx %3,%0" \
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: "=g" ((USItype)(sh)), \
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"=&g" ((USItype)(sl)) \
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: "0" ((USItype)(ah)), \
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@@ -282,8 +282,8 @@
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#if defined (__hppa) && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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- __asm__ ("add %4,%5,%1
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- addc %2,%3,%0" \
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+ __asm__ ("add %4,%5,%1 \n\t" \
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+ "addc %2,%3,%0" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "%rM" ((USItype)(ah)), \
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@@ -291,8 +291,8 @@
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"%rM" ((USItype)(al)), \
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"rM" ((USItype)(bl)))
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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- __asm__ ("sub %4,%5,%1
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- subb %2,%3,%0" \
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+ __asm__ ("sub %4,%5,%1 \n\t" \
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+ "subb %2,%3,%0" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "rM" ((USItype)(ah)), \
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@@ -330,22 +330,22 @@
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do { \
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USItype __tmp; \
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__asm__ ( \
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- "ldi 1,%0
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- extru,= %1,15,16,%%r0 ; Bits 31..16 zero?
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- extru,tr %1,15,16,%1 ; No. Shift down, skip add.
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- ldo 16(%0),%0 ; Yes. Perform add.
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- extru,= %1,23,8,%%r0 ; Bits 15..8 zero?
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- extru,tr %1,23,8,%1 ; No. Shift down, skip add.
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- ldo 8(%0),%0 ; Yes. Perform add.
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- extru,= %1,27,4,%%r0 ; Bits 7..4 zero?
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- extru,tr %1,27,4,%1 ; No. Shift down, skip add.
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- ldo 4(%0),%0 ; Yes. Perform add.
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- extru,= %1,29,2,%%r0 ; Bits 3..2 zero?
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- extru,tr %1,29,2,%1 ; No. Shift down, skip add.
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- ldo 2(%0),%0 ; Yes. Perform add.
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- extru %1,30,1,%1 ; Extract bit 1.
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- sub %0,%1,%0 ; Subtract it.
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- " : "=r" (count), "=r" (__tmp) : "1" (x)); \
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+ "ldi 1,%0 \n\t" \
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+ "extru,= %1,15,16,%%r0 ; Bits 31..16 zero? \n\t"\
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+ "extru,tr %1,15,16,%1 ; No. Shift down, skip add. \n\t"\
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+ "ldo 16(%0),%0 ; Yes. Perform add. \n\t"\
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+ "extru,= %1,23,8,%%r0 ; Bits 15..8 zero? \n\t"\
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+ "extru,tr %1,23,8,%1 ; No. Shift down, skip add. \n\t"\
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+ "ldo 8(%0),%0 ; Yes. Perform add. \n\t"\
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+ "extru,= %1,27,4,%%r0 ; Bits 7..4 zero? \n\t"\
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+ "extru,tr %1,27,4,%1 ; No. Shift down, skip add. \n\t"\
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+ "ldo 4(%0),%0 ; Yes. Perform add. \n\t"\
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+ "extru,= %1,29,2,%%r0 ; Bits 3..2 zero? \n\t"\
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+ "extru,tr %1,29,2,%1 ; No. Shift down, skip add. \n\t"\
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+ "ldo 2(%0),%0 ; Yes. Perform add. \n\t"\
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+ "extru %1,30,1,%1 ; Extract bit 1. \n\t"\
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+ "sub %0,%1,%0 ; Subtract it."\
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+ : "=r" (count), "=r" (__tmp) : "1" (x)); \
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} while (0)
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#endif /* hppa */
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@@ -392,8 +392,8 @@
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#if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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- __asm__ ("addl %5,%1
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- adcl %3,%0" \
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+ __asm__ ("addl %5,%1 \n\t" \
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+ "adcl %3,%0" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "%0" ((USItype)(ah)), \
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@@ -401,8 +401,8 @@
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"%1" ((USItype)(al)), \
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"g" ((USItype)(bl)))
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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- __asm__ ("subl %5,%1
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- sbbl %3,%0" \
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+ __asm__ ("subl %5,%1 \n\t" \
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+ "sbbl %3,%0" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "0" ((USItype)(ah)), \
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@@ -514,8 +514,8 @@
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#if (defined (__mc68000__) || defined (__mc68020__) || defined (__NeXT__) || defined(mc68020)) && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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- __asm__ ("add%.l %5,%1
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- addx%.l %3,%0" \
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+ __asm__ ("add%.l %5,%1 \n\t" \
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+ "addx%.l %3,%0" \
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: "=d" ((USItype)(sh)), \
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"=&d" ((USItype)(sl)) \
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: "%0" ((USItype)(ah)), \
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@@ -523,8 +523,8 @@
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"%1" ((USItype)(al)), \
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"g" ((USItype)(bl)))
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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- __asm__ ("sub%.l %5,%1
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- subx%.l %3,%0" \
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+ __asm__ ("sub%.l %5,%1 \n\t" \
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+ "subx%.l %3,%0" \
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: "=d" ((USItype)(sh)), \
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"=&d" ((USItype)(sl)) \
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: "0" ((USItype)(ah)), \
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@@ -562,28 +562,28 @@
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#else /* not mc68020 */
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#define umul_ppmm(xh, xl, a, b) \
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do { USItype __umul_tmp1, __umul_tmp2; \
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- __asm__ ("| Inlined umul_ppmm
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- move%.l %5,%3
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- move%.l %2,%0
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- move%.w %3,%1
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- swap %3
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- swap %0
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- mulu %2,%1
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- mulu %3,%0
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- mulu %2,%3
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- swap %2
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- mulu %5,%2
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- add%.l %3,%2
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- jcc 1f
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- add%.l %#0x10000,%0
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-1: move%.l %2,%3
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- clr%.w %2
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- swap %2
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- swap %3
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- clr%.w %3
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- add%.l %3,%1
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- addx%.l %2,%0
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- | End inlined umul_ppmm" \
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+ __asm__ ("| Inlined umul_ppmm \n\t" \
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+ "move%.l %5,%3 \n\t" \
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+ "move%.l %2,%0 \n\t" \
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+ "move%.w %3,%1 \n\t" \
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+ "swap %3 \n\t" \
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+ "swap %0 \n\t" \
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+ "mulu %2,%1 \n\t" \
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+ "mulu %3,%0 \n\t" \
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+ "mulu %2,%3 \n\t" \
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+ "swap %2 \n\t" \
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+ "mulu %5,%2 \n\t" \
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+ "add%.l %3,%2 \n\t" \
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+ "jcc 1f \n\t" \
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+ "add%.l %#0x10000,%0 \n" \
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+"1: move%.l %2,%3 \n\t" \
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+ "clr%.w %2 \n\t" \
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+ "swap %2 \n\t" \
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+ "swap %3 \n\t" \
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+ "clr%.w %3 \n\t" \
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+ "add%.l %3,%1 \n\t" \
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+ "addx%.l %2,%0 \n\t" \
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+ "| End inlined umul_ppmm" \
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: "=&d" ((USItype)(xh)), "=&d" ((USItype)(xl)), \
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"=d" (__umul_tmp1), "=&d" (__umul_tmp2) \
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: "%2" ((USItype)(a)), "d" ((USItype)(b))); \
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@@ -595,8 +595,8 @@
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#if defined (__m88000__) && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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- __asm__ ("addu.co %1,%r4,%r5
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- addu.ci %0,%r2,%r3" \
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+ __asm__ ("addu.co %1,%r4,%r5 \n\t" \
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+ "addu.ci %0,%r2,%r3" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "%rJ" ((USItype)(ah)), \
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@@ -604,8 +604,8 @@
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"%rJ" ((USItype)(al)), \
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"rJ" ((USItype)(bl)))
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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- __asm__ ("subu.co %1,%r4,%r5
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- subu.ci %0,%r2,%r3" \
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+ __asm__ ("subu.co %1,%r4,%r5 \n\t" \
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+ "subu.ci %0,%r2,%r3" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "rJ" ((USItype)(ah)), \
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@@ -663,9 +663,9 @@
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"d" ((USItype)(v)))
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#else
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#define umul_ppmm(w1, w0, u, v) \
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- __asm__ ("multu %2,%3
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- mflo %0
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- mfhi %1" \
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+ __asm__ ("multu %2,%3 \n\t" \
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+ "mflo %0 \n\t" \
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+ "mfhi %1" \
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: "=d" ((USItype)(w0)), \
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"=d" ((USItype)(w1)) \
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: "d" ((USItype)(u)), \
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@@ -685,9 +685,9 @@
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"d" ((UDItype)(v)))
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#else
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#define umul_ppmm(w1, w0, u, v) \
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- __asm__ ("dmultu %2,%3
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- mflo %0
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- mfhi %1" \
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+ __asm__ ("dmultu %2,%3 \n\t" \
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+ "mflo %0 \n\t" \
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+ "mfhi %1" \
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: "=d" ((UDItype)(w0)), \
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"=d" ((UDItype)(w1)) \
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: "d" ((UDItype)(u)), \
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@@ -855,8 +855,8 @@
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#if defined (__pyr__) && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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- __asm__ ("addw %5,%1
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- addwc %3,%0" \
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+ __asm__ ("addw %5,%1 \n\t" \
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+ "addwc %3,%0" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "%0" ((USItype)(ah)), \
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@@ -864,8 +864,8 @@
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"%1" ((USItype)(al)), \
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"g" ((USItype)(bl)))
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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- __asm__ ("subw %5,%1
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- subwb %3,%0" \
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+ __asm__ ("subw %5,%1 \n\t" \
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+ "subwb %3,%0" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "0" ((USItype)(ah)), \
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@@ -877,8 +877,8 @@
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({union {UDItype __ll; \
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struct {USItype __h, __l;} __i; \
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} __xx; \
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- __asm__ ("movw %1,%R0
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- uemul %2,%0" \
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+ __asm__ ("movw %1,%R0 \n\t" \
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+ "uemul %2,%0" \
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: "=&r" (__xx.__ll) \
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: "g" ((USItype) (u)), \
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"g" ((USItype)(v))); \
|
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@@ -887,8 +887,8 @@
|
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|
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#if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
|
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- __asm__ ("a %1,%5
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- ae %0,%3" \
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+ __asm__ ("a %1,%5 \n\t" \
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+ "ae %0,%3" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
|
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: "%0" ((USItype)(ah)), \
|
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@@ -896,8 +896,8 @@
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"%1" ((USItype)(al)), \
|
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"r" ((USItype)(bl)))
|
||||
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
|
||||
- __asm__ ("s %1,%5
|
||||
- se %0,%3" \
|
||||
+ __asm__ ("s %1,%5 \n\t" \
|
||||
+ "se %0,%3" \
|
||||
: "=r" ((USItype)(sh)), \
|
||||
"=&r" ((USItype)(sl)) \
|
||||
: "0" ((USItype)(ah)), \
|
||||
@@ -908,26 +908,26 @@
|
||||
do { \
|
||||
USItype __m0 = (m0), __m1 = (m1); \
|
||||
__asm__ ( \
|
||||
- "s r2,r2
|
||||
- mts r10,%2
|
||||
- m r2,%3
|
||||
- m r2,%3
|
||||
- m r2,%3
|
||||
- m r2,%3
|
||||
- m r2,%3
|
||||
- m r2,%3
|
||||
- m r2,%3
|
||||
- m r2,%3
|
||||
- m r2,%3
|
||||
- m r2,%3
|
||||
- m r2,%3
|
||||
- m r2,%3
|
||||
- m r2,%3
|
||||
- m r2,%3
|
||||
- m r2,%3
|
||||
- m r2,%3
|
||||
- cas %0,r2,r0
|
||||
- mfs r10,%1" \
|
||||
+ "\t s r2,r2 \n\t" \
|
||||
+ "mts r10,%2 \n\t" \
|
||||
+ "m r2,%3 \n\t" \
|
||||
+ "m r2,%3 \n\t" \
|
||||
+ "m r2,%3 \n\t" \
|
||||
+ "m r2,%3 \n\t" \
|
||||
+ "m r2,%3 \n\t" \
|
||||
+ "m r2,%3 \n\t" \
|
||||
+ "m r2,%3 \n\t" \
|
||||
+ "m r2,%3 \n\t" \
|
||||
+ "m r2,%3 \n\t" \
|
||||
+ "m r2,%3 \n\t" \
|
||||
+ "m r2,%3 \n\t" \
|
||||
+ "m r2,%3 \n\t" \
|
||||
+ "m r2,%3 \n\t" \
|
||||
+ "m r2,%3 \n\t" \
|
||||
+ "m r2,%3 \n\t" \
|
||||
+ "m r2,%3 \n\t" \
|
||||
+ "cas %0,r2,r0 \n\t" \
|
||||
+ "mfs r10,%1" \
|
||||
: "=r" ((USItype)(ph)), \
|
||||
"=r" ((USItype)(pl)) \
|
||||
: "%r" (__m0), \
|
||||
@@ -957,9 +957,9 @@
|
||||
#if defined (__sh2__) && W_TYPE_SIZE == 32
|
||||
#define umul_ppmm(w1, w0, u, v) \
|
||||
__asm__ ( \
|
||||
- "dmulu.l %2,%3
|
||||
- sts macl,%1
|
||||
- sts mach,%0" \
|
||||
+ "dmulu.l %2,%3 \n\t" \
|
||||
+ "sts macl,%1 \n\t" \
|
||||
+ "sts mach,%0" \
|
||||
: "=r" ((USItype)(w1)), \
|
||||
"=r" ((USItype)(w0)) \
|
||||
: "r" ((USItype)(u)), \
|
||||
@@ -970,8 +970,8 @@
|
||||
|
||||
#if defined (__sparc__) && W_TYPE_SIZE == 32
|
||||
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
|
||||
- __asm__ ("addcc %r4,%5,%1
|
||||
- addx %r2,%3,%0" \
|
||||
+ __asm__ ("addcc %r4,%5,%1 \n\t" \
|
||||
+ "addx %r2,%3,%0 \n\t" \
|
||||
: "=r" ((USItype)(sh)), \
|
||||
"=&r" ((USItype)(sl)) \
|
||||
: "%rJ" ((USItype)(ah)), \
|
||||
@@ -980,8 +980,8 @@
|
||||
"rI" ((USItype)(bl)) \
|
||||
__CLOBBER_CC)
|
||||
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
|
||||
- __asm__ ("subcc %r4,%5,%1
|
||||
- subx %r2,%3,%0" \
|
||||
+ __asm__ ("subcc %r4,%5,%1 \n\t" \
|
||||
+ "subx %r2,%3,%0" \
|
||||
: "=r" ((USItype)(sh)), \
|
||||
"=&r" ((USItype)(sl)) \
|
||||
: "rJ" ((USItype)(ah)), \
|
||||
@@ -1027,45 +1027,45 @@
|
||||
"r" ((USItype)(v)))
|
||||
#define UMUL_TIME 5
|
||||
#define udiv_qrnnd(q, r, n1, n0, d) \
|
||||
- __asm__ ("! Inlined udiv_qrnnd
|
||||
- wr %%g0,%2,%%y ! Not a delayed write for sparclite
|
||||
- tst %%g0
|
||||
- divscc %3,%4,%%g1
|
||||
- divscc %%g1,%4,%%g1
|
||||
- divscc %%g1,%4,%%g1
|
||||
- divscc %%g1,%4,%%g1
|
||||
- divscc %%g1,%4,%%g1
|
||||
- divscc %%g1,%4,%%g1
|
||||
- divscc %%g1,%4,%%g1
|
||||
- divscc %%g1,%4,%%g1
|
||||
- divscc %%g1,%4,%%g1
|
||||
- divscc %%g1,%4,%%g1
|
||||
- divscc %%g1,%4,%%g1
|
||||
- divscc %%g1,%4,%%g1
|
||||
- divscc %%g1,%4,%%g1
|
||||
- divscc %%g1,%4,%%g1
|
||||
- divscc %%g1,%4,%%g1
|
||||
- divscc %%g1,%4,%%g1
|
||||
- divscc %%g1,%4,%%g1
|
||||
- divscc %%g1,%4,%%g1
|
||||
- divscc %%g1,%4,%%g1
|
||||
- divscc %%g1,%4,%%g1
|
||||
- divscc %%g1,%4,%%g1
|
||||
- divscc %%g1,%4,%%g1
|
||||
- divscc %%g1,%4,%%g1
|
||||
- divscc %%g1,%4,%%g1
|
||||
- divscc %%g1,%4,%%g1
|
||||
- divscc %%g1,%4,%%g1
|
||||
- divscc %%g1,%4,%%g1
|
||||
- divscc %%g1,%4,%%g1
|
||||
- divscc %%g1,%4,%%g1
|
||||
- divscc %%g1,%4,%%g1
|
||||
- divscc %%g1,%4,%%g1
|
||||
- divscc %%g1,%4,%0
|
||||
- rd %%y,%1
|
||||
- bl,a 1f
|
||||
- add %1,%4,%1
|
||||
-1: ! End of inline udiv_qrnnd" \
|
||||
+ __asm__ ("! Inlined udiv_qrnnd \n\t" \
|
||||
+ "wr %%g0,%2,%%y ! Not a delayed write for sparclite \n\t" \
|
||||
+ "tst %%g0 \n\t" \
|
||||
+ "divscc %3,%4,%%g1 \n\t" \
|
||||
+ "divscc %%g1,%4,%%g1 \n\t" \
|
||||
+ "divscc %%g1,%4,%%g1 \n\t" \
|
||||
+ "divscc %%g1,%4,%%g1 \n\t" \
|
||||
+ "divscc %%g1,%4,%%g1 \n\t" \
|
||||
+ "divscc %%g1,%4,%%g1 \n\t" \
|
||||
+ "divscc %%g1,%4,%%g1 \n\t" \
|
||||
+ "divscc %%g1,%4,%%g1 \n\t" \
|
||||
+ "divscc %%g1,%4,%%g1 \n\t" \
|
||||
+ "divscc %%g1,%4,%%g1 \n\t" \
|
||||
+ "divscc %%g1,%4,%%g1 \n\t" \
|
||||
+ "divscc %%g1,%4,%%g1 \n\t" \
|
||||
+ "divscc %%g1,%4,%%g1 \n\t" \
|
||||
+ "divscc %%g1,%4,%%g1 \n\t" \
|
||||
+ "divscc %%g1,%4,%%g1 \n\t" \
|
||||
+ "divscc %%g1,%4,%%g1 \n\t" \
|
||||
+ "divscc %%g1,%4,%%g1 \n\t" \
|
||||
+ "divscc %%g1,%4,%%g1 \n\t" \
|
||||
+ "divscc %%g1,%4,%%g1 \n\t" \
|
||||
+ "divscc %%g1,%4,%%g1 \n\t" \
|
||||
+ "divscc %%g1,%4,%%g1 \n\t" \
|
||||
+ "divscc %%g1,%4,%%g1 \n\t" \
|
||||
+ "divscc %%g1,%4,%%g1 \n\t" \
|
||||
+ "divscc %%g1,%4,%%g1 \n\t" \
|
||||
+ "divscc %%g1,%4,%%g1 \n\t" \
|
||||
+ "divscc %%g1,%4,%%g1 \n\t" \
|
||||
+ "divscc %%g1,%4,%%g1 \n\t" \
|
||||
+ "divscc %%g1,%4,%%g1 \n\t" \
|
||||
+ "divscc %%g1,%4,%%g1 \n\t" \
|
||||
+ "divscc %%g1,%4,%%g1 \n\t" \
|
||||
+ "divscc %%g1,%4,%%g1 \n\t" \
|
||||
+ "divscc %%g1,%4,%0 \n\t" \
|
||||
+ "rd %%y,%1 \n\t" \
|
||||
+ "bl,a 1f \n\t" \
|
||||
+ "add %1,%4,%1 \n" \
|
||||
+"1: ! End of inline udiv_qrnnd" \
|
||||
: "=r" ((USItype)(q)), \
|
||||
"=r" ((USItype)(r)) \
|
||||
: "r" ((USItype)(n1)), \
|
||||
@@ -1085,46 +1085,46 @@
|
||||
/* Default to sparc v7 versions of umul_ppmm and udiv_qrnnd. */
|
||||
#ifndef umul_ppmm
|
||||
#define umul_ppmm(w1, w0, u, v) \
|
||||
- __asm__ ("! Inlined umul_ppmm
|
||||
- wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr
|
||||
- sra %3,31,%%g2 ! Don't move this insn
|
||||
- and %2,%%g2,%%g2 ! Don't move this insn
|
||||
- andcc %%g0,0,%%g1 ! Don't move this insn
|
||||
- mulscc %%g1,%3,%%g1
|
||||
- mulscc %%g1,%3,%%g1
|
||||
- mulscc %%g1,%3,%%g1
|
||||
- mulscc %%g1,%3,%%g1
|
||||
- mulscc %%g1,%3,%%g1
|
||||
- mulscc %%g1,%3,%%g1
|
||||
- mulscc %%g1,%3,%%g1
|
||||
- mulscc %%g1,%3,%%g1
|
||||
- mulscc %%g1,%3,%%g1
|
||||
- mulscc %%g1,%3,%%g1
|
||||
- mulscc %%g1,%3,%%g1
|
||||
- mulscc %%g1,%3,%%g1
|
||||
- mulscc %%g1,%3,%%g1
|
||||
- mulscc %%g1,%3,%%g1
|
||||
- mulscc %%g1,%3,%%g1
|
||||
- mulscc %%g1,%3,%%g1
|
||||
- mulscc %%g1,%3,%%g1
|
||||
- mulscc %%g1,%3,%%g1
|
||||
- mulscc %%g1,%3,%%g1
|
||||
- mulscc %%g1,%3,%%g1
|
||||
- mulscc %%g1,%3,%%g1
|
||||
- mulscc %%g1,%3,%%g1
|
||||
- mulscc %%g1,%3,%%g1
|
||||
- mulscc %%g1,%3,%%g1
|
||||
- mulscc %%g1,%3,%%g1
|
||||
- mulscc %%g1,%3,%%g1
|
||||
- mulscc %%g1,%3,%%g1
|
||||
- mulscc %%g1,%3,%%g1
|
||||
- mulscc %%g1,%3,%%g1
|
||||
- mulscc %%g1,%3,%%g1
|
||||
- mulscc %%g1,%3,%%g1
|
||||
- mulscc %%g1,%3,%%g1
|
||||
- mulscc %%g1,0,%%g1
|
||||
- add %%g1,%%g2,%0
|
||||
- rd %%y,%1" \
|
||||
+ __asm__ ("! Inlined umul_ppmm \n\t" \
|
||||
+ "wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr \n\t" \
|
||||
+ "sra %3,31,%%g2 ! Don't move this insn \n\t" \
|
||||
+ "and %2,%%g2,%%g2 ! Don't move this insn \n\t" \
|
||||
+ "andcc %%g0,0,%%g1 ! Don't move this insn \n\t" \
|
||||
+ "mulscc %%g1,%3,%%g1 \n\t" \
|
||||
+ "mulscc %%g1,%3,%%g1 \n\t" \
|
||||
+ "mulscc %%g1,%3,%%g1 \n\t" \
|
||||
+ "mulscc %%g1,%3,%%g1 \n\t" \
|
||||
+ "mulscc %%g1,%3,%%g1 \n\t" \
|
||||
+ "mulscc %%g1,%3,%%g1 \n\t" \
|
||||
+ "mulscc %%g1,%3,%%g1 \n\t" \
|
||||
+ "mulscc %%g1,%3,%%g1 \n\t" \
|
||||
+ "mulscc %%g1,%3,%%g1 \n\t" \
|
||||
+ "mulscc %%g1,%3,%%g1 \n\t" \
|
||||
+ "mulscc %%g1,%3,%%g1 \n\t" \
|
||||
+ "mulscc %%g1,%3,%%g1 \n\t" \
|
||||
+ "mulscc %%g1,%3,%%g1 \n\t" \
|
||||
+ "mulscc %%g1,%3,%%g1 \n\t" \
|
||||
+ "mulscc %%g1,%3,%%g1 \n\t" \
|
||||
+ "mulscc %%g1,%3,%%g1 \n\t" \
|
||||
+ "mulscc %%g1,%3,%%g1 \n\t" \
|
||||
+ "mulscc %%g1,%3,%%g1 \n\t" \
|
||||
+ "mulscc %%g1,%3,%%g1 \n\t" \
|
||||
+ "mulscc %%g1,%3,%%g1 \n\t" \
|
||||
+ "mulscc %%g1,%3,%%g1 \n\t" \
|
||||
+ "mulscc %%g1,%3,%%g1 \n\t" \
|
||||
+ "mulscc %%g1,%3,%%g1 \n\t" \
|
||||
+ "mulscc %%g1,%3,%%g1 \n\t" \
|
||||
+ "mulscc %%g1,%3,%%g1 \n\t" \
|
||||
+ "mulscc %%g1,%3,%%g1 \n\t" \
|
||||
+ "mulscc %%g1,%3,%%g1 \n\t" \
|
||||
+ "mulscc %%g1,%3,%%g1 \n\t" \
|
||||
+ "mulscc %%g1,%3,%%g1 \n\t" \
|
||||
+ "mulscc %%g1,%3,%%g1 \n\t" \
|
||||
+ "mulscc %%g1,%3,%%g1 \n\t" \
|
||||
+ "mulscc %%g1,%3,%%g1 \n\t" \
|
||||
+ "mulscc %%g1,0,%%g1 \n\t" \
|
||||
+ "add %%g1,%%g2,%0 \n\t" \
|
||||
+ "rd %%y,%1" \
|
||||
: "=r" ((USItype)(w1)), \
|
||||
"=r" ((USItype)(w0)) \
|
||||
: "%rI" ((USItype)(u)), \
|
||||
@@ -1147,8 +1147,8 @@
|
||||
|
||||
#if defined (__vax__) && W_TYPE_SIZE == 32
|
||||
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
|
||||
- __asm__ ("addl2 %5,%1
|
||||
- adwc %3,%0" \
|
||||
+ __asm__ ("addl2 %5,%1 \n\t" \
|
||||
+ "adwc %3,%0" \
|
||||
: "=g" ((USItype)(sh)), \
|
||||
"=&g" ((USItype)(sl)) \
|
||||
: "%0" ((USItype)(ah)), \
|
||||
@@ -1156,8 +1156,8 @@
|
||||
"%1" ((USItype)(al)), \
|
||||
"g" ((USItype)(bl)))
|
||||
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
|
||||
- __asm__ ("subl2 %5,%1
|
||||
- sbwc %3,%0" \
|
||||
+ __asm__ ("subl2 %5,%1 \n\t" \
|
||||
+ "sbwc %3,%0" \
|
||||
: "=g" ((USItype)(sh)), \
|
||||
"=&g" ((USItype)(sl)) \
|
||||
: "0" ((USItype)(ah)), \
|
||||
Loading…
Reference in a new issue