audio/sfizz: fix build on powerpc* and probably also riscv64

1. Apply ee3d91cf13
2. Use abseil patch from other ports.
3. Run the strip command meant obviously only for amd64 only on amd64.

audio/sfizz/Makefile

@@ -13,7 +13,6 @@ BROKEN_aarch64=	fails to compile: fatal error: 'linux/auxvec.h' file not found,
 BROKEN_armv6=	fails to compile: src/external/cpuid/src/cpuid/detail/init_linux_gcc_arm.hpp: unknown type name 'Elf32_auxv_t', see https://github.com/sfztools/sfizz/issues/1116
 BROKEN_armv7=	fails to compile: src/external/cpuid/src/cpuid/detail/init_linux_gcc_arm.hpp: unknown type name 'Elf32_auxv_t', see https://github.com/sfztools/sfizz/issues/1116
 BROKEN_i386=	fails to compile: unknown type name 'Elf64_Auxinfo', see https://github.com/sfztools/sfizz/issues/1110
-BROKEN_riscv64=	fails to compile: src/external/atomic_queue/defs.h:45:2: Unknown CPU architecture
 
 LIB_DEPENDS=	libsndfile.so:audio/libsndfile
 RUN_DEPENDS=	zenity:x11/zenity
@@ -78,7 +77,9 @@ post-install-LV2-on:
 		${STAGEDIR}${PREFIX}/lib/lv2/sfizz.lv2/Contents/Binary/sfizz_ui.so
 
 post-install-VST-on:
+.if ${ARCH} == amd64
 	@${STRIP_CMD} \
 		${STAGEDIR}${PREFIX}/lib/vst3/sfizz.vst3/Contents/x86_64-linux/sfizz.so
+.endif
 
 .include <bsd.port.post.mk>

audio/sfizz/files/patch-external_abseil-cpp_absl_base_internal_unscaledcycleclock.cc

@@ -0,0 +1,13 @@
+--- external/abseil-cpp/absl/base/internal/unscaledcycleclock.cc.orig	2023-02-07 02:19:11 UTC
++++ external/abseil-cpp/absl/base/internal/unscaledcycleclock.cc
+@@ -24,8 +24,9 @@
+ #ifdef __GLIBC__
+ #include <sys/platform/ppc.h>
+ #elif defined(__FreeBSD__)
+-#include <sys/sysctl.h>
++#include "absl/base/call_once.h"
+ #include <sys/types.h>
++#include <sys/sysctl.h>
+ #endif
+ #endif
+ 

audio/sfizz/files/patch-external_atomic__queue_include_atomic__queue_defs.h

@@ -0,0 +1,23 @@
+--- external/atomic_queue/include/atomic_queue/defs.h.orig	2023-02-07 02:20:07 UTC
++++ external/atomic_queue/include/atomic_queue/defs.h
+@@ -36,8 +36,19 @@ static inline void spin_loop_pause() noexcept {
+ #endif
+ }
+ } // namespace atomic_queue
++#elif defined(__ppc64__) || defined(__powerpc64__)
++namespace atomic_queue {
++constexpr int CACHE_LINE_SIZE = 128; // TODO: Review that this is the correct value.
++static inline void spin_loop_pause() noexcept {
++    asm volatile("or 31,31,31 # very low priority"); // TODO: Review and benchmark that this is the right instruction.
++}
++} // namespace atomic_queue
+ #else
+-#error "Unknown CPU architecture."
++#warning "Unknown CPU architecture. Using L1 cache line size of 64 bytes and no spinloop pause instruction."
++namespace atomic_queue {
++constexpr int CACHE_LINE_SIZE = 64; // TODO: Review that this is the correct value.
++static inline void spin_loop_pause() noexcept {}
++} // namespace atomic_queue
+ #endif
+ 
+ ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////