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- Update to version 0.9.4

Browse source 
- Give maintainership to submitter

PR:		ports/162069
Submitted by:	Niclas Zeising <niclas.zeising@gmail.com>
This commit is contained in:
Pawel Pekala 2011-10-30 12:42:28 +00:00
parent 3c2476fa4b
commit 7149ddb9e9
Notes: svn2git 2021-03-31 03:12:20 +00:00 
svn path=/head/; revision=284713
2 changed files with 4 additions and 5 deletions
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5
cad/iverilog/Makefile
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@ -7,14 +7,13 @@
#
PORTNAME= iverilog
PORTVERSION= 0.9.2
PORTREVISION= 0
PORTVERSION= 0.9.4
CATEGORIES= cad
MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v${PORTVERSION:C,\.[0-9]$,,}/ \
ftp://ftp.geda.seul.org/pub/geda/dist/
DISTNAME= verilog-${PORTVERSION}
MAINTAINER= ports@FreeBSD.org
MAINTAINER= niclas.zeising@gmail.com
COMMENT= A Verilog simulation and synthesis tool
GNU_CONFIGURE= yes

4
cad/iverilog/distinfo
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@ -1,2 +1,2 @@
SHA256 (verilog-0.9.2.tar.gz) = 321b6f32b5608d7cdd745a9ff8e21f3e2ec1feba9f0e3f92d8bd7042d80647c3
SIZE (verilog-0.9.2.tar.gz) = 1127067
SHA256 (verilog-0.9.4.tar.gz) = b4eac7276975cf2d7c2c94246f733dc187feb4d5944034d053c5094279511eb1
SIZE (verilog-0.9.4.tar.gz) = 1200614