Commit graph

7 commits

Author SHA1 Message Date
Renato Botelho
b2b68f19a3 - Update to 3.404
- Fix build, it needs gcc

PR:		191368
Submitted by:	otaciliodearaujo@gmail.com (maintainer)
2014-06-27 18:59:28 +00:00
Mathieu Arnold
61de712f46 Remove all the bootstrap files (.bs) from the plists.
Starting with perl 5.20, they're not installed any more if empty,
and on FreeBSD, they're (always ?) empty.

PR:		190681
Submitted by:	mat
Exp-Run by:	antoine
Sponsored by:	Absolight
2014-06-10 12:14:12 +00:00
Olli Hauer
2f3121abfc - add stage support
- unbreak
2014-06-01 14:19:13 +00:00
Sylvio Cesar Teixeira
913a43d5b5 - Update to 3.251
PR:		ports/148726
Submitted by:	Otacilio de Araujo Ramos Neto <otacilio.neto@ee.ufcg.edu.br> (maintainer)
2010-07-23 14:33:24 +00:00
Martin Wilke
cdd7d962f8 - Update to 3.221
PR:		140231
Submitted by:	Otacílio de Araújo Ramos Neto <otacilio.neto@ee.ufcg.edu.br> (maintainer)
2009-11-04 15:43:10 +00:00
Philip M. Gollucci
a07e750d89 - Update to 2.11
PR:             ports/136485
Submitted by:   otacilio.neto@ee.ufcg.edu.br (maintainer)
2009-07-15 00:42:29 +00:00
Renato Botelho
a20392af84 The Verilog-Perl library is a building point for Verilog support in the Perl
language. It includes:
* Verilog::Getopt which parses command line options similar to C++ and VCS.
* Verilog::Language which knows the language keywords and parses numbers.
* Verilog::Netlist which builds netlists out of Verilog files. This allows
  easy scripts to determine things such as the hierarchy of modules.
* Verilog::Parser invokes callbacks for language tokens.
* Verilog::Preproc preprocesses the language, and allows reading
  post-processed files right from Perl without temporary files.
* vpassert inserts PLIish warnings and assertions for any simulator.
* vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language.
* vrename renames and cross-references Verilog symbols. Vrename creates Verilog
  cross references and makes it easy to rename signal and module names across
  multiple files. Vrename uses a simple and efficient three step process.
  First, you run vrename to create a list of signals in the design. You then
  edit this list, changing as many symbols as you wish. Vrename is then run a
  second time to apply the changes.

WWW:	http://www.veripool.org/wiki/verilog-perl

PR:		ports/134124
Submitted by:	Otacílio de Araújo Ramos Neto <otacilio.neto at ee.ufcg.edu.br>
2009-05-26 11:01:39 +00:00