Commit graph

24 commits

Author SHA1 Message Date
Marcus Alves Grando
371f431d81 Update to 0.8.1
Add second MASTER_SITES
Add SHA256

PR:		88749
Submitted by:	Joachim Strombergson <watchman@ludd.ltu.se> (maintainer)
2005-11-09 21:36:06 +00:00
Mark Linimon
f5b7121c2a Update maintainer's email address. 2005-10-12 06:25:10 +00:00
Tilman Keskinoz
b84151b7e4 Update to 0.8
PR:		72949
Submitted by:	Joachim Strombergson <watchman@ludd.ltu.se>
2004-11-05 13:16:52 +00:00
MANTANI Nobutaka
8e22e0d446 Update to 0.7.20040606.
PR:		ports/68643
Submitted by:	maintainer
2004-07-04 15:53:09 +00:00
Kirill Ponomarev
a0d455de93 - Update to version 20040220
PR:		ports/64432
Submitted by:	maintainer
2004-03-18 22:19:00 +00:00
Joe Marcus Clarke
053fdb6a6b Bump PORTREVISION on all ports that depend on gettext to aid with upgrading.
(Part 2)
2004-02-04 05:21:48 +00:00
Mark Linimon
253cf23efa Unbreak on 4.x.
PR:		ports/62073
Submitted by:	Hiroki Sato <hrs@freebsd.org>
2004-01-30 10:30:07 +00:00
Mark Linimon
4805bf3d84 Update to 20031202 snapshot. Summary of changes listed on
ftp://icarus.com/pub/eda/verilog/snapshots/verilog-20031202.txt:

Combination 64bit/32bit runtime support now works fully on AMD64
systems; wait on lists of named events now works; there is no
longer a common iverilog.conf, instead there are target specific
foo.conf files with a new and cleaner format; 64bit values are more
portably handled; several synthesis bugs related to the control inputs
of flip-flops have been fixed.

Committer is marking this BROKEN on 4.x while we investigate install
problems.  It works on 5.x only for now.

PR:		ports/60162
Submitted by:	Joachim Strombergson <watchman@ludd.luth.se> (maintainer)
2003-12-17 16:02:50 +00:00
Mark Linimon
e08f6b73c8 Mark as broken while we muddle through the compile problem with
the author.
2003-11-20 03:19:37 +00:00
Mark Linimon
09752ef262 Maintainer Update to latest snapshot. Changes: add AMD64 support
(experimental); time 0 race resolution; identation cleanup; manpage
update.
PR: ports/58320
2003-10-27 10:02:34 +00:00
Mark Linimon
bb01be3ddb Maintainer update to snapshot version. In addition to fixing the port
for gcc3.3, 10 months of updates are included:

- Rework expression parsing and elaboration to accomodate real/realtime
values and expressions.
- Calculate delay statement delays using elaborated expressions instead
of pre-elaborated expression trees.
- Implement the wait statement behaviorally instead of as nets.
- Support event names as expression elements.
- Fix configuration errors, spelling errors, clarification of certain
objects.

See internal revision logs in each file for more elaboration.
2003-10-17 08:26:42 +00:00
Kris Kennaway
7eaa422598 Partial fix for builds with gcc 3.3. This still blows up later on. 2003-07-18 04:17:17 +00:00
Michael C . Wu
0028c8f9cd Change the Maintainer to someone who uses this port more than I do. 2003-05-19 08:24:55 +00:00
Will Andrews
158f9c87d6 Fix MAN. This commit completes changes submitted in the PR. I made
the earlier changes unaware that the submitter had sent the PR.

PR:		51989
Submitted by:	Ports Fury
2003-05-17 03:17:55 +00:00
Will Andrews
e388d96ffa Fix this port and remove BROKEN. 2003-05-16 18:18:38 +00:00
Kris Kennaway
55f0f920a1 BROKEN: Does not install 2003-05-06 07:23:45 +00:00
Ade Lovett
7e52725f2a Clear moonlight beckons.
Requiem mors pacem pkg-comment,
And be calm ports tree.

E Nomini Patri, E Fili, E Spiritu Sancti.
2003-03-07 06:14:21 +00:00
Michael C . Wu
01c6cdf8b1 Update to iverilog 0.7
Submitted by:	 Joachim Str?mbergson <watchman@ludd.luth.se>
2003-01-31 17:49:45 +00:00
Joe Marcus Clarke
acf861feb2 Fix build with bison 1.75.
Reported by:	bento
2002-12-02 04:57:52 +00:00
Kris Kennaway
e05ef340d7 Add missing files 2002-09-19 03:04:23 +00:00
Michael C . Wu
74d5524ae6 Update to 0.6 after my long absence
PR:		35317
Submitted by:	Joachim Strömbergson <watchman@ludd.luth.se>
2002-03-04 00:46:10 +00:00
Ying-Chieh Liao
d64d4c06fc pass maintainership to keichii 2001-05-18 16:01:46 +00:00
Ying-Chieh Liao
2c0a6391e9 forgot bison dependence 2001-02-22 04:58:04 +00:00
Ying-Chieh Liao
7bf8e1d6ec add iverilog, a Verilog simulation and synthesis tool 2001-02-13 11:02:15 +00:00