fb16dfecae
Commit b7f05445c0 has added WWW entries to port Makefiles based on
WWW: lines in pkg-descr files.
This commit removes the WWW: lines of moved-over URLs from these
pkg-descr files.
Approved by: portmgr (tcberner)
3 lines
179 B
Text
3 lines
179 B
Text
Yosys is a framework for Verilog RTL synthesis. It currently has
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extensive Verilog-2005 support and provides a basic set of synthesis
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algorithms for various application domains.
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