358 lines
10 KiB
C
358 lines
10 KiB
C
--- ./include/opcode/mips.h.orig 2011-08-09 15:20:03.000000000 +0000
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+++ ./include/opcode/mips.h 2012-01-21 13:31:35.000000000 +0000
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@@ -216,6 +216,228 @@
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#define MDMX_FMTSEL_VEC_QH 0x15
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#define MDMX_FMTSEL_VEC_OB 0x16
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+#include "vfpu.h"
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+
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+#define VF_MASK_VT 0x7f
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+#define VF_SH_VT 16
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+#define VF_MASK_VS 0x7f
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+#define VF_SH_VS 8
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+#define VF_MASK_VD 0x7f
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+#define VF_SH_VD 0
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+#define VF_MASK_VML 0x1f
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+#define VF_SH_VML 16
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+#define VF_MASK_VMH 0x3
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+#define VF_SH_VMH 0
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+#define VF_MASK_VNL 0x1f
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+#define VF_SH_VNL 16
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+#define VF_MASK_VNH 0x1
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+#define VF_SH_VNH 0
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+#define VF_MASK_OFFSET 0x3fff
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+#define VF_SH_OFFSET 2
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+#define VF_MASK_CC 0xf
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+#define VF_SH_CC 0
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+#define VF_MASK_CONST 0x1f
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+#define VF_SH_CONST 16
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+#define VF_MASK_SCALE 0x1f
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+#define VF_SH_SCALE 16
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+#define VF_MASK_BCOND 0x7
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+#define VF_SH_BCOND 18
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+#define VF_MASK_MCOND 0x7
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+#define VF_SH_MCOND 16
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+#define VF_MASK_VCD 0xff
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+#define VF_SH_VCD 0
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+#define VF_MASK_VCS 0xff
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+#define VF_SH_VCS 8
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+#define VF_MASK_ROT 0x1f
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+#define VF_SH_ROT 16
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+#define VF_MASK_WRAP 0xff
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+#define VF_SH_WRAP 16
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+#define VF_MASK_TSIGN 0x1
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+#define VF_SH_TSIGN 5
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+#define VF_MASK_BMCOND 0x1f
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+#define VF_SH_BMCOND 0
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+#define VF_MASK_HFLOAT 0xffff
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+#define VF_SH_HFLOAT 0
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+#define VF_MASK_PFX 0xffffff
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+#define VF_SH_PFX 0
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+#define VF_MASK_RWB 0x1
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+#define VF_SH_RWB 1
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+
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+#define VF_MASK_PFX_SWZ 0x3
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+#define VF_SH_PFX_SWZ 0
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+#define VF_MASK_PFX_ABS 0x1
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+#define VF_SH_PFX_ABS 8
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+#define VF_MASK_PFX_CST 0x1
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+#define VF_SH_PFX_CST 12
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+#define VF_MASK_PFX_NEG 0x1
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+#define VF_SH_PFX_NEG 16
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+#define VF_MASK_PFX_SAT 0x3
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+#define VF_SH_PFX_SAT 0
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+#define VF_MASK_PFX_MSK 0x1
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+#define VF_SH_PFX_MSK 8
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+
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+#define VF_MASK_ROT_COS 0x3
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+#define VF_SH_ROT_COS 0
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+#define VF_MASK_ROT_SIN 0x3
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+#define VF_SH_ROT_SIN 2
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+#define VF_MASK_ROT_NEG 0x1
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+#define VF_SH_ROT_NEG 4
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+
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+#define VF_MASK_MR_MTX 0x7
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+#define VF_SH_MR_MTX 2
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+#define VF_MASK_MR_IDX 0x3
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+#define VF_SH_MR_IDX 0
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+#define VF_MASK_MR_FSL 0x3
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+#define VF_SH_MR_FSL 5
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+#define VF_MASK_MR_RXC 0x1
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+#define VF_SH_MR_RXC 5
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+#define VF_MASK_MR_VFSL 0x1
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+#define VF_SH_MR_VFSL 6
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+
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+#define VF_MAX_MR_MTX 7
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+#define VF_MAX_MR_IDX 3
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+#define VF_MAX_MR_FSL 3
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+#define VF_MAX_MR_VIDX 1
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+#define VF_MAX_MR_VFSL 1
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+
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+#define VF_MIN_MR 0
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+#define VF_MAX_MR 127
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+#define VF_MIN_CR 128
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+#define VF_MAX_CR 255
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+#define VF_MIN_VCR 128
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+#define VF_MAX_VCR 143
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+#define VF_MIN_CC 0
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+#define VF_MAX_CC 15
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+#define VF_MIN_CONST 1
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+#define VF_MAX_CONST 19
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+#define VF_MIN_SCALE 0
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+#define VF_MAX_SCALE 31
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+#define VF_MIN_BCOND 0
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+#define VF_MAX_BCOND 5
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+#define VF_MIN_MCOND 0
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+#define VF_MAX_MCOND 6
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+#define VF_MIN_WRAP 0
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+#define VF_MAX_WRAP 255
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+#define VF_MIN_ROT 0
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+#define VF_MAX_ROT 31
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+#define VF_MIN_TSIGN 0
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+#define VF_MAX_TSIGN 1
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+#define VF_MIN_BMCOND 0
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+#define VF_MAX_BMCOND 31
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+#define VF_MIN_HFLOAT 0
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+#define VF_MAX_HFLOAT 0xffff
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+
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+#define VF_MASK_F32_SIGN 0x1
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+#define VF_SH_F32_SIGN 31
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+#define VF_MASK_F32_EXP 0xff
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+#define VF_SH_F32_EXP 23
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+#define VF_MASK_F32_FRA 0x7fffff
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+#define VF_SH_F32_FRA 0
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+#define VF_MASK_F16_SIGN 0x1
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+#define VF_SH_F16_SIGN 15
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+#define VF_MASK_F16_EXP 0x1f
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+#define VF_SH_F16_EXP 10
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+#define VF_MASK_F16_FRA 0x3ff
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+#define VF_SH_F16_FRA 0
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+
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+#define VF_MIN_F32_EXP 0
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+#define VF_MAX_F32_EXP 255
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+#define VF_BIAS_F32_EXP 127
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+#define VF_MIN_F16_EXP 0
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+#define VF_MAX_F16_EXP 31
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+#define VF_BIAS_F16_EXP 15
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+
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+#define OP_SH_VFPU_DELTA 0
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+#define OP_MASK_VFPU_DELTA 0xfffc
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+#define OP_SH_VFPU_IMM3 16
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+#define OP_MASK_VFPU_IMM3 0x7
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+#define OP_SH_VFPU_IMM5 16
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+#define OP_MASK_VFPU_IMM5 0x1f
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+#define OP_SH_VFPU_IMM8 16
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+#define OP_MASK_VFPU_IMM8 0xff
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+#define OP_SH_VFPU_CC 18 /* Condition code. */
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+#define OP_MASK_VFPU_CC 0x7
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+#define OP_SH_VFPU_CONST 16
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+#define OP_MASK_VFPU_CONST 0x1f
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+#define OP_SH_VFPU_COND 0 /* Conditional compare. */
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+#define OP_MASK_VFPU_COND 0xf
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+#define OP_SH_VFPU_VMTVC 0
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+#define OP_MASK_VFPU_VMTVC 0xff
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+#define OP_SH_VFPU_VMFVC 8
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+#define OP_MASK_VFPU_VMFVC 0xff
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+#define OP_SH_VFPU_RWB 1
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+#define OP_MASK_VFPU_RWB 0x1
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+#define OP_SH_VFPU_ROT 16 /* Rotators used in vrot. */
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+#define OP_MASK_VFPU_ROT 0x1f
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+#define OP_SH_VFPU_FLOAT16 0
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+#define OP_MASK_VFPU_FLOAT16 0xffff
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+
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+/* VFPU registers. */
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+#define OP_SH_VFPU_VD 0
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+#define OP_MASK_VFPU_VD 0x7f
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+#define OP_SH_VFPU_VS 8
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+#define OP_MASK_VFPU_VS 0x7f
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+#define OP_SH_VFPU_VT 16
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+#define OP_MASK_VFPU_VT 0x7f
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+#define OP_SH_VFPU_VT_LO 16 /* Bits 0-4 of vt. */
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+#define OP_MASK_VFPU_VT_LO 0x1f
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+#define OP_SH_VFPU_VT_HI 5 /* Right-shifted. */
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+#define OP_MASK_VFPU_VT_HI1 0x1 /* Bit 5 of vt. */
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+#define OP_MASK_VFPU_VT_HI2 0x3 /* Bits 5-6 of vt. */
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+/* Special handling of vs in vmmul instructions. */
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+#define VFPU_OP_VT_VS_VD 0xff800000
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+#define VFPU_OPCODE_VMMUL 0xf0000000
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+
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+/* VFPU condition codes. FL and TR accept no arguments, while any conditions
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+ above and including EZ only accept one argument. The rest require two
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+ arguments. */
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+enum
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+{
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+ VFPU_COND_FL, VFPU_COND_EQ, VFPU_COND_LT, VFPU_COND_LE,
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+ VFPU_COND_TR, VFPU_COND_NE, VFPU_COND_GE, VFPU_COND_GT,
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+ VFPU_COND_EZ, VFPU_COND_EN, VFPU_COND_EI, VFPU_COND_ES,
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+ VFPU_COND_NZ, VFPU_COND_NN, VFPU_COND_NI, VFPU_COND_NS,
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+ VFPU_NUM_CONDS
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+};
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+
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+/* VFPU prefix instruction operands. The *_SH_* values really specify where
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+ the bitfield begins, as VFPU prefix instructions have four operands
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+ encoded within the immediate field. */
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+#define VFPU_SH_PFX_NEG 16
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+#define VFPU_MASK_PFX_NEG 0x1 /* Negation. */
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+#define VFPU_SH_PFX_CST 12
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+#define VFPU_MASK_PFX_CST 0x1 /* Constant. */
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+#define VFPU_SH_PFX_ABS_CSTHI 8
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+#define VFPU_MASK_PFX_ABS_CSTHI 0x1 /* Abs/Constant (bit 2). */
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+#define VFPU_SH_PFX_SWZ_CSTLO 0
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+#define VFPU_MASK_PFX_SWZ_CSTLO 0x3 /* Swizzle/Constant (bits 0-1). */
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+#define VFPU_SH_PFX_MASK 8
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+#define VFPU_MASK_PFX_MASK 0x1 /* Mask. */
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+#define VFPU_SH_PFX_SAT 0
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+#define VFPU_MASK_PFX_SAT 0x3 /* Saturation. */
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+
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+/* Special handling of the vrot instructions. */
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+#define VFPU_MASK_OP_SIZE 0x8080 /* Masks the operand size (pair, triple, quad). */
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+#define VFPU_OP_SIZE_PAIR 0x80
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+#define VFPU_OP_SIZE_TRIPLE 0x8000
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+#define VFPU_OP_SIZE_QUAD 0x8080
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+/* Note that these are within the rotators field, and not the full opcode. */
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+#define VFPU_SH_ROT_HI 2
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+#define VFPU_MASK_ROT_HI 0x3
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+#define VFPU_SH_ROT_LO 0
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+#define VFPU_MASK_ROT_LO 0x3
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+#define VFPU_SH_ROT_NEG 4 /* Negation. */
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+#define VFPU_MASK_ROT_NEG 0x1
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+
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+/* VFPU 16-bit floating-point format. */
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+#define VFPU_FLOAT16_EXP_MAX 0x1f
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+#define VFPU_SH_FLOAT16_SIGN 15
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+#define VFPU_MASK_FLOAT16_SIGN 0x1
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+#define VFPU_SH_FLOAT16_EXP 10
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+#define VFPU_MASK_FLOAT16_EXP 0x1f
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+#define VFPU_SH_FLOAT16_FRAC 0
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+#define VFPU_MASK_FLOAT16_FRAC 0x3ff
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+
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/* UDI */
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#define OP_SH_UDI1 6
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#define OP_MASK_UDI1 0x1f
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@@ -416,6 +638,29 @@
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Requires that "+A" or "+E" occur first to set position.
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Enforces: 32 < (pos+size) <= 64.
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+ Sony Allegrex VFPU instructions:
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+ "?o"
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+ "?0" - "?3"
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+ "?4" - "?7"
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+ "?a"
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+ "?b"
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+ "?c"
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+ "?e"
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+ "?f"
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+ "?i"
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+ "?q"
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+ "?r"
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+ "?u"
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+ "?w"
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+ "?d"
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+ "?m"
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+ "?n"
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+ "?s"
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+ "?t"
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+ "?v"
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+ "?x"
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+ "?z"
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+
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Floating point instructions:
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"D" 5 bit destination register (OP_*_FD)
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"M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
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@@ -750,6 +995,8 @@
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#define INSN_5400 0x01000000
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/* NEC VR5500 instruction. */
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#define INSN_5500 0x02000000
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+/* Sony Allegrex instruction. */
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+#define INSN_ALLEGREX 0x10000000
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/* MDMX ASE */
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#define INSN_MDMX 0x04000000
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@@ -819,6 +1066,7 @@
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#define CPU_MIPS64 64
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#define CPU_MIPS64R2 65
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#define CPU_SB1 12310201 /* octal 'SB', 01. */
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+#define CPU_ALLEGREX 10111431 /* octal 'AL', 31. */
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#define CPU_LOONGSON_2E 3001
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#define CPU_LOONGSON_2F 3002
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#define CPU_LOONGSON_3A 3003
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@@ -851,6 +1099,7 @@
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|| (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
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|| (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
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|| (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
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+ || (cpu == CPU_ALLEGREX && ((insn)->membership & INSN_ALLEGREX) != 0) \
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|| (cpu == CPU_LOONGSON_2E \
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&& ((insn)->membership & INSN_LOONGSON_2E) != 0) \
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|| (cpu == CPU_LOONGSON_2F \
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@@ -1005,11 +1254,27 @@
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M_LI_DD,
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M_LI_S,
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M_LI_SS,
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+ M_LVHI_S_SS,
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+ M_LVHI_P_SS,
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+ M_LVI_S_SS,
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+ M_LVI_P_SS,
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+ M_LVI_T_SS,
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+ M_LVI_Q_SS,
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M_LL_AB,
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M_LL_OB,
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M_LLD_AB,
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M_LLD_OB,
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M_LS_A,
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+ M_LVHI_P,
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+ M_LVHI_S,
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+ M_LVI_P,
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+ M_LVI_Q,
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+ M_LVI_S,
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+ M_LVI_T,
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+ M_LVL_Q_AB,
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+ M_LVR_Q_AB,
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+ M_LV_Q_AB,
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+ M_LV_Q_AB_2,
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M_LW_A,
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M_LW_AB,
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M_LWC0_A,
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@@ -1021,6 +1286,7 @@
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M_LWC2_OB,
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M_LWC3_A,
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M_LWC3_AB,
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+ M_LV_S_AB,
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M_LWL_A,
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M_LWL_AB,
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M_LWL_OB,
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@@ -1130,6 +1396,10 @@
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M_SUB_I,
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M_SUBU_I,
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M_SUBU_I_2,
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+ M_SVL_Q_AB,
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+ M_SV_Q_AB,
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+ M_SVR_Q_AB,
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+ M_SV_S_AB,
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M_TEQ_I,
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M_TGE_I,
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M_TGEU_I,
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@@ -1144,14 +1414,24 @@
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M_ULH_A,
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M_ULHU,
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M_ULHU_A,
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+ M_ULV_Q,
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+ M_ULV_Q_AB,
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+ M_ULV_S,
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M_ULW,
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M_ULW_A,
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M_USH,
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M_USH_A,
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+ M_USV_Q,
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+ M_USV_Q_AB,
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+ M_USV_S,
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M_USW,
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M_USW_A,
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M_USD,
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M_USD_A,
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+ M_VCMOV_P,
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+ M_VCMOV_Q,
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+ M_VCMOV_S,
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+ M_VCMOV_T,
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M_XOR_I,
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M_COP0,
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M_COP1,
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