108 lines
2.5 KiB
Makefile
108 lines
2.5 KiB
Makefile
# $FreeBSD$
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#
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COMMENT = CAD tools
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SUBDIR += NASTRAN-95
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SUBDIR += abc
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SUBDIR += admesh
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SUBDIR += adms
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SUBDIR += alliance
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SUBDIR += astk-client
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SUBDIR += astk-serveur
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SUBDIR += atlc
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SUBDIR += basicdsp
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SUBDIR += brickutils
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SUBDIR += calculix
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SUBDIR += calculix-ccx
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SUBDIR += cascade
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SUBDIR += chipvault
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SUBDIR += cura-engine
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SUBDIR += digital
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SUBDIR += dinotrace
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SUBDIR += dxf2fig
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SUBDIR += electric
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SUBDIR += electric-ng
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SUBDIR += feappv
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SUBDIR += fidocadj
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SUBDIR += freecad
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SUBDIR += freehdl
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SUBDIR += fritzing
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SUBDIR += gdsreader
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SUBDIR += gdt
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SUBDIR += geda
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SUBDIR += gerbv
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SUBDIR += ghdl
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SUBDIR += gmsh
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SUBDIR += gnucap
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SUBDIR += gplcver
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SUBDIR += gspiceui
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SUBDIR += gtkwave
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SUBDIR += impact
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SUBDIR += irsim
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SUBDIR += iverilog
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SUBDIR += jspice3
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SUBDIR += k40-whisperer
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SUBDIR += kicad
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SUBDIR += kicad-devel
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SUBDIR += kicad-doc
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SUBDIR += kicad-library-footprints
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SUBDIR += kicad-library-footprints-devel
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SUBDIR += kicad-library-packages3d
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SUBDIR += kicad-library-packages3d-devel
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SUBDIR += kicad-library-symbols
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SUBDIR += kicad-library-symbols-devel
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SUBDIR += kicad-library-templates
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SUBDIR += kicad-library-templates-devel
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SUBDIR += klayout
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SUBDIR += ldraw
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SUBDIR += leocad
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SUBDIR += lepton-eda
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SUBDIR += libopencad
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SUBDIR += librecad
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SUBDIR += libredwg
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SUBDIR += linux-eagle5
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SUBDIR += linuxcnc-devel
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SUBDIR += logisim
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SUBDIR += magic
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SUBDIR += meshdev
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SUBDIR += netgen
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SUBDIR += ngspice_rework
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SUBDIR += opencascade
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SUBDIR += openscad
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SUBDIR += openscad-devel
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SUBDIR += openvsp
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SUBDIR += p5-GDS2
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SUBDIR += p5-Verilog-Perl
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SUBDIR += pcb
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SUBDIR += pdnmesh
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SUBDIR += py-gdspy
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SUBDIR += py-lcapy
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SUBDIR += py-phidl
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SUBDIR += py-pycam
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SUBDIR += py-pyfda
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SUBDIR += python-gdsii
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SUBDIR += pythoncad
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SUBDIR += qcad
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SUBDIR += qelectrotech
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SUBDIR += qmls
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SUBDIR += repsnapper
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SUBDIR += rubygem-gdsii
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SUBDIR += scotch
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SUBDIR += solvespace
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SUBDIR += sp2sp
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SUBDIR += spice
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SUBDIR += stepcode
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SUBDIR += sumo
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SUBDIR += sweethome3d
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SUBDIR += tkgate
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SUBDIR += tochnog
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SUBDIR += transcalc
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SUBDIR += varkon
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SUBDIR += verilator
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SUBDIR += verilog-mode.el
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SUBDIR += xcircuit
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SUBDIR += z88
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SUBDIR += zcad
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.include <bsd.port.subdir.mk>
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