572 lines
15 KiB
C
572 lines
15 KiB
C
--- lib/gmp/longlong.h.orig Wed Oct 15 06:11:33 2003
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+++ lib/gmp/longlong.h Wed Oct 15 06:23:05 2003
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@@ -112,7 +112,7 @@
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#if (defined (__a29k__) || defined (_AM29K)) && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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- __asm__ ("add %1,%4,%5
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+ __asm__ ("add %1,%4,%5 \n\
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addc %0,%2,%3" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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@@ -121,7 +121,7 @@
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"%r" ((USItype)(al)), \
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"rI" ((USItype)(bl)))
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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- __asm__ ("sub %1,%4,%5
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+ __asm__ ("sub %1,%4,%5 \n\
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subc %0,%2,%3" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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@@ -179,7 +179,7 @@
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#if defined (__arm__) && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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- __asm__ ("adds %1, %4, %5
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+ __asm__ ("adds %1, %4, %5 \n\
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adc %0, %2, %3" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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@@ -188,7 +188,7 @@
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"%r" ((USItype)(al)), \
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"rI" ((USItype)(bl)))
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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- __asm__ ("subs %1, %4, %5
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+ __asm__ ("subs %1, %4, %5 \n\
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sbc %0, %2, %3" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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@@ -197,18 +197,18 @@
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"r" ((USItype)(al)), \
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"rI" ((USItype)(bl)))
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#define umul_ppmm(xh, xl, a, b) \
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- __asm__ ("%@ Inlined umul_ppmm
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- mov %|r0, %2, lsr #16
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- mov %|r2, %3, lsr #16
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- bic %|r1, %2, %|r0, lsl #16
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- bic %|r2, %3, %|r2, lsl #16
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- mul %1, %|r1, %|r2
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- mul %|r2, %|r0, %|r2
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- mul %|r1, %0, %|r1
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- mul %0, %|r0, %0
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- adds %|r1, %|r2, %|r1
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- addcs %0, %0, #65536
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- adds %1, %1, %|r1, lsl #16
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+ __asm__ ("%@ Inlined umul_ppmm \n\
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+ mov %|r0, %2, lsr #16 \n\
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+ mov %|r2, %3, lsr #16 \n\
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+ bic %|r1, %2, %|r0, lsl #16 \n\
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+ bic %|r2, %3, %|r2, lsl #16 \n\
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+ mul %1, %|r1, %|r2 \n\
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+ mul %|r2, %|r0, %|r2 \n\
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+ mul %|r1, %0, %|r1 \n\
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+ mul %0, %|r0, %0 \n\
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+ adds %|r1, %|r2, %|r1 \n\
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+ addcs %0, %0, #65536 \n\
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+ adds %1, %1, %|r1, lsl #16 \n\
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adc %0, %0, %|r1, lsr #16" \
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: "=&r" ((USItype)(xh)), \
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"=r" ((USItype)(xl)) \
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@@ -249,7 +249,7 @@
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#if defined (__gmicro__) && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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- __asm__ ("add.w %5,%1
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+ __asm__ ("add.w %5,%1 \n\
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addx %3,%0" \
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: "=g" ((USItype)(sh)), \
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"=&g" ((USItype)(sl)) \
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@@ -258,7 +258,7 @@
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"%1" ((USItype)(al)), \
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"g" ((USItype)(bl)))
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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- __asm__ ("sub.w %5,%1
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+ __asm__ ("sub.w %5,%1 \n\
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subx %3,%0" \
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: "=g" ((USItype)(sh)), \
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"=&g" ((USItype)(sl)) \
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@@ -288,7 +288,7 @@
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#if defined (__hppa) && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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- __asm__ ("add %4,%5,%1
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+ __asm__ ("add %4,%5,%1 \n\
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addc %2,%3,%0" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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@@ -297,7 +297,7 @@
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"%rM" ((USItype)(al)), \
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"rM" ((USItype)(bl)))
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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- __asm__ ("sub %4,%5,%1
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+ __asm__ ("sub %4,%5,%1 \n\
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subb %2,%3,%0" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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@@ -336,21 +336,21 @@
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do { \
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USItype __tmp; \
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__asm__ ( \
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- "ldi 1,%0
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- extru,= %1,15,16,%%r0 ; Bits 31..16 zero?
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- extru,tr %1,15,16,%1 ; No. Shift down, skip add.
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- ldo 16(%0),%0 ; Yes. Perform add.
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- extru,= %1,23,8,%%r0 ; Bits 15..8 zero?
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- extru,tr %1,23,8,%1 ; No. Shift down, skip add.
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- ldo 8(%0),%0 ; Yes. Perform add.
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- extru,= %1,27,4,%%r0 ; Bits 7..4 zero?
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- extru,tr %1,27,4,%1 ; No. Shift down, skip add.
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- ldo 4(%0),%0 ; Yes. Perform add.
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- extru,= %1,29,2,%%r0 ; Bits 3..2 zero?
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- extru,tr %1,29,2,%1 ; No. Shift down, skip add.
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- ldo 2(%0),%0 ; Yes. Perform add.
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- extru %1,30,1,%1 ; Extract bit 1.
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- sub %0,%1,%0 ; Subtract it.
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+ "ldi 1,%0\n\
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+ extru,= %1,15,16,%%r0 ; Bits 31..16 zero?\n\
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+ extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n\
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+ ldo 16(%0),%0 ; Yes. Perform add.\n\
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+ extru,= %1,23,8,%%r0 ; Bits 15..8 zero?\n\
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+ extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n\
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+ ldo 8(%0),%0 ; Yes. Perform add.\n\
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+ extru,= %1,27,4,%%r0 ; Bits 7..4 zero?\n\
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+ extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n\
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+ ldo 4(%0),%0 ; Yes. Perform add.\n\
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+ extru,= %1,29,2,%%r0 ; Bits 3..2 zero?\n\
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+ extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n\
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+ ldo 2(%0),%0 ; Yes. Perform add.\n\
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+ extru %1,30,1,%1 ; Extract bit 1.\n\
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+ sub %0,%1,%0 ; Subtract it.\n\
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" : "=r" (count), "=r" (__tmp) : "1" (x)); \
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} while (0)
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#endif /* hppa */
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@@ -398,7 +398,7 @@
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#if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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- __asm__ ("addl %5,%1
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+ __asm__ ("addl %5,%1 \n\
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adcl %3,%0" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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@@ -407,7 +407,7 @@
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"%1" ((USItype)(al)), \
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"g" ((USItype)(bl)))
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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- __asm__ ("subl %5,%1
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+ __asm__ ("subl %5,%1 \n\
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sbbl %3,%0" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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@@ -520,7 +520,7 @@
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#if (defined (__mc68000__) || defined (__mc68020__) || defined (__NeXT__) || defined(mc68020)) && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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- __asm__ ("add%.l %5,%1
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+ __asm__ ("add%.l %5,%1 \n\
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addx%.l %3,%0" \
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: "=d" ((USItype)(sh)), \
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"=&d" ((USItype)(sl)) \
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@@ -529,7 +529,7 @@
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"%1" ((USItype)(al)), \
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"g" ((USItype)(bl)))
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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- __asm__ ("sub%.l %5,%1
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+ __asm__ ("sub%.l %5,%1 \n\
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subx%.l %3,%0" \
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: "=d" ((USItype)(sh)), \
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"=&d" ((USItype)(sl)) \
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@@ -568,27 +568,27 @@
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#else /* not mc68020 */
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#define umul_ppmm(xh, xl, a, b) \
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do { USItype __umul_tmp1, __umul_tmp2; \
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- __asm__ ("| Inlined umul_ppmm
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- move%.l %5,%3
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- move%.l %2,%0
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- move%.w %3,%1
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- swap %3
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- swap %0
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- mulu %2,%1
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- mulu %3,%0
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- mulu %2,%3
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- swap %2
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- mulu %5,%2
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- add%.l %3,%2
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- jcc 1f
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- add%.l %#0x10000,%0
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-1: move%.l %2,%3
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- clr%.w %2
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- swap %2
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- swap %3
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- clr%.w %3
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- add%.l %3,%1
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- addx%.l %2,%0
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+ __asm__ ("| Inlined umul_ppmm\n\
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+ move%.l %5,%3\n\
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+ move%.l %2,%0\n\
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+ move%.w %3,%1\n\
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+ swap %3\n\
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+ swap %0\n\
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+ mulu %2,%1\n\
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+ mulu %3,%0\n\
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+ mulu %2,%3\n\
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+ swap %2\n\
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+ mulu %5,%2\n\
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+ add%.l %3,%2\n\
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+ jcc 1f\n\
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+ add%.l %#0x10000,%0\n\
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+1: move%.l %2,%3\n\
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+ clr%.w %2\n\
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+ swap %2\n\
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+ swap %3\n\
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+ clr%.w %3\n\
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+ add%.l %3,%1\n\
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+ addx%.l %2,%0\n\
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| End inlined umul_ppmm" \
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: "=&d" ((USItype)(xh)), "=&d" ((USItype)(xl)), \
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"=d" (__umul_tmp1), "=&d" (__umul_tmp2) \
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@@ -601,7 +601,7 @@
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#if defined (__m88000__) && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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- __asm__ ("addu.co %1,%r4,%r5
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+ __asm__ ("addu.co %1,%r4,%r5 \n\
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addu.ci %0,%r2,%r3" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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@@ -610,7 +610,7 @@
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"%rJ" ((USItype)(al)), \
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"rJ" ((USItype)(bl)))
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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- __asm__ ("subu.co %1,%r4,%r5
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+ __asm__ ("subu.co %1,%r4,%r5 \n\
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subu.ci %0,%r2,%r3" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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@@ -669,8 +669,8 @@
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"d" ((USItype)(v)))
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#else
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#define umul_ppmm(w1, w0, u, v) \
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- __asm__ ("multu %2,%3
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- mflo %0
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+ __asm__ ("multu %2,%3 \n\
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+ mflo %0 \n\
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mfhi %1" \
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: "=d" ((USItype)(w0)), \
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"=d" ((USItype)(w1)) \
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@@ -691,8 +691,8 @@
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"d" ((UDItype)(v)))
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#else
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#define umul_ppmm(w1, w0, u, v) \
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- __asm__ ("dmultu %2,%3
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- mflo %0
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+ __asm__ ("dmultu %2,%3 \n\
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+ mflo %0 \n\
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mfhi %1" \
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: "=d" ((UDItype)(w0)), \
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"=d" ((UDItype)(w1)) \
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@@ -861,7 +861,7 @@
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#if defined (__pyr__) && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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- __asm__ ("addw %5,%1
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+ __asm__ ("addw %5,%1 \n\
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addwc %3,%0" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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@@ -870,7 +870,7 @@
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"%1" ((USItype)(al)), \
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"g" ((USItype)(bl)))
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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- __asm__ ("subw %5,%1
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+ __asm__ ("subw %5,%1 \n\
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subwb %3,%0" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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@@ -883,7 +883,7 @@
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({union {UDItype __ll; \
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struct {USItype __h, __l;} __i; \
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} __xx; \
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- __asm__ ("movw %1,%R0
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+ __asm__ ("movw %1,%R0 \n\
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uemul %2,%0" \
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: "=&r" (__xx.__ll) \
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: "g" ((USItype) (u)), \
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@@ -893,7 +893,7 @@
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#if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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- __asm__ ("a %1,%5
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+ __asm__ ("a %1,%5 \n\
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ae %0,%3" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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@@ -902,7 +902,7 @@
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"%1" ((USItype)(al)), \
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"r" ((USItype)(bl)))
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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- __asm__ ("s %1,%5
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+ __asm__ ("s %1,%5 \n\
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se %0,%3" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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@@ -914,25 +914,25 @@
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do { \
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USItype __m0 = (m0), __m1 = (m1); \
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__asm__ ( \
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- "s r2,r2
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- mts r10,%2
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- m r2,%3
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- m r2,%3
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- m r2,%3
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- m r2,%3
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- m r2,%3
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- m r2,%3
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- m r2,%3
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- m r2,%3
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- m r2,%3
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- m r2,%3
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- m r2,%3
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- m r2,%3
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- m r2,%3
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- m r2,%3
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- m r2,%3
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- m r2,%3
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- cas %0,r2,r0
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+ "s r2,r2 \n\
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+ mts r10,%2 \n\
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+ m r2,%3 \n\
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+ m r2,%3 \n\
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+ m r2,%3 \n\
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+ m r2,%3 \n\
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+ m r2,%3 \n\
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+ m r2,%3 \n\
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+ m r2,%3 \n\
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+ m r2,%3 \n\
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+ m r2,%3 \n\
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+ m r2,%3 \n\
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+ m r2,%3 \n\
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+ m r2,%3 \n\
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+ m r2,%3 \n\
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+ m r2,%3 \n\
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+ m r2,%3 \n\
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+ m r2,%3 \n\
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+ cas %0,r2,r0 \n\
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mfs r10,%1" \
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: "=r" ((USItype)(ph)), \
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"=r" ((USItype)(pl)) \
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@@ -963,8 +963,8 @@
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#if defined (__sh2__) && W_TYPE_SIZE == 32
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#define umul_ppmm(w1, w0, u, v) \
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__asm__ ( \
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- "dmulu.l %2,%3
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- sts macl,%1
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+ "dmulu.l %2,%3 \n\
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+ sts macl,%1 \n\
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sts mach,%0" \
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: "=r" ((USItype)(w1)), \
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"=r" ((USItype)(w0)) \
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@@ -976,7 +976,7 @@
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#if defined (__sparc__) && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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- __asm__ ("addcc %r4,%5,%1
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+ __asm__ ("addcc %r4,%5,%1 \n\
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addx %r2,%3,%0" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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@@ -986,7 +986,7 @@
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"rI" ((USItype)(bl)) \
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__CLOBBER_CC)
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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- __asm__ ("subcc %r4,%5,%1
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+ __asm__ ("subcc %r4,%5,%1 \n\
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subx %r2,%3,%0" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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@@ -1033,44 +1033,44 @@
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"r" ((USItype)(v)))
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#define UMUL_TIME 5
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#define udiv_qrnnd(q, r, n1, n0, d) \
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- __asm__ ("! Inlined udiv_qrnnd
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- wr %%g0,%2,%%y ! Not a delayed write for sparclite
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- tst %%g0
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- divscc %3,%4,%%g1
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- divscc %%g1,%4,%%g1
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- divscc %%g1,%4,%%g1
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- divscc %%g1,%4,%%g1
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- divscc %%g1,%4,%%g1
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- divscc %%g1,%4,%%g1
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- divscc %%g1,%4,%%g1
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- divscc %%g1,%4,%%g1
|
|
- divscc %%g1,%4,%%g1
|
|
- divscc %%g1,%4,%%g1
|
|
- divscc %%g1,%4,%%g1
|
|
- divscc %%g1,%4,%%g1
|
|
- divscc %%g1,%4,%%g1
|
|
- divscc %%g1,%4,%%g1
|
|
- divscc %%g1,%4,%%g1
|
|
- divscc %%g1,%4,%%g1
|
|
- divscc %%g1,%4,%%g1
|
|
- divscc %%g1,%4,%%g1
|
|
- divscc %%g1,%4,%%g1
|
|
- divscc %%g1,%4,%%g1
|
|
- divscc %%g1,%4,%%g1
|
|
- divscc %%g1,%4,%%g1
|
|
- divscc %%g1,%4,%%g1
|
|
- divscc %%g1,%4,%%g1
|
|
- divscc %%g1,%4,%%g1
|
|
- divscc %%g1,%4,%%g1
|
|
- divscc %%g1,%4,%%g1
|
|
- divscc %%g1,%4,%%g1
|
|
- divscc %%g1,%4,%%g1
|
|
- divscc %%g1,%4,%%g1
|
|
- divscc %%g1,%4,%%g1
|
|
- divscc %%g1,%4,%0
|
|
- rd %%y,%1
|
|
- bl,a 1f
|
|
- add %1,%4,%1
|
|
+ __asm__ ("! Inlined udiv_qrnnd \n\
|
|
+ wr %%g0,%2,%%y ! Not a delayed write for sparclite \n\
|
|
+ tst %%g0 \n\
|
|
+ divscc %3,%4,%%g1 \n\
|
|
+ divscc %%g1,%4,%%g1 \n\
|
|
+ divscc %%g1,%4,%%g1 \n\
|
|
+ divscc %%g1,%4,%%g1 \n\
|
|
+ divscc %%g1,%4,%%g1 \n\
|
|
+ divscc %%g1,%4,%%g1 \n\
|
|
+ divscc %%g1,%4,%%g1 \n\
|
|
+ divscc %%g1,%4,%%g1 \n\
|
|
+ divscc %%g1,%4,%%g1 \n\
|
|
+ divscc %%g1,%4,%%g1 \n\
|
|
+ divscc %%g1,%4,%%g1 \n\
|
|
+ divscc %%g1,%4,%%g1 \n\
|
|
+ divscc %%g1,%4,%%g1 \n\
|
|
+ divscc %%g1,%4,%%g1 \n\
|
|
+ divscc %%g1,%4,%%g1 \n\
|
|
+ divscc %%g1,%4,%%g1 \n\
|
|
+ divscc %%g1,%4,%%g1 \n\
|
|
+ divscc %%g1,%4,%%g1 \n\
|
|
+ divscc %%g1,%4,%%g1 \n\
|
|
+ divscc %%g1,%4,%%g1 \n\
|
|
+ divscc %%g1,%4,%%g1 \n\
|
|
+ divscc %%g1,%4,%%g1 \n\
|
|
+ divscc %%g1,%4,%%g1 \n\
|
|
+ divscc %%g1,%4,%%g1 \n\
|
|
+ divscc %%g1,%4,%%g1 \n\
|
|
+ divscc %%g1,%4,%%g1 \n\
|
|
+ divscc %%g1,%4,%%g1 \n\
|
|
+ divscc %%g1,%4,%%g1 \n\
|
|
+ divscc %%g1,%4,%%g1 \n\
|
|
+ divscc %%g1,%4,%%g1 \n\
|
|
+ divscc %%g1,%4,%%g1 \n\
|
|
+ divscc %%g1,%4,%0 \n\
|
|
+ rd %%y,%1 \n\
|
|
+ bl,a 1f \n\
|
|
+ add %1,%4,%1 \n\
|
|
1: ! End of inline udiv_qrnnd" \
|
|
: "=r" ((USItype)(q)), \
|
|
"=r" ((USItype)(r)) \
|
|
@@ -1091,45 +1091,45 @@
|
|
/* Default to sparc v7 versions of umul_ppmm and udiv_qrnnd. */
|
|
#ifndef umul_ppmm
|
|
#define umul_ppmm(w1, w0, u, v) \
|
|
- __asm__ ("! Inlined umul_ppmm
|
|
- wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr
|
|
- sra %3,31,%%g2 ! Don't move this insn
|
|
- and %2,%%g2,%%g2 ! Don't move this insn
|
|
- andcc %%g0,0,%%g1 ! Don't move this insn
|
|
- mulscc %%g1,%3,%%g1
|
|
- mulscc %%g1,%3,%%g1
|
|
- mulscc %%g1,%3,%%g1
|
|
- mulscc %%g1,%3,%%g1
|
|
- mulscc %%g1,%3,%%g1
|
|
- mulscc %%g1,%3,%%g1
|
|
- mulscc %%g1,%3,%%g1
|
|
- mulscc %%g1,%3,%%g1
|
|
- mulscc %%g1,%3,%%g1
|
|
- mulscc %%g1,%3,%%g1
|
|
- mulscc %%g1,%3,%%g1
|
|
- mulscc %%g1,%3,%%g1
|
|
- mulscc %%g1,%3,%%g1
|
|
- mulscc %%g1,%3,%%g1
|
|
- mulscc %%g1,%3,%%g1
|
|
- mulscc %%g1,%3,%%g1
|
|
- mulscc %%g1,%3,%%g1
|
|
- mulscc %%g1,%3,%%g1
|
|
- mulscc %%g1,%3,%%g1
|
|
- mulscc %%g1,%3,%%g1
|
|
- mulscc %%g1,%3,%%g1
|
|
- mulscc %%g1,%3,%%g1
|
|
- mulscc %%g1,%3,%%g1
|
|
- mulscc %%g1,%3,%%g1
|
|
- mulscc %%g1,%3,%%g1
|
|
- mulscc %%g1,%3,%%g1
|
|
- mulscc %%g1,%3,%%g1
|
|
- mulscc %%g1,%3,%%g1
|
|
- mulscc %%g1,%3,%%g1
|
|
- mulscc %%g1,%3,%%g1
|
|
- mulscc %%g1,%3,%%g1
|
|
- mulscc %%g1,%3,%%g1
|
|
- mulscc %%g1,0,%%g1
|
|
- add %%g1,%%g2,%0
|
|
+ __asm__ ("! Inlined umul_ppmm\n\
|
|
+ wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n\
|
|
+ sra %3,31,%%g2 ! Don't move this insn\n\
|
|
+ and %2,%%g2,%%g2 ! Don't move this insn\n\
|
|
+ andcc %%g0,0,%%g1 ! Don't move this insn\n\
|
|
+ mulscc %%g1,%3,%%g1\n\
|
|
+ mulscc %%g1,%3,%%g1\n\
|
|
+ mulscc %%g1,%3,%%g1\n\
|
|
+ mulscc %%g1,%3,%%g1\n\
|
|
+ mulscc %%g1,%3,%%g1\n\
|
|
+ mulscc %%g1,%3,%%g1\n\
|
|
+ mulscc %%g1,%3,%%g1\n\
|
|
+ mulscc %%g1,%3,%%g1\n\
|
|
+ mulscc %%g1,%3,%%g1\n\
|
|
+ mulscc %%g1,%3,%%g1\n\
|
|
+ mulscc %%g1,%3,%%g1\n\
|
|
+ mulscc %%g1,%3,%%g1\n\
|
|
+ mulscc %%g1,%3,%%g1\n\
|
|
+ mulscc %%g1,%3,%%g1\n\
|
|
+ mulscc %%g1,%3,%%g1\n\
|
|
+ mulscc %%g1,%3,%%g1\n\
|
|
+ mulscc %%g1,%3,%%g1\n\
|
|
+ mulscc %%g1,%3,%%g1\n\
|
|
+ mulscc %%g1,%3,%%g1\n\
|
|
+ mulscc %%g1,%3,%%g1\n\
|
|
+ mulscc %%g1,%3,%%g1\n\
|
|
+ mulscc %%g1,%3,%%g1\n\
|
|
+ mulscc %%g1,%3,%%g1\n\
|
|
+ mulscc %%g1,%3,%%g1\n\
|
|
+ mulscc %%g1,%3,%%g1\n\
|
|
+ mulscc %%g1,%3,%%g1\n\
|
|
+ mulscc %%g1,%3,%%g1\n\
|
|
+ mulscc %%g1,%3,%%g1\n\
|
|
+ mulscc %%g1,%3,%%g1\n\
|
|
+ mulscc %%g1,%3,%%g1\n\
|
|
+ mulscc %%g1,%3,%%g1\n\
|
|
+ mulscc %%g1,%3,%%g1\n\
|
|
+ mulscc %%g1,0,%%g1\n\
|
|
+ add %%g1,%%g2,%0\n\
|
|
rd %%y,%1" \
|
|
: "=r" ((USItype)(w1)), \
|
|
"=r" ((USItype)(w0)) \
|
|
@@ -1153,7 +1153,7 @@
|
|
|
|
#if defined (__vax__) && W_TYPE_SIZE == 32
|
|
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
|
|
- __asm__ ("addl2 %5,%1
|
|
+ __asm__ ("addl2 %5,%1 \n\
|
|
adwc %3,%0" \
|
|
: "=g" ((USItype)(sh)), \
|
|
"=&g" ((USItype)(sl)) \
|
|
@@ -1162,7 +1162,7 @@
|
|
"%1" ((USItype)(al)), \
|
|
"g" ((USItype)(bl)))
|
|
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
|
|
- __asm__ ("subl2 %5,%1
|
|
+ __asm__ ("subl2 %5,%1 \n\
|
|
sbwc %3,%0" \
|
|
: "=g" ((USItype)(sh)), \
|
|
"=&g" ((USItype)(sl)) \
|