947c9874a1
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. WWW: http://www.clifford.at/yosys/ PR: 227591 Submitted by: Johnny Sorocil <jsorocil@gmail.com> Differential Revision: https://reviews.freebsd.org/D15632
86 lines
2.8 KiB
Text
86 lines
2.8 KiB
Text
bin/yosys
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bin/yosys-config
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bin/yosys-filterlib
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bin/yosys-smtbmc
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%%DATADIR%%/achronix/speedster22i/cells_map.v
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%%DATADIR%%/achronix/speedster22i/cells_sim.v
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%%DATADIR%%/adff2dff.v
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%%DATADIR%%/cells.lib
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%%DATADIR%%/coolrunner2/cells_latch.v
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%%DATADIR%%/coolrunner2/cells_sim.v
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%%DATADIR%%/coolrunner2/tff_extract.v
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%%DATADIR%%/coolrunner2/xc2_dff.lib
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%%DATADIR%%/dff2ff.v
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%%DATADIR%%/gowin/cells_map.v
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%%DATADIR%%/gowin/cells_sim.v
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%%DATADIR%%/greenpak4/cells_blackbox.v
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%%DATADIR%%/greenpak4/cells_latch.v
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%%DATADIR%%/greenpak4/cells_map.v
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%%DATADIR%%/greenpak4/cells_sim_ams.v
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%%DATADIR%%/greenpak4/cells_sim_digital.v
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%%DATADIR%%/greenpak4/cells_sim_wip.v
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%%DATADIR%%/greenpak4/cells_sim.v
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%%DATADIR%%/greenpak4/gp_dff.lib
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%%DATADIR%%/ice40/arith_map.v
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%%DATADIR%%/ice40/brams_init1.vh
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%%DATADIR%%/ice40/brams_init2.vh
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%%DATADIR%%/ice40/brams_init3.vh
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%%DATADIR%%/ice40/brams_map.v
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%%DATADIR%%/ice40/brams.txt
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%%DATADIR%%/ice40/cells_map.v
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%%DATADIR%%/ice40/cells_sim.v
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%%DATADIR%%/ice40/latches_map.v
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%%DATADIR%%/include/backends/ilang/ilang_backend.h
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%%DATADIR%%/include/frontends/ast/ast.h
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%%DATADIR%%/include/kernel/celledges.h
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%%DATADIR%%/include/kernel/celltypes.h
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%%DATADIR%%/include/kernel/consteval.h
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%%DATADIR%%/include/kernel/hashlib.h
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%%DATADIR%%/include/kernel/log.h
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%%DATADIR%%/include/kernel/macc.h
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%%DATADIR%%/include/kernel/modtools.h
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%%DATADIR%%/include/kernel/register.h
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%%DATADIR%%/include/kernel/rtlil.h
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%%DATADIR%%/include/kernel/satgen.h
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%%DATADIR%%/include/kernel/sigtools.h
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%%DATADIR%%/include/kernel/utils.h
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%%DATADIR%%/include/kernel/yosys.h
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%%DATADIR%%/include/libs/ezsat/ezminisat.h
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%%DATADIR%%/include/libs/ezsat/ezsat.h
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%%DATADIR%%/include/libs/sha1/sha1.h
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%%DATADIR%%/include/passes/fsm/fsmdata.h
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%%DATADIR%%/intel/a10gx/cells_map.v
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%%DATADIR%%/intel/a10gx/cells_sim.v
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%%DATADIR%%/intel/common/altpll_bb.v
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%%DATADIR%%/intel/common/brams_map.v
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%%DATADIR%%/intel/common/brams.txt
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%%DATADIR%%/intel/common/m9k_bb.v
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%%DATADIR%%/intel/cyclone10/cells_map.v
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%%DATADIR%%/intel/cyclone10/cells_sim.v
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%%DATADIR%%/intel/cycloneiv/cells_map.v
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%%DATADIR%%/intel/cycloneiv/cells_sim.v
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%%DATADIR%%/intel/cycloneive/cells_map.v
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%%DATADIR%%/intel/cycloneive/cells_sim.v
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%%DATADIR%%/intel/cyclonev/cells_map.v
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%%DATADIR%%/intel/cyclonev/cells_sim.v
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%%DATADIR%%/intel/max10/cells_map.v
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%%DATADIR%%/intel/max10/cells_sim.v
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%%DATADIR%%/pmux2mux.v
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%%DATADIR%%/python3/smtio.py
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%%DATADIR%%/simcells.v
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%%DATADIR%%/simlib.v
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%%DATADIR%%/techmap.v
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%%DATADIR%%/xilinx/arith_map.v
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%%DATADIR%%/xilinx/brams_bb.v
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%%DATADIR%%/xilinx/brams_init_%%PYTHON_SUFFIX%%.vh
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%%DATADIR%%/xilinx/brams_init_16.vh
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%%DATADIR%%/xilinx/brams_init_18.vh
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%%DATADIR%%/xilinx/brams_init_32.vh
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%%DATADIR%%/xilinx/brams_map.v
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%%DATADIR%%/xilinx/brams.txt
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%%DATADIR%%/xilinx/cells_map.v
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%%DATADIR%%/xilinx/cells_sim.v
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%%DATADIR%%/xilinx/cells_xtra.v
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%%DATADIR%%/xilinx/drams_map.v
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%%DATADIR%%/xilinx/drams.txt
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%%DATADIR%%/xilinx/lut2lut.v
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