19 lines
412 B
Makefile
19 lines
412 B
Makefile
# Created by: Ying-Chieh Liao <ijliao@FreeBSD.org>
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PORTNAME= iverilog
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PORTVERSION= 11.0
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CATEGORIES= cad
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MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v11/
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DISTNAME= verilog-${PORTVERSION}
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MAINTAINER= zeising@FreeBSD.org
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COMMENT= Verilog simulation and synthesis tool
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LICENSE= GPLv2
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GNU_CONFIGURE= yes
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CONFIGURE_ARGS= --disable-suffix
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USES= bison compiler:c++11-lang gmake readline
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.include <bsd.port.mk>
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