47300ad9f4
* Add firmware for the YiXingDianZi MDSO (VID/PID: 1D50:608E). * Sainsmart DDS120: Fix the 1kHz reference signal. * Hantek 6022BL: Fix the voltage range selection (bug #1360). * Allow LA captures at 48MHz samplerate (as long as bus conditions permit). * Updated build requirement: sdcc >= 3.4.0 (bug #1326). * Fix a build issue with sdcc >= 3.9.0 (bug #1404). * Bump the firmware version (major.minor) to 1.4. This version is backwards-compatible and doesn't require host-side (libsigrok) changes.
48 lines
1.2 KiB
Makefile
48 lines
1.2 KiB
Makefile
# Created by: Uffe Jakobsen <uffe@uffe.org>
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# $FreeBSD$
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PORTNAME= firmware
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PORTVERSION= 0.1.7
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CATEGORIES= science
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MASTER_SITES= http://sigrok.org/download/binary/${PKGNAMEPREFIX}${PORTNAME}${PKGNAMESUFFIX}/
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PKGNAMEPREFIX= sigrok-
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PKGNAMESUFFIX= -fx2lafw
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DISTNAME= ${PKGNAMEPREFIX}${PORTNAME}${PKGNAMESUFFIX}-bin-${PORTVERSION}
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MAINTAINER= bsam@FreeBSD.org
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COMMENT= Cypress FX2 firmware for hardware logic analyzers
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LICENSE= GPLv2
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NO_BUILD= yes
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FW_FILES= fx2lafw-braintechnology-usb-lps.fw \
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fx2lafw-cwav-usbeeax.fw \
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fx2lafw-cwav-usbeedx.fw \
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fx2lafw-cwav-usbeesx.fw \
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fx2lafw-cwav-usbeezx.fw \
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fx2lafw-cypress-fx2.fw \
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fx2lafw-hantek-6022be.fw \
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fx2lafw-hantek-6022bl.fw \
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fx2lafw-sainsmart-dds120.fw \
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fx2lafw-saleae-logic.fw \
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fx2lafw-sigrok-fx2-16ch.fw \
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fx2lafw-sigrok-fx2-8ch.fw
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PORTDOCS= README NEWS
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PLIST_FILES= ${FW_FILES:S,^,share/sigrok-firmware/,}
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OPTIONS_DEFINE= DOCS
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do-install:
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@${MKDIR} ${STAGEDIR}${DOCSDIR}
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.for docfile in README NEWS
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${INSTALL_DATA} ${WRKSRC}/${docfile} ${STAGEDIR}${DOCSDIR}
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.endfor
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@${MKDIR} ${STAGEDIR}${PREFIX}/share/sigrok-firmware
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.for fwfile in ${FW_FILES}
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${INSTALL_DATA} ${WRKSRC}/${fwfile} \
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${STAGEDIR}${PREFIX}/share/sigrok-firmware/
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.endfor
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.include <bsd.port.mk>
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