241 lines
8.2 KiB
C
241 lines
8.2 KiB
C
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/*
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* driver for ENE KB3926 B/C/D CIR (also known as ENE0100/ENE0200/ENE0201)
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*
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* Copyright (C) 2010 Maxim Levitsky <maximlevitsky@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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* USA
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*/
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#include <linux/spinlock.h>
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#include <media/lirc.h>
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#include <media/lirc_dev.h>
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/* hardware address */
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#define ENE_STATUS 0 /* hardware status - unused */
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#define ENE_ADDR_HI 1 /* hi byte of register address */
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#define ENE_ADDR_LO 2 /* low byte of register address */
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#define ENE_IO 3 /* read/write window */
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#define ENE_MAX_IO 4
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/* 8 bytes of samples, divided in 2 halfs*/
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#define ENE_SAMPLE_BUFFER 0xF8F0 /* regular sample buffer */
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#define ENE_SAMPLE_SPC_MASK 0x80 /* sample is space */
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#define ENE_SAMPLE_VALUE_MASK 0x7F
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#define ENE_SAMPLE_OVERFLOW 0x7F
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#define ENE_SAMPLES_SIZE 4
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/* fan input sample buffer */
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#define ENE_SAMPLE_BUFFER_FAN 0xF8FB /* this buffer holds high byte of */
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/* each sample of normal buffer */
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#define ENE_FAN_SMPL_PULS_MSK 0x8000 /* this bit of combined sample */
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/* if set, says that sample is pulse */
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#define ENE_FAN_VALUE_MASK 0x0FFF /* mask for valid bits of the value */
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/* first firmware register */
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#define ENE_FW1 0xF8F8
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#define ENE_FW1_ENABLE 0x01 /* enable fw processing */
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#define ENE_FW1_TXIRQ 0x02 /* TX interrupt pending */
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#define ENE_FW1_WAKE 0x40 /* enable wake from S3 */
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#define ENE_FW1_IRQ 0x80 /* enable interrupt */
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/* second firmware register */
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#define ENE_FW2 0xF8F9
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#define ENE_FW2_BUF_HIGH 0x01 /* which half of the buffer to read */
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#define ENE_FW2_IRQ_CLR 0x04 /* clear this on IRQ */
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#define ENE_FW2_GP40_AS_LEARN 0x08 /* normal input is used as */
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/* learning input */
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#define ENE_FW2_FAN_AS_NRML_IN 0x40 /* fan is used as normal input */
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#define ENE_FW2_LEARNING 0x80 /* hardware supports learning and TX */
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/* transmitter ports */
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#define ENE_TX_PORT2 0xFC01 /* this enables one or both */
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#define ENE_TX_PORT2_EN 0x20 /* TX ports */
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#define ENE_TX_PORT1 0xFC08
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#define ENE_TX_PORT1_EN 0x02
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/* IRQ registers block (for revision B) */
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#define ENEB_IRQ 0xFD09 /* IRQ number */
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#define ENEB_IRQ_UNK1 0xFD17 /* unknown setting = 1 */
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#define ENEB_IRQ_STATUS 0xFD80 /* irq status */
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#define ENEB_IRQ_STATUS_IR 0x20 /* IR irq */
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/* fan as input settings - only if learning capable */
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#define ENE_FAN_AS_IN1 0xFE30 /* fan init reg 1 */
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#define ENE_FAN_AS_IN1_EN 0xCD
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#define ENE_FAN_AS_IN2 0xFE31 /* fan init reg 2 */
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#define ENE_FAN_AS_IN2_EN 0x03
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#define ENE_SAMPLE_PERIOD_FAN 61 /* fan input has fixed sample period */
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/* IRQ registers block (for revision C,D) */
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#define ENEC_IRQ 0xFE9B /* new irq settings register */
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#define ENEC_IRQ_MASK 0x0F /* irq number mask */
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#define ENEC_IRQ_UNK_EN 0x10 /* always enabled */
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#define ENEC_IRQ_STATUS 0x20 /* irq status and ACK */
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/* CIR block settings */
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#define ENE_CIR_CONF1 0xFEC0
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#define ENE_CIR_CONF1_TX_CLEAR 0x01 /* clear that on revC */
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/* while transmitting */
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#define ENE_CIR_CONF1_RX_ON 0x07 /* normal reciever enabled */
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#define ENE_CIR_CONF1_LEARN1 0x08 /* enabled on learning mode */
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#define ENE_CIR_CONF1_TX_ON 0x30 /* enabled on transmit */
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#define ENE_CIR_CONF1_TX_CARR 0x80 /* send TX carrier or not */
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#define ENE_CIR_CONF2 0xFEC1 /* unknown setting = 0 */
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#define ENE_CIR_CONF2_LEARN2 0x10 /* set on enable learning */
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#define ENE_CIR_CONF2_GPIO40DIS 0x20 /* disable input via gpio40 */
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#define ENE_CIR_SAMPLE_PERIOD 0xFEC8 /* sample period in us */
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#define ENE_CIR_SAMPLE_OVERFLOW 0x80 /* interrupt on overflows if set */
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/* Two byte tx buffer */
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#define ENE_TX_INPUT1 0xFEC9
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#define ENE_TX_INPUT2 0xFECA
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#define ENE_TX_PULSE_MASK 0x80 /* Transmitted sample is pulse */
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#define ENE_TX_SMLP_MASK 0x7F
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#define ENE_TX_SMPL_PERIOD 50 /* transmit sample period - fixed */
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/* Unknown TX setting - TX sample period ??? */
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#define ENE_TX_UNK1 0xFECB /* set to 0x63 */
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/* Current recieved carrier period */
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#define ENE_RX_CARRIER 0xFECC /* RX period (500 ns) */
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#define ENE_RX_CARRIER_VALID 0x80 /* Register content valid */
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/* TX period (1/carrier) */
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#define ENE_TX_PERIOD 0xFECE /* TX period (500 ns) */
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#define ENE_TX_PERIOD_UNKBIT 0x80 /* This bit set on transmit*/
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#define ENE_TX_PERIOD_PULSE 0xFECF /* TX pulse period (500 ns)*/
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/* Hardware versions */
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#define ENE_HW_VERSION 0xFF00 /* hardware revision */
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#define ENE_HW_UNK 0xFF1D
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#define ENE_HW_UNK_CLR 0x04
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#define ENE_HW_VER_MAJOR 0xFF1E /* chip version */
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#define ENE_HW_VER_MINOR 0xFF1F
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#define ENE_HW_VER_OLD 0xFD00
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/* Normal/Learning carrier ranges - only valid if we have learning input*/
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/* TODO: test */
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#define ENE_NORMAL_RX_LOW 34
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#define ENE_NORMAL_RX_HI 38
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/* Tx carrier range */
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/* Hardware might be able to do more, but this range is enough for
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all purposes */
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#define ENE_TX_PERIOD_MAX 32 /* corresponds to 29.4 kHz */
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#define ENE_TX_PERIOD_MIN 16 /* corrsponds to 62.5 kHz */
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/* Minimal and maximal gaps */
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/* Normal case:
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Minimal gap is 0x7F * sample period
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Maximum gap depends on hardware.
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For KB3926B, it is unlimited, for newer models its around
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250000, after which HW stops sending samples, and that is
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not possible to change */
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/* Fan case:
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Both minimal and maximal gaps are same, and equal to 0xFFF * 0x61
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And there is nothing to change this setting
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*/
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#define ENE_MAXGAP 250000
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#define ENE_MINGAP (127 * sample_period)
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/******************************************************************************/
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#define ENE_DRIVER_NAME "enecir"
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#define ENE_TXBUF_SIZE (500 * sizeof(int)) /* 500 samples (arbitary) */
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#define ENE_IRQ_RX 1
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#define ENE_IRQ_TX 2
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#define ENE_HW_B 1 /* 3926B */
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#define ENE_HW_C 2 /* 3926C */
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#define ENE_HW_D 3 /* 3926D */
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#define ene_printk(level, text, ...) \
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printk(level ENE_DRIVER_NAME ": " text, ## __VA_ARGS__)
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#define ene_dbg(text, ...) \
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if (debug) \
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printk(KERN_DEBUG \
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ENE_DRIVER_NAME ": " text "\n" , ## __VA_ARGS__)
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#define ene_dbg_verbose(text, ...) \
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if (debug > 1) \
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printk(KERN_DEBUG \
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ENE_DRIVER_NAME ": " text "\n" , ## __VA_ARGS__)
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struct ene_device {
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struct pnp_dev *pnp_dev;
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struct lirc_driver *lirc_driver;
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int in_use;
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/* hw IO settings */
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unsigned long hw_io;
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int irq;
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spinlock_t hw_lock;
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/* HW features */
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int hw_revision; /* hardware revision */
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int hw_learning_and_tx_capable; /* learning capable */
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int hw_gpio40_learning; /* gpio40 is learning */
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int hw_fan_as_normal_input; /* fan input is used as */
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/* regular input */
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/* HW state*/
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int rx_pointer; /* hw pointer to rx buffer */
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int rx_fan_input_inuse; /* is fan input in use for rx*/
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int tx_reg; /* current reg used for TX */
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u8 saved_conf1; /* saved FEC0 reg */
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int learning_enabled; /* learning input enabled */
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/* RX sample handling */
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int rx_sample; /* current recieved sample */
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int rx_sample_pulse; /* recieved sample is pulse */
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int rx_idle; /* idle mode for RX activated */
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struct timeval rx_gap_start; /* time of start of idle */
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int rx_timeout; /* time in ms of RX timeout */
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int rx_send_timeout_packet; /* do we send RX timeout */
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int rx_timeout_sent; /* we sent the timeout packet */
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int rx_carrier_sense; /* sense carrier */
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/* TX sample handling */
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unsigned int tx_sample; /* current sample for TX */
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int tx_sample_pulse; /* current sample is pulse */
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/* TX buffer */
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int tx_buffer[ENE_TXBUF_SIZE]; /* input samples buffer*/
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int tx_pos; /* position in that bufer */
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int tx_len; /* current len of tx buffer */
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int tx_underway; /* TX is under way*/
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int tx_done; /* done transmitting */
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/* one more sample pending*/
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struct completion tx_complete; /* TX completion */
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struct timer_list tx_sim_timer;
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/*TX settings */
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int tx_period;
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int tx_duty_cycle;
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int transmitter_mask;
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};
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