2009-10-15 00:13:45 +02:00
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config STMMAC_ETH
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tristate "STMicroelectronics 10/100/1000 Ethernet driver"
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2011-05-16 09:05:19 +02:00
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depends on HAS_IOMEM
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2011-09-14 23:23:14 +02:00
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select NET_CORE
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2009-10-15 00:13:45 +02:00
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select MII
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select PHYLIB
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2010-03-31 23:44:03 +02:00
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select CRC32
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2011-05-16 09:05:19 +02:00
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---help---
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2010-01-07 00:07:22 +01:00
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This is the driver for the Ethernet IPs are built around a
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2010-08-23 22:40:41 +02:00
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Synopsys IP Core and only tested on the STMicroelectronics
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2010-01-07 00:07:22 +01:00
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platforms.
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2009-10-15 00:13:45 +02:00
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if STMMAC_ETH
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2011-09-01 23:51:39 +02:00
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config STMMAC_DEBUG_FS
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bool "Enable monitoring via sysFS "
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default n
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depends on STMMAC_ETH && DEBUG_FS
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-- help
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2011-09-01 23:51:41 +02:00
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The stmmac entry in /sys reports DMA TX/RX rings
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or (if supported) the HW cap register.
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2011-09-01 23:51:39 +02:00
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2009-10-15 00:13:45 +02:00
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config STMMAC_DA
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bool "STMMAC DMA arbitration scheme"
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default n
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2011-05-16 09:05:19 +02:00
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---help---
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2009-10-15 00:13:45 +02:00
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Selecting this option, rx has priority over Tx (only for Giga
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Ethernet device).
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By default, the DMA arbitration scheme is based on Round-robin
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(rx:tx priority is 1:1).
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config STMMAC_TIMER
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bool "STMMAC Timer optimisation"
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default n
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2010-08-27 05:32:02 +02:00
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depends on RTC_HCTOSYS_DEVICE
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2011-05-16 09:05:19 +02:00
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---help---
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2009-10-15 00:13:45 +02:00
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Use an external timer for mitigating the number of network
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2010-01-07 00:07:22 +01:00
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interrupts. Currently, for SH architectures, it is possible
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to use the TMU channel 2 and the SH-RTC device.
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2009-10-15 00:13:45 +02:00
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choice
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prompt "Select Timer device"
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depends on STMMAC_TIMER
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config STMMAC_TMU_TIMER
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bool "TMU channel 2"
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depends on CPU_SH4
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2011-05-16 09:05:19 +02:00
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---help---
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2009-10-15 00:13:45 +02:00
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config STMMAC_RTC_TIMER
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bool "Real time clock"
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depends on RTC_CLASS
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2011-05-16 09:05:19 +02:00
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---help---
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2009-10-15 00:13:45 +02:00
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endchoice
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2011-10-18 02:01:24 +02:00
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choice
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prompt "Select the DMA TX/RX descriptor operating modes"
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depends on STMMAC_ETH
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---help---
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This driver supports DMA descriptor to operate both in dual buffer
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(RING) and linked-list(CHAINED) mode. In RING mode each descriptor
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points to two data buffer pointers whereas in CHAINED mode they
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points to only one data buffer pointer.
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config STMMAC_RING
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bool "Enable Descriptor Ring Mode"
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config STMMAC_CHAINED
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bool "Enable Descriptor Chained Mode"
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endchoice
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2009-10-15 00:13:45 +02:00
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endif
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