linux-hardened/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt

DT bindings for the R-/SH-Mobile irqpin controller

Required properties:

- compatible: has to be "renesas,intc-irqpin-<soctype>", "renesas,intc-irqpin"
  as fallback.
  Examples with soctypes are:
    - "renesas,intc-irqpin-r8a7740" (R-Mobile A1)
    - "renesas,intc-irqpin-r8a7778" (R-Car M1A)
    - "renesas,intc-irqpin-r8a7779" (R-Car H1)
    - "renesas,intc-irqpin-sh73a0" (SH-Mobile AG5)

- reg: Base address and length of each register bank used by the external
  IRQ pins driven by the interrupt controller hardware module. The base
  addresses, length and number of required register banks varies with soctype.

- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
  interrupts.txt in this directory

Optional properties:

- any properties, listed in interrupts.txt, and any standard resource allocation
  properties
- sense-bitfield-width: width of a single sense bitfield in the SENSE register,
  if different from the default 4 bits
- control-parent: disable and enable interrupts on the parent interrupt
  controller, needed for some broken implementations
irqchip: renesas-intc-irqpin: DT binding for sense bitfield width Most Renesas irqpin controllers have 4-bit sense fields, however, some have different widths. This patch adds a DT binding to optionally specify such non-standard values. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> 2013-06-13 11:23:38 +02:00			`DT bindings for the R-/SH-Mobile irqpin controller`

			`Required properties:`

irqchip: renesas-intc-irqpin: Document SoC-specific bindings The documentation only mentioned the generic fallback compatible property. Add the missing SoC-specific compatible properties, which are already in use. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Simon Horman <horms+renesas@verge.net.au> Link: https://lkml.kernel.org/r/1409212800-4957-1-git-send-email-geert+renesas@glider.be Signed-off-by: Jason Cooper <jason@lakedaemon.net> 2014-08-28 09:59:58 +02:00			`- compatible: has to be "renesas,intc-irqpin-<soctype>", "renesas,intc-irqpin"`
			`as fallback.`
			`Examples with soctypes are:`
			`- "renesas,intc-irqpin-r8a7740" (R-Mobile A1)`
			`- "renesas,intc-irqpin-r8a7778" (R-Car M1A)`
			`- "renesas,intc-irqpin-r8a7779" (R-Car H1)`
			`- "renesas,intc-irqpin-sh73a0" (SH-Mobile AG5)`
irqchip: renesas-intc-irqpin: r8a7779 IRLM setup support Add r8a7779 specific support for IRLM bit configuration in the INTC-IRQPIN driver. Without this code we need special workaround code in arch/arm/mach-shmobile. The IRLM bit for the INTC hardware exists on various older SH-based SoCs and is used to select between two modes for the external interrupt pins IRQ0 to IRQ3: IRLM = 0: (default from reset on r8a7779) In this mode the pins IRQ0 to IRQ3 are used together to give a value between 0 and 15 to the SoC. External logic is required for masking. This mode is not supported by the INTC-IRQPIN driver. IRLM = 1: (needs this patch or configuration elsewhere) In this mode IRQ0 to IRQ3 operate as 4 individual external interrupt pins. In this mode the SMSC ethernet chip can be used via IRQ1 on r8a7779 Marzen. This mode is the only supported mode by the INTC-IRQPIN driver. For this patch to work the r8a7779 DTS needs to pass the ICR0 register as the last register bank. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: horms@verge.net.au Cc: jason@lakedaemon.net Link: http://lkml.kernel.org/r/20141203121803.5936.35881.sendpatchset@w520 Signed-off-by: Thomas Gleixner <tglx@linutronix.de> 2014-12-03 13:18:03 +01:00
			`- reg: Base address and length of each register bank used by the external`
			`IRQ pins driven by the interrupt controller hardware module. The base`
			`addresses, length and number of required register banks varies with soctype.`

irqchip: renesas-intc-irqpin: DT binding for sense bitfield width Most Renesas irqpin controllers have 4-bit sense fields, however, some have different widths. This patch adds a DT binding to optionally specify such non-standard values. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> 2013-06-13 11:23:38 +02:00			`- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in`
			`interrupts.txt in this directory`

			`Optional properties:`

			`- any properties, listed in interrupts.txt, and any standard resource allocation`
			`properties`
			`- sense-bitfield-width: width of a single sense bitfield in the SENSE register,`
			`if different from the default 4 bits`
ARM: shmobile: irqpin: add a DT property to enable masking on parent To disable spurious interrupts, that get triggered on certain hardware, the irqpin driver masks them on the parent interrupt controller. To specify such broken devices a .control_parent parameter can be provided in the platform data. In the DT case we need a property, to do the same. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> 2013-06-19 07:53:09 +02:00			`- control-parent: disable and enable interrupts on the parent interrupt`
			`controller, needed for some broken implementations`