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ARM: mm: improve do_ldrd_abort macro

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Improve the do_ldrd_abort macro code - firstly, it inefficiently checks
for the LDRD encoding by doing a multi-stage test of various bits.  This
can be simplified by generating a mask, bitmasking the instruction and
then comparing the result.

Secondly, we want to be able to test the result rather than branching
to do_DataAbort, so remove the branch at the end and rename the macro
to 'teq_ldrd' to reflect it's new usage.  teq_ldrd macro returns 'eq'
if the instruction was a LDRD.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King 2015-08-25 14:59:15 +01:00
parent 1fb6755f16
commit 08446b129b
4 changed files with 11 additions and 11 deletions
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3
arch/arm/mm/abort-ev5t.S
View file

@ -22,7 +22,8 @@ ENTRY(v5t_early_abort)
do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3 do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
ldreq r3, [r4] @ read aborted ARM instruction ldreq r3, [r4] @ read aborted ARM instruction
bic r1, r1, #1 << 11 @ clear bits 11 of FSR bic r1, r1, #1 << 11 @ clear bits 11 of FSR
do_ldrd_abort tmp=ip, insn=r3 teq_ldrd tmp=ip, insn=r3 @ insn was LDRD?
beq do_DataAbort @ yes
tst r3, #1 << 20 @ check write tst r3, #1 << 20 @ check write
orreq r1, r1, #1 << 11 orreq r1, r1, #1 << 11
b do_DataAbort b do_DataAbort

3
arch/arm/mm/abort-ev5tj.S
View file

@ -24,7 +24,8 @@ ENTRY(v5tj_early_abort)
bne do_DataAbort bne do_DataAbort
do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3 do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
ldreq r3, [r4] @ read aborted ARM instruction ldreq r3, [r4] @ read aborted ARM instruction
do_ldrd_abort tmp=ip, insn=r3 teq_ldrd tmp=ip, insn=r3 @ insn was LDRD?
beq do_DataAbort @ yes
tst r3, #1 << 20 @ L = 0 -> write tst r3, #1 << 20 @ L = 0 -> write
orreq r1, r1, #1 << 11 @ yes. orreq r1, r1, #1 << 11 @ yes.
b do_DataAbort b do_DataAbort

3
arch/arm/mm/abort-ev6.S
View file

@ -34,7 +34,8 @@ ENTRY(v6_early_abort)
ldr r3, [r4] @ read aborted ARM instruction ldr r3, [r4] @ read aborted ARM instruction
ARM_BE8(rev r3, r3) ARM_BE8(rev r3, r3)
do_ldrd_abort tmp=ip, insn=r3 teq_ldrd tmp=ip, insn=r3 @ insn was LDRD?
beq do_DataAbort @ yes
tst r3, #1 << 20 @ L = 0 -> write tst r3, #1 << 20 @ L = 0 -> write
orreq r1, r1, #1 << 11 @ yes. orreq r1, r1, #1 << 11 @ yes.
#endif #endif

13
arch/arm/mm/abort-macro.S
View file

@ -29,12 +29,9 @@ not_thumb:
* [7:4] == 1101 * [7:4] == 1101
* [20] == 0 * [20] == 0
*/ */
.macro do_ldrd_abort, tmp, insn .macro teq_ldrd, tmp, insn
tst \insn, #0x0e100000 @ [27:25,20] == 0 mov \tmp, #0x0e100000
bne not_ldrd orr \tmp, #0x000000f0
and \tmp, \insn, #0x000000f0 @ [7:4] == 1101 and \tmp, \insn, \tmp
cmp \tmp, #0x000000d0 teq \tmp, #0x000000d0
beq do_DataAbort
not_ldrd:
.endm .endm