clocksource: orion: Use atomic access for shared registers
Replace the driver-specific thread-safe shared register API by the recently introduced atomic_io_clear_set(). Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Willy Tarreau <w@1wt.eu> Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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1 changed files with 10 additions and 18 deletions
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@ -35,20 +35,6 @@
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#define ORION_ONESHOT_MAX 0xfffffffe
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static void __iomem *timer_base;
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static DEFINE_SPINLOCK(timer_ctrl_lock);
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/*
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* Thread-safe access to TIMER_CTRL register
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* (shared with watchdog timer)
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*/
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void orion_timer_ctrl_clrset(u32 clr, u32 set)
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{
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spin_lock(&timer_ctrl_lock);
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writel((readl(timer_base + TIMER_CTRL) & ~clr) | set,
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timer_base + TIMER_CTRL);
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spin_unlock(&timer_ctrl_lock);
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}
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EXPORT_SYMBOL(orion_timer_ctrl_clrset);
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/*
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* Free-running clocksource handling.
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@ -68,7 +54,8 @@ static int orion_clkevt_next_event(unsigned long delta,
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{
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/* setup and enable one-shot timer */
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writel(delta, timer_base + TIMER1_VAL);
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orion_timer_ctrl_clrset(TIMER1_RELOAD_EN, TIMER1_EN);
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atomic_io_modify(timer_base + TIMER_CTRL,
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TIMER1_RELOAD_EN | TIMER1_EN, TIMER1_EN);
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return 0;
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}
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@ -80,10 +67,13 @@ static void orion_clkevt_mode(enum clock_event_mode mode,
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/* setup and enable periodic timer at 1/HZ intervals */
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writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD);
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writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL);
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orion_timer_ctrl_clrset(0, TIMER1_RELOAD_EN | TIMER1_EN);
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atomic_io_modify(timer_base + TIMER_CTRL,
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TIMER1_RELOAD_EN | TIMER1_EN,
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TIMER1_RELOAD_EN | TIMER1_EN);
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} else {
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/* disable timer */
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orion_timer_ctrl_clrset(TIMER1_RELOAD_EN | TIMER1_EN, 0);
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atomic_io_modify(timer_base + TIMER_CTRL,
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TIMER1_RELOAD_EN | TIMER1_EN, 0);
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}
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}
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@ -131,7 +121,9 @@ static void __init orion_timer_init(struct device_node *np)
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/* setup timer0 as free-running clocksource */
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writel(~0, timer_base + TIMER0_VAL);
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writel(~0, timer_base + TIMER0_RELOAD);
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orion_timer_ctrl_clrset(0, TIMER0_RELOAD_EN | TIMER0_EN);
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atomic_io_modify(timer_base + TIMER_CTRL,
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TIMER0_RELOAD_EN | TIMER0_EN,
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TIMER0_RELOAD_EN | TIMER0_EN);
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clocksource_mmio_init(timer_base + TIMER0_VAL, "orion_clocksource",
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clk_get_rate(clk), 300, 32,
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clocksource_mmio_readl_down);
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