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Merge branch 'bcmring/removal' into next/cleanup2

Browse source 
From "Christian Daudt" <csd@broadcom.com>:

Remove mach-bcmring as this is no longer maintained or used.

Updated the removal with:
 - drop the edit to mach-types requested by Russell King
 - eliminate defconfig mod from patch 1 requested Olof Johansson

Also switched to using git send-email to avoid word-wrapping
problems

* bcmring/removal:
  ARM: Remove mach-bcmring

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2012-09-28 21:43:35 +02:00
commit 0b40b4b443
68 changed files with 42 additions and 15820 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

16
MAINTAINERS
View file

@ -658,22 +658,6 @@ W: http://www.linux4sam.org
S: Supported
F: arch/arm/mach-at91/
ARM/BCMRING ARM ARCHITECTURE
M: Jiandong Zheng <jdzheng@broadcom.com>
M: Scott Branden <sbranden@broadcom.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-bcmring
ARM/BCMRING MTD NAND DRIVER
M: Jiandong Zheng <jdzheng@broadcom.com>
M: Scott Branden <sbranden@broadcom.com>
L: linux-mtd@lists.infradead.org
S: Maintained
F: drivers/mtd/nand/bcm_umi_nand.c
F: drivers/mtd/nand/bcm_umi_bch.c
F: drivers/mtd/nand/nand_bcm_umi.h
ARM/CALXEDA HIGHBANK ARCHITECTURE
M: Rob Herring <rob.herring@calxeda.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

14
arch/arm/Kconfig
View file

@ -350,18 +350,6 @@ config ARCH_AT91
This enables support for systems based on Atmel
AT91RM9200 and AT91SAM9* processors.
config ARCH_BCMRING
bool "Broadcom BCMRING"
depends on MMU
select CPU_V6
select ARM_AMBA
select ARM_TIMER_SP804
select CLKDEV_LOOKUP
select GENERIC_CLOCKEVENTS
select ARCH_WANT_OPTIONAL_GPIOLIB
help
Support for Broadcom's BCMRing platform.
config ARCH_HIGHBANK
bool "Calxeda Highbank-based"
select ARCH_WANT_OPTIONAL_GPIOLIB
@ -1034,8 +1022,6 @@ source "arch/arm/mach-mvebu/Kconfig"
source "arch/arm/mach-at91/Kconfig"
source "arch/arm/mach-bcmring/Kconfig"
source "arch/arm/mach-clps711x/Kconfig"
source "arch/arm/mach-cns3xxx/Kconfig"

1
arch/arm/Makefile
View file

@ -136,7 +136,6 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
# Machine directory name. This list is sorted alphanumerically
# by CONFIG_* macro name.
machine-$(CONFIG_ARCH_AT91) := at91
machine-$(CONFIG_ARCH_BCMRING) := bcmring
machine-$(CONFIG_ARCH_CLPS711X) := clps711x
machine-$(CONFIG_ARCH_CNS3XXX) := cns3xxx
machine-$(CONFIG_ARCH_DAVINCI) := davinci

79
arch/arm/configs/bcmring_defconfig
View file

@ -1,79 +0,0 @@
CONFIG_EXPERIMENTAL=y
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_EXPERT=y
CONFIG_KALLSYMS_EXTRA_PASS=y
# CONFIG_HOTPLUG is not set
# CONFIG_ELF_CORE is not set
# CONFIG_EPOLL is not set
# CONFIG_SIGNALFD is not set
# CONFIG_TIMERFD is not set
# CONFIG_EVENTFD is not set
# CONFIG_AIO is not set
CONFIG_PERF_EVENTS=y
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_SLUB_DEBUG is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_BCMRING=y
CONFIG_BCM_ZRELADDR=0x8000
CONFIG_CPU_32v6K=y
CONFIG_NO_HZ=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set
CONFIG_UACCESS_WITH_MEMCPY=y
CONFIG_ZBOOT_ROM_TEXT=0x0e000000
CONFIG_ZBOOT_ROM_BSS=0x0ea00000
CONFIG_ZBOOT_ROM=y
CONFIG_NET=y
# CONFIG_WIRELESS is not set
CONFIG_MTD=y
CONFIG_MTD_CONCAT=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_GEOMETRY=y
# CONFIG_MTD_CFI_I2 is not set
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_VERIFY_WRITE=y
CONFIG_MTD_NAND_BCM_UMI=y
CONFIG_MTD_NAND_BCM_UMI_HWCS=y
# CONFIG_MISC_DEVICES is not set
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_CONSOLE_TRANSLATIONS is not set
# CONFIG_DEVKMEM is not set
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_LEGACY_PTY_COUNT=64
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
# CONFIG_VGA_CONSOLE is not set
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
# CONFIG_FILE_LOCKING is not set
# CONFIG_DNOTIFY is not set
# CONFIG_INOTIFY_USER is not set
# CONFIG_PROC_PAGE_MONITOR is not set
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_SUMMARY=y
CONFIG_JFFS2_FS_XATTR=y
# CONFIG_JFFS2_FS_SECURITY is not set
# CONFIG_NETWORK_FILESYSTEMS is not set
# CONFIG_ENABLE_WARN_DEPRECATED is not set
CONFIG_MAGIC_SYSRQ=y
CONFIG_HEADERS_CHECK=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_ARM_UNWIND is not set

19
arch/arm/mach-bcmring/Kconfig
View file

@ -1,19 +0,0 @@
choice
prompt "Processor selection in BCMRING family of devices"
depends on ARCH_BCMRING
default ARCH_BCM11107
config ARCH_FPGA11107
bool "FPGA11107"
config ARCH_BCM11107
bool "BCM11107"
endchoice
menu "BCMRING Options"
depends on ARCH_BCMRING
config BCM_ZRELADDR
hex "Compressed ZREL ADDR"
endmenu

8
arch/arm/mach-bcmring/Makefile
View file

@ -1,8 +0,0 @@
#
# Makefile for the linux kernel.
#
# Object file lists.
obj-y := arch.o mm.o irq.o clock.o core.o timer.o dma.o
obj-y += csp/

6
arch/arm/mach-bcmring/Makefile.boot
View file

@ -1,6 +0,0 @@
# Address where decompressor will be written and eventually executed.
#
# default to SDRAM
zreladdr-y += $(CONFIG_BCM_ZRELADDR)
params_phys-y := 0x00000800

199
arch/arm/mach-bcmring/arch.c
View file

@ -1,199 +0,0 @@
/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/spinlock.h>
#include <linux/module.h>
#include <linux/proc_fs.h>
#include <linux/sysctl.h>
#include <asm/irq.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/time.h>
#include <asm/pmu.h>
#include <asm/mach/arch.h>
#include <mach/dma.h>
#include <mach/hardware.h>
#include <mach/csp/mm_io.h>
#include <mach/csp/chipcHw_def.h>
#include <mach/csp/chipcHw_inline.h>
#include <cfg_global.h>
#include "core.h"
HW_DECLARE_SPINLOCK(arch)
HW_DECLARE_SPINLOCK(gpio)
#if defined(CONFIG_DEBUG_SPINLOCK)
EXPORT_SYMBOL(bcmring_gpio_reg_lock);
#endif
/* sysctl */
static int bcmring_arch_warm_reboot; /* do a warm reboot on hard reset */
static void bcmring_restart(char mode, const char *cmd)
{
printk("arch_reset:%c %x\n", mode, bcmring_arch_warm_reboot);
if (mode == 'h') {
/* Reboot configured in proc entry */
if (bcmring_arch_warm_reboot) {
printk("warm reset\n");
/* Issue Warm reset (do not reset ethernet switch, keep alive) */
chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_WARM);
} else {
/* Force reset of everything */
printk("force reset\n");
chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
}
} else {
/* Force reset of everything */
printk("force reset\n");
chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
}
}
static struct ctl_table_header *bcmring_sysctl_header;
static struct ctl_table bcmring_sysctl_warm_reboot[] = {
{
.procname = "warm",
.data = &bcmring_arch_warm_reboot,
.maxlen = sizeof(int),
.mode = 0644,
.proc_handler = proc_dointvec},
{}
};
static struct ctl_table bcmring_sysctl_reboot[] = {
{
.procname = "reboot",
.mode = 0555,
.child = bcmring_sysctl_warm_reboot},
{}
};
static struct resource nand_resource[] = {
[0] = {
.start = MM_ADDR_IO_NAND,
.end = MM_ADDR_IO_NAND + 0x1000 - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device nand_device = {
.name = "bcm-nand",
.id = -1,
.resource = nand_resource,
.num_resources = ARRAY_SIZE(nand_resource),
};
static struct resource pmu_resource = {
.start = IRQ_PMUIRQ,
.end = IRQ_PMUIRQ,
.flags = IORESOURCE_IRQ,
};
static struct platform_device pmu_device = {
.name = "arm-pmu",
.id = ARM_PMU_DEVICE_CPU,
.resource = &pmu_resource,
.num_resources = 1,
};
static struct platform_device *devices[] __initdata = {
&nand_device,
&pmu_device,
};
/****************************************************************************
*
* Called from the customize_machine function in arch/arm/kernel/setup.c
*
* The customize_machine function is tagged as an arch_initcall
* (see include/linux/init.h for the order that the various init sections
* are called in.
*
*****************************************************************************/
static void __init bcmring_init_machine(void)
{
bcmring_sysctl_header = register_sysctl_table(bcmring_sysctl_reboot);
/* Enable spread spectrum */
chipcHw_enableSpreadSpectrum();
platform_add_devices(devices, ARRAY_SIZE(devices));
bcmring_amba_init();
dma_init();
}
/****************************************************************************
*
* Called from setup_arch (in arch/arm/kernel/setup.c) to fixup any tags
* passed in by the boot loader.
*
*****************************************************************************/
static void __init bcmring_fixup(struct tag *t, char **cmdline,
struct meminfo *mi) {
#ifdef CONFIG_BLK_DEV_INITRD
printk(KERN_NOTICE "bcmring_fixup\n");
t->hdr.tag = ATAG_CORE;
t->hdr.size = tag_size(tag_core);
t->u.core.flags = 0;
t->u.core.pagesize = PAGE_SIZE;
t->u.core.rootdev = 31 << 8 | 0;
t = tag_next(t);
t->hdr.tag = ATAG_MEM;
t->hdr.size = tag_size(tag_mem32);
t->u.mem.start = CFG_GLOBAL_RAM_BASE;
t->u.mem.size = CFG_GLOBAL_RAM_SIZE;
t = tag_next(t);
t->hdr.tag = ATAG_NONE;
t->hdr.size = 0;
#endif
}
/****************************************************************************
*
* Machine Description
*
*****************************************************************************/
MACHINE_START(BCMRING, "BCMRING")
/* Maintainer: Broadcom Corporation */
.fixup = bcmring_fixup,
.map_io = bcmring_map_io,
.init_early = bcmring_init_early,
.init_irq = bcmring_init_irq,
.timer = &bcmring_timer,
.init_machine = bcmring_init_machine,
.restart = bcmring_restart,
MACHINE_END

223
arch/arm/mach-bcmring/clock.c
View file

@ -1,223 +0,0 @@
/*****************************************************************************
* Copyright 2001 - 2009 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/string.h>
#include <linux/clk.h>
#include <linux/spinlock.h>
#include <linux/clkdev.h>
#include <mach/csp/hw_cfg.h>
#include <mach/csp/chipcHw_def.h>
#include <mach/csp/chipcHw_reg.h>
#include <mach/csp/chipcHw_inline.h>
#include "clock.h"
#define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY)
#define clk_is_pll1(x) ((x)->type & CLK_TYPE_PLL1)
#define clk_is_pll2(x) ((x)->type & CLK_TYPE_PLL2)
#define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE)
#define clk_is_bypassable(x) ((x)->type & CLK_TYPE_BYPASSABLE)
#define clk_is_using_xtal(x) ((x)->mode & CLK_MODE_XTAL)
static DEFINE_SPINLOCK(clk_lock);
static void __clk_enable(struct clk *clk)
{
if (!clk)
return;
/* enable parent clock first */
if (clk->parent)
__clk_enable(clk->parent);
if (clk->use_cnt++ == 0) {
if (clk_is_pll1(clk)) { /* PLL1 */
chipcHw_pll1Enable(clk->rate_hz, 0);
} else if (clk_is_pll2(clk)) { /* PLL2 */
chipcHw_pll2Enable(clk->rate_hz);
} else if (clk_is_using_xtal(clk)) { /* source is crystal */
if (!clk_is_primary(clk))
chipcHw_bypassClockEnable(clk->csp_id);
} else { /* source is PLL */
chipcHw_setClockEnable(clk->csp_id);
}
}
}
int clk_enable(struct clk *clk)
{
unsigned long flags;
if (!clk)
return -EINVAL;
spin_lock_irqsave(&clk_lock, flags);
__clk_enable(clk);
spin_unlock_irqrestore(&clk_lock, flags);
return 0;
}
EXPORT_SYMBOL(clk_enable);
static void __clk_disable(struct clk *clk)
{
if (!clk)
return;
BUG_ON(clk->use_cnt == 0);
if (--clk->use_cnt == 0) {
if (clk_is_pll1(clk)) { /* PLL1 */
chipcHw_pll1Disable();
} else if (clk_is_pll2(clk)) { /* PLL2 */
chipcHw_pll2Disable();
} else if (clk_is_using_xtal(clk)) { /* source is crystal */
if (!clk_is_primary(clk))
chipcHw_bypassClockDisable(clk->csp_id);
} else { /* source is PLL */
chipcHw_setClockDisable(clk->csp_id);
}
}
if (clk->parent)
__clk_disable(clk->parent);
}
void clk_disable(struct clk *clk)
{
unsigned long flags;
if (!clk)
return;
spin_lock_irqsave(&clk_lock, flags);
__clk_disable(clk);
spin_unlock_irqrestore(&clk_lock, flags);
}
EXPORT_SYMBOL(clk_disable);
unsigned long clk_get_rate(struct clk *clk)
{
if (!clk)
return 0;
return clk->rate_hz;
}
EXPORT_SYMBOL(clk_get_rate);
long clk_round_rate(struct clk *clk, unsigned long rate)
{
unsigned long flags;
unsigned long actual;
unsigned long rate_hz;
if (!clk)
return -EINVAL;
if (!clk_is_programmable(clk))
return -EINVAL;
if (clk->use_cnt)
return -EBUSY;
spin_lock_irqsave(&clk_lock, flags);
actual = clk->parent->rate_hz;
rate_hz = min(actual, rate);
spin_unlock_irqrestore(&clk_lock, flags);
return rate_hz;
}
EXPORT_SYMBOL(clk_round_rate);
int clk_set_rate(struct clk *clk, unsigned long rate)
{
unsigned long flags;
unsigned long actual;
unsigned long rate_hz;
if (!clk)
return -EINVAL;
if (!clk_is_programmable(clk))
return -EINVAL;
if (clk->use_cnt)
return -EBUSY;
spin_lock_irqsave(&clk_lock, flags);
actual = clk->parent->rate_hz;
rate_hz = min(actual, rate);
rate_hz = chipcHw_setClockFrequency(clk->csp_id, rate_hz);
clk->rate_hz = rate_hz;
spin_unlock_irqrestore(&clk_lock, flags);
return 0;
}
EXPORT_SYMBOL(clk_set_rate);
struct clk *clk_get_parent(struct clk *clk)
{
if (!clk)
return NULL;
return clk->parent;
}
EXPORT_SYMBOL(clk_get_parent);
int clk_set_parent(struct clk *clk, struct clk *parent)
{
unsigned long flags;
struct clk *old_parent;
if (!clk || !parent)
return -EINVAL;
if (!clk_is_primary(parent) || !clk_is_bypassable(clk))
return -EINVAL;
/* if more than one user, parent is not allowed */
if (clk->use_cnt > 1)
return -EBUSY;
if (clk->parent == parent)
return 0;
spin_lock_irqsave(&clk_lock, flags);
old_parent = clk->parent;
clk->parent = parent;
if (clk_is_using_xtal(parent))
clk->mode |= CLK_MODE_XTAL;
else
clk->mode &= (~CLK_MODE_XTAL);
/* if clock is active */
if (clk->use_cnt != 0) {
clk->use_cnt--;
/* enable clock with the new parent */
__clk_enable(clk);
/* disable the old parent */
__clk_disable(old_parent);
}
spin_unlock_irqrestore(&clk_lock, flags);
return 0;
}
EXPORT_SYMBOL(clk_set_parent);

33
arch/arm/mach-bcmring/clock.h
View file

@ -1,33 +0,0 @@
/*****************************************************************************
* Copyright 2001 - 2009 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
#include <mach/csp/chipcHw_def.h>
#define CLK_TYPE_PRIMARY 1 /* primary clock must NOT have a parent */
#define CLK_TYPE_PLL1 2 /* PPL1 */
#define CLK_TYPE_PLL2 4 /* PPL2 */
#define CLK_TYPE_PROGRAMMABLE 8 /* programmable clock rate */
#define CLK_TYPE_BYPASSABLE 16 /* parent can be changed */
#define CLK_MODE_XTAL 1 /* clock source is from crystal */
struct clk {
const char *name; /* clock name */
unsigned int type; /* clock type */
unsigned int mode; /* current mode */
volatile int use_bypass; /* indicate if it's in bypass mode */
chipcHw_CLOCK_e csp_id; /* clock ID for CSP CHIPC */
unsigned long rate_hz; /* clock rate in Hz */
unsigned int use_cnt; /* usage count */
struct clk *parent; /* parent clock */
};

228
arch/arm/mach-bcmring/core.c
View file

@ -1,228 +0,0 @@
/*
* derived from linux/arch/arm/mach-versatile/core.c
* linux/arch/arm/mach-bcmring/core.c
*
* Copyright (C) 1999 - 2003 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/* Portions copyright Broadcom 2008 */
#include <linux/init.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/amba/bus.h>
#include <linux/clkdev.h>
#include <mach/csp/mm_addr.h>
#include <mach/hardware.h>
#include <linux/io.h>
#include <asm/irq.h>
#include <asm/hardware/arm_timer.h>
#include <asm/hardware/timer-sp.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <cfg_global.h>
#include "clock.h"
#include <csp/secHw.h>
#include <mach/csp/secHw_def.h>
#include <mach/csp/chipcHw_inline.h>
#include <mach/csp/tmrHw_reg.h>
static AMBA_APB_DEVICE(uartA, "uartA", 0, MM_ADDR_IO_UARTA, {IRQ_UARTA}, NULL);
static AMBA_APB_DEVICE(uartB, "uartB", 0, MM_ADDR_IO_UARTB, {IRQ_UARTB}, NULL);
static struct clk pll1_clk = {
.name = "PLL1",
.type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL1,
.rate_hz = 2000000000,
.use_cnt = 7,
};
static struct clk uart_clk = {
.name = "UART",
.type = CLK_TYPE_PROGRAMMABLE,
.csp_id = chipcHw_CLOCK_UART,
.rate_hz = HW_CFG_UART_CLK_HZ,
.parent = &pll1_clk,
};
static struct clk dummy_apb_pclk = {
.name = "BUSCLK",
.type = CLK_TYPE_PRIMARY,
.mode = CLK_MODE_XTAL,
};
/* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically 150-166 MHz */
#if defined(CONFIG_ARCH_FPGA11107)
/* fpga cpu/bus are currently 30 times slower so scale frequency as well to */
/* slow down Linux's sense of time */
#define TIMER0_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30)
#define TIMER1_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30)
#define TIMER3_FREQUENCY_MHZ (tmrHw_HIGH_FREQUENCY_MHZ * 30)
#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30)
#else
#define TIMER0_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ
#define TIMER1_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ
#define TIMER3_FREQUENCY_MHZ tmrHw_HIGH_FREQUENCY_MHZ
#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000)
#endif
static struct clk sp804_timer012_clk = {
.name = "sp804-timer-0,1,2",
.type = CLK_TYPE_PRIMARY,
.mode = CLK_MODE_XTAL,
.rate_hz = TIMER1_FREQUENCY_MHZ * 1000000,
};
static struct clk sp804_timer3_clk = {
.name = "sp804-timer-3",
.type = CLK_TYPE_PRIMARY,
.mode = CLK_MODE_XTAL,
.rate_hz = TIMER3_FREQUENCY_KHZ * 1000,
};
static struct clk_lookup lookups[] = {
{ /* Bus clock */
.con_id = "apb_pclk",
.clk = &dummy_apb_pclk,
}, { /* UART0 */
.dev_id = "uarta",
.clk = &uart_clk,
}, { /* UART1 */
.dev_id = "uartb",
.clk = &uart_clk,
}, { /* SP804 timer 0 */
.dev_id = "sp804",
.con_id = "timer0",
.clk = &sp804_timer012_clk,
}, { /* SP804 timer 1 */
.dev_id = "sp804",
.con_id = "timer1",
.clk = &sp804_timer012_clk,
}, { /* SP804 timer 3 */
.dev_id = "sp804",
.con_id = "timer3",
.clk = &sp804_timer3_clk,
}
};
static struct amba_device *amba_devs[] __initdata = {
&uartA_device,
&uartB_device,
};
void __init bcmring_amba_init(void)
{
int i;
u32 bus_clock;
/* Linux is run initially in non-secure mode. Secure peripherals */
/* generate FIQ, and must be handled in secure mode. Until we have */
/* a linux security monitor implementation, keep everything in */
/* non-secure mode. */
chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_SPU);
secHw_setUnsecure(secHw_BLK_MASK_CHIP_CONTROL |
secHw_BLK_MASK_KEY_SCAN |
secHw_BLK_MASK_TOUCH_SCREEN |
secHw_BLK_MASK_UART0 |
secHw_BLK_MASK_UART1 |
secHw_BLK_MASK_WATCHDOG |
secHw_BLK_MASK_SPUM |
secHw_BLK_MASK_DDR2 |
secHw_BLK_MASK_SPU |
secHw_BLK_MASK_PKA |
secHw_BLK_MASK_RNG |
secHw_BLK_MASK_RTC |
secHw_BLK_MASK_OTP |
secHw_BLK_MASK_BOOT |
secHw_BLK_MASK_MPU |
secHw_BLK_MASK_TZCTRL | secHw_BLK_MASK_INTR);
/* Only the devices attached to the AMBA bus are enabled just before the bus is */
/* scanned and the drivers are loaded. The clocks need to be on for the AMBA bus */
/* driver to access these blocks. The bus is probed, and the drivers are loaded. */
/* FIXME Need to remove enable of PIF once CLCD clock enable used properly in FPGA. */
bus_clock = chipcHw_REG_BUS_CLOCK_GE
| chipcHw_REG_BUS_CLOCK_SDIO0 | chipcHw_REG_BUS_CLOCK_SDIO1;
chipcHw_busInterfaceClockEnable(bus_clock);
for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
struct amba_device *d = amba_devs[i];
amba_device_register(d, &iomem_resource);
}
}
/*
* Where is the timer (VA)?
*/
#define TIMER0_VA_BASE ((void __iomem *)MM_IO_BASE_TMR)
#define TIMER1_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x20))
#define TIMER2_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x40))
#define TIMER3_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x60))
static int __init bcmring_clocksource_init(void)
{
/* setup timer1 as free-running clocksource */
sp804_clocksource_init(TIMER1_VA_BASE, "timer1");
/* setup timer3 as free-running clocksource */
sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
return 0;
}
/*
* Set up timer interrupt, and return the current time in seconds.
*/
void __init bcmring_init_timer(void)
{
printk(KERN_INFO "bcmring_init_timer\n");
/*
* Initialise to a known state (all timers off)
*/
writel(0, TIMER0_VA_BASE + TIMER_CTRL);
writel(0, TIMER1_VA_BASE + TIMER_CTRL);
writel(0, TIMER2_VA_BASE + TIMER_CTRL);
writel(0, TIMER3_VA_BASE + TIMER_CTRL);
/*
* Make irqs happen for the system timer
*/
bcmring_clocksource_init();
sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMER0, "timer0");
}
struct sys_timer bcmring_timer = {
.init = bcmring_init_timer,
};
void __init bcmring_init_early(void)
{
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
}

31
arch/arm/mach-bcmring/core.h
View file

@ -1,31 +0,0 @@
/*
* linux/arch/arm/mach-versatile/core.h
*
* Copyright (C) 2004 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/* Portions copyright Broadcom 2008 */
#ifndef __ASM_ARCH_BCMRING_H
#define __ASM_ARCH_BCMRING_H
void __init bcmring_amba_init(void);
void __init bcmring_map_io(void);
void __init bcmring_init_irq(void);
void __init bcmring_init_early(void);
extern struct sys_timer bcmring_timer;
#endif

3
arch/arm/mach-bcmring/csp/Makefile
View file

@ -1,3 +0,0 @@
obj-y += dmac/
obj-y += tmr/
obj-y += chipc/

1
arch/arm/mach-bcmring/csp/chipc/Makefile
View file

@ -1 +0,0 @@
obj-y += chipcHw.o chipcHw_str.o chipcHw_reset.o chipcHw_init.o

776
arch/arm/mach-bcmring/csp/chipc/chipcHw.c
View file

@ -1,776 +0,0 @@
/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/****************************************************************************/
/**
* @file chipcHw.c
*
* @brief Low level Various CHIP clock controlling routines
*
* @note
*
* These routines provide basic clock controlling functionality only.
*/
/****************************************************************************/
/* ---- Include Files ---------------------------------------------------- */
#include <csp/errno.h>
#include <csp/stdint.h>
#include <csp/module.h>
#include <mach/csp/chipcHw_def.h>
#include <mach/csp/chipcHw_inline.h>
#include <csp/reg.h>
#include <csp/delay.h>
/* ---- Private Constants and Types --------------------------------------- */
/* VPM alignment algorithm uses this */
#define MAX_PHASE_ADJUST_COUNT 0xFFFF /* Max number of times allowed to adjust the phase */
#define MAX_PHASE_ALIGN_ATTEMPTS 10 /* Max number of attempt to align the phase */
/* Local definition of clock type */
#define PLL_CLOCK 1 /* PLL Clock */
#define NON_PLL_CLOCK 2 /* Divider clock */
static int chipcHw_divide(int num, int denom)
__attribute__ ((section(".aramtext")));
/****************************************************************************/
/**
* @brief Set clock fequency for miscellaneous configurable clocks
*
* This function sets clock frequency
*
* @return Configured clock frequency in hertz
*
*/
/****************************************************************************/
chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */
) {
volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
volatile uint32_t *pDependentClock = (uint32_t *) 0x0;
uint32_t vcoFreqPll1Hz = 0; /* Effective VCO frequency for PLL1 in Hz */
uint32_t vcoFreqPll2Hz = 0; /* Effective VCO frequency for PLL2 in Hz */
uint32_t dependentClockType = 0;
uint32_t vcoHz = 0;
/* Get VCO frequencies */
if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
uint64_t adjustFreq = 0;
vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
/* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
adjustFreq = (uint64_t) chipcHw_XTAL_FREQ_Hz *
(uint64_t) chipcHw_REG_PLL_DIVIDER_NDIV_f_SS *
chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, (chipcHw_REG_PLL_PREDIVIDER_P2 * (uint64_t) chipcHw_REG_PLL_DIVIDER_FRAC));
vcoFreqPll1Hz += (uint32_t) adjustFreq;
} else {
vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
}
vcoFreqPll2Hz =
chipcHw_XTAL_FREQ_Hz *
chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
switch (clock) {
case chipcHw_CLOCK_DDR:
pPLLReg = &pChipcHw->DDRClock;
vcoHz = vcoFreqPll1Hz;
break;
case chipcHw_CLOCK_ARM:
pPLLReg = &pChipcHw->ARMClock;
vcoHz = vcoFreqPll1Hz;
break;
case chipcHw_CLOCK_ESW:
pPLLReg = &pChipcHw->ESWClock;
vcoHz = vcoFreqPll1Hz;
break;
case chipcHw_CLOCK_VPM:
pPLLReg = &pChipcHw->VPMClock;
vcoHz = vcoFreqPll1Hz;
break;
case chipcHw_CLOCK_ESW125:
pPLLReg = &pChipcHw->ESW125Clock;
vcoHz = vcoFreqPll1Hz;
break;
case chipcHw_CLOCK_UART:
pPLLReg = &pChipcHw->UARTClock;
vcoHz = vcoFreqPll1Hz;
break;
case chipcHw_CLOCK_SDIO0:
pPLLReg = &pChipcHw->SDIO0Clock;
vcoHz = vcoFreqPll1Hz;
break;
case chipcHw_CLOCK_SDIO1:
pPLLReg = &pChipcHw->SDIO1Clock;
vcoHz = vcoFreqPll1Hz;
break;
case chipcHw_CLOCK_SPI:
pPLLReg = &pChipcHw->SPIClock;
vcoHz = vcoFreqPll1Hz;
break;
case chipcHw_CLOCK_ETM:
pPLLReg = &pChipcHw->ETMClock;
vcoHz = vcoFreqPll1Hz;
break;
case chipcHw_CLOCK_USB:
pPLLReg = &pChipcHw->USBClock;
vcoHz = vcoFreqPll2Hz;
break;
case chipcHw_CLOCK_LCD:
pPLLReg = &pChipcHw->LCDClock;
vcoHz = vcoFreqPll2Hz;
break;
case chipcHw_CLOCK_APM:
pPLLReg = &pChipcHw->APMClock;
vcoHz = vcoFreqPll2Hz;
break;
case chipcHw_CLOCK_BUS:
pClockCtrl = &pChipcHw->ACLKClock;
pDependentClock = &pChipcHw->ARMClock;
vcoHz = vcoFreqPll1Hz;
dependentClockType = PLL_CLOCK;
break;
case chipcHw_CLOCK_OTP:
pClockCtrl = &pChipcHw->OTPClock;
break;
case chipcHw_CLOCK_I2C:
pClockCtrl = &pChipcHw->I2CClock;
break;
case chipcHw_CLOCK_I2S0:
pClockCtrl = &pChipcHw->I2S0Clock;
break;
case chipcHw_CLOCK_RTBUS:
pClockCtrl = &pChipcHw->RTBUSClock;
pDependentClock = &pChipcHw->ACLKClock;
dependentClockType = NON_PLL_CLOCK;
break;
case chipcHw_CLOCK_APM100:
pClockCtrl = &pChipcHw->APM100Clock;
pDependentClock = &pChipcHw->APMClock;
vcoHz = vcoFreqPll2Hz;
dependentClockType = PLL_CLOCK;
break;
case chipcHw_CLOCK_TSC:
pClockCtrl = &pChipcHw->TSCClock;
break;
case chipcHw_CLOCK_LED:
pClockCtrl = &pChipcHw->LEDClock;
break;
case chipcHw_CLOCK_I2S1:
pClockCtrl = &pChipcHw->I2S1Clock;
break;
}
if (pPLLReg) {
/* Obtain PLL clock frequency */
if (*pPLLReg & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
/* Return crystal clock frequency when bypassed */
return chipcHw_XTAL_FREQ_Hz;
} else if (clock == chipcHw_CLOCK_DDR) {
/* DDR frequency is configured in PLLDivider register */
return chipcHw_divide (vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256));
} else {
/* From chip revision number B0, LCD clock is internally divided by 2 */
if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
vcoHz >>= 1;
}
/* Obtain PLL clock frequency using VCO dividers */
return chipcHw_divide(vcoHz, ((*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
}
} else if (pClockCtrl) {
/* Obtain divider clock frequency */
uint32_t div;
uint32_t freq = 0;
if (*pClockCtrl & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
/* Return crystal clock frequency when bypassed */
return chipcHw_XTAL_FREQ_Hz;
} else if (pDependentClock) {
/* Identify the dependent clock frequency */
switch (dependentClockType) {
case PLL_CLOCK:
if (*pDependentClock & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
/* Use crystal clock frequency when dependent PLL clock is bypassed */
freq = chipcHw_XTAL_FREQ_Hz;
} else {
/* Obtain PLL clock frequency using VCO dividers */
div = *pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK;
freq = div ? chipcHw_divide(vcoHz, div) : 0;
}
break;
case NON_PLL_CLOCK:
if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) {
freq = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS);
} else {
if (*pDependentClock & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
/* Use crystal clock frequency when dependent divider clock is bypassed */
freq = chipcHw_XTAL_FREQ_Hz;
} else {
/* Obtain divider clock frequency using XTAL dividers */
div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK;
freq = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, (div ? div : 256));
}
}
break;
}
} else {
/* Dependent on crystal clock */
freq = chipcHw_XTAL_FREQ_Hz;
}
div = *pClockCtrl & chipcHw_REG_DIV_CLOCK_DIV_MASK;
return chipcHw_divide(freq, (div ? div : 256));
}
return 0;
}
/****************************************************************************/
/**
* @brief Set clock fequency for miscellaneous configurable clocks
*
* This function sets clock frequency
*
* @return Configured clock frequency in Hz
*
*/
/****************************************************************************/
chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configurable clock */
uint32_t freq /* [ IN ] Clock frequency in Hz */
) {
volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
volatile uint32_t *pDependentClock = (uint32_t *) 0x0;
uint32_t vcoFreqPll1Hz = 0; /* Effective VCO frequency for PLL1 in Hz */
uint32_t desVcoFreqPll1Hz = 0; /* Desired VCO frequency for PLL1 in Hz */
uint32_t vcoFreqPll2Hz = 0; /* Effective VCO frequency for PLL2 in Hz */
uint32_t dependentClockType = 0;
uint32_t vcoHz = 0;
uint32_t desVcoHz = 0;
/* Get VCO frequencies */
if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
uint64_t adjustFreq = 0;
vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
/* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
adjustFreq = (uint64_t) chipcHw_XTAL_FREQ_Hz *
(uint64_t) chipcHw_REG_PLL_DIVIDER_NDIV_f_SS *
chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, (chipcHw_REG_PLL_PREDIVIDER_P2 * (uint64_t) chipcHw_REG_PLL_DIVIDER_FRAC));
vcoFreqPll1Hz += (uint32_t) adjustFreq;
/* Desired VCO frequency */
desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
(((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) + 1);
} else {
vcoFreqPll1Hz = desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
}
vcoFreqPll2Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
switch (clock) {
case chipcHw_CLOCK_DDR:
/* Configure the DDR_ctrl:BUS ratio settings */
{
REG_LOCAL_IRQ_SAVE;
/* Dvide DDR_phy by two to obtain DDR_ctrl clock */
pChipcHw->DDRClock = (pChipcHw->DDRClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1)
<< chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT);
REG_LOCAL_IRQ_RESTORE;
}
pPLLReg = &pChipcHw->DDRClock;
vcoHz = vcoFreqPll1Hz;
desVcoHz = desVcoFreqPll1Hz;
break;
case chipcHw_CLOCK_ARM:
pPLLReg = &pChipcHw->ARMClock;
vcoHz = vcoFreqPll1Hz;
desVcoHz = desVcoFreqPll1Hz;
break;
case chipcHw_CLOCK_ESW:
pPLLReg = &pChipcHw->ESWClock;
vcoHz = vcoFreqPll1Hz;
desVcoHz = desVcoFreqPll1Hz;
break;
case chipcHw_CLOCK_VPM:
/* Configure the VPM:BUS ratio settings */
{
REG_LOCAL_IRQ_SAVE;
pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1)
<< chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT);
REG_LOCAL_IRQ_RESTORE;
}
pPLLReg = &pChipcHw->VPMClock;
vcoHz = vcoFreqPll1Hz;
desVcoHz = desVcoFreqPll1Hz;
break;
case chipcHw_CLOCK_ESW125:
pPLLReg = &pChipcHw->ESW125Clock;
vcoHz = vcoFreqPll1Hz;
desVcoHz = desVcoFreqPll1Hz;
break;
case chipcHw_CLOCK_UART:
pPLLReg = &pChipcHw->UARTClock;
vcoHz = vcoFreqPll1Hz;
desVcoHz = desVcoFreqPll1Hz;
break;
case chipcHw_CLOCK_SDIO0:
pPLLReg = &pChipcHw->SDIO0Clock;
vcoHz = vcoFreqPll1Hz;
desVcoHz = desVcoFreqPll1Hz;
break;
case chipcHw_CLOCK_SDIO1:
pPLLReg = &pChipcHw->SDIO1Clock;
vcoHz = vcoFreqPll1Hz;
desVcoHz = desVcoFreqPll1Hz;
break;
case chipcHw_CLOCK_SPI:
pPLLReg = &pChipcHw->SPIClock;
vcoHz = vcoFreqPll1Hz;
desVcoHz = desVcoFreqPll1Hz;
break;
case chipcHw_CLOCK_ETM:
pPLLReg = &pChipcHw->ETMClock;
vcoHz = vcoFreqPll1Hz;
desVcoHz = desVcoFreqPll1Hz;
break;
case chipcHw_CLOCK_USB:
pPLLReg = &pChipcHw->USBClock;
vcoHz = vcoFreqPll2Hz;
desVcoHz = vcoFreqPll2Hz;
break;
case chipcHw_CLOCK_LCD:
pPLLReg = &pChipcHw->LCDClock;
vcoHz = vcoFreqPll2Hz;
desVcoHz = vcoFreqPll2Hz;
break;
case chipcHw_CLOCK_APM:
pPLLReg = &pChipcHw->APMClock;
vcoHz = vcoFreqPll2Hz;
desVcoHz = vcoFreqPll2Hz;
break;
case chipcHw_CLOCK_BUS:
pClockCtrl = &pChipcHw->ACLKClock;
pDependentClock = &pChipcHw->ARMClock;
vcoHz = vcoFreqPll1Hz;
desVcoHz = desVcoFreqPll1Hz;
dependentClockType = PLL_CLOCK;
break;
case chipcHw_CLOCK_OTP:
pClockCtrl = &pChipcHw->OTPClock;
break;
case chipcHw_CLOCK_I2C:
pClockCtrl = &pChipcHw->I2CClock;
break;
case chipcHw_CLOCK_I2S0:
pClockCtrl = &pChipcHw->I2S0Clock;
break;
case chipcHw_CLOCK_RTBUS:
pClockCtrl = &pChipcHw->RTBUSClock;
pDependentClock = &pChipcHw->ACLKClock;
dependentClockType = NON_PLL_CLOCK;
break;
case chipcHw_CLOCK_APM100:
pClockCtrl = &pChipcHw->APM100Clock;
pDependentClock = &pChipcHw->APMClock;
vcoHz = vcoFreqPll2Hz;
desVcoHz = vcoFreqPll2Hz;
dependentClockType = PLL_CLOCK;
break;
case chipcHw_CLOCK_TSC:
pClockCtrl = &pChipcHw->TSCClock;
break;
case chipcHw_CLOCK_LED:
pClockCtrl = &pChipcHw->LEDClock;
break;
case chipcHw_CLOCK_I2S1:
pClockCtrl = &pChipcHw->I2S1Clock;
break;
}
if (pPLLReg) {
/* Select XTAL as bypass source */
reg32_modify_and(pPLLReg, ~chipcHw_REG_PLL_CLOCK_SOURCE_GPIO);
reg32_modify_or(pPLLReg, chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
/* For DDR settings use only the PLL divider clock */
if (pPLLReg == &pChipcHw->DDRClock) {
/* Set M1DIV for PLL1, which controls the DDR clock */
reg32_write(&pChipcHw->PLLDivider, (pChipcHw->PLLDivider & 0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24));
/* Calculate expected frequency */
freq = chipcHw_divide(vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256));
} else {
/* From chip revision number B0, LCD clock is internally divided by 2 */
if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
desVcoHz >>= 1;
vcoHz >>= 1;
}
/* Set MDIV to change the frequency */
reg32_modify_and(pPLLReg, ~(chipcHw_REG_PLL_CLOCK_MDIV_MASK));
reg32_modify_or(pPLLReg, chipcHw_REG_PLL_DIVIDER_MDIV(desVcoHz, freq));
/* Calculate expected frequency */
freq = chipcHw_divide(vcoHz, ((*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
}
/* Wait for for atleast 200ns as per the protocol to change frequency */
udelay(1);
/* Do not bypass */
reg32_modify_and(pPLLReg, ~chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
/* Return the configured frequency */
return freq;
} else if (pClockCtrl) {
uint32_t divider = 0;
/* Divider clock should not be bypassed */
reg32_modify_and(pClockCtrl,
~chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
/* Identify the clock source */
if (pDependentClock) {
switch (dependentClockType) {
case PLL_CLOCK:
divider = chipcHw_divide(chipcHw_divide (desVcoHz, (*pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq);
break;
case NON_PLL_CLOCK:
{
uint32_t sourceClock = 0;
if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) {
sourceClock = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS);
} else {
uint32_t div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK;
sourceClock = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, ((div) ? div : 256));
}
divider = chipcHw_divide(sourceClock, freq);
}
break;
}
} else {
divider = chipcHw_divide(chipcHw_XTAL_FREQ_Hz, freq);
}
if (divider) {
REG_LOCAL_IRQ_SAVE;
/* Set the divider to obtain the required frequency */
*pClockCtrl = (*pClockCtrl & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | (((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & chipcHw_REG_DIV_CLOCK_DIV_MASK);
REG_LOCAL_IRQ_RESTORE;
return freq;
}
}
return 0;
}
EXPORT_SYMBOL(chipcHw_setClockFrequency);
/****************************************************************************/
/**
* @brief Set VPM clock in sync with BUS clock for Chip Rev #A0
*
* This function does the phase adjustment between VPM and BUS clock
*
* @return >= 0 : On success (# of adjustment required)
* -1 : On failure
*
*/
/****************************************************************************/
static int vpmPhaseAlignA0(void)
{
uint32_t phaseControl;
uint32_t phaseValue;
uint32_t prevPhaseComp;
int iter = 0;
int adjustCount = 0;
int count = 0;
for (iter = 0; (iter < MAX_PHASE_ALIGN_ATTEMPTS) && (adjustCount < MAX_PHASE_ADJUST_COUNT); iter++) {
phaseControl = (pChipcHw->VPMClock & chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT;
phaseValue = 0;
prevPhaseComp = 0;
/* Step 1: Look for falling PH_COMP transition */
/* Read the contents of VPM Clock resgister */
phaseValue = pChipcHw->VPMClock;
do {
/* Store previous value of phase comparator */
prevPhaseComp = phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP;
/* Change the value of PH_CTRL. */
reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
/* Wait atleast 20 ns */
udelay(1);
/* Toggle the LOAD_CH after phase control is written. */
pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
/* Read the contents of VPM Clock resgister. */
phaseValue = pChipcHw->VPMClock;
if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) {
phaseControl = (0x3F & (phaseControl - 1));
} else {
/* Increment to the Phase count value for next write, if Phase is not stable. */
phaseControl = (0x3F & (phaseControl + 1));
}
/* Count number of adjustment made */
adjustCount++;
} while (((prevPhaseComp == (phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP)) || /* Look for a transition */
((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) != 0x0)) && /* Look for a falling edge */
(adjustCount < MAX_PHASE_ADJUST_COUNT) /* Do not exceed the limit while trying */
);
if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
/* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
return -1;
}
/* Step 2: Keep moving forward to make sure falling PH_COMP transition was valid */
for (count = 0; (count < 5) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) {
phaseControl = (0x3F & (phaseControl + 1));
reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
/* Wait atleast 20 ns */
udelay(1);
/* Toggle the LOAD_CH after phase control is written. */
pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
phaseValue = pChipcHw->VPMClock;
/* Count number of adjustment made */
adjustCount++;
}
if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
/* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
return -1;
}
if (count != 5) {
/* Detected false transition */
continue;
}
/* Step 3: Keep moving backward to make sure falling PH_COMP transition was stable */
for (count = 0; (count < 3) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) {
phaseControl = (0x3F & (phaseControl - 1));
reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
/* Wait atleast 20 ns */
udelay(1);
/* Toggle the LOAD_CH after phase control is written. */
pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
phaseValue = pChipcHw->VPMClock;
/* Count number of adjustment made */
adjustCount++;
}
if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
/* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
return -1;
}
if (count != 3) {
/* Detected noisy transition */
continue;
}
/* Step 4: Keep moving backward before the original transition took place. */
for (count = 0; (count < 5); count++) {
phaseControl = (0x3F & (phaseControl - 1));
reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
/* Wait atleast 20 ns */
udelay(1);
/* Toggle the LOAD_CH after phase control is written. */
pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
phaseValue = pChipcHw->VPMClock;
/* Count number of adjustment made */
adjustCount++;
}
if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
/* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
return -1;
}
if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0) {
/* Detected false transition */
continue;
}
/* Step 5: Re discover the valid transition */
do {
/* Store previous value of phase comparator */
prevPhaseComp = phaseValue;
/* Change the value of PH_CTRL. */
reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
/* Wait atleast 20 ns */
udelay(1);
/* Toggle the LOAD_CH after phase control is written. */
pChipcHw->VPMClock ^=
chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
/* Read the contents of VPM Clock resgister. */
phaseValue = pChipcHw->VPMClock;
if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) {
phaseControl = (0x3F & (phaseControl - 1));
} else {
/* Increment to the Phase count value for next write, if Phase is not stable. */
phaseControl = (0x3F & (phaseControl + 1));
}
/* Count number of adjustment made */
adjustCount++;
} while (((prevPhaseComp == (phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP)) || ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) != 0x0)) && (adjustCount < MAX_PHASE_ADJUST_COUNT));
if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
/* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
return -1;
} else {
/* Valid phase must have detected */
break;
}
}
/* For VPM Phase should be perfectly aligned. */
phaseControl = (((pChipcHw->VPMClock >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F);
{
REG_LOCAL_IRQ_SAVE;
pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT);
/* Load new phase value */
pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
REG_LOCAL_IRQ_RESTORE;
}
/* Return the status */
return (int)adjustCount;
}
/****************************************************************************/
/**
* @brief Set VPM clock in sync with BUS clock
*
* This function does the phase adjustment between VPM and BUS clock
*
* @return >= 0 : On success (# of adjustment required)
* -1 : On failure
*
*/
/****************************************************************************/
int chipcHw_vpmPhaseAlign(void)
{
if (chipcHw_getChipRevisionNumber() == chipcHw_REV_NUMBER_A0) {
return vpmPhaseAlignA0();
} else {
uint32_t phaseControl = chipcHw_getVpmPhaseControl();
uint32_t phaseValue = 0;
int adjustCount = 0;
/* Disable VPM access */
pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
/* Disable HW VPM phase alignment */
chipcHw_vpmHwPhaseAlignDisable();
/* Enable SW VPM phase alignment */
chipcHw_vpmSwPhaseAlignEnable();
/* Adjust VPM phase */
while (adjustCount < MAX_PHASE_ADJUST_COUNT) {
phaseValue = chipcHw_getVpmHwPhaseAlignStatus();
/* Adjust phase control value */
if (phaseValue > 0xF) {
/* Increment phase control value */
phaseControl++;
} else if (phaseValue < 0xF) {
/* Decrement phase control value */
phaseControl--;
} else {
/* Enable VPM access */
pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
/* Return adjust count */
return adjustCount;
}
/* Change the value of PH_CTRL. */
reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
/* Wait atleast 20 ns */
udelay(1);
/* Toggle the LOAD_CH after phase control is written. */
pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
/* Count adjustment */
adjustCount++;
}
}
/* Disable VPM access */
pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
return -1;
}
/****************************************************************************/
/**
* @brief Local Divide function
*
* This function does the divide
*
* @return divide value
*
*/
/****************************************************************************/
static int chipcHw_divide(int num, int denom)
{
int r;
int t = 1;
/* Shift denom and t up to the largest value to optimize algorithm */
/* t contains the units of each divide */
while ((denom & 0x40000000) == 0) { /* fails if denom=0 */
denom = denom << 1;
t = t << 1;
}
/* Initialize the result */
r = 0;
do {
/* Determine if there exists a positive remainder */
if ((num - denom) >= 0) {
/* Accumlate t to the result and calculate a new remainder */
num = num - denom;
r = r + t;
}
/* Continue to shift denom and shift t down to 0 */
denom = denom >> 1;
t = t >> 1;
} while (t != 0);
return r;
}

293
arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
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@ -1,293 +0,0 @@
/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/****************************************************************************/
/**
* @file chipcHw_init.c
*
* @brief Low level CHIPC PLL configuration functions
*
* @note
*
* These routines provide basic PLL controlling functionality only.
*/
/****************************************************************************/
/* ---- Include Files ---------------------------------------------------- */
#include <csp/errno.h>
#include <csp/stdint.h>
#include <csp/module.h>
#include <mach/csp/chipcHw_def.h>
#include <mach/csp/chipcHw_inline.h>
#include <csp/reg.h>
#include <csp/delay.h>
/* ---- Private Constants and Types --------------------------------------- */
/*
Calculation for NDIV_i to obtain VCO frequency
-----------------------------------------------
Freq_vco = Freq_ref * (P2 / P1) * (PLL_NDIV_i + PLL_NDIV_f)
for Freq_vco = VCO_FREQ_MHz
Freq_ref = chipcHw_XTAL_FREQ_Hz
PLL_P1 = PLL_P2 = 1
and
PLL_NDIV_f = 0
We get:
PLL_NDIV_i = Freq_vco / Freq_ref = VCO_FREQ_MHz / chipcHw_XTAL_FREQ_Hz
Calculation for PLL MDIV to obtain frequency Freq_x for channel x
-----------------------------------------------------------------
Freq_x = chipcHw_XTAL_FREQ_Hz * PLL_NDIV_i / PLL_MDIV_x = VCO_FREQ_MHz / PLL_MDIV_x
PLL_MDIV_x = VCO_FREQ_MHz / Freq_x
*/
/* ---- Private Variables ------------------------------------------------- */
/****************************************************************************/
/**
* @brief Initializes the PLL2
*
* This function initializes the PLL2
*
*/
/****************************************************************************/
void chipcHw_pll2Enable(uint32_t vcoFreqHz)
{
uint32_t pllPreDivider2 = 0;
{
REG_LOCAL_IRQ_SAVE;
pChipcHw->PLLConfig2 =
chipcHw_REG_PLL_CONFIG_D_RESET |
chipcHw_REG_PLL_CONFIG_A_RESET;
pllPreDivider2 = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
(chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) <<
chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
(chipcHw_REG_PLL_PREDIVIDER_P1 <<
chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
(chipcHw_REG_PLL_PREDIVIDER_P2 <<
chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
/* Enable CHIPC registers to control the PLL */
pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
/* Set pre divider to get desired VCO frequency */
pChipcHw->PLLPreDivider2 = pllPreDivider2;
/* Set NDIV Frac */
pChipcHw->PLLDivider2 = chipcHw_REG_PLL_DIVIDER_NDIV_f;
/* This has to be removed once the default values are fixed for PLL2. */
pChipcHw->PLLControl12 = 0x38000700;
pChipcHw->PLLControl22 = 0x00000015;
/* Reset PLL2 */
if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
chipcHw_REG_PLL_CONFIG_A_RESET |
chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
chipcHw_REG_PLL_CONFIG_POWER_DOWN;
} else {
pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
chipcHw_REG_PLL_CONFIG_A_RESET |
chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
chipcHw_REG_PLL_CONFIG_POWER_DOWN;
}
REG_LOCAL_IRQ_RESTORE;
}
/* Insert certain amount of delay before deasserting ARESET. */
udelay(1);
{
REG_LOCAL_IRQ_SAVE;
/* Remove analog reset and Power on the PLL */
pChipcHw->PLLConfig2 &=
~(chipcHw_REG_PLL_CONFIG_A_RESET |
chipcHw_REG_PLL_CONFIG_POWER_DOWN);
REG_LOCAL_IRQ_RESTORE;
}
/* Wait until PLL is locked */
while (!(pChipcHw->PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
;
{
REG_LOCAL_IRQ_SAVE;
/* Remove digital reset */
pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
REG_LOCAL_IRQ_RESTORE;
}
}
EXPORT_SYMBOL(chipcHw_pll2Enable);
/****************************************************************************/
/**
* @brief Initializes the PLL1
*
* This function initializes the PLL1
*
*/
/****************************************************************************/
void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport)
{
uint32_t pllPreDivider = 0;
{
REG_LOCAL_IRQ_SAVE;
pChipcHw->PLLConfig =
chipcHw_REG_PLL_CONFIG_D_RESET |
chipcHw_REG_PLL_CONFIG_A_RESET;
/* Setting VCO frequency */
if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
pllPreDivider =
chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_1_8 |
((chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) -
1) << chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
(chipcHw_REG_PLL_PREDIVIDER_P1 <<
chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
(chipcHw_REG_PLL_PREDIVIDER_P2 <<
chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
} else {
pllPreDivider = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
(chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) <<
chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
(chipcHw_REG_PLL_PREDIVIDER_P1 <<
chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
(chipcHw_REG_PLL_PREDIVIDER_P2 <<
chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
}
/* Enable CHIPC registers to control the PLL */
pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
/* Set pre divider to get desired VCO frequency */
pChipcHw->PLLPreDivider = pllPreDivider;
/* Set NDIV Frac */
if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
chipcHw_REG_PLL_DIVIDER_NDIV_f_SS;
} else {
pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
chipcHw_REG_PLL_DIVIDER_NDIV_f;
}
/* Reset PLL1 */
if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
chipcHw_REG_PLL_CONFIG_A_RESET |
chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
chipcHw_REG_PLL_CONFIG_POWER_DOWN;
} else {
pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
chipcHw_REG_PLL_CONFIG_A_RESET |
chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
chipcHw_REG_PLL_CONFIG_POWER_DOWN;
}
REG_LOCAL_IRQ_RESTORE;
/* Insert certain amount of delay before deasserting ARESET. */
udelay(1);
{
REG_LOCAL_IRQ_SAVE;
/* Remove analog reset and Power on the PLL */
pChipcHw->PLLConfig &=
~(chipcHw_REG_PLL_CONFIG_A_RESET |
chipcHw_REG_PLL_CONFIG_POWER_DOWN);
REG_LOCAL_IRQ_RESTORE;
}
/* Wait until PLL is locked */
while (!(pChipcHw->PLLStatus & chipcHw_REG_PLL_STATUS_LOCKED)
|| !(pChipcHw->
PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
;
/* Remove digital reset */
{
REG_LOCAL_IRQ_SAVE;
pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
REG_LOCAL_IRQ_RESTORE;
}
}
}
EXPORT_SYMBOL(chipcHw_pll1Enable);
/****************************************************************************/
/**
* @brief Initializes the chipc module
*
* This function initializes the PLLs and core system clocks
*
*/
/****************************************************************************/
void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam /* [ IN ] Misc chip initialization parameter */
) {
#if !(defined(__KERNEL__) && !defined(STANDALONE))
delay_init();
#endif
/* Do not program PLL, when warm reset */
if (!(chipcHw_getStickyBits() & chipcHw_REG_STICKY_CHIP_WARM_RESET)) {
chipcHw_pll1Enable(initParam->pllVcoFreqHz,
initParam->ssSupport);
chipcHw_pll2Enable(initParam->pll2VcoFreqHz);
} else {
/* Clear sticky bits */
chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_WARM_RESET);
}
/* Clear sticky bits */
chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_SOFT_RESET);
/* Before configuring the ARM clock, atleast we need to make sure BUS clock maintains the proper ratio with ARM clock */
pChipcHw->ACLKClock =
(pChipcHw->
ACLKClock & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam->
armBusRatio &
chipcHw_REG_ACLKClock_CLK_DIV_MASK);
/* Set various core component frequencies. The order in which this is done is important for some. */
/* The RTBUS (DDR PHY) is derived from the BUS, and the BUS from the ARM, and VPM needs to know BUS */
/* frequency to find its ratio with the BUS. Hence we must set the ARM first, followed by the BUS, */
/* then VPM and RTBUS. */
chipcHw_setClockFrequency(chipcHw_CLOCK_ARM,
initParam->busClockFreqHz *
initParam->armBusRatio);
chipcHw_setClockFrequency(chipcHw_CLOCK_BUS, initParam->busClockFreqHz);
chipcHw_setClockFrequency(chipcHw_CLOCK_VPM,
initParam->busClockFreqHz *
initParam->vpmBusRatio);
chipcHw_setClockFrequency(chipcHw_CLOCK_DDR,
initParam->busClockFreqHz *
initParam->ddrBusRatio);
chipcHw_setClockFrequency(chipcHw_CLOCK_RTBUS,
initParam->busClockFreqHz / 2);
}

124
arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
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@ -1,124 +0,0 @@
/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/* ---- Include Files ---------------------------------------------------- */
#include <csp/stdint.h>
#include <mach/csp/chipcHw_def.h>
#include <mach/csp/chipcHw_inline.h>
#include <csp/intcHw.h>
#include <csp/cache.h>
/* ---- Private Constants and Types --------------------------------------- */
/* ---- Private Variables ------------------------------------------------- */
void chipcHw_reset_run_from_aram(void);
typedef void (*RUNFUNC) (void);
/****************************************************************************/
/**
* @brief warmReset
*
* @note warmReset configures the clocks which are not reset back to the state
* required to execute on reset. To do so we need to copy the code into internal
* memory to change the ARM clock while we are not executing from DDR.
*/
/****************************************************************************/
void chipcHw_reset(uint32_t mask)
{
int i = 0;
RUNFUNC runFunc = (RUNFUNC) (unsigned long)MM_ADDR_IO_ARAM;
/* Disable all interrupts */
intcHw_irq_disable(INTCHW_INTC0, 0xffffffff);
intcHw_irq_disable(INTCHW_INTC1, 0xffffffff);
intcHw_irq_disable(INTCHW_SINTC, 0xffffffff);
{
REG_LOCAL_IRQ_SAVE;
if (mask & chipcHw_REG_SOFT_RESET_CHIP_SOFT) {
chipcHw_softReset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
}
/* Bypass the PLL clocks before reboot */
pChipcHw->UARTClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;
pChipcHw->SPIClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;
/* Copy the chipcHw_warmReset_run_from_aram function into ARAM */
do {
((uint32_t *) MM_IO_BASE_ARAM)[i] =
((uint32_t *) &chipcHw_reset_run_from_aram)[i];
i++;
} while (((uint32_t *) MM_IO_BASE_ARAM)[i - 1] != 0xe1a0f00f); /* 0xe1a0f00f == asm ("mov r15, r15"); */
CSP_CACHE_FLUSH_ALL;
/* run the function from ARAM */
runFunc();
/* Code will never get here, but include it to balance REG_LOCAL_IRQ_SAVE above */
REG_LOCAL_IRQ_RESTORE;
}
}
/* This function must run from internal memory */
void chipcHw_reset_run_from_aram(void)
{
/* Make sure, pipeline is filled with instructions coming from ARAM */
__asm (" nop \n\t"
" nop \n\t"
#if defined(__KERNEL__) && !defined(STANDALONE)
" MRC p15,#0x0,r0,c1,c0,#0 \n\t"
" BIC r0,r0,#0xd \n\t"
" MCR p15,#0x0,r0,c1,c0,#0 \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
#endif
" nop \n\t"
" nop \n\t"
/* Bypass the ARM clock and switch to XTAL clock */
" MOV r2,#0x80000000 \n\t"
" LDR r3,[r2,#8] \n\t"
" ORR r3,r3,#0x20000 \n\t"
" STR r3,[r2,#8] \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
" nop \n\t"
/* Issue reset */
" MOV r3,#0x2 \n\t"
" STR r3,[r2,#0x80] \n\t"
/* End here */
" MOV pc,pc \n\t");
/* 0xe1a0f00f == asm ("mov r15, r15"); */
}

64
arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
View file

@ -1,64 +0,0 @@
/*****************************************************************************
* Copyright 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/****************************************************************************/
/**
* @file chipcHw_str.c
*
* @brief Contains strings which are useful to linux and csp
*
* @note
*/
/****************************************************************************/
/* ---- Include Files ---------------------------------------------------- */
#include <mach/csp/chipcHw_inline.h>
/* ---- Private Constants and Types --------------------------------------- */
static const char *gMuxStr[] = {
"GPIO", /* 0 */
"KeyPad", /* 1 */
"I2C-Host", /* 2 */
"SPI", /* 3 */
"Uart", /* 4 */
"LED-Mtx-P", /* 5 */
"LED-Mtx-S", /* 6 */
"SDIO-0", /* 7 */
"SDIO-1", /* 8 */
"PCM", /* 9 */
"I2S", /* 10 */
"ETM", /* 11 */
"Debug", /* 12 */
"Misc", /* 13 */
"0xE", /* 14 */
"0xF", /* 15 */
};
/****************************************************************************/
/**
* @brief Retrieves a string representation of the mux setting for a pin.
*
* @return Pointer to a character string.
*/
/****************************************************************************/
const char *chipcHw_getGpioPinFunctionStr(int pin)
{
if ((pin < 0) || (pin >= chipcHw_GPIO_COUNT)) {
return "";
}
return gMuxStr[chipcHw_getGpioPinFunction(pin)];
}

1
arch/arm/mach-bcmring/csp/dmac/Makefile
View file

@ -1 +0,0 @@
obj-y += dmacHw.o dmacHw_extra.o

917
arch/arm/mach-bcmring/csp/dmac/dmacHw.c
View file

@ -1,917 +0,0 @@
/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/****************************************************************************/
/**
* @file dmacHw.c
*
* @brief Low level DMA controller driver routines
*
* @note
*
* These routines provide basic DMA functionality only.
*/
/****************************************************************************/
/* ---- Include Files ---------------------------------------------------- */
#include <csp/stdint.h>
#include <csp/string.h>
#include <stddef.h>
#include <csp/dmacHw.h>
#include <mach/csp/dmacHw_reg.h>
#include <mach/csp/dmacHw_priv.h>
#include <mach/csp/chipcHw_inline.h>
/* ---- External Function Prototypes ------------------------------------- */
/* Allocate DMA control blocks */
dmacHw_CBLK_t dmacHw_gCblk[dmacHw_MAX_CHANNEL_COUNT];
uint32_t dmaChannelCount_0 = dmacHw_MAX_CHANNEL_COUNT / 2;
uint32_t dmaChannelCount_1 = dmacHw_MAX_CHANNEL_COUNT / 2;
/****************************************************************************/
/**
* @brief Get maximum FIFO for a DMA channel
*
* @return Maximum allowable FIFO size
*
*
*/
/****************************************************************************/
static uint32_t GetFifoSize(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
) {
uint32_t val = 0;
dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
dmacHw_MISC_t *pMiscReg =
(dmacHw_MISC_t *) dmacHw_REG_MISC_BASE(pCblk->module);
switch (pCblk->channel) {
case 0:
val = (pMiscReg->CompParm2.lo & 0x70000000) >> 28;
break;
case 1:
val = (pMiscReg->CompParm3.hi & 0x70000000) >> 28;
break;
case 2:
val = (pMiscReg->CompParm3.lo & 0x70000000) >> 28;
break;
case 3:
val = (pMiscReg->CompParm4.hi & 0x70000000) >> 28;
break;
case 4:
val = (pMiscReg->CompParm4.lo & 0x70000000) >> 28;
break;
case 5:
val = (pMiscReg->CompParm5.hi & 0x70000000) >> 28;
break;
case 6:
val = (pMiscReg->CompParm5.lo & 0x70000000) >> 28;
break;
case 7:
val = (pMiscReg->CompParm6.hi & 0x70000000) >> 28;
break;
}
if (val <= 0x4) {
return 8 << val;
} else {
dmacHw_ASSERT(0);
}
return 0;
}
/****************************************************************************/
/**
* @brief Program channel register to initiate transfer
*
* @return void
*
*
* @note
* - Descriptor buffer MUST ALWAYS be flushed before calling this function
* - This function should also be called from ISR to program the channel with
* pending descriptors
*/
/****************************************************************************/
void dmacHw_initiateTransfer(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
void *pDescriptor /* [ IN ] Descriptor buffer */
) {
dmacHw_DESC_RING_t *pRing;
dmacHw_DESC_t *pProg;
dmacHw_CBLK_t *pCblk;
pCblk = dmacHw_HANDLE_TO_CBLK(handle);
pRing = dmacHw_GET_DESC_RING(pDescriptor);
if (CHANNEL_BUSY(pCblk->module, pCblk->channel)) {
/* Not safe yet to program the channel */
return;
}
if (pCblk->varDataStarted) {
if (pCblk->descUpdated) {
pCblk->descUpdated = 0;
pProg =
(dmacHw_DESC_t *) ((uint32_t)
dmacHw_REG_LLP(pCblk->module,
pCblk->channel) +
pRing->virt2PhyOffset);
/* Load descriptor if not loaded */
if (!(pProg->ctl.hi & dmacHw_REG_CTL_DONE)) {
dmacHw_SET_SAR(pCblk->module, pCblk->channel,
pProg->sar);
dmacHw_SET_DAR(pCblk->module, pCblk->channel,
pProg->dar);
dmacHw_REG_CTL_LO(pCblk->module,
pCblk->channel) =
pProg->ctl.lo;
dmacHw_REG_CTL_HI(pCblk->module,
pCblk->channel) =
pProg->ctl.hi;
} else if (pProg == (dmacHw_DESC_t *) pRing->pEnd->llp) {
/* Return as end descriptor is processed */
return;
} else {
dmacHw_ASSERT(0);
}
} else {
return;
}
} else {
if (pConfig->transferMode == dmacHw_TRANSFER_MODE_PERIODIC) {
/* Do not make a single chain, rather process one descriptor at a time */
pProg = pRing->pHead;
/* Point to the next descriptor for next iteration */
dmacHw_NEXT_DESC(pRing, pHead);
} else {
/* Return if no more pending descriptor */
if (pRing->pEnd == NULL) {
return;
}
pProg = pRing->pProg;
if (pConfig->transferMode ==
dmacHw_TRANSFER_MODE_CONTINUOUS) {
/* Make sure a complete ring can be formed */
dmacHw_ASSERT((dmacHw_DESC_t *) pRing->pEnd->
llp == pRing->pProg);
/* Make sure pProg pointing to the pHead */
dmacHw_ASSERT((dmacHw_DESC_t *) pRing->pProg ==
pRing->pHead);
/* Make a complete ring */
do {
pRing->pProg->ctl.lo |=
(dmacHw_REG_CTL_LLP_DST_EN |
dmacHw_REG_CTL_LLP_SRC_EN);
pRing->pProg =
(dmacHw_DESC_t *) pRing->pProg->llp;
} while (pRing->pProg != pRing->pHead);
} else {
/* Make a single long chain */
while (pRing->pProg != pRing->pEnd) {
pRing->pProg->ctl.lo |=
(dmacHw_REG_CTL_LLP_DST_EN |
dmacHw_REG_CTL_LLP_SRC_EN);
pRing->pProg =
(dmacHw_DESC_t *) pRing->pProg->llp;
}
}
}
/* Program the channel registers */
dmacHw_SET_SAR(pCblk->module, pCblk->channel, pProg->sar);
dmacHw_SET_DAR(pCblk->module, pCblk->channel, pProg->dar);
dmacHw_SET_LLP(pCblk->module, pCblk->channel,
(uint32_t) pProg - pRing->virt2PhyOffset);
dmacHw_REG_CTL_LO(pCblk->module, pCblk->channel) =
pProg->ctl.lo;
dmacHw_REG_CTL_HI(pCblk->module, pCblk->channel) =
pProg->ctl.hi;
if (pRing->pEnd) {
/* Remember the descriptor to use next */
pRing->pProg = (dmacHw_DESC_t *) pRing->pEnd->llp;
}
/* Indicate no more pending descriptor */
pRing->pEnd = (dmacHw_DESC_t *) NULL;
}
/* Start DMA operation */
dmacHw_DMA_START(pCblk->module, pCblk->channel);
}
/****************************************************************************/
/**
* @brief Initializes DMA
*
* This function initializes DMA CSP driver
*
* @note
* Must be called before using any DMA channel
*/
/****************************************************************************/
void dmacHw_initDma(void)
{
uint32_t i = 0;
dmaChannelCount_0 = dmacHw_GET_NUM_CHANNEL(0);
dmaChannelCount_1 = dmacHw_GET_NUM_CHANNEL(1);
/* Enable access to the DMA block */
chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_DMAC0);
chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_DMAC1);
if ((dmaChannelCount_0 + dmaChannelCount_1) > dmacHw_MAX_CHANNEL_COUNT) {
dmacHw_ASSERT(0);
}
memset((void *)dmacHw_gCblk, 0,
sizeof(dmacHw_CBLK_t) * (dmaChannelCount_0 + dmaChannelCount_1));
for (i = 0; i < dmaChannelCount_0; i++) {
dmacHw_gCblk[i].module = 0;
dmacHw_gCblk[i].channel = i;
}
for (i = 0; i < dmaChannelCount_1; i++) {
dmacHw_gCblk[i + dmaChannelCount_0].module = 1;
dmacHw_gCblk[i + dmaChannelCount_0].channel = i;
}
}
/****************************************************************************/
/**
* @brief Exit function for DMA
*
* This function isolates DMA from the system
*
*/
/****************************************************************************/
void dmacHw_exitDma(void)
{
/* Disable access to the DMA block */
chipcHw_busInterfaceClockDisable(chipcHw_REG_BUS_CLOCK_DMAC0);
chipcHw_busInterfaceClockDisable(chipcHw_REG_BUS_CLOCK_DMAC1);
}
/****************************************************************************/
/**
* @brief Gets a handle to a DMA channel
*
* This function returns a handle, representing a control block of a particular DMA channel
*
* @return -1 - On Failure
* handle - On Success, representing a channel control block
*
* @note
* None Channel ID must be created using "dmacHw_MAKE_CHANNEL_ID" macro
*/
/****************************************************************************/
dmacHw_HANDLE_t dmacHw_getChannelHandle(dmacHw_ID_t channelId /* [ IN ] DMA Channel Id */
) {
int idx;
switch ((channelId >> 8)) {
case 0:
dmacHw_ASSERT((channelId & 0xff) < dmaChannelCount_0);
idx = (channelId & 0xff);
break;
case 1:
dmacHw_ASSERT((channelId & 0xff) < dmaChannelCount_1);
idx = dmaChannelCount_0 + (channelId & 0xff);
break;
default:
dmacHw_ASSERT(0);
return (dmacHw_HANDLE_t) -1;
}
return dmacHw_CBLK_TO_HANDLE(&dmacHw_gCblk[idx]);
}
/****************************************************************************/
/**
* @brief Initializes a DMA channel for use
*
* This function initializes and resets a DMA channel for use
*
* @return -1 - On Failure
* 0 - On Success
*
* @note
* None
*/
/****************************************************************************/
int dmacHw_initChannel(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
) {
dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
int module = pCblk->module;
int channel = pCblk->channel;
/* Reinitialize the control block */
memset((void *)pCblk, 0, sizeof(dmacHw_CBLK_t));
pCblk->module = module;
pCblk->channel = channel;
/* Enable DMA controller */
dmacHw_DMA_ENABLE(pCblk->module);
/* Reset DMA channel */
dmacHw_RESET_CONTROL_LO(pCblk->module, pCblk->channel);
dmacHw_RESET_CONTROL_HI(pCblk->module, pCblk->channel);
dmacHw_RESET_CONFIG_LO(pCblk->module, pCblk->channel);
dmacHw_RESET_CONFIG_HI(pCblk->module, pCblk->channel);
/* Clear all raw interrupt status */
dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
/* Mask event specific interrupts */
dmacHw_TRAN_INT_DISABLE(pCblk->module, pCblk->channel);
dmacHw_BLOCK_INT_DISABLE(pCblk->module, pCblk->channel);
dmacHw_STRAN_INT_DISABLE(pCblk->module, pCblk->channel);
dmacHw_DTRAN_INT_DISABLE(pCblk->module, pCblk->channel);
dmacHw_ERROR_INT_DISABLE(pCblk->module, pCblk->channel);
return 0;
}
/****************************************************************************/
/**
* @brief Finds amount of memory required to form a descriptor ring
*
*
* @return Number of bytes required to form a descriptor ring
*
*
*/
/****************************************************************************/
uint32_t dmacHw_descriptorLen(uint32_t descCnt /* [ IN ] Number of descriptor in the ring */
) {
/* Need extra 4 byte to ensure 32 bit alignment */
return (descCnt * sizeof(dmacHw_DESC_t)) + sizeof(dmacHw_DESC_RING_t) +
sizeof(uint32_t);
}
/****************************************************************************/
/**
* @brief Initializes descriptor ring
*
* This function will initializes the descriptor ring of a DMA channel
*
*
* @return -1 - On failure
* 0 - On success
* @note
* - "len" parameter should be obtained from "dmacHw_descriptorLen"
* - Descriptor buffer MUST be 32 bit aligned and uncached as it is
* accessed by ARM and DMA
*/
/****************************************************************************/
int dmacHw_initDescriptor(void *pDescriptorVirt, /* [ IN ] Virtual address of uncahced buffer allocated to form descriptor ring */
uint32_t descriptorPhyAddr, /* [ IN ] Physical address of pDescriptorVirt (descriptor buffer) */
uint32_t len, /* [ IN ] Size of the pBuf */
uint32_t num /* [ IN ] Number of descriptor in the ring */
) {
uint32_t i;
dmacHw_DESC_RING_t *pRing;
dmacHw_DESC_t *pDesc;
/* Check the alignment of the descriptor */
if ((uint32_t) pDescriptorVirt & 0x00000003) {
dmacHw_ASSERT(0);
return -1;
}
/* Check if enough space has been allocated for descriptor ring */
if (len < dmacHw_descriptorLen(num)) {
return -1;
}
pRing = dmacHw_GET_DESC_RING(pDescriptorVirt);
pRing->pHead =
(dmacHw_DESC_t *) ((uint32_t) pRing + sizeof(dmacHw_DESC_RING_t));
pRing->pFree = pRing->pTail = pRing->pEnd = pRing->pHead;
pRing->pProg = dmacHw_DESC_INIT;
/* Initialize link item chain, starting from the head */
pDesc = pRing->pHead;
/* Find the offset between virtual to physical address */
pRing->virt2PhyOffset = (uint32_t) pDescriptorVirt - descriptorPhyAddr;
/* Form the descriptor ring */
for (i = 0; i < num - 1; i++) {
/* Clear link list item */
memset((void *)pDesc, 0, sizeof(dmacHw_DESC_t));
/* Point to the next item in the physical address */
pDesc->llpPhy = (uint32_t) (pDesc + 1) - pRing->virt2PhyOffset;
/* Point to the next item in the virtual address */
pDesc->llp = (uint32_t) (pDesc + 1);
/* Mark descriptor is ready to use */
pDesc->ctl.hi = dmacHw_DESC_FREE;
/* Look into next link list item */
pDesc++;
}
/* Clear last link list item */
memset((void *)pDesc, 0, sizeof(dmacHw_DESC_t));
/* Last item pointing to the first item in the
physical address to complete the ring */
pDesc->llpPhy = (uint32_t) pRing->pHead - pRing->virt2PhyOffset;
/* Last item pointing to the first item in the
virtual address to complete the ring
*/
pDesc->llp = (uint32_t) pRing->pHead;
/* Mark descriptor is ready to use */
pDesc->ctl.hi = dmacHw_DESC_FREE;
/* Set the number of descriptors in the ring */
pRing->num = num;
return 0;
}
/****************************************************************************/
/**
* @brief Configure DMA channel
*
* @return 0 : On success
* -1 : On failure
*/
/****************************************************************************/
int dmacHw_configChannel(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
dmacHw_CONFIG_t *pConfig /* [ IN ] Configuration settings */
) {
dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
uint32_t cfgHigh = 0;
int srcTrSize;
int dstTrSize;
pCblk->varDataStarted = 0;
pCblk->userData = NULL;
/* Configure
- Burst transaction when enough data in available in FIFO
- AHB Access protection 1
- Source and destination peripheral ports
*/
cfgHigh =
dmacHw_REG_CFG_HI_FIFO_ENOUGH | dmacHw_REG_CFG_HI_AHB_HPROT_1 |
dmacHw_SRC_PERI_INTF(pConfig->
srcPeripheralPort) |
dmacHw_DST_PERI_INTF(pConfig->dstPeripheralPort);
/* Set priority */
dmacHw_SET_CHANNEL_PRIORITY(pCblk->module, pCblk->channel,
pConfig->channelPriority);
if (pConfig->dstStatusRegisterAddress != 0) {
/* Destination status update enable */
cfgHigh |= dmacHw_REG_CFG_HI_UPDATE_DST_STAT;
/* Configure status registers */
dmacHw_SET_DSTATAR(pCblk->module, pCblk->channel,
pConfig->dstStatusRegisterAddress);
}
if (pConfig->srcStatusRegisterAddress != 0) {
/* Source status update enable */
cfgHigh |= dmacHw_REG_CFG_HI_UPDATE_SRC_STAT;
/* Source status update enable */
dmacHw_SET_SSTATAR(pCblk->module, pCblk->channel,
pConfig->srcStatusRegisterAddress);
}
/* Configure the config high register */
dmacHw_GET_CONFIG_HI(pCblk->module, pCblk->channel) = cfgHigh;
/* Clear all raw interrupt status */
dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
/* Configure block interrupt */
if (pConfig->blockTransferInterrupt == dmacHw_INTERRUPT_ENABLE) {
dmacHw_BLOCK_INT_ENABLE(pCblk->module, pCblk->channel);
} else {
dmacHw_BLOCK_INT_DISABLE(pCblk->module, pCblk->channel);
}
/* Configure complete transfer interrupt */
if (pConfig->completeTransferInterrupt == dmacHw_INTERRUPT_ENABLE) {
dmacHw_TRAN_INT_ENABLE(pCblk->module, pCblk->channel);
} else {
dmacHw_TRAN_INT_DISABLE(pCblk->module, pCblk->channel);
}
/* Configure error interrupt */
if (pConfig->errorInterrupt == dmacHw_INTERRUPT_ENABLE) {
dmacHw_ERROR_INT_ENABLE(pCblk->module, pCblk->channel);
} else {
dmacHw_ERROR_INT_DISABLE(pCblk->module, pCblk->channel);
}
/* Configure gather register */
if (pConfig->srcGatherWidth) {
srcTrSize =
dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
if (!
((pConfig->srcGatherWidth % srcTrSize)
&& (pConfig->srcGatherJump % srcTrSize))) {
dmacHw_REG_SGR_LO(pCblk->module, pCblk->channel) =
((pConfig->srcGatherWidth /
srcTrSize) << 20) | (pConfig->srcGatherJump /
srcTrSize);
} else {
return -1;
}
}
/* Configure scatter register */
if (pConfig->dstScatterWidth) {
dstTrSize =
dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
if (!
((pConfig->dstScatterWidth % dstTrSize)
&& (pConfig->dstScatterJump % dstTrSize))) {
dmacHw_REG_DSR_LO(pCblk->module, pCblk->channel) =
((pConfig->dstScatterWidth /
dstTrSize) << 20) | (pConfig->dstScatterJump /
dstTrSize);
} else {
return -1;
}
}
return 0;
}
/****************************************************************************/
/**
* @brief Indicates whether DMA transfer is in progress or completed
*
* @return DMA transfer status
* dmacHw_TRANSFER_STATUS_BUSY: DMA Transfer ongoing
* dmacHw_TRANSFER_STATUS_DONE: DMA Transfer completed
* dmacHw_TRANSFER_STATUS_ERROR: DMA Transfer error
*
*/
/****************************************************************************/
dmacHw_TRANSFER_STATUS_e dmacHw_transferCompleted(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
) {
dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
if (CHANNEL_BUSY(pCblk->module, pCblk->channel)) {
return dmacHw_TRANSFER_STATUS_BUSY;
} else if (dmacHw_REG_INT_RAW_ERROR(pCblk->module) &
(0x00000001 << pCblk->channel)) {
return dmacHw_TRANSFER_STATUS_ERROR;
}
return dmacHw_TRANSFER_STATUS_DONE;
}
/****************************************************************************/
/**
* @brief Set descriptors for known data length
*
* When DMA has to work as a flow controller, this function prepares the
* descriptor chain to transfer data
*
* from:
* - Memory to memory
* - Peripheral to memory
* - Memory to Peripheral
* - Peripheral to Peripheral
*
* @return -1 - On failure
* 0 - On success
*
*/
/****************************************************************************/
int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
void *pDescriptor, /* [ IN ] Descriptor buffer */
void *pSrcAddr, /* [ IN ] Source (Peripheral/Memory) address */
void *pDstAddr, /* [ IN ] Destination (Peripheral/Memory) address */
size_t dataLen /* [ IN ] Data length in bytes */
) {
dmacHw_TRANSACTION_WIDTH_e dstTrWidth;
dmacHw_TRANSACTION_WIDTH_e srcTrWidth;
dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
dmacHw_DESC_t *pStart;
dmacHw_DESC_t *pProg;
int srcTs = 0;
int blkTs = 0;
int oddSize = 0;
int descCount = 0;
int count = 0;
int dstTrSize = 0;
int srcTrSize = 0;
uint32_t maxBlockSize = dmacHw_MAX_BLOCKSIZE;
dstTrSize = dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
/* Skip Tx if buffer is NULL or length is unknown */
if ((pSrcAddr == NULL) || (pDstAddr == NULL) || (dataLen == 0)) {
/* Do not initiate transfer */
return -1;
}
/* Ensure scatter and gather are transaction aligned */
if ((pConfig->srcGatherWidth % srcTrSize)
|| (pConfig->dstScatterWidth % dstTrSize)) {
return -2;
}
/*
Background 1: DMAC can not perform DMA if source and destination addresses are
not properly aligned with the channel's transaction width. So, for successful
DMA transfer, transaction width must be set according to the alignment of the
source and destination address.
*/
/* Adjust destination transaction width if destination address is not aligned properly */
dstTrWidth = pConfig->dstMaxTransactionWidth;
while (dmacHw_ADDRESS_MASK(dstTrSize) & (uint32_t) pDstAddr) {
dstTrWidth = dmacHw_GetNextTrWidth(dstTrWidth);
dstTrSize = dmacHw_GetTrWidthInBytes(dstTrWidth);
}
/* Adjust source transaction width if source address is not aligned properly */
srcTrWidth = pConfig->srcMaxTransactionWidth;
while (dmacHw_ADDRESS_MASK(srcTrSize) & (uint32_t) pSrcAddr) {
srcTrWidth = dmacHw_GetNextTrWidth(srcTrWidth);
srcTrSize = dmacHw_GetTrWidthInBytes(srcTrWidth);
}
/* Find the maximum transaction per descriptor */
if (pConfig->maxDataPerBlock
&& ((pConfig->maxDataPerBlock / srcTrSize) <
dmacHw_MAX_BLOCKSIZE)) {
maxBlockSize = pConfig->maxDataPerBlock / srcTrSize;
}
/* Find number of source transactions needed to complete the DMA transfer */
srcTs = dataLen / srcTrSize;
/* Find the odd number of bytes that need to be transferred as single byte transaction width */
if (srcTs && (dstTrSize > srcTrSize)) {
oddSize = dataLen % dstTrSize;
/* Adjust source transaction count due to "oddSize" */
srcTs = srcTs - (oddSize / srcTrSize);
} else {
oddSize = dataLen % srcTrSize;
}
/* Adjust "descCount" due to "oddSize" */
if (oddSize) {
descCount++;
}
/* Find the number of descriptor needed for total "srcTs" */
if (srcTs) {
descCount += ((srcTs - 1) / maxBlockSize) + 1;
}
/* Check the availability of "descCount" discriptors in the ring */
pProg = pRing->pHead;
for (count = 0; (descCount <= pRing->num) && (count < descCount);
count++) {
if ((pProg->ctl.hi & dmacHw_DESC_FREE) == 0) {
/* Sufficient descriptors are not available */
return -3;
}
pProg = (dmacHw_DESC_t *) pProg->llp;
}
/* Remember the link list item to program the channel registers */
pStart = pProg = pRing->pHead;
/* Make a link list with "descCount(=count)" number of descriptors */
while (count) {
/* Reset channel control information */
pProg->ctl.lo = 0;
/* Enable source gather if configured */
if (pConfig->srcGatherWidth) {
pProg->ctl.lo |= dmacHw_REG_CTL_SG_ENABLE;
}
/* Enable destination scatter if configured */
if (pConfig->dstScatterWidth) {
pProg->ctl.lo |= dmacHw_REG_CTL_DS_ENABLE;
}
/* Set source and destination address */
pProg->sar = (uint32_t) pSrcAddr;
pProg->dar = (uint32_t) pDstAddr;
/* Use "devCtl" to mark that user memory need to be freed later if needed */
if (pProg == pRing->pHead) {
pProg->devCtl = dmacHw_FREE_USER_MEMORY;
} else {
pProg->devCtl = 0;
}
blkTs = srcTs;
/* Special treatmeant for last descriptor */
if (count == 1) {
/* Mark the last descriptor */
pProg->ctl.lo &=
~(dmacHw_REG_CTL_LLP_DST_EN |
dmacHw_REG_CTL_LLP_SRC_EN);
/* Treatment for odd data bytes */
if (oddSize) {
/* Adjust for single byte transaction width */
switch (pConfig->transferType) {
case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
dstTrWidth =
dmacHw_DST_TRANSACTION_WIDTH_8;
blkTs =
(oddSize / srcTrSize) +
((oddSize % srcTrSize) ? 1 : 0);
break;
case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
srcTrWidth =
dmacHw_SRC_TRANSACTION_WIDTH_8;
blkTs = oddSize;
break;
case dmacHw_TRANSFER_TYPE_MEM_TO_MEM:
srcTrWidth =
dmacHw_SRC_TRANSACTION_WIDTH_8;
dstTrWidth =
dmacHw_DST_TRANSACTION_WIDTH_8;
blkTs = oddSize;
break;
case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL:
/* Do not adjust the transaction width */
break;
}
} else {
srcTs -= blkTs;
}
} else {
if (srcTs / maxBlockSize) {
blkTs = maxBlockSize;
}
/* Remaining source transactions for next iteration */
srcTs -= blkTs;
}
/* Must have a valid source transactions */
dmacHw_ASSERT(blkTs > 0);
/* Set control information */
if (pConfig->flowControler == dmacHw_FLOW_CONTROL_DMA) {
pProg->ctl.lo |= pConfig->transferType |
pConfig->srcUpdate |
pConfig->dstUpdate |
srcTrWidth |
dstTrWidth |
pConfig->srcMaxBurstWidth |
pConfig->dstMaxBurstWidth |
pConfig->srcMasterInterface |
pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN;
} else {
uint32_t transferType = 0;
switch (pConfig->transferType) {
case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
transferType = dmacHw_REG_CTL_TTFC_PM_PERI;
break;
case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
transferType = dmacHw_REG_CTL_TTFC_MP_PERI;
break;
default:
dmacHw_ASSERT(0);
}
pProg->ctl.lo |= transferType |
pConfig->srcUpdate |
pConfig->dstUpdate |
srcTrWidth |
dstTrWidth |
pConfig->srcMaxBurstWidth |
pConfig->dstMaxBurstWidth |
pConfig->srcMasterInterface |
pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN;
}
/* Set block transaction size */
pProg->ctl.hi = blkTs & dmacHw_REG_CTL_BLOCK_TS_MASK;
/* Look for next descriptor */
if (count > 1) {
/* Point to the next descriptor */
pProg = (dmacHw_DESC_t *) pProg->llp;
/* Update source and destination address for next iteration */
switch (pConfig->transferType) {
case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
if (pConfig->dstScatterWidth) {
pDstAddr =
(char *)pDstAddr +
blkTs * srcTrSize +
(((blkTs * srcTrSize) /
pConfig->dstScatterWidth) *
pConfig->dstScatterJump);
} else {
pDstAddr =
(char *)pDstAddr +
blkTs * srcTrSize;
}
break;
case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
if (pConfig->srcGatherWidth) {
pSrcAddr =
(char *)pDstAddr +
blkTs * srcTrSize +
(((blkTs * srcTrSize) /
pConfig->srcGatherWidth) *
pConfig->srcGatherJump);
} else {
pSrcAddr =
(char *)pSrcAddr +
blkTs * srcTrSize;
}
break;
case dmacHw_TRANSFER_TYPE_MEM_TO_MEM:
if (pConfig->dstScatterWidth) {
pDstAddr =
(char *)pDstAddr +
blkTs * srcTrSize +
(((blkTs * srcTrSize) /
pConfig->dstScatterWidth) *
pConfig->dstScatterJump);
} else {
pDstAddr =
(char *)pDstAddr +
blkTs * srcTrSize;
}
if (pConfig->srcGatherWidth) {
pSrcAddr =
(char *)pDstAddr +
blkTs * srcTrSize +
(((blkTs * srcTrSize) /
pConfig->srcGatherWidth) *
pConfig->srcGatherJump);
} else {
pSrcAddr =
(char *)pSrcAddr +
blkTs * srcTrSize;
}
break;
case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL:
/* Do not adjust the address */
break;
default:
dmacHw_ASSERT(0);
}
} else {
/* At the end of transfer "srcTs" must be zero */
dmacHw_ASSERT(srcTs == 0);
}
count--;
}
/* Remember the descriptor to initialize the registers */
if (pRing->pProg == dmacHw_DESC_INIT) {
pRing->pProg = pStart;
}
/* Indicate that the descriptor is updated */
pRing->pEnd = pProg;
/* Head pointing to the next descriptor */
pRing->pHead = (dmacHw_DESC_t *) pProg->llp;
/* Update Tail pointer if destination is a peripheral,
because no one is going to read from the pTail
*/
if (!dmacHw_DST_IS_MEMORY(pConfig->transferType)) {
pRing->pTail = pRing->pHead;
}
return 0;
}
/****************************************************************************/
/**
* @brief Provides DMA controller attributes
*
*
* @return DMA controller attributes
*
* @note
* None
*/
/****************************************************************************/
uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
dmacHw_CONTROLLER_ATTRIB_e attr /* [ IN ] DMA Controller attribute of type dmacHw_CONTROLLER_ATTRIB_e */
) {
dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
switch (attr) {
case dmacHw_CONTROLLER_ATTRIB_CHANNEL_NUM:
return dmacHw_GET_NUM_CHANNEL(pCblk->module);
case dmacHw_CONTROLLER_ATTRIB_CHANNEL_MAX_BLOCK_SIZE:
return (1 <<
(dmacHw_GET_MAX_BLOCK_SIZE
(pCblk->module, pCblk->module) + 2)) - 8;
case dmacHw_CONTROLLER_ATTRIB_MASTER_INTF_NUM:
return dmacHw_GET_NUM_INTERFACE(pCblk->module);
case dmacHw_CONTROLLER_ATTRIB_CHANNEL_BUS_WIDTH:
return 32 << dmacHw_GET_CHANNEL_DATA_WIDTH(pCblk->module,
pCblk->channel);
case dmacHw_CONTROLLER_ATTRIB_CHANNEL_FIFO_SIZE:
return GetFifoSize(handle);
}
dmacHw_ASSERT(0);
return 0;
}

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arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
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arch/arm/mach-bcmring/csp/tmr/Makefile
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obj-y += tmrHw.o

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arch/arm/mach-bcmring/csp/tmr/tmrHw.c
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@ -1,576 +0,0 @@
/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/****************************************************************************/
/**
* @file tmrHw.c
*
* @brief Low level Timer driver routines
*
* @note
*
* These routines provide basic timer functionality only.
*/
/****************************************************************************/
/* ---- Include Files ---------------------------------------------------- */
#include <csp/errno.h>
#include <csp/stdint.h>
#include <csp/tmrHw.h>
#include <mach/csp/tmrHw_reg.h>
#define tmrHw_ASSERT(a) if (!(a)) *(char *)0 = 0
#define tmrHw_MILLISEC_PER_SEC (1000)
#define tmrHw_LOW_1_RESOLUTION_COUNT (tmrHw_LOW_RESOLUTION_CLOCK / tmrHw_MILLISEC_PER_SEC)
#define tmrHw_LOW_1_MAX_MILLISEC (0xFFFFFFFF / tmrHw_LOW_1_RESOLUTION_COUNT)
#define tmrHw_LOW_16_RESOLUTION_COUNT (tmrHw_LOW_1_RESOLUTION_COUNT / 16)
#define tmrHw_LOW_16_MAX_MILLISEC (0xFFFFFFFF / tmrHw_LOW_16_RESOLUTION_COUNT)
#define tmrHw_LOW_256_RESOLUTION_COUNT (tmrHw_LOW_1_RESOLUTION_COUNT / 256)
#define tmrHw_LOW_256_MAX_MILLISEC (0xFFFFFFFF / tmrHw_LOW_256_RESOLUTION_COUNT)
#define tmrHw_HIGH_1_RESOLUTION_COUNT (tmrHw_HIGH_RESOLUTION_CLOCK / tmrHw_MILLISEC_PER_SEC)
#define tmrHw_HIGH_1_MAX_MILLISEC (0xFFFFFFFF / tmrHw_HIGH_1_RESOLUTION_COUNT)
#define tmrHw_HIGH_16_RESOLUTION_COUNT (tmrHw_HIGH_1_RESOLUTION_COUNT / 16)
#define tmrHw_HIGH_16_MAX_MILLISEC (0xFFFFFFFF / tmrHw_HIGH_16_RESOLUTION_COUNT)
#define tmrHw_HIGH_256_RESOLUTION_COUNT (tmrHw_HIGH_1_RESOLUTION_COUNT / 256)
#define tmrHw_HIGH_256_MAX_MILLISEC (0xFFFFFFFF / tmrHw_HIGH_256_RESOLUTION_COUNT)
static void ResetTimer(tmrHw_ID_t timerId)
__attribute__ ((section(".aramtext")));
static int tmrHw_divide(int num, int denom)
__attribute__ ((section(".aramtext")));
/****************************************************************************/
/**
* @brief Get timer capability
*
* This function returns various capabilities/attributes of a timer
*
* @return Capability
*
*/
/****************************************************************************/
uint32_t tmrHw_getTimerCapability(tmrHw_ID_t timerId, /* [ IN ] Timer Id */
tmrHw_CAPABILITY_e capability /* [ IN ] Timer capability */
) {
switch (capability) {
case tmrHw_CAPABILITY_CLOCK:
return (timerId <=
1) ? tmrHw_LOW_RESOLUTION_CLOCK :
tmrHw_HIGH_RESOLUTION_CLOCK;
case tmrHw_CAPABILITY_RESOLUTION:
return 32;
default:
return 0;
}
return 0;
}
/****************************************************************************/
/**
* @brief Resets a timer
*
* This function initializes timer
*
* @return void
*
*/
/****************************************************************************/
static void ResetTimer(tmrHw_ID_t timerId /* [ IN ] Timer Id */
) {
/* Reset timer */
pTmrHw[timerId].LoadValue = 0;
pTmrHw[timerId].CurrentValue = 0xFFFFFFFF;
pTmrHw[timerId].Control = 0;
pTmrHw[timerId].BackgroundLoad = 0;
/* Always configure as a 32 bit timer */
pTmrHw[timerId].Control |= tmrHw_CONTROL_32BIT;
/* Clear interrupt only if raw status interrupt is set */
if (pTmrHw[timerId].RawInterruptStatus) {
pTmrHw[timerId].InterruptClear = 0xFFFFFFFF;
}
}
/****************************************************************************/
/**
* @brief Sets counter value for an interval in ms
*
* @return On success: Effective counter value set
* On failure: 0
*
*/
/****************************************************************************/
static tmrHw_INTERVAL_t SetTimerPeriod(tmrHw_ID_t timerId, /* [ IN ] Timer Id */
tmrHw_INTERVAL_t msec /* [ IN ] Interval in milli-second */
) {
uint32_t scale = 0;
uint32_t count = 0;
if (timerId == 0 || timerId == 1) {
if (msec <= tmrHw_LOW_1_MAX_MILLISEC) {
pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
scale = tmrHw_LOW_1_RESOLUTION_COUNT;
} else if (msec <= tmrHw_LOW_16_MAX_MILLISEC) {
pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16;
scale = tmrHw_LOW_16_RESOLUTION_COUNT;
} else if (msec <= tmrHw_LOW_256_MAX_MILLISEC) {
pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256;
scale = tmrHw_LOW_256_RESOLUTION_COUNT;
} else {
return 0;
}
count = msec * scale;
/* Set counter value */
pTmrHw[timerId].LoadValue = count;
pTmrHw[timerId].BackgroundLoad = count;
} else if (timerId == 2 || timerId == 3) {
if (msec <= tmrHw_HIGH_1_MAX_MILLISEC) {
pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
scale = tmrHw_HIGH_1_RESOLUTION_COUNT;
} else if (msec <= tmrHw_HIGH_16_MAX_MILLISEC) {
pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16;
scale = tmrHw_HIGH_16_RESOLUTION_COUNT;
} else if (msec <= tmrHw_HIGH_256_MAX_MILLISEC) {
pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256;
scale = tmrHw_HIGH_256_RESOLUTION_COUNT;
} else {
return 0;
}
count = msec * scale;
/* Set counter value */
pTmrHw[timerId].LoadValue = count;
pTmrHw[timerId].BackgroundLoad = count;
}
return count / scale;
}
/****************************************************************************/
/**
* @brief Configures a periodic timer in terms of timer interrupt rate
*
* This function initializes a periodic timer to generate specific number of
* timer interrupt per second
*
* @return On success: Effective timer frequency
* On failure: 0
*
*/
/****************************************************************************/
tmrHw_RATE_t tmrHw_setPeriodicTimerRate(tmrHw_ID_t timerId, /* [ IN ] Timer Id */
tmrHw_RATE_t rate /* [ IN ] Number of timer interrupt per second */
) {
uint32_t resolution = 0;
uint32_t count = 0;
ResetTimer(timerId);
/* Set timer mode periodic */
pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC;
pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT;
/* Set timer in highest resolution */
pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
if (rate && (timerId == 0 || timerId == 1)) {
if (rate > tmrHw_LOW_RESOLUTION_CLOCK) {
return 0;
}
resolution = tmrHw_LOW_RESOLUTION_CLOCK;
} else if (rate && (timerId == 2 || timerId == 3)) {
if (rate > tmrHw_HIGH_RESOLUTION_CLOCK) {
return 0;
} else {
resolution = tmrHw_HIGH_RESOLUTION_CLOCK;
}
} else {
return 0;
}
/* Find the counter value */
count = resolution / rate;
/* Set counter value */
pTmrHw[timerId].LoadValue = count;
pTmrHw[timerId].BackgroundLoad = count;
return resolution / count;
}
/****************************************************************************/
/**
* @brief Configures a periodic timer to generate timer interrupt after
* certain time interval
*
* This function initializes a periodic timer to generate timer interrupt
* after every time interval in millisecond
*
* @return On success: Effective interval set in milli-second
* On failure: 0
*
*/
/****************************************************************************/
tmrHw_INTERVAL_t tmrHw_setPeriodicTimerInterval(tmrHw_ID_t timerId, /* [ IN ] Timer Id */
tmrHw_INTERVAL_t msec /* [ IN ] Interval in milli-second */
) {
ResetTimer(timerId);
/* Set timer mode periodic */
pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC;
pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT;
return SetTimerPeriod(timerId, msec);
}
/****************************************************************************/
/**
* @brief Configures a periodic timer to generate timer interrupt just once
* after certain time interval
*
* This function initializes a periodic timer to generate a single ticks after
* certain time interval in millisecond
*
* @return On success: Effective interval set in milli-second
* On failure: 0
*
*/
/****************************************************************************/
tmrHw_INTERVAL_t tmrHw_setOneshotTimerInterval(tmrHw_ID_t timerId, /* [ IN ] Timer Id */
tmrHw_INTERVAL_t msec /* [ IN ] Interval in milli-second */
) {
ResetTimer(timerId);
/* Set timer mode oneshot */
pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC;
pTmrHw[timerId].Control |= tmrHw_CONTROL_ONESHOT;
return SetTimerPeriod(timerId, msec);
}
/****************************************************************************/
/**
* @brief Configures a timer to run as a free running timer
*
* This function initializes a timer to run as a free running timer
*
* @return Timer resolution (count / sec)
*
*/
/****************************************************************************/
tmrHw_RATE_t tmrHw_setFreeRunningTimer(tmrHw_ID_t timerId, /* [ IN ] Timer Id */
uint32_t divider /* [ IN ] Dividing the clock frequency */
) {
uint32_t scale = 0;
ResetTimer(timerId);
/* Set timer as free running mode */
pTmrHw[timerId].Control &= ~tmrHw_CONTROL_PERIODIC;
pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT;
if (divider >= 64) {
pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256;
scale = 256;
} else if (divider >= 8) {
pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16;
scale = 16;
} else {
pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
scale = 1;
}
if (timerId == 0 || timerId == 1) {
return tmrHw_divide(tmrHw_LOW_RESOLUTION_CLOCK, scale);
} else if (timerId == 2 || timerId == 3) {
return tmrHw_divide(tmrHw_HIGH_RESOLUTION_CLOCK, scale);
}
return 0;
}
/****************************************************************************/
/**
* @brief Starts a timer
*
* This function starts a preconfigured timer
*
* @return -1 - On Failure
* 0 - On Success
*
*/
/****************************************************************************/
int tmrHw_startTimer(tmrHw_ID_t timerId /* [ IN ] Timer id */
) {
pTmrHw[timerId].Control |= tmrHw_CONTROL_TIMER_ENABLE;
return 0;
}
/****************************************************************************/
/**
* @brief Stops a timer
*
* This function stops a running timer
*
* @return -1 - On Failure
* 0 - On Success
*
*/
/****************************************************************************/
int tmrHw_stopTimer(tmrHw_ID_t timerId /* [ IN ] Timer id */
) {
pTmrHw[timerId].Control &= ~tmrHw_CONTROL_TIMER_ENABLE;
return 0;
}
/****************************************************************************/
/**
* @brief Gets current timer count
*
* This function returns the current timer value
*
* @return Current downcounting timer value
*
*/
/****************************************************************************/
uint32_t tmrHw_GetCurrentCount(tmrHw_ID_t timerId /* [ IN ] Timer id */
) {
/* return 32 bit timer value */
switch (pTmrHw[timerId].Control & tmrHw_CONTROL_MODE_MASK) {
case tmrHw_CONTROL_FREE_RUNNING:
if (pTmrHw[timerId].CurrentValue) {
return tmrHw_MAX_COUNT - pTmrHw[timerId].CurrentValue;
}
break;
case tmrHw_CONTROL_PERIODIC:
case tmrHw_CONTROL_ONESHOT:
return pTmrHw[timerId].BackgroundLoad -
pTmrHw[timerId].CurrentValue;
}
return 0;
}
/****************************************************************************/
/**
* @brief Gets timer count rate
*
* This function returns the number of counts per second
*
* @return Count rate
*
*/
/****************************************************************************/
tmrHw_RATE_t tmrHw_getCountRate(tmrHw_ID_t timerId /* [ IN ] Timer id */
) {
uint32_t divider = 0;
switch (pTmrHw[timerId].Control & tmrHw_CONTROL_PRESCALE_MASK) {
case tmrHw_CONTROL_PRESCALE_1:
divider = 1;
break;
case tmrHw_CONTROL_PRESCALE_16:
divider = 16;
break;
case tmrHw_CONTROL_PRESCALE_256:
divider = 256;
break;
default:
tmrHw_ASSERT(0);
}
if (timerId == 0 || timerId == 1) {
return tmrHw_divide(tmrHw_LOW_RESOLUTION_CLOCK, divider);
} else {
return tmrHw_divide(tmrHw_HIGH_RESOLUTION_CLOCK, divider);
}
return 0;
}
/****************************************************************************/
/**
* @brief Enables timer interrupt
*
* This function enables the timer interrupt
*
* @return N/A
*
*/
/****************************************************************************/
void tmrHw_enableInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */
) {
pTmrHw[timerId].Control |= tmrHw_CONTROL_INTERRUPT_ENABLE;
}
/****************************************************************************/
/**
* @brief Disables timer interrupt
*
* This function disable the timer interrupt
*
* @return N/A
*
*/
/****************************************************************************/
void tmrHw_disableInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */
) {
pTmrHw[timerId].Control &= ~tmrHw_CONTROL_INTERRUPT_ENABLE;
}
/****************************************************************************/
/**
* @brief Clears the interrupt
*
* This function clears the timer interrupt
*
* @return N/A
*
* @note
* Must be called under the context of ISR
*/
/****************************************************************************/
void tmrHw_clearInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */
) {
pTmrHw[timerId].InterruptClear = 0x1;
}
/****************************************************************************/
/**
* @brief Gets the interrupt status
*
* This function returns timer interrupt status
*
* @return Interrupt status
*/
/****************************************************************************/
tmrHw_INTERRUPT_STATUS_e tmrHw_getInterruptStatus(tmrHw_ID_t timerId /* [ IN ] Timer id */
) {
if (pTmrHw[timerId].InterruptStatus) {
return tmrHw_INTERRUPT_STATUS_SET;
} else {
return tmrHw_INTERRUPT_STATUS_UNSET;
}
}
/****************************************************************************/
/**
* @brief Indentifies a timer causing interrupt
*
* This functions returns a timer causing interrupt
*
* @return 0xFFFFFFFF : No timer causing an interrupt
* ! 0xFFFFFFFF : timer causing an interrupt
* @note
* tmrHw_clearIntrrupt() must be called with a valid timer id after calling this function
*/
/****************************************************************************/
tmrHw_ID_t tmrHw_getInterruptSource(void /* void */
) {
int i;
for (i = 0; i < tmrHw_TIMER_NUM_COUNT; i++) {
if (pTmrHw[i].InterruptStatus) {
return i;
}
}
return 0xFFFFFFFF;
}
/****************************************************************************/
/**
* @brief Displays specific timer registers
*
*
* @return void
*
*/
/****************************************************************************/
void tmrHw_printDebugInfo(tmrHw_ID_t timerId, /* [ IN ] Timer id */
int (*fpPrint) (const char *, ...) /* [ IN ] Print callback function */
) {
(*fpPrint) ("Displaying register contents \n\n");
(*fpPrint) ("Timer %d: Load value 0x%X\n", timerId,
pTmrHw[timerId].LoadValue);
(*fpPrint) ("Timer %d: Background load value 0x%X\n", timerId,
pTmrHw[timerId].BackgroundLoad);
(*fpPrint) ("Timer %d: Control 0x%X\n", timerId,
pTmrHw[timerId].Control);
(*fpPrint) ("Timer %d: Interrupt clear 0x%X\n", timerId,
pTmrHw[timerId].InterruptClear);
(*fpPrint) ("Timer %d: Interrupt raw interrupt 0x%X\n", timerId,
pTmrHw[timerId].RawInterruptStatus);
(*fpPrint) ("Timer %d: Interrupt status 0x%X\n", timerId,
pTmrHw[timerId].InterruptStatus);
}
/****************************************************************************/
/**
* @brief Use a timer to perform a busy wait delay for a number of usecs.
*
* @return N/A
*/
/****************************************************************************/
void tmrHw_udelay(tmrHw_ID_t timerId, /* [ IN ] Timer id */
unsigned long usecs /* [ IN ] usec to delay */
) {
tmrHw_RATE_t usec_tick_rate;
tmrHw_COUNT_t start_time;
tmrHw_COUNT_t delta_time;
start_time = tmrHw_GetCurrentCount(timerId);
usec_tick_rate = tmrHw_divide(tmrHw_getCountRate(timerId), 1000000);
delta_time = usecs * usec_tick_rate;
/* Busy wait */
while (delta_time > (tmrHw_GetCurrentCount(timerId) - start_time))
;
}
/****************************************************************************/
/**
* @brief Local Divide function
*
* This function does the divide
*
* @return divide value
*
*/
/****************************************************************************/
static int tmrHw_divide(int num, int denom)
{
int r;
int t = 1;
/* Shift denom and t up to the largest value to optimize algorithm */
/* t contains the units of each divide */
while ((denom & 0x40000000) == 0) { /* fails if denom=0 */
denom = denom << 1;
t = t << 1;
}
/* Initialize the result */
r = 0;
do {
/* Determine if there exists a positive remainder */
if ((num - denom) >= 0) {
/* Accumlate t to the result and calculate a new remainder */
num = num - denom;
r = r + t;
}
/* Continue to shift denom and shift t down to 0 */
denom = denom >> 1;
t = t >> 1;
} while (t != 0);
return r;
}

1518
arch/arm/mach-bcmring/dma.c
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593
arch/arm/mach-bcmring/dma_device.c
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@ -1,593 +0,0 @@
/*****************************************************************************
* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/****************************************************************************/
/**
* @file dma_device.c
*
* @brief private array of DMA_DeviceAttribute_t
*/
/****************************************************************************/
DMA_DeviceAttribute_t DMA_gDeviceAttribute[DMA_NUM_DEVICE_ENTRIES] = {
[DMA_DEVICE_MEM_TO_MEM] = /* MEM 2 MEM */
{
.flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
.name = "mem-to-mem",
.config = {
.srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
.dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
.transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
.transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
.srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
.dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
.completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
.errorInterrupt = dmacHw_INTERRUPT_ENABLE,
.channelPriority = dmacHw_CHANNEL_PRIORITY_7,
.srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
.dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
},
},
[DMA_DEVICE_VPM_MEM_TO_MEM] = /* VPM */
{
.flags = DMA_DEVICE_FLAG_IS_DEDICATED | DMA_DEVICE_FLAG_NO_ISR,
.name = "vpm",
.dedicatedController = 0,
.dedicatedChannel = 0,
/* reserve DMA0:0 for VPM */
},
[DMA_DEVICE_NAND_MEM_TO_MEM] = /* NAND */
{
.flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
.name = "nand",
.config = {
.srcPeripheralPort = 0,
.dstPeripheralPort = 0,
.srcStatusRegisterAddress = 0x00000000,
.dstStatusRegisterAddress = 0x00000000,
.transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
.srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
.dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
.srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
.dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
.srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
.dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
.completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
.errorInterrupt = dmacHw_INTERRUPT_ENABLE,
.channelPriority = dmacHw_CHANNEL_PRIORITY_6,
},
},
[DMA_DEVICE_PIF_MEM_TO_DEV] = /* PIF TX */
{
.flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1
| DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO
| DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST | DMA_DEVICE_FLAG_PORT_PER_DMAC,
.name = "pif_tx",
.dmacPort = {14, 5},
.config = {
.srcPeripheralPort = 0, /* SRC: memory */
/* dstPeripheralPort = 5 or 14 */
.srcStatusRegisterAddress = 0x00000000,
.dstStatusRegisterAddress = 0x00000000,
.srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
.dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
.transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
.srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
.dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
.completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
.errorInterrupt = dmacHw_INTERRUPT_ENABLE,
.channelPriority = dmacHw_CHANNEL_PRIORITY_7,
.srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
.dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
.srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
.dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
.maxDataPerBlock = 16256,
},
},
[DMA_DEVICE_PIF_DEV_TO_MEM] = /* PIF RX */
{
.flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1
| DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO
/* DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST */
| DMA_DEVICE_FLAG_PORT_PER_DMAC,
.name = "pif_rx",
.dmacPort = {14, 5},
.config = {
/* srcPeripheralPort = 5 or 14 */
.dstPeripheralPort = 0, /* DST: memory */
.srcStatusRegisterAddress = 0x00000000,
.dstStatusRegisterAddress = 0x00000000,
.srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
.dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
.transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
.srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
.dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
.completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
.errorInterrupt = dmacHw_INTERRUPT_ENABLE,
.channelPriority = dmacHw_CHANNEL_PRIORITY_7,
.srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
.dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
.srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
.dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
.maxDataPerBlock = 16256,
},
},
[DMA_DEVICE_I2S0_DEV_TO_MEM] = /* I2S RX */
{
.flags = DMA_DEVICE_FLAG_ON_DMA0,
.name = "i2s0_rx",
.config = {
.srcPeripheralPort = 0, /* SRC: I2S0 */
.dstPeripheralPort = 0, /* DST: memory */
.srcStatusRegisterAddress = 0,
.dstStatusRegisterAddress = 0,
.transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
.srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
.dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
.srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_16,
.dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
.srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
.dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
.blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
.completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
.errorInterrupt = dmacHw_INTERRUPT_ENABLE,
.channelPriority = dmacHw_CHANNEL_PRIORITY_7,
.transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
},
},
[DMA_DEVICE_I2S0_MEM_TO_DEV] = /* I2S TX */
{
.flags = DMA_DEVICE_FLAG_ON_DMA0,
.name = "i2s0_tx",
.config = {
.srcPeripheralPort = 0, /* SRC: memory */
.dstPeripheralPort = 1, /* DST: I2S0 */
.srcStatusRegisterAddress = 0,
.dstStatusRegisterAddress = 0,
.transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
.srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
.dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
.srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
.dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_16,
.srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
.dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
.blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
.completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
.errorInterrupt = dmacHw_INTERRUPT_ENABLE,
.channelPriority = dmacHw_CHANNEL_PRIORITY_7,
.transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
},
},
[DMA_DEVICE_I2S1_DEV_TO_MEM] = /* I2S1 RX */
{
.flags = DMA_DEVICE_FLAG_ON_DMA1,
.name = "i2s1_rx",
.config = {
.srcPeripheralPort = 2, /* SRC: I2S1 */
.dstPeripheralPort = 0, /* DST: memory */
.srcStatusRegisterAddress = 0,
.dstStatusRegisterAddress = 0,
.transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
.srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
.dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
.srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_16,
.dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
.srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
.dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
.blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
.completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
.errorInterrupt = dmacHw_INTERRUPT_ENABLE,
.channelPriority = dmacHw_CHANNEL_PRIORITY_7,
.transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
},
},
[DMA_DEVICE_I2S1_MEM_TO_DEV] = /* I2S1 TX */
{
.flags = DMA_DEVICE_FLAG_ON_DMA1,
.name = "i2s1_tx",
.config = {
.srcPeripheralPort = 0, /* SRC: memory */
.dstPeripheralPort = 3, /* DST: I2S1 */
.srcStatusRegisterAddress = 0,
.dstStatusRegisterAddress = 0,
.transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
.srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
.dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
.srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
.dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_16,
.srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
.dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
.blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
.completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
.errorInterrupt = dmacHw_INTERRUPT_ENABLE,
.channelPriority = dmacHw_CHANNEL_PRIORITY_7,
.transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
},
},
[DMA_DEVICE_ESW_MEM_TO_DEV] = /* ESW TX */
{
.name = "esw_tx",
.flags = DMA_DEVICE_FLAG_IS_DEDICATED,
.dedicatedController = 1,
.dedicatedChannel = 3,
.config = {
.srcPeripheralPort = 0, /* SRC: memory */
.dstPeripheralPort = 1, /* DST: ESW (MTP) */
.completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
.errorInterrupt = dmacHw_INTERRUPT_DISABLE,
/* DMAx_AHB_SSTATARy */
.srcStatusRegisterAddress = 0x00000000,
/* DMAx_AHB_DSTATARy */
.dstStatusRegisterAddress = 0x30490010,
/* DMAx_AHB_CFGy */
.channelPriority = dmacHw_CHANNEL_PRIORITY_7,
/* DMAx_AHB_CTLy */
.srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
.dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
.transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
.srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
.dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
.srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
.dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
.srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
.dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
},
},
[DMA_DEVICE_ESW_DEV_TO_MEM] = /* ESW RX */
{
.name = "esw_rx",
.flags = DMA_DEVICE_FLAG_IS_DEDICATED,
.dedicatedController = 1,
.dedicatedChannel = 2,
.config = {
.srcPeripheralPort = 0, /* SRC: ESW (PTM) */
.dstPeripheralPort = 0, /* DST: memory */
.completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
.errorInterrupt = dmacHw_INTERRUPT_DISABLE,
/* DMAx_AHB_SSTATARy */
.srcStatusRegisterAddress = 0x30480010,
/* DMAx_AHB_DSTATARy */
.dstStatusRegisterAddress = 0x00000000,
/* DMAx_AHB_CFGy */
.channelPriority = dmacHw_CHANNEL_PRIORITY_7,
/* DMAx_AHB_CTLy */
.srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
.dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
.transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
.srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
.dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
.srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
.dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
.srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
.dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
},
},
[DMA_DEVICE_APM_CODEC_A_DEV_TO_MEM] = /* APM Codec A Ingress */
{
.flags = DMA_DEVICE_FLAG_ON_DMA0,
.name = "apm_a_rx",
.config = {
.srcPeripheralPort = 2, /* SRC: Codec A Ingress FIFO */
.dstPeripheralPort = 0, /* DST: memory */
.srcStatusRegisterAddress = 0x00000000,
.dstStatusRegisterAddress = 0x00000000,
.srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
.dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
.transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
.srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
.dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
.blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
.completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
.errorInterrupt = dmacHw_INTERRUPT_ENABLE,
.channelPriority = dmacHw_CHANNEL_PRIORITY_7,
.srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
.dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
.srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
.dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
.transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
},
},
[DMA_DEVICE_APM_CODEC_A_MEM_TO_DEV] = /* APM Codec A Egress */
{
.flags = DMA_DEVICE_FLAG_ON_DMA0,
.name = "apm_a_tx",
.config = {
.srcPeripheralPort = 0, /* SRC: memory */
.dstPeripheralPort = 3, /* DST: Codec A Egress FIFO */
.srcStatusRegisterAddress = 0x00000000,
.dstStatusRegisterAddress = 0x00000000,
.srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
.dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
.transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
.srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
.dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
.blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
.completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
.errorInterrupt = dmacHw_INTERRUPT_ENABLE,
.channelPriority = dmacHw_CHANNEL_PRIORITY_7,
.srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
.dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
.srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
.dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
.transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
},
},
[DMA_DEVICE_APM_CODEC_B_DEV_TO_MEM] = /* APM Codec B Ingress */
{
.flags = DMA_DEVICE_FLAG_ON_DMA0,
.name = "apm_b_rx",
.config = {
.srcPeripheralPort = 4, /* SRC: Codec B Ingress FIFO */
.dstPeripheralPort = 0, /* DST: memory */
.srcStatusRegisterAddress = 0x00000000,
.dstStatusRegisterAddress = 0x00000000,
.srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
.dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
.transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
.srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
.dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
.blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
.completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
.errorInterrupt = dmacHw_INTERRUPT_ENABLE,
.channelPriority = dmacHw_CHANNEL_PRIORITY_7,
.srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
.dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
.srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
.dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
.transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
},
},
[DMA_DEVICE_APM_CODEC_B_MEM_TO_DEV] = /* APM Codec B Egress */
{
.flags = DMA_DEVICE_FLAG_ON_DMA0,
.name = "apm_b_tx",
.config = {
.srcPeripheralPort = 0, /* SRC: memory */
.dstPeripheralPort = 5, /* DST: Codec B Egress FIFO */
.srcStatusRegisterAddress = 0x00000000,
.dstStatusRegisterAddress = 0x00000000,
.srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
.dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
.transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
.srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
.dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
.blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
.completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
.errorInterrupt = dmacHw_INTERRUPT_ENABLE,
.channelPriority = dmacHw_CHANNEL_PRIORITY_7,
.srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
.dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
.srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
.dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
.transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
},
},
[DMA_DEVICE_APM_CODEC_C_DEV_TO_MEM] = /* APM Codec C Ingress */
{
.flags = DMA_DEVICE_FLAG_ON_DMA1,
.name = "apm_c_rx",
.config = {
.srcPeripheralPort = 4, /* SRC: Codec C Ingress FIFO */
.dstPeripheralPort = 0, /* DST: memory */
.srcStatusRegisterAddress = 0x00000000,
.dstStatusRegisterAddress = 0x00000000,
.srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
.dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
.transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
.srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
.dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
.blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
.completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
.errorInterrupt = dmacHw_INTERRUPT_ENABLE,
.channelPriority = dmacHw_CHANNEL_PRIORITY_7,
.srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
.dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
.srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
.dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
.transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
},
},
[DMA_DEVICE_APM_PCM0_DEV_TO_MEM] = /* PCM0 RX */
{
.flags = DMA_DEVICE_FLAG_ON_DMA0,
.name = "pcm0_rx",
.config = {
.srcPeripheralPort = 12, /* SRC: PCM0 */
.dstPeripheralPort = 0, /* DST: memory */
.srcStatusRegisterAddress = 0,
.dstStatusRegisterAddress = 0,
.transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
.srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
.dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
.srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
.dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
.srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
.dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
.blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
.completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
.errorInterrupt = dmacHw_INTERRUPT_ENABLE,
.channelPriority = dmacHw_CHANNEL_PRIORITY_7,
.transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
},
},
[DMA_DEVICE_APM_PCM0_MEM_TO_DEV] = /* PCM0 TX */
{
.flags = DMA_DEVICE_FLAG_ON_DMA0,
.name = "pcm0_tx",
.config = {
.srcPeripheralPort = 0, /* SRC: memory */
.dstPeripheralPort = 13, /* DST: PCM0 */
.srcStatusRegisterAddress = 0,
.dstStatusRegisterAddress = 0,
.transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
.srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
.dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
.srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
.dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
.srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
.dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
.blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
.completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
.errorInterrupt = dmacHw_INTERRUPT_ENABLE,
.channelPriority = dmacHw_CHANNEL_PRIORITY_7,
.transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
},
},
[DMA_DEVICE_APM_PCM1_DEV_TO_MEM] = /* PCM1 RX */
{
.flags = DMA_DEVICE_FLAG_ON_DMA1,
.name = "pcm1_rx",
.config = {
.srcPeripheralPort = 14, /* SRC: PCM1 */
.dstPeripheralPort = 0, /* DST: memory */
.srcStatusRegisterAddress = 0,
.dstStatusRegisterAddress = 0,
.transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
.srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
.dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
.srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
.dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
.srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
.dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
.blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
.completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
.errorInterrupt = dmacHw_INTERRUPT_ENABLE,
.channelPriority = dmacHw_CHANNEL_PRIORITY_7,
.transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
},
},
[DMA_DEVICE_APM_PCM1_MEM_TO_DEV] = /* PCM1 TX */
{
.flags = DMA_DEVICE_FLAG_ON_DMA1,
.name = "pcm1_tx",
.config = {
.srcPeripheralPort = 0, /* SRC: memory */
.dstPeripheralPort = 15, /* DST: PCM1 */
.srcStatusRegisterAddress = 0,
.dstStatusRegisterAddress = 0,
.transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
.srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
.dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
.srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
.dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
.srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
.dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
.blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
.completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
.errorInterrupt = dmacHw_INTERRUPT_ENABLE,
.channelPriority = dmacHw_CHANNEL_PRIORITY_7,
.transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
},
},
[DMA_DEVICE_SPUM_DEV_TO_MEM] = /* SPUM RX */
{
.flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
.name = "spum_rx",
.config = {
.srcPeripheralPort = 6, /* SRC: Codec A Ingress FIFO */
.dstPeripheralPort = 0, /* DST: memory */
.srcStatusRegisterAddress = 0x00000000,
.dstStatusRegisterAddress = 0x00000000,
.srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
.dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
.transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
.srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
.dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
.blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
.completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
.errorInterrupt = dmacHw_INTERRUPT_ENABLE,
.channelPriority = dmacHw_CHANNEL_PRIORITY_7,
.srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
.dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
/* Busrt size **MUST** be 16 for SPUM to work */
.srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_16,
.dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_16,
.transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
/* on the RX side, SPU needs to be the flow controller */
.flowControler = dmacHw_FLOW_CONTROL_PERIPHERAL,
},
},
[DMA_DEVICE_SPUM_MEM_TO_DEV] = /* SPUM TX */
{
.flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
.name = "spum_tx",
.config = {
.srcPeripheralPort = 0, /* SRC: memory */
.dstPeripheralPort = 7, /* DST: SPUM */
.srcStatusRegisterAddress = 0x00000000,
.dstStatusRegisterAddress = 0x00000000,
.srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
.dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
.transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
.srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
.dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
.blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
.completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
.errorInterrupt = dmacHw_INTERRUPT_ENABLE,
.channelPriority = dmacHw_CHANNEL_PRIORITY_7,
.srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
.dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
/* Busrt size **MUST** be 16 for SPUM to work */
.srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_16,
.dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_16,
.transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
},
},
[DMA_DEVICE_MEM_TO_VRAM] = /* MEM 2 VRAM */
{
.flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
.name = "mem-to-vram",
.config = {
.srcPeripheralPort = 0, /* SRC: memory */
.srcStatusRegisterAddress = 0x00000000,
.dstStatusRegisterAddress = 0x00000000,
.srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
.dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
.transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
.srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
.dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
.completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
.errorInterrupt = dmacHw_INTERRUPT_ENABLE,
.channelPriority = dmacHw_CHANNEL_PRIORITY_7,
.srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
.dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
.srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
.dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
},
},
[DMA_DEVICE_VRAM_TO_MEM] = /* VRAM 2 MEM */
{
.flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
.name = "vram-to-mem",
.config = {
.dstPeripheralPort = 0, /* DST: memory */
.srcStatusRegisterAddress = 0x00000000,
.dstStatusRegisterAddress = 0x00000000,
.srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
.dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
.transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
.srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
.dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
.completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
.errorInterrupt = dmacHw_INTERRUPT_ENABLE,
.channelPriority = dmacHw_CHANNEL_PRIORITY_7,
.srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
.dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
.srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
.dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
},
},
};
EXPORT_SYMBOL(DMA_gDeviceAttribute); /* primarily for dma-test.c */

13
arch/arm/mach-bcmring/include/cfg_global.h
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@ -1,13 +0,0 @@
#ifndef _CFG_GLOBAL_H_
#define _CFG_GLOBAL_H_
#include <cfg_global_defines.h>
#define CFG_GLOBAL_CHIP BCM11107
#define CFG_GLOBAL_CHIP_FAMILY CFG_GLOBAL_CHIP_FAMILY_BCMRING
#define CFG_GLOBAL_CHIP_REV 0xB0
#define CFG_GLOBAL_RAM_SIZE 0x10000000
#define CFG_GLOBAL_RAM_BASE 0x00000000
#define CFG_GLOBAL_RAM_RESERVED_SIZE 0x000000
#endif /* _CFG_GLOBAL_H_ */

40
arch/arm/mach-bcmring/include/cfg_global_defines.h
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@ -1,40 +0,0 @@
/*****************************************************************************
* Copyright 2006 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
#ifndef CFG_GLOBAL_DEFINES_H
#define CFG_GLOBAL_DEFINES_H
/* CHIP */
#define BCM1103 1
#define BCM1191 4
#define BCM2153 5
#define BCM2820 6
#define BCM2826 8
#define FPGA11107 9
#define BCM11107 10
#define BCM11109 11
#define BCM11170 12
#define BCM11110 13
#define BCM11211 14
/* CFG_GLOBAL_CHIP_FAMILY types */
#define CFG_GLOBAL_CHIP_FAMILY_NONE 0
#define CFG_GLOBAL_CHIP_FAMILY_BCM116X 2
#define CFG_GLOBAL_CHIP_FAMILY_BCMRING 4
#define CFG_GLOBAL_CHIP_FAMILY_BCM1103 8
#define IMAGE_HEADER_SIZE_CHECKSUM 4
#endif

35
arch/arm/mach-bcmring/include/csp/cache.h
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@ -1,35 +0,0 @@
/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
#ifndef CSP_CACHE_H
#define CSP_CACHE_H
/* ---- Include Files ---------------------------------------------------- */
#include <csp/stdint.h>
/* ---- Public Constants and Types --------------------------------------- */
#if defined(__KERNEL__) && !defined(STANDALONE)
#include <asm/cacheflush.h>
#define CSP_CACHE_FLUSH_ALL flush_cache_all()
#else
#define CSP_CACHE_FLUSH_ALL
#endif
#endif /* CSP_CACHE_H */

36
arch/arm/mach-bcmring/include/csp/delay.h
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@ -1,36 +0,0 @@
/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
#ifndef CSP_DELAY_H
#define CSP_DELAY_H
/* ---- Include Files ---------------------------------------------------- */
/* Some CSP routines require use of the following delay routines. Use the OS */
/* version if available, otherwise use a CSP specific definition. */
/* void udelay(unsigned long usecs); */
/* void mdelay(unsigned long msecs); */
#if defined(__KERNEL__) && !defined(STANDALONE)
#include <linux/delay.h>
#else
#include <mach/csp/delay.h>
#endif
/* ---- Public Constants and Types --------------------------------------- */
/* ---- Public Variable Externs ------------------------------------------ */
/* ---- Public Function Prototypes --------------------------------------- */
#endif /* CSP_DELAY_H */

596
arch/arm/mach-bcmring/include/csp/dmacHw.h
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@ -1,596 +0,0 @@
/*****************************************************************************
* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/****************************************************************************/
/**
* @file dmacHw.h
*
* @brief API definitions for low level DMA controller driver
*
*/
/****************************************************************************/
#ifndef _DMACHW_H
#define _DMACHW_H
#include <stddef.h>
#include <csp/stdint.h>
#include <mach/csp/dmacHw_reg.h>
/* Define DMA Channel ID using DMA controller number (m) and channel number (c).
System specific channel ID should be defined as follows
For example:
#include <dmacHw.h>
...
#define systemHw_LCD_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,5)
#define systemHw_SWITCH_RX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,0)
#define systemHw_SWITCH_TX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,1)
#define systemHw_APM_RX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,3)
#define systemHw_APM_TX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,4)
...
#define systemHw_SHARED1_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(1,4)
#define systemHw_SHARED2_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(1,5)
#define systemHw_SHARED3_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,6)
...
*/
#define dmacHw_MAKE_CHANNEL_ID(m, c) (m << 8 | c)
typedef enum {
dmacHw_CHANNEL_PRIORITY_0 = dmacHw_REG_CFG_LO_CH_PRIORITY_0, /* Channel priority 0. Lowest priority DMA channel */
dmacHw_CHANNEL_PRIORITY_1 = dmacHw_REG_CFG_LO_CH_PRIORITY_1, /* Channel priority 1 */
dmacHw_CHANNEL_PRIORITY_2 = dmacHw_REG_CFG_LO_CH_PRIORITY_2, /* Channel priority 2 */
dmacHw_CHANNEL_PRIORITY_3 = dmacHw_REG_CFG_LO_CH_PRIORITY_3, /* Channel priority 3 */
dmacHw_CHANNEL_PRIORITY_4 = dmacHw_REG_CFG_LO_CH_PRIORITY_4, /* Channel priority 4 */
dmacHw_CHANNEL_PRIORITY_5 = dmacHw_REG_CFG_LO_CH_PRIORITY_5, /* Channel priority 5 */
dmacHw_CHANNEL_PRIORITY_6 = dmacHw_REG_CFG_LO_CH_PRIORITY_6, /* Channel priority 6 */
dmacHw_CHANNEL_PRIORITY_7 = dmacHw_REG_CFG_LO_CH_PRIORITY_7 /* Channel priority 7. Highest priority DMA channel */
} dmacHw_CHANNEL_PRIORITY_e;
/* Source destination master interface */
typedef enum {
dmacHw_SRC_MASTER_INTERFACE_1 = dmacHw_REG_CTL_SMS_1, /* Source DMA master interface 1 */
dmacHw_SRC_MASTER_INTERFACE_2 = dmacHw_REG_CTL_SMS_2, /* Source DMA master interface 2 */
dmacHw_DST_MASTER_INTERFACE_1 = dmacHw_REG_CTL_DMS_1, /* Destination DMA master interface 1 */
dmacHw_DST_MASTER_INTERFACE_2 = dmacHw_REG_CTL_DMS_2 /* Destination DMA master interface 2 */
} dmacHw_MASTER_INTERFACE_e;
typedef enum {
dmacHw_SRC_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_SRC_TR_WIDTH_8, /* Source 8 bit (1 byte) per transaction */
dmacHw_SRC_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_SRC_TR_WIDTH_16, /* Source 16 bit (2 byte) per transaction */
dmacHw_SRC_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_SRC_TR_WIDTH_32, /* Source 32 bit (4 byte) per transaction */
dmacHw_SRC_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_SRC_TR_WIDTH_64, /* Source 64 bit (8 byte) per transaction */
dmacHw_DST_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_DST_TR_WIDTH_8, /* Destination 8 bit (1 byte) per transaction */
dmacHw_DST_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_DST_TR_WIDTH_16, /* Destination 16 bit (2 byte) per transaction */
dmacHw_DST_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_DST_TR_WIDTH_32, /* Destination 32 bit (4 byte) per transaction */
dmacHw_DST_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_DST_TR_WIDTH_64 /* Destination 64 bit (8 byte) per transaction */
} dmacHw_TRANSACTION_WIDTH_e;
typedef enum {
dmacHw_SRC_BURST_WIDTH_0 = dmacHw_REG_CTL_SRC_MSIZE_0, /* Source No burst */
dmacHw_SRC_BURST_WIDTH_4 = dmacHw_REG_CTL_SRC_MSIZE_4, /* Source 4 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
dmacHw_SRC_BURST_WIDTH_8 = dmacHw_REG_CTL_SRC_MSIZE_8, /* Source 8 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
dmacHw_SRC_BURST_WIDTH_16 = dmacHw_REG_CTL_SRC_MSIZE_16, /* Source 16 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
dmacHw_DST_BURST_WIDTH_0 = dmacHw_REG_CTL_DST_MSIZE_0, /* Destination No burst */
dmacHw_DST_BURST_WIDTH_4 = dmacHw_REG_CTL_DST_MSIZE_4, /* Destination 4 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
dmacHw_DST_BURST_WIDTH_8 = dmacHw_REG_CTL_DST_MSIZE_8, /* Destination 8 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
dmacHw_DST_BURST_WIDTH_16 = dmacHw_REG_CTL_DST_MSIZE_16 /* Destination 16 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
} dmacHw_BURST_WIDTH_e;
typedef enum {
dmacHw_TRANSFER_TYPE_MEM_TO_MEM = dmacHw_REG_CTL_TTFC_MM_DMAC, /* Memory to memory transfer */
dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM = dmacHw_REG_CTL_TTFC_PM_DMAC, /* Peripheral to memory transfer */
dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL = dmacHw_REG_CTL_TTFC_MP_DMAC, /* Memory to peripheral transfer */
dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL = dmacHw_REG_CTL_TTFC_PP_DMAC /* Peripheral to peripheral transfer */
} dmacHw_TRANSFER_TYPE_e;
typedef enum {
dmacHw_TRANSFER_MODE_PERREQUEST, /* Block transfer per DMA request */
dmacHw_TRANSFER_MODE_CONTINUOUS, /* Continuous transfer of streaming data */
dmacHw_TRANSFER_MODE_PERIODIC /* Periodic transfer of streaming data */
} dmacHw_TRANSFER_MODE_e;
typedef enum {
dmacHw_SRC_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_SINC_INC, /* Increment source address after every transaction */
dmacHw_SRC_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_SINC_DEC, /* Decrement source address after every transaction */
dmacHw_DST_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_DINC_INC, /* Increment destination address after every transaction */
dmacHw_DST_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_DINC_DEC, /* Decrement destination address after every transaction */
dmacHw_SRC_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_SINC_NC, /* No change in source address after every transaction */
dmacHw_DST_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_DINC_NC /* No change in destination address after every transaction */
} dmacHw_ADDRESS_UPDATE_MODE_e;
typedef enum {
dmacHw_FLOW_CONTROL_DMA, /* DMA working as flow controller (default) */
dmacHw_FLOW_CONTROL_PERIPHERAL /* Peripheral working as flow controller */
} dmacHw_FLOW_CONTROL_e;
typedef enum {
dmacHw_TRANSFER_STATUS_BUSY, /* DMA Transfer ongoing */
dmacHw_TRANSFER_STATUS_DONE, /* DMA Transfer completed */
dmacHw_TRANSFER_STATUS_ERROR /* DMA Transfer error */
} dmacHw_TRANSFER_STATUS_e;
typedef enum {
dmacHw_INTERRUPT_DISABLE, /* Interrupt disable */
dmacHw_INTERRUPT_ENABLE /* Interrupt enable */
} dmacHw_INTERRUPT_e;
typedef enum {
dmacHw_INTERRUPT_STATUS_NONE = 0x0, /* No DMA interrupt */
dmacHw_INTERRUPT_STATUS_TRANS = 0x1, /* End of DMA transfer interrupt */
dmacHw_INTERRUPT_STATUS_BLOCK = 0x2, /* End of block transfer interrupt */
dmacHw_INTERRUPT_STATUS_ERROR = 0x4 /* Error interrupt */
} dmacHw_INTERRUPT_STATUS_e;
typedef enum {
dmacHw_CONTROLLER_ATTRIB_CHANNEL_NUM, /* Number of DMA channel */
dmacHw_CONTROLLER_ATTRIB_CHANNEL_MAX_BLOCK_SIZE, /* Maximum channel burst size */
dmacHw_CONTROLLER_ATTRIB_MASTER_INTF_NUM, /* Number of DMA master interface */
dmacHw_CONTROLLER_ATTRIB_CHANNEL_BUS_WIDTH, /* Channel Data bus width */
dmacHw_CONTROLLER_ATTRIB_CHANNEL_FIFO_SIZE /* Channel FIFO size */
} dmacHw_CONTROLLER_ATTRIB_e;
typedef unsigned long dmacHw_HANDLE_t; /* DMA channel handle */
typedef uint32_t dmacHw_ID_t; /* DMA channel Id. Must be created using
"dmacHw_MAKE_CHANNEL_ID" macro
*/
/* DMA channel configuration parameters */
typedef struct {
uint32_t srcPeripheralPort; /* Source peripheral port */
uint32_t dstPeripheralPort; /* Destination peripheral port */
uint32_t srcStatusRegisterAddress; /* Source status register address */
uint32_t dstStatusRegisterAddress; /* Destination status register address of type */
uint32_t srcGatherWidth; /* Number of bytes gathered before successive gather opearation */
uint32_t srcGatherJump; /* Number of bytes jumpped before successive gather opearation */
uint32_t dstScatterWidth; /* Number of bytes sacattered before successive scatter opearation */
uint32_t dstScatterJump; /* Number of bytes jumpped before successive scatter opearation */
uint32_t maxDataPerBlock; /* Maximum number of bytes to be transferred per block/descrptor.
0 = Maximum possible.
*/
dmacHw_ADDRESS_UPDATE_MODE_e srcUpdate; /* Source address update mode */
dmacHw_ADDRESS_UPDATE_MODE_e dstUpdate; /* Destination address update mode */
dmacHw_TRANSFER_TYPE_e transferType; /* DMA transfer type */
dmacHw_TRANSFER_MODE_e transferMode; /* DMA transfer mode */
dmacHw_MASTER_INTERFACE_e srcMasterInterface; /* DMA source interface */
dmacHw_MASTER_INTERFACE_e dstMasterInterface; /* DMA destination interface */
dmacHw_TRANSACTION_WIDTH_e srcMaxTransactionWidth; /* Source transaction width */
dmacHw_TRANSACTION_WIDTH_e dstMaxTransactionWidth; /* Destination transaction width */
dmacHw_BURST_WIDTH_e srcMaxBurstWidth; /* Source burst width */
dmacHw_BURST_WIDTH_e dstMaxBurstWidth; /* Destination burst width */
dmacHw_INTERRUPT_e blockTransferInterrupt; /* Block trsnafer interrupt */
dmacHw_INTERRUPT_e completeTransferInterrupt; /* Complete DMA trsnafer interrupt */
dmacHw_INTERRUPT_e errorInterrupt; /* Error interrupt */
dmacHw_CHANNEL_PRIORITY_e channelPriority; /* Channel priority */
dmacHw_FLOW_CONTROL_e flowControler; /* Data flow controller */
} dmacHw_CONFIG_t;
/****************************************************************************/
/**
* @brief Initializes DMA
*
* This function initializes DMA CSP driver
*
* @note
* Must be called before using any DMA channel
*/
/****************************************************************************/
void dmacHw_initDma(void);
/****************************************************************************/
/**
* @brief Exit function for DMA
*
* This function isolates DMA from the system
*
*/
/****************************************************************************/
void dmacHw_exitDma(void);
/****************************************************************************/
/**
* @brief Gets a handle to a DMA channel
*
* This function returns a handle, representing a control block of a particular DMA channel
*
* @return -1 - On Failure
* handle - On Success, representing a channel control block
*
* @note
* None Channel ID must be created using "dmacHw_MAKE_CHANNEL_ID" macro
*/
/****************************************************************************/
dmacHw_HANDLE_t dmacHw_getChannelHandle(dmacHw_ID_t channelId /* [ IN ] DMA Channel Id */
);
/****************************************************************************/
/**
* @brief Initializes a DMA channel for use
*
* This function initializes and resets a DMA channel for use
*
* @return -1 - On Failure
* 0 - On Success
*
* @note
* None
*/
/****************************************************************************/
int dmacHw_initChannel(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
);
/****************************************************************************/
/**
* @brief Estimates number of descriptor needed to perform certain DMA transfer
*
*
* @return On failure : -1
* On success : Number of descriptor count
*
*
*/
/****************************************************************************/
int dmacHw_calculateDescriptorCount(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
void *pSrcAddr, /* [ IN ] Source (Peripheral/Memory) address */
void *pDstAddr, /* [ IN ] Destination (Peripheral/Memory) address */
size_t dataLen /* [ IN ] Data length in bytes */
);
/****************************************************************************/
/**
* @brief Initializes descriptor ring
*
* This function will initializes the descriptor ring of a DMA channel
*
*
* @return -1 - On failure
* 0 - On success
* @note
* - "len" parameter should be obtained from "dmacHw_descriptorLen"
* - Descriptor buffer MUST be 32 bit aligned and uncached as it
* is accessed by ARM and DMA
*/
/****************************************************************************/
int dmacHw_initDescriptor(void *pDescriptorVirt, /* [ IN ] Virtual address of uncahced buffer allocated to form descriptor ring */
uint32_t descriptorPhyAddr, /* [ IN ] Physical address of pDescriptorVirt (descriptor buffer) */
uint32_t len, /* [ IN ] Size of the pBuf */
uint32_t num /* [ IN ] Number of descriptor in the ring */
);
/****************************************************************************/
/**
* @brief Finds amount of memory required to form a descriptor ring
*
*
* @return Number of bytes required to form a descriptor ring
*
*
* @note
* None
*/
/****************************************************************************/
uint32_t dmacHw_descriptorLen(uint32_t descCnt /* [ IN ] Number of descriptor in the ring */
);
/****************************************************************************/
/**
* @brief Configure DMA channel
*
* @return 0 : On success
* -1 : On failure
*/
/****************************************************************************/
int dmacHw_configChannel(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
dmacHw_CONFIG_t *pConfig /* [ IN ] Configuration settings */
);
/****************************************************************************/
/**
* @brief Set descriptors for known data length
*
* When DMA has to work as a flow controller, this function prepares the
* descriptor chain to transfer data
*
* from:
* - Memory to memory
* - Peripheral to memory
* - Memory to Peripheral
* - Peripheral to Peripheral
*
* @return -1 - On failure
* 0 - On success
*
*/
/****************************************************************************/
int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
void *pDescriptor, /* [ IN ] Descriptor buffer */
void *pSrcAddr, /* [ IN ] Source (Peripheral/Memory) address */
void *pDstAddr, /* [ IN ] Destination (Peripheral/Memory) address */
size_t dataLen /* [ IN ] Length in bytes */
);
/****************************************************************************/
/**
* @brief Indicates whether DMA transfer is in progress or completed
*
* @return DMA transfer status
* dmacHw_TRANSFER_STATUS_BUSY: DMA Transfer ongoing
* dmacHw_TRANSFER_STATUS_DONE: DMA Transfer completed
* dmacHw_TRANSFER_STATUS_ERROR: DMA Transfer error
*
*/
/****************************************************************************/
dmacHw_TRANSFER_STATUS_e dmacHw_transferCompleted(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
);
/****************************************************************************/
/**
* @brief Set descriptor carrying control information
*
* This function will be used to send specific control information to the device
* using the DMA channel
*
*
* @return -1 - On failure
* 0 - On success
*
* @note
* None
*/
/****************************************************************************/
int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
void *pDescriptor, /* [ IN ] Descriptor buffer */
uint32_t ctlAddress, /* [ IN ] Address of the device control register */
uint32_t control /* [ IN ] Device control information */
);
/****************************************************************************/
/**
* @brief Read data DMA transferred to memory
*
* This function will read data that has been DMAed to memory while transferring from:
* - Memory to memory
* - Peripheral to memory
*
* @return 0 - No more data is available to read
* 1 - More data might be available to read
*
*/
/****************************************************************************/
int dmacHw_readTransferredData(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
void *pDescriptor, /* [ IN ] Descriptor buffer */
void **ppBbuf, /* [ OUT ] Data received */
size_t *pLlen /* [ OUT ] Length of the data received */
);
/****************************************************************************/
/**
* @brief Prepares descriptor ring, when source peripheral working as a flow controller
*
* This function will form the descriptor ring by allocating buffers, when source peripheral
* has to work as a flow controller to transfer data from:
* - Peripheral to memory.
*
* @return -1 - On failure
* 0 - On success
*
*
* @note
* None
*/
/****************************************************************************/
int dmacHw_setVariableDataDescriptor(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
void *pDescriptor, /* [ IN ] Descriptor buffer */
uint32_t srcAddr, /* [ IN ] Source peripheral address */
void *(*fpAlloc) (int len), /* [ IN ] Function pointer that provides destination memory */
int len, /* [ IN ] Number of bytes "fpAlloc" will allocate for destination */
int num /* [ IN ] Number of descriptor to set */
);
/****************************************************************************/
/**
* @brief Program channel register to initiate transfer
*
* @return void
*
*
* @note
* - Descriptor buffer MUST ALWAYS be flushed before calling this function
* - This function should also be called from ISR to program the channel with
* pending descriptors
*/
/****************************************************************************/
void dmacHw_initiateTransfer(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
void *pDescriptor /* [ IN ] Descriptor buffer */
);
/****************************************************************************/
/**
* @brief Resets descriptor control information
*
* @return void
*/
/****************************************************************************/
void dmacHw_resetDescriptorControl(void *pDescriptor /* [ IN ] Descriptor buffer */
);
/****************************************************************************/
/**
* @brief Program channel register to stop transfer
*
* Ensures the channel is not doing any transfer after calling this function
*
* @return void
*
*/
/****************************************************************************/
void dmacHw_stopTransfer(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
);
/****************************************************************************/
/**
* @brief Check the existence of pending descriptor
*
* This function confirmes if there is any pending descriptor in the chain
* to program the channel
*
* @return 1 : Channel need to be programmed with pending descriptor
* 0 : No more pending descriptor to programe the channel
*
* @note
* - This function should be called from ISR in case there are pending
* descriptor to program the channel.
*
* Example:
*
* dmac_isr ()
* {
* ...
* if (dmacHw_descriptorPending (handle))
* {
* dmacHw_initiateTransfer (handle);
* }
* }
*
*/
/****************************************************************************/
uint32_t dmacHw_descriptorPending(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
void *pDescriptor /* [ IN ] Descriptor buffer */
);
/****************************************************************************/
/**
* @brief Deallocates source or destination memory, allocated
*
* This function can be called to deallocate data memory that was DMAed successfully
*
* @return -1 - On failure
* 0 - On success
*
* @note
* This function will be called ONLY, when source OR destination address is pointing
* to dynamic memory
*/
/****************************************************************************/
int dmacHw_freeMem(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
void *pDescriptor, /* [ IN ] Descriptor buffer */
void (*fpFree) (void *) /* [ IN ] Function pointer to free data memory */
);
/****************************************************************************/
/**
* @brief Clears the interrupt
*
* This function clears the DMA channel specific interrupt
*
* @return N/A
*
* @note
* Must be called under the context of ISR
*/
/****************************************************************************/
void dmacHw_clearInterrupt(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
);
/****************************************************************************/
/**
* @brief Returns the cause of channel specific DMA interrupt
*
* This function returns the cause of interrupt
*
* @return Interrupt status, each bit representing a specific type of interrupt
* of type dmacHw_INTERRUPT_STATUS_e
* @note
* This function should be called under the context of ISR
*/
/****************************************************************************/
dmacHw_INTERRUPT_STATUS_e dmacHw_getInterruptStatus(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
);
/****************************************************************************/
/**
* @brief Indentifies a DMA channel causing interrupt
*
* This functions returns a channel causing interrupt of type dmacHw_INTERRUPT_STATUS_e
*
* @return NULL : No channel causing DMA interrupt
* ! NULL : Handle to a channel causing DMA interrupt
* @note
* dmacHw_clearInterrupt() must be called with a valid handle after calling this function
*/
/****************************************************************************/
dmacHw_HANDLE_t dmacHw_getInterruptSource(void);
/****************************************************************************/
/**
* @brief Sets channel specific user data
*
* This function associates user data to a specific DMA channel
*
*/
/****************************************************************************/
void dmacHw_setChannelUserData(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
void *userData /* [ IN ] User data */
);
/****************************************************************************/
/**
* @brief Gets channel specific user data
*
* This function returns user data specific to a DMA channel
*
* @return user data
*/
/****************************************************************************/
void *dmacHw_getChannelUserData(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
);
/****************************************************************************/
/**
* @brief Displays channel specific registers and other control parameters
*
*
* @return void
*
* @note
* None
*/
/****************************************************************************/
void dmacHw_printDebugInfo(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
void *pDescriptor, /* [ IN ] Descriptor buffer */
int (*fpPrint) (const char *, ...) /* [ IN ] Print callback function */
);
/****************************************************************************/
/**
* @brief Provides DMA controller attributes
*
*
* @return DMA controller attributes
*
* @note
* None
*/
/****************************************************************************/
uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
dmacHw_CONTROLLER_ATTRIB_e attr /* [ IN ] DMA Controller attribute of type dmacHw_CONTROLLER_ATTRIB_e */
);
#endif /* _DMACHW_H */

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/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
#ifndef CSP_ERRNO_H
#define CSP_ERRNO_H
/* ---- Include Files ---------------------------------------------------- */
#if defined(__KERNEL__)
#include <linux/errno.h>
#elif defined(CSP_SIMULATION)
#include <asm-generic/errno.h>
#else
#include <errno.h>
#endif
/* ---- Public Constants and Types --------------------------------------- */
/* ---- Public Variable Externs ------------------------------------------ */
/* ---- Public Function Prototypes --------------------------------------- */
#endif /* CSP_ERRNO_H */

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/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/****************************************************************************/
/**
* @file intcHw.h
*
* @brief generic interrupt controller API
*
* @note
* None
*/
/****************************************************************************/
#ifndef _INTCHW_H
#define _INTCHW_H
/* ---- Include Files ---------------------------------------------------- */
#include <mach/csp/intcHw_reg.h>
/* ---- Public Constants and Types --------------------------------------- */
/* ---- Public Variable Externs ------------------------------------------ */
/* ---- Public Function Prototypes --------------------------------------- */
static inline void intcHw_irq_disable(void *basep, uint32_t mask);
static inline void intcHw_irq_enable(void *basep, uint32_t mask);
#endif /* _INTCHW_H */

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arch/arm/mach-bcmring/include/csp/module.h
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@ -1,32 +0,0 @@
/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
#ifndef CSP_MODULE_H
#define CSP_MODULE_H
/* ---- Include Files ---------------------------------------------------- */
#ifdef __KERNEL__
#include <linux/module.h>
#else
#define EXPORT_SYMBOL(symbol)
#endif
/* ---- Public Constants and Types --------------------------------------- */
/* ---- Public Variable Externs ------------------------------------------ */
/* ---- Public Function Prototypes --------------------------------------- */
#endif /* CSP_MODULE_H */

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/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/****************************************************************************/
/**
* @file reg.h
*
* @brief Generic register definitions used in CSP
*/
/****************************************************************************/
#ifndef CSP_REG_H
#define CSP_REG_H
/* ---- Include Files ---------------------------------------------------- */
#include <csp/stdint.h>
/* ---- Public Constants and Types --------------------------------------- */
#define __REG32(x) (*((volatile uint32_t *)(x)))
#define __REG16(x) (*((volatile uint16_t *)(x)))
#define __REG8(x) (*((volatile uint8_t *) (x)))
/* Macros used to define a sequence of reserved registers. The start / end */
/* are byte offsets in the particular register definition, with the "end" */
/* being the offset of the next un-reserved register. E.g. if offsets */
/* 0x10 through to 0x1f are reserved, then this reserved area could be */
/* specified as follows. */
/* typedef struct */
/* { */
/* uint32_t reg1; offset 0x00 */
/* uint32_t reg2; offset 0x04 */
/* uint32_t reg3; offset 0x08 */
/* uint32_t reg4; offset 0x0c */
/* REG32_RSVD(0x10, 0x20); */
/* uint32_t reg5; offset 0x20 */
/* ... */
/* } EXAMPLE_REG_t; */
#define REG8_RSVD(start, end) uint8_t rsvd_##start[(end - start) / sizeof(uint8_t)]
#define REG16_RSVD(start, end) uint16_t rsvd_##start[(end - start) / sizeof(uint16_t)]
#define REG32_RSVD(start, end) uint32_t rsvd_##start[(end - start) / sizeof(uint32_t)]
/* ---- Public Variable Externs ------------------------------------------ */
/* ---- Public Function Prototypes --------------------------------------- */
/* Note: When protecting multiple statements, the REG_LOCAL_IRQ_SAVE and */
/* REG_LOCAL_IRQ_RESTORE must be enclosed in { } to allow the */
/* flags variable to be declared locally. */
/* e.g. */
/* statement1; */
/* { */
/* REG_LOCAL_IRQ_SAVE; */
/* <multiple statements here> */
/* REG_LOCAL_IRQ_RESTORE; */
/* } */
/* statement2; */
/* */
#if defined(__KERNEL__) && !defined(STANDALONE)
#include <mach/hardware.h>
#include <linux/interrupt.h>
#define REG_LOCAL_IRQ_SAVE HW_DECLARE_SPINLOCK(reg32) \
unsigned long flags; HW_IRQ_SAVE(reg32, flags)
#define REG_LOCAL_IRQ_RESTORE HW_IRQ_RESTORE(reg32, flags)
#else
#define REG_LOCAL_IRQ_SAVE
#define REG_LOCAL_IRQ_RESTORE
#endif
static inline void reg32_modify_and(volatile uint32_t *reg, uint32_t value)
{
REG_LOCAL_IRQ_SAVE;
*reg &= value;
REG_LOCAL_IRQ_RESTORE;
}
static inline void reg32_modify_or(volatile uint32_t *reg, uint32_t value)
{
REG_LOCAL_IRQ_SAVE;
*reg |= value;
REG_LOCAL_IRQ_RESTORE;
}
static inline void reg32_modify_mask(volatile uint32_t *reg, uint32_t mask,
uint32_t value)
{
REG_LOCAL_IRQ_SAVE;
*reg = (*reg & mask) | value;
REG_LOCAL_IRQ_RESTORE;
}
static inline void reg32_write(volatile uint32_t *reg, uint32_t value)
{
*reg = value;
}
#endif /* CSP_REG_H */

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/*****************************************************************************
* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/****************************************************************************/
/**
* @file secHw.h
*
* @brief Definitions for accessing low level security features
*
*/
/****************************************************************************/
#ifndef SECHW_H
#define SECHW_H
typedef void (*secHw_FUNC_t) (void);
typedef enum {
secHw_MODE_SECURE = 0x0, /* Switches processor into secure mode */
secHw_MODE_NONSECURE = 0x1 /* Switches processor into non-secure mode */
} secHw_MODE;
/****************************************************************************/
/**
* @brief Requesting to execute the function in secure mode
*
* This function requests the given function to run in secure mode
*
*/
/****************************************************************************/
void secHw_RunSecure(secHw_FUNC_t /* Function to run in secure mode */
);
/****************************************************************************/
/**
* @brief Sets the mode
*
* his function sets the processor mode (secure/non-secure)
*
*/
/****************************************************************************/
void secHw_SetMode(secHw_MODE /* Processor mode */
);
/****************************************************************************/
/**
* @brief Get the current mode
*
* This function retieves the processor mode (secure/non-secure)
*
*/
/****************************************************************************/
void secHw_GetMode(secHw_MODE *);
#endif /* SECHW_H */

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arch/arm/mach-bcmring/include/csp/stdint.h
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/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
#ifndef CSP_STDINT_H
#define CSP_STDINT_H
/* ---- Include Files ---------------------------------------------------- */
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <stdint.h>
#endif
/* ---- Public Constants and Types --------------------------------------- */
/* ---- Public Variable Externs ------------------------------------------ */
/* ---- Public Function Prototypes --------------------------------------- */
#endif /* CSP_STDINT_H */

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arch/arm/mach-bcmring/include/csp/string.h
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/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
#ifndef CSP_STRING_H
#define CSP_STRING_H
/* ---- Include Files ---------------------------------------------------- */
#ifdef __KERNEL__
#include <linux/string.h>
#else
#include <string.h>
#endif
/* ---- Public Constants and Types --------------------------------------- */
/* ---- Public Variable Externs ------------------------------------------ */
/* ---- Public Function Prototypes --------------------------------------- */
#endif /* CSP_STRING_H */

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/*****************************************************************************
* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/****************************************************************************/
/**
* @file tmrHw.h
*
* @brief API definitions for low level Timer driver
*
*/
/****************************************************************************/
#ifndef _TMRHW_H
#define _TMRHW_H
#include <csp/stdint.h>
typedef uint32_t tmrHw_ID_t; /* Timer ID */
typedef uint32_t tmrHw_COUNT_t; /* Timer count */
typedef uint32_t tmrHw_INTERVAL_t; /* Timer interval */
typedef uint32_t tmrHw_RATE_t; /* Timer event (count/interrupt) rate */
typedef enum {
tmrHw_INTERRUPT_STATUS_SET, /* Interrupted */
tmrHw_INTERRUPT_STATUS_UNSET /* No Interrupt */
} tmrHw_INTERRUPT_STATUS_e;
typedef enum {
tmrHw_CAPABILITY_CLOCK, /* Clock speed in HHz */
tmrHw_CAPABILITY_RESOLUTION /* Timer resolution in bits */
} tmrHw_CAPABILITY_e;
/****************************************************************************/
/**
* @brief Get timer capability
*
* This function returns various capabilities/attributes of a timer
*
* @return Numeric capability
*
*/
/****************************************************************************/
uint32_t tmrHw_getTimerCapability(tmrHw_ID_t timerId, /* [ IN ] Timer Id */
tmrHw_CAPABILITY_e capability /* [ IN ] Timer capability */
);
/****************************************************************************/
/**
* @brief Configures a periodic timer in terms of timer interrupt rate
*
* This function initializes a periodic timer to generate specific number of
* timer interrupt per second
*
* @return On success: Effective timer frequency
* On failure: 0
*
*/
/****************************************************************************/
tmrHw_RATE_t tmrHw_setPeriodicTimerRate(tmrHw_ID_t timerId, /* [ IN ] Timer Id */
tmrHw_RATE_t rate /* [ IN ] Number of timer interrupt per second */
);
/****************************************************************************/
/**
* @brief Configures a periodic timer to generate timer interrupt after
* certain time interval
*
* This function initializes a periodic timer to generate timer interrupt
* after every time interval in millisecond
*
* @return On success: Effective interval set in mili-second
* On failure: 0
*
*/
/****************************************************************************/
tmrHw_INTERVAL_t tmrHw_setPeriodicTimerInterval(tmrHw_ID_t timerId, /* [ IN ] Timer Id */
tmrHw_INTERVAL_t msec /* [ IN ] Interval in mili-second */
);
/****************************************************************************/
/**
* @brief Configures a periodic timer to generate timer interrupt just once
* after certain time interval
*
* This function initializes a periodic timer to generate a single ticks after
* certain time interval in millisecond
*
* @return On success: Effective interval set in mili-second
* On failure: 0
*
*/
/****************************************************************************/
tmrHw_INTERVAL_t tmrHw_setOneshotTimerInterval(tmrHw_ID_t timerId, /* [ IN ] Timer Id */
tmrHw_INTERVAL_t msec /* [ IN ] Interval in mili-second */
);
/****************************************************************************/
/**
* @brief Configures a timer to run as a free running timer
*
* This function initializes a timer to run as a free running timer
*
* @return Timer resolution (count / sec)
*
*/
/****************************************************************************/
tmrHw_RATE_t tmrHw_setFreeRunningTimer(tmrHw_ID_t timerId, /* [ IN ] Timer Id */
uint32_t divider /* [ IN ] Dividing the clock frequency */
) __attribute__ ((section(".aramtext")));
/****************************************************************************/
/**
* @brief Starts a timer
*
* This function starts a preconfigured timer
*
* @return -1 - On Failure
* 0 - On Success
*/
/****************************************************************************/
int tmrHw_startTimer(tmrHw_ID_t timerId /* [ IN ] Timer id */
) __attribute__ ((section(".aramtext")));
/****************************************************************************/
/**
* @brief Stops a timer
*
* This function stops a running timer
*
* @return -1 - On Failure
* 0 - On Success
*/
/****************************************************************************/
int tmrHw_stopTimer(tmrHw_ID_t timerId /* [ IN ] Timer id */
);
/****************************************************************************/
/**
* @brief Gets current timer count
*
* This function returns the current timer value
*
* @return Current downcounting timer value
*
*/
/****************************************************************************/
tmrHw_COUNT_t tmrHw_GetCurrentCount(tmrHw_ID_t timerId /* [ IN ] Timer id */
) __attribute__ ((section(".aramtext")));
/****************************************************************************/
/**
* @brief Gets timer count rate
*
* This function returns the number of counts per second
*
* @return Count rate
*
*/
/****************************************************************************/
tmrHw_RATE_t tmrHw_getCountRate(tmrHw_ID_t timerId /* [ IN ] Timer id */
) __attribute__ ((section(".aramtext")));
/****************************************************************************/
/**
* @brief Enables timer interrupt
*
* This function enables the timer interrupt
*
* @return N/A
*
*/
/****************************************************************************/
void tmrHw_enableInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */
);
/****************************************************************************/
/**
* @brief Disables timer interrupt
*
* This function disable the timer interrupt
*
* @return N/A
*/
/****************************************************************************/
void tmrHw_disableInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */
);
/****************************************************************************/
/**
* @brief Clears the interrupt
*
* This function clears the timer interrupt
*
* @return N/A
*
* @note
* Must be called under the context of ISR
*/
/****************************************************************************/
void tmrHw_clearInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */
);
/****************************************************************************/
/**
* @brief Gets the interrupt status
*
* This function returns timer interrupt status
*
* @return Interrupt status
*/
/****************************************************************************/
tmrHw_INTERRUPT_STATUS_e tmrHw_getInterruptStatus(tmrHw_ID_t timerId /* [ IN ] Timer id */
);
/****************************************************************************/
/**
* @brief Indentifies a timer causing interrupt
*
* This functions returns a timer causing interrupt
*
* @return 0xFFFFFFFF : No timer causing an interrupt
* ! 0xFFFFFFFF : timer causing an interrupt
* @note
* tmrHw_clearIntrrupt() must be called with a valid timer id after calling this function
*/
/****************************************************************************/
tmrHw_ID_t tmrHw_getInterruptSource(void);
/****************************************************************************/
/**
* @brief Displays specific timer registers
*
*
* @return void
*
*/
/****************************************************************************/
void tmrHw_printDebugInfo(tmrHw_ID_t timerId, /* [ IN ] Timer id */
int (*fpPrint) (const char *, ...) /* [ IN ] Print callback function */
);
/****************************************************************************/
/**
* @brief Use a timer to perform a busy wait delay for a number of usecs.
*
* @return N/A
*/
/****************************************************************************/
void tmrHw_udelay(tmrHw_ID_t timerId, /* [ IN ] Timer id */
unsigned long usecs /* [ IN ] usec to delay */
) __attribute__ ((section(".aramtext")));
#endif /* _TMRHW_H */

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@ -1,63 +0,0 @@
/*****************************************************************************
* Copyright 2009 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
#ifndef CAP_H
#define CAP_H
/* ---- Include Files ---------------------------------------------------- */
/* ---- Public Constants and Types --------------------------------------- */
typedef enum {
CAP_NOT_PRESENT = 0,
CAP_PRESENT
} CAP_RC_T;
typedef enum {
CAP_VPM,
CAP_ETH_PHY,
CAP_ETH_GMII,
CAP_ETH_SGMII,
CAP_USB,
CAP_TSC,
CAP_EHSS,
CAP_SDIO,
CAP_UARTB,
CAP_KEYPAD,
CAP_CLCD,
CAP_GE,
CAP_LEDM,
CAP_BBL,
CAP_VDEC,
CAP_PIF,
CAP_APM,
CAP_SPU,
CAP_PKA,
CAP_RNG,
} CAP_CAPABILITY_T;
typedef enum {
CAP_LCD_WVGA = 0,
CAP_LCD_VGA = 0x1,
CAP_LCD_WQVGA = 0x2,
CAP_LCD_QVGA = 0x3
} CAP_LCD_RES_T;
/* ---- Public Variable Externs ------------------------------------------ */
/* ---- Public Function Prototypes --------------------------------------- */
static inline CAP_RC_T cap_isPresent(CAP_CAPABILITY_T capability, int index);
static inline uint32_t cap_getMaxArmSpeedHz(void);
static inline uint32_t cap_getMaxVpmSpeedHz(void);
static inline CAP_LCD_RES_T cap_getMaxLcdRes(void);
#endif

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/*****************************************************************************
* Copyright 2009 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
#ifndef CAP_INLINE_H
#define CAP_INLINE_H
/* ---- Include Files ---------------------------------------------------- */
#include <mach/csp/cap.h>
#include <cfg_global.h>
/* ---- Public Constants and Types --------------------------------------- */
#define CAP_CONFIG0_VPM_DIS 0x00000001
#define CAP_CONFIG0_ETH_PHY0_DIS 0x00000002
#define CAP_CONFIG0_ETH_PHY1_DIS 0x00000004
#define CAP_CONFIG0_ETH_GMII0_DIS 0x00000008
#define CAP_CONFIG0_ETH_GMII1_DIS 0x00000010
#define CAP_CONFIG0_ETH_SGMII0_DIS 0x00000020
#define CAP_CONFIG0_ETH_SGMII1_DIS 0x00000040
#define CAP_CONFIG0_USB0_DIS 0x00000080
#define CAP_CONFIG0_USB1_DIS 0x00000100
#define CAP_CONFIG0_TSC_DIS 0x00000200
#define CAP_CONFIG0_EHSS0_DIS 0x00000400
#define CAP_CONFIG0_EHSS1_DIS 0x00000800
#define CAP_CONFIG0_SDIO0_DIS 0x00001000
#define CAP_CONFIG0_SDIO1_DIS 0x00002000
#define CAP_CONFIG0_UARTB_DIS 0x00004000
#define CAP_CONFIG0_KEYPAD_DIS 0x00008000
#define CAP_CONFIG0_CLCD_DIS 0x00010000
#define CAP_CONFIG0_GE_DIS 0x00020000
#define CAP_CONFIG0_LEDM_DIS 0x00040000
#define CAP_CONFIG0_BBL_DIS 0x00080000
#define CAP_CONFIG0_VDEC_DIS 0x00100000
#define CAP_CONFIG0_PIF_DIS 0x00200000
#define CAP_CONFIG0_RESERVED1_DIS 0x00400000
#define CAP_CONFIG0_RESERVED2_DIS 0x00800000
#define CAP_CONFIG1_APMA_DIS 0x00000001
#define CAP_CONFIG1_APMB_DIS 0x00000002
#define CAP_CONFIG1_APMC_DIS 0x00000004
#define CAP_CONFIG1_CLCD_RES_MASK 0x00000600
#define CAP_CONFIG1_CLCD_RES_SHIFT 9
#define CAP_CONFIG1_CLCD_RES_WVGA (CAP_LCD_WVGA << CAP_CONFIG1_CLCD_RES_SHIFT)
#define CAP_CONFIG1_CLCD_RES_VGA (CAP_LCD_VGA << CAP_CONFIG1_CLCD_RES_SHIFT)
#define CAP_CONFIG1_CLCD_RES_WQVGA (CAP_LCD_WQVGA << CAP_CONFIG1_CLCD_RES_SHIFT)
#define CAP_CONFIG1_CLCD_RES_QVGA (CAP_LCD_QVGA << CAP_CONFIG1_CLCD_RES_SHIFT)
#define CAP_CONFIG2_SPU_DIS 0x00000010
#define CAP_CONFIG2_PKA_DIS 0x00000020
#define CAP_CONFIG2_RNG_DIS 0x00000080
#if (CFG_GLOBAL_CHIP == BCM11107)
#define capConfig0 0
#define capConfig1 CAP_CONFIG1_CLCD_RES_WVGA
#define capConfig2 0
#define CAP_APM_MAX_NUM_CHANS 3
#elif (CFG_GLOBAL_CHIP == FPGA11107)
#define capConfig0 0
#define capConfig1 CAP_CONFIG1_CLCD_RES_WVGA
#define capConfig2 0
#define CAP_APM_MAX_NUM_CHANS 3
#elif (CFG_GLOBAL_CHIP == BCM11109)
#define capConfig0 (CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS)
#define capConfig1 (CAP_CONFIG1_APMC_DIS | CAP_CONFIG1_CLCD_RES_WQVGA)
#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
#define CAP_APM_MAX_NUM_CHANS 2
#elif (CFG_GLOBAL_CHIP == BCM11170)
#define capConfig0 (CAP_CONFIG0_ETH_GMII0_DIS | CAP_CONFIG0_ETH_GMII1_DIS | CAP_CONFIG0_USB0_DIS | CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_TSC_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO0_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_UARTB_DIS | CAP_CONFIG0_CLCD_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS)
#define capConfig1 (CAP_CONFIG1_APMC_DIS | CAP_CONFIG1_CLCD_RES_WQVGA)
#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
#define CAP_APM_MAX_NUM_CHANS 2
#elif (CFG_GLOBAL_CHIP == BCM11110)
#define capConfig0 (CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_TSC_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO0_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_UARTB_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS)
#define capConfig1 CAP_CONFIG1_APMC_DIS
#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
#define CAP_APM_MAX_NUM_CHANS 2
#elif (CFG_GLOBAL_CHIP == BCM11211)
#define capConfig0 (CAP_CONFIG0_ETH_PHY0_DIS | CAP_CONFIG0_ETH_GMII0_DIS | CAP_CONFIG0_ETH_GMII1_DIS | CAP_CONFIG0_ETH_SGMII0_DIS | CAP_CONFIG0_ETH_SGMII1_DIS | CAP_CONFIG0_CLCD_DIS)
#define capConfig1 CAP_CONFIG1_APMC_DIS
#define capConfig2 0
#define CAP_APM_MAX_NUM_CHANS 2
#else
#error CFG_GLOBAL_CHIP type capabilities not defined
#endif
#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == FPGA11107))
#define CAP_HW_CFG_ARM_CLK_HZ 500000000
#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
#define CAP_HW_CFG_ARM_CLK_HZ 300000000
#elif (CFG_GLOBAL_CHIP == BCM11211)
#define CAP_HW_CFG_ARM_CLK_HZ 666666666
#else
#error CFG_GLOBAL_CHIP type capabilities not defined
#endif
#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == BCM11211) || (CFG_GLOBAL_CHIP == FPGA11107))
#define CAP_HW_CFG_VPM_CLK_HZ 333333333
#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
#define CAP_HW_CFG_VPM_CLK_HZ 200000000
#else
#error CFG_GLOBAL_CHIP type capabilities not defined
#endif
/* ---- Public Variable Externs ------------------------------------------ */
/* ---- Public Function Prototypes --------------------------------------- */
/****************************************************************************
* cap_isPresent -
*
* PURPOSE:
* Determines if the chip has a certain capability present
*
* PARAMETERS:
* capability - type of capability to determine if present
*
* RETURNS:
* CAP_PRESENT or CAP_NOT_PRESENT
****************************************************************************/
static inline CAP_RC_T cap_isPresent(CAP_CAPABILITY_T capability, int index)
{
CAP_RC_T returnVal = CAP_NOT_PRESENT;
switch (capability) {
case CAP_VPM:
{
if (!(capConfig0 & CAP_CONFIG0_VPM_DIS)) {
returnVal = CAP_PRESENT;
}
}
break;
case CAP_ETH_PHY:
{
if ((index == 0)
&& (!(capConfig0 & CAP_CONFIG0_ETH_PHY0_DIS))) {
returnVal = CAP_PRESENT;
}
if ((index == 1)
&& (!(capConfig0 & CAP_CONFIG0_ETH_PHY1_DIS))) {
returnVal = CAP_PRESENT;
}
}
break;
case CAP_ETH_GMII:
{
if ((index == 0)
&& (!(capConfig0 & CAP_CONFIG0_ETH_GMII0_DIS))) {
returnVal = CAP_PRESENT;
}
if ((index == 1)
&& (!(capConfig0 & CAP_CONFIG0_ETH_GMII1_DIS))) {
returnVal = CAP_PRESENT;
}
}
break;
case CAP_ETH_SGMII:
{
if ((index == 0)
&& (!(capConfig0 & CAP_CONFIG0_ETH_SGMII0_DIS))) {
returnVal = CAP_PRESENT;
}
if ((index == 1)
&& (!(capConfig0 & CAP_CONFIG0_ETH_SGMII1_DIS))) {
returnVal = CAP_PRESENT;
}
}
break;
case CAP_USB:
{
if ((index == 0)
&& (!(capConfig0 & CAP_CONFIG0_USB0_DIS))) {
returnVal = CAP_PRESENT;
}
if ((index == 1)
&& (!(capConfig0 & CAP_CONFIG0_USB1_DIS))) {
returnVal = CAP_PRESENT;
}
}
break;
case CAP_TSC:
{
if (!(capConfig0 & CAP_CONFIG0_TSC_DIS)) {
returnVal = CAP_PRESENT;
}
}
break;
case CAP_EHSS:
{
if ((index == 0)
&& (!(capConfig0 & CAP_CONFIG0_EHSS0_DIS))) {
returnVal = CAP_PRESENT;
}
if ((index == 1)
&& (!(capConfig0 & CAP_CONFIG0_EHSS1_DIS))) {
returnVal = CAP_PRESENT;
}
}
break;
case CAP_SDIO:
{
if ((index == 0)
&& (!(capConfig0 & CAP_CONFIG0_SDIO0_DIS))) {
returnVal = CAP_PRESENT;
}
if ((index == 1)
&& (!(capConfig0 & CAP_CONFIG0_SDIO1_DIS))) {
returnVal = CAP_PRESENT;
}
}
break;
case CAP_UARTB:
{
if (!(capConfig0 & CAP_CONFIG0_UARTB_DIS)) {
returnVal = CAP_PRESENT;
}
}
break;
case CAP_KEYPAD:
{
if (!(capConfig0 & CAP_CONFIG0_KEYPAD_DIS)) {
returnVal = CAP_PRESENT;
}
}
break;
case CAP_CLCD:
{
if (!(capConfig0 & CAP_CONFIG0_CLCD_DIS)) {
returnVal = CAP_PRESENT;
}
}
break;
case CAP_GE:
{
if (!(capConfig0 & CAP_CONFIG0_GE_DIS)) {
returnVal = CAP_PRESENT;
}
}
break;
case CAP_LEDM:
{
if (!(capConfig0 & CAP_CONFIG0_LEDM_DIS)) {
returnVal = CAP_PRESENT;
}
}
break;
case CAP_BBL:
{
if (!(capConfig0 & CAP_CONFIG0_BBL_DIS)) {
returnVal = CAP_PRESENT;
}
}
break;
case CAP_VDEC:
{
if (!(capConfig0 & CAP_CONFIG0_VDEC_DIS)) {
returnVal = CAP_PRESENT;
}
}
break;
case CAP_PIF:
{
if (!(capConfig0 & CAP_CONFIG0_PIF_DIS)) {
returnVal = CAP_PRESENT;
}
}
break;
case CAP_APM:
{
if ((index == 0)
&& (!(capConfig1 & CAP_CONFIG1_APMA_DIS))) {
returnVal = CAP_PRESENT;
}
if ((index == 1)
&& (!(capConfig1 & CAP_CONFIG1_APMB_DIS))) {
returnVal = CAP_PRESENT;
}
if ((index == 2)
&& (!(capConfig1 & CAP_CONFIG1_APMC_DIS))) {
returnVal = CAP_PRESENT;
}
}
break;
case CAP_SPU:
{
if (!(capConfig2 & CAP_CONFIG2_SPU_DIS)) {
returnVal = CAP_PRESENT;
}
}
break;
case CAP_PKA:
{
if (!(capConfig2 & CAP_CONFIG2_PKA_DIS)) {
returnVal = CAP_PRESENT;
}
}
break;
case CAP_RNG:
{
if (!(capConfig2 & CAP_CONFIG2_RNG_DIS)) {
returnVal = CAP_PRESENT;
}
}
break;
default:
{
}
break;
}
return returnVal;
}
/****************************************************************************
* cap_getMaxArmSpeedHz -
*
* PURPOSE:
* Determines the maximum speed of the ARM CPU
*
* PARAMETERS:
* none
*
* RETURNS:
* clock speed in Hz that the ARM processor is able to run at
****************************************************************************/
static inline uint32_t cap_getMaxArmSpeedHz(void)
{
#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == FPGA11107))
return 500000000;
#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
return 300000000;
#elif (CFG_GLOBAL_CHIP == BCM11211)
return 666666666;
#else
#error CFG_GLOBAL_CHIP type capabilities not defined
#endif
}
/****************************************************************************
* cap_getMaxVpmSpeedHz -
*
* PURPOSE:
* Determines the maximum speed of the VPM
*
* PARAMETERS:
* none
*
* RETURNS:
* clock speed in Hz that the VPM is able to run at
****************************************************************************/
static inline uint32_t cap_getMaxVpmSpeedHz(void)
{
#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == BCM11211) || (CFG_GLOBAL_CHIP == FPGA11107))
return 333333333;
#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
return 200000000;
#else
#error CFG_GLOBAL_CHIP type capabilities not defined
#endif
}
/****************************************************************************
* cap_getMaxLcdRes -
*
* PURPOSE:
* Determines the maximum LCD resolution capabilities
*
* PARAMETERS:
* none
*
* RETURNS:
* CAP_LCD_WVGA, CAP_LCD_VGA, CAP_LCD_WQVGA or CAP_LCD_QVGA
*
****************************************************************************/
static inline CAP_LCD_RES_T cap_getMaxLcdRes(void)
{
return (CAP_LCD_RES_T)
((capConfig1 & CAP_CONFIG1_CLCD_RES_MASK) >>
CAP_CONFIG1_CLCD_RES_SHIFT);
}
#endif

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arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
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arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
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arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
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/*****************************************************************************
* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/****************************************************************************/
/**
* @file chipcHw_reg.h
*
* @brief Definitions for low level chip control registers
*
*/
/****************************************************************************/
#ifndef CHIPCHW_REG_H
#define CHIPCHW_REG_H
#include <mach/csp/mm_io.h>
#include <csp/reg.h>
#include <mach/csp/ddrcReg.h>
#define chipcHw_BASE_ADDRESS MM_IO_BASE_CHIPC
typedef struct {
uint32_t ChipId; /* Chip ID */
uint32_t DDRClock; /* PLL1 Channel 1 for DDR clock */
uint32_t ARMClock; /* PLL1 Channel 2 for ARM clock */
uint32_t ESWClock; /* PLL1 Channel 3 for ESW system clock */
uint32_t VPMClock; /* PLL1 Channel 4 for VPM clock */
uint32_t ESW125Clock; /* PLL1 Channel 5 for ESW 125MHz clock */
uint32_t UARTClock; /* PLL1 Channel 6 for UART clock */
uint32_t SDIO0Clock; /* PLL1 Channel 7 for SDIO 0 clock */
uint32_t SDIO1Clock; /* PLL1 Channel 8 for SDIO 1 clock */
uint32_t SPIClock; /* PLL1 Channel 9 for SPI master Clock */
uint32_t ETMClock; /* PLL1 Channel 10 for ARM ETM Clock */
uint32_t ACLKClock; /* ACLK Clock (Divider) */
uint32_t OTPClock; /* OTP Clock (Divider) */
uint32_t I2CClock; /* I2C Clock (CK_13m) (Divider) */
uint32_t I2S0Clock; /* I2S0 Clock (Divider) */
uint32_t RTBUSClock; /* RTBUS (DDR PHY Config.) Clock (Divider) */
uint32_t pad1;
uint32_t APM100Clock; /* APM 100MHz CLK Clock (Divider) */
uint32_t TSCClock; /* TSC Clock (Divider) */
uint32_t LEDClock; /* LED Clock (Divider) */
uint32_t USBClock; /* PLL2 Channel 1 for USB clock */
uint32_t LCDClock; /* PLL2 Channel 2 for LCD clock */
uint32_t APMClock; /* PLL2 Channel 3 for APM 200 MHz clock */
uint32_t BusIntfClock; /* Bus interface clock */
uint32_t PLLStatus; /* PLL status register (PLL1) */
uint32_t PLLConfig; /* PLL configuration register (PLL1) */
uint32_t PLLPreDivider; /* PLL pre-divider control register (PLL1) */
uint32_t PLLDivider; /* PLL divider control register (PLL1) */
uint32_t PLLControl1; /* PLL analog control register #1 (PLL1) */
uint32_t PLLControl2; /* PLL analog control register #2 (PLL1) */
uint32_t I2S1Clock; /* I2S1 Clock */
uint32_t AudioEnable; /* Enable/ disable audio channel */
uint32_t SoftReset1; /* Reset blocks */
uint32_t SoftReset2; /* Reset blocks */
uint32_t Spare1; /* Phase align interrupts */
uint32_t Sticky; /* Sticky bits */
uint32_t MiscCtrl; /* Misc. control */
uint32_t pad3[3];
uint32_t PLLStatus2; /* PLL status register (PLL2) */
uint32_t PLLConfig2; /* PLL configuration register (PLL2) */
uint32_t PLLPreDivider2; /* PLL pre-divider control register (PLL2) */
uint32_t PLLDivider2; /* PLL divider control register (PLL2) */
uint32_t PLLControl12; /* PLL analog control register #1 (PLL2) */
uint32_t PLLControl22; /* PLL analog control register #2 (PLL2) */
uint32_t DDRPhaseCtrl1; /* DDR Clock Phase Alignment control1 */
uint32_t VPMPhaseCtrl1; /* VPM Clock Phase Alignment control1 */
uint32_t PhaseAlignStatus; /* DDR/VPM Clock Phase Alignment Status */
uint32_t PhaseCtrlStatus; /* DDR/VPM Clock HW DDR/VPM ph_ctrl and load_ch Status */
uint32_t DDRPhaseCtrl2; /* DDR Clock Phase Alignment control2 */
uint32_t VPMPhaseCtrl2; /* VPM Clock Phase Alignment control2 */
uint32_t pad4[9];
uint32_t SoftOTP1; /* Software OTP control */
uint32_t SoftOTP2; /* Software OTP control */
uint32_t SoftStraps; /* Software strap */
uint32_t PinStraps; /* Pin Straps */
uint32_t DiffOscCtrl; /* Diff oscillator control */
uint32_t DiagsCtrl; /* Diagnostic control */
uint32_t DiagsOutputCtrl; /* Diagnostic output enable */
uint32_t DiagsReadBackCtrl; /* Diagnostic read back control */
uint32_t LcdPifMode; /* LCD/PIF Pin Sharing MUX Mode */
uint32_t GpioMux_0_7; /* Pin Sharing MUX0 Control */
uint32_t GpioMux_8_15; /* Pin Sharing MUX1 Control */
uint32_t GpioMux_16_23; /* Pin Sharing MUX2 Control */
uint32_t GpioMux_24_31; /* Pin Sharing MUX3 Control */
uint32_t GpioMux_32_39; /* Pin Sharing MUX4 Control */
uint32_t GpioMux_40_47; /* Pin Sharing MUX5 Control */
uint32_t GpioMux_48_55; /* Pin Sharing MUX6 Control */
uint32_t GpioMux_56_63; /* Pin Sharing MUX7 Control */
uint32_t GpioSR_0_7; /* Slew rate for GPIO 0 - 7 */
uint32_t GpioSR_8_15; /* Slew rate for GPIO 8 - 15 */
uint32_t GpioSR_16_23; /* Slew rate for GPIO 16 - 23 */
uint32_t GpioSR_24_31; /* Slew rate for GPIO 24 - 31 */
uint32_t GpioSR_32_39; /* Slew rate for GPIO 32 - 39 */
uint32_t GpioSR_40_47; /* Slew rate for GPIO 40 - 47 */
uint32_t GpioSR_48_55; /* Slew rate for GPIO 48 - 55 */
uint32_t GpioSR_56_63; /* Slew rate for GPIO 56 - 63 */
uint32_t MiscSR_0_7; /* Slew rate for MISC 0 - 7 */
uint32_t MiscSR_8_15; /* Slew rate for MISC 8 - 15 */
uint32_t GpioPull_0_15; /* Pull up registers for GPIO 0 - 15 */
uint32_t GpioPull_16_31; /* Pull up registers for GPIO 16 - 31 */
uint32_t GpioPull_32_47; /* Pull up registers for GPIO 32 - 47 */
uint32_t GpioPull_48_63; /* Pull up registers for GPIO 48 - 63 */
uint32_t MiscPull_0_15; /* Pull up registers for MISC 0 - 15 */
uint32_t GpioInput_0_31; /* Input type for GPIO 0 - 31 */
uint32_t GpioInput_32_63; /* Input type for GPIO 32 - 63 */
uint32_t MiscInput_0_15; /* Input type for MISC 0 - 16 */
} chipcHw_REG_t;
#define pChipcHw ((volatile chipcHw_REG_t *) chipcHw_BASE_ADDRESS)
#define pChipcPhysical ((volatile chipcHw_REG_t *) MM_ADDR_IO_CHIPC)
#define chipcHw_REG_CHIPID_BASE_MASK 0xFFFFF000
#define chipcHw_REG_CHIPID_BASE_SHIFT 12
#define chipcHw_REG_CHIPID_REV_MASK 0x00000FFF
#define chipcHw_REG_REV_A0 0xA00
#define chipcHw_REG_REV_B0 0x0B0
#define chipcHw_REG_PLL_STATUS_CONTROL_ENABLE 0x80000000 /* Allow controlling PLL registers */
#define chipcHw_REG_PLL_STATUS_LOCKED 0x00000001 /* PLL is settled */
#define chipcHw_REG_PLL_CONFIG_D_RESET 0x00000008 /* Digital reset */
#define chipcHw_REG_PLL_CONFIG_A_RESET 0x00000004 /* Analog reset */
#define chipcHw_REG_PLL_CONFIG_BYPASS_ENABLE 0x00000020 /* Bypass enable */
#define chipcHw_REG_PLL_CONFIG_OUTPUT_ENABLE 0x00000010 /* Output enable */
#define chipcHw_REG_PLL_CONFIG_POWER_DOWN 0x00000001 /* Power down */
#define chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ 1600000000 /* 1.6GHz VCO split frequency */
#define chipcHw_REG_PLL_CONFIG_VCO_800_1600 0x00000000 /* VCO range 800-1600 MHz */
#define chipcHw_REG_PLL_CONFIG_VCO_1601_3200 0x00000080 /* VCO range 1601-3200 MHz */
#define chipcHw_REG_PLL_CONFIG_TEST_ENABLE 0x00010000 /* PLL test output enable */
#define chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK 0x003E0000 /* Mask to set test values */
#define chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT 17
#define chipcHw_REG_PLL_CLOCK_PHASE_COMP 0x00800000 /* Phase comparator output */
#define chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK 0x00300000 /* Clock to bus ratio mask */
#define chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT 20 /* Number of bits to be shifted */
#define chipcHw_REG_PLL_CLOCK_POWER_DOWN 0x00080000 /* PLL channel power down */
#define chipcHw_REG_PLL_CLOCK_SOURCE_GPIO 0x00040000 /* Use GPIO as source */
#define chipcHw_REG_PLL_CLOCK_BYPASS_SELECT 0x00020000 /* Select bypass clock */
#define chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE 0x00010000 /* Clock gated ON */
#define chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE 0x00008000 /* Clock phase update enable */
#define chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT 8 /* Number of bits to be shifted */
#define chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK 0x00003F00 /* Phase control mask */
#define chipcHw_REG_PLL_CLOCK_MDIV_MASK 0x000000FF /* Clock post divider mask
00000000 = divide-by-256
00000001 = divide-by-1
00000010 = divide-by-2
00000011 = divide-by-3
00000100 = divide-by-4
00000101 = divide-by-5
00000110 = divide-by-6
.
.
11111011 = divide-by-251
11111100 = divide-by-252
11111101 = divide-by-253
11111110 = divide-by-254
*/
#define chipcHw_REG_DIV_CLOCK_SOURCE_OTHER 0x00040000 /* NON-PLL clock source select */
#define chipcHw_REG_DIV_CLOCK_BYPASS_SELECT 0x00020000 /* NON-PLL clock bypass enable */
#define chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE 0x00010000 /* NON-PLL clock output enable */
#define chipcHw_REG_DIV_CLOCK_DIV_MASK 0x000000FF /* NON-PLL clock post-divide mask */
#define chipcHw_REG_DIV_CLOCK_DIV_256 0x00000000 /* NON-PLL clock post-divide by 256 */
#define chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT 0
#define chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT 4
#define chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT 8
#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK 0x0001FF00
#define chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN 0x02000000
#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK 0x00700000 /* Divider mask */
#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER 0x00000000 /* Integer-N Mode */
#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_UNIT 0x00100000 /* MASH Sigma-Delta Modulator Unit Mode */
#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MFB_UNIT 0x00200000 /* MFB Sigma-Delta Modulator Unit Mode */
#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_1_8 0x00300000 /* MASH Sigma-Delta Modulator 1/8 Mode */
#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MFB_1_8 0x00400000 /* MFB Sigma-Delta Modulator 1/8 Mode */
#define chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vco) ((vco) / chipcHw_XTAL_FREQ_Hz)
#define chipcHw_REG_PLL_PREDIVIDER_P1 1
#define chipcHw_REG_PLL_PREDIVIDER_P2 1
#define chipcHw_REG_PLL_DIVIDER_M1DIV 0x03000000
#define chipcHw_REG_PLL_DIVIDER_FRAC 0x00FFFFFF /* Fractional divider */
#define chipcHw_REG_PLL_DIVIDER_NDIV_f_SS (0x00FFFFFF) /* To attain spread with max frequency */
#define chipcHw_REG_PLL_DIVIDER_NDIV_f 0 /* ndiv_frac = chipcHw_REG_PLL_DIVIDER_NDIV_f /
chipcHw_REG_PLL_DIVIDER_FRAC
= 0, when SS is disable
*/
#define chipcHw_REG_PLL_DIVIDER_MDIV(vco, Hz) ((chipcHw_divide((vco), (Hz)) > 255) ? 0 : chipcHw_divide((vco), (Hz)))
#define chipcHw_REG_ACLKClock_CLK_DIV_MASK 0x3
/* System booting strap options */
#define chipcHw_STRAPS_SOFT_OVERRIDE 0x00000001 /* Software Strap Override */
#define chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_8 0x00000000 /* 8 bit NAND FLASH Boot */
#define chipcHw_STRAPS_BOOT_DEVICE_NOR_FLASH_16 0x00000002 /* 16 bit NOR FLASH Boot */
#define chipcHw_STRAPS_BOOT_DEVICE_SERIAL_FLASH 0x00000004 /* Serial FLASH Boot */
#define chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_16 0x00000006 /* 16 bit NAND FLASH Boot */
#define chipcHw_STRAPS_BOOT_DEVICE_UART 0x00000008 /* UART Boot */
#define chipcHw_STRAPS_BOOT_DEVICE_MASK 0x0000000E /* Mask */
/* System boot option */
#define chipcHw_STRAPS_BOOT_OPTION_BROM 0x00000000 /* Boot from Boot ROM */
#define chipcHw_STRAPS_BOOT_OPTION_ARAM 0x00000020 /* Boot from ARAM */
#define chipcHw_STRAPS_BOOT_OPTION_NOR 0x00000030 /* Boot from NOR flash */
/* NAND Flash page size strap options */
#define chipcHw_STRAPS_NAND_PAGESIZE_512 0x00000000 /* NAND FLASH page size of 512 bytes */
#define chipcHw_STRAPS_NAND_PAGESIZE_2048 0x00000040 /* NAND FLASH page size of 2048 bytes */
#define chipcHw_STRAPS_NAND_PAGESIZE_4096 0x00000080 /* NAND FLASH page size of 4096 bytes */
#define chipcHw_STRAPS_NAND_PAGESIZE_EXT 0x000000C0 /* NAND FLASH page of extened size */
#define chipcHw_STRAPS_NAND_PAGESIZE_MASK 0x000000C0 /* Mask */
#define chipcHw_STRAPS_NAND_EXTRA_CYCLE 0x00000400 /* NAND FLASH address cycle configuration */
#define chipcHw_STRAPS_REBOOT_TO_UART 0x00000800 /* Reboot to UART on error */
/* Secure boot mode strap options */
#define chipcHw_STRAPS_BOOT_MODE_NORMAL 0x00000000 /* Normal Boot */
#define chipcHw_STRAPS_BOOT_MODE_DBG_SW 0x00000100 /* Software debugging Boot */
#define chipcHw_STRAPS_BOOT_MODE_DBG_BOOT 0x00000200 /* Boot rom debugging Boot */
#define chipcHw_STRAPS_BOOT_MODE_NORMAL_QUIET 0x00000300 /* Normal Boot (Quiet BootRom) */
#define chipcHw_STRAPS_BOOT_MODE_MASK 0x00000300 /* Mask */
/* Slave Mode straps */
#define chipcHw_STRAPS_I2CS 0x02000000 /* I2C Slave */
#define chipcHw_STRAPS_SPIS 0x01000000 /* SPI Slave */
/* Strap pin options */
#define chipcHw_REG_SW_STRAPS ((pChipcHw->PinStraps & 0x0000FC00) >> 10)
/* PIF/LCD pin sharing defines */
#define chipcHw_REG_LCD_PIN_ENABLE 0x00000001 /* LCD Controller is used and the pins have LCD functions */
#define chipcHw_REG_PIF_PIN_ENABLE 0x00000002 /* LCD pins are used to perform PIF functions */
#define chipcHw_GPIO_COUNT 61 /* Number of GPIO pin accessible thorugh CHIPC */
/* NOTE: Any changes to these constants will require a corresponding change to chipcHw_str.c */
#define chipcHw_REG_GPIO_MUX_KEYPAD 0x00000001 /* GPIO mux for Keypad */
#define chipcHw_REG_GPIO_MUX_I2CH 0x00000002 /* GPIO mux for I2CH */
#define chipcHw_REG_GPIO_MUX_SPI 0x00000003 /* GPIO mux for SPI */
#define chipcHw_REG_GPIO_MUX_UART 0x00000004 /* GPIO mux for UART */
#define chipcHw_REG_GPIO_MUX_LEDMTXP 0x00000005 /* GPIO mux for LEDMTXP */
#define chipcHw_REG_GPIO_MUX_LEDMTXS 0x00000006 /* GPIO mux for LEDMTXS */
#define chipcHw_REG_GPIO_MUX_SDIO0 0x00000007 /* GPIO mux for SDIO0 */
#define chipcHw_REG_GPIO_MUX_SDIO1 0x00000008 /* GPIO mux for SDIO1 */
#define chipcHw_REG_GPIO_MUX_PCM 0x00000009 /* GPIO mux for PCM */
#define chipcHw_REG_GPIO_MUX_I2S 0x0000000A /* GPIO mux for I2S */
#define chipcHw_REG_GPIO_MUX_ETM 0x0000000B /* GPIO mux for ETM */
#define chipcHw_REG_GPIO_MUX_DEBUG 0x0000000C /* GPIO mux for DEBUG */
#define chipcHw_REG_GPIO_MUX_MISC 0x0000000D /* GPIO mux for MISC */
#define chipcHw_REG_GPIO_MUX_GPIO 0x00000000 /* GPIO mux for GPIO */
#define chipcHw_REG_GPIO_MUX(pin) (&pChipcHw->GpioMux_0_7 + ((pin) >> 3))
#define chipcHw_REG_GPIO_MUX_POSITION(pin) (((pin) & 0x00000007) << 2)
#define chipcHw_REG_GPIO_MUX_MASK 0x0000000F /* Mask */
#define chipcHw_REG_SLEW_RATE_HIGH 0x00000000 /* High speed slew rate */
#define chipcHw_REG_SLEW_RATE_NORMAL 0x00000008 /* Normal slew rate */
/* Pins beyond 42 are defined by skipping 8 bits within the register */
#define chipcHw_REG_SLEW_RATE(pin) (((pin) > 42) ? (&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcHw->GpioSR_0_7 + ((pin) >> 3)))
#define chipcHw_REG_SLEW_RATE_POSITION(pin) (((pin) > 42) ? ((((pin) + 2) & 0x00000007) << 2) : (((pin) & 0x00000007) << 2))
#define chipcHw_REG_SLEW_RATE_MASK 0x00000008 /* Mask */
#define chipcHw_REG_CURRENT_STRENGTH_2mA 0x00000001 /* Current driving strength 2 milli ampere */
#define chipcHw_REG_CURRENT_STRENGTH_4mA 0x00000002 /* Current driving strength 4 milli ampere */
#define chipcHw_REG_CURRENT_STRENGTH_6mA 0x00000004 /* Current driving strength 6 milli ampere */
#define chipcHw_REG_CURRENT_STRENGTH_8mA 0x00000005 /* Current driving strength 8 milli ampere */
#define chipcHw_REG_CURRENT_STRENGTH_10mA 0x00000006 /* Current driving strength 10 milli ampere */
#define chipcHw_REG_CURRENT_STRENGTH_12mA 0x00000007 /* Current driving strength 12 milli ampere */
#define chipcHw_REG_CURRENT_MASK 0x00000007 /* Mask */
/* Pins beyond 42 are defined by skipping 8 bits */
#define chipcHw_REG_CURRENT(pin) (((pin) > 42) ? (&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcHw->GpioSR_0_7 + ((pin) >> 3)))
#define chipcHw_REG_CURRENT_POSITION(pin) (((pin) > 42) ? ((((pin) + 2) & 0x00000007) << 2) : (((pin) & 0x00000007) << 2))
#define chipcHw_REG_PULL_NONE 0x00000000 /* No pull up register */
#define chipcHw_REG_PULL_UP 0x00000001 /* Pull up register enable */
#define chipcHw_REG_PULL_DOWN 0x00000002 /* Pull down register enable */
#define chipcHw_REG_PULLUP_MASK 0x00000003 /* Mask */
/* Pins beyond 42 are defined by skipping 4 bits */
#define chipcHw_REG_PULLUP(pin) (((pin) > 42) ? (&pChipcHw->GpioPull_0_15 + (((pin) + 2) >> 4)) : (&pChipcHw->GpioPull_0_15 + ((pin) >> 4)))
#define chipcHw_REG_PULLUP_POSITION(pin) (((pin) > 42) ? ((((pin) + 2) & 0x0000000F) << 1) : (((pin) & 0x0000000F) << 1))
#define chipcHw_REG_INPUTTYPE_CMOS 0x00000000 /* Normal CMOS logic */
#define chipcHw_REG_INPUTTYPE_ST 0x00000001 /* High speed Schmitt Trigger */
#define chipcHw_REG_INPUTTYPE_MASK 0x00000001 /* Mask */
/* Pins beyond 42 are defined by skipping 2 bits */
#define chipcHw_REG_INPUTTYPE(pin) (((pin) > 42) ? (&pChipcHw->GpioInput_0_31 + (((pin) + 2) >> 5)) : (&pChipcHw->GpioInput_0_31 + ((pin) >> 5)))
#define chipcHw_REG_INPUTTYPE_POSITION(pin) (((pin) > 42) ? ((((pin) + 2) & 0x0000001F)) : (((pin) & 0x0000001F)))
/* Device connected to the bus clock */
#define chipcHw_REG_BUS_CLOCK_ARM 0x00000001 /* Bus interface clock for ARM */
#define chipcHw_REG_BUS_CLOCK_VDEC 0x00000002 /* Bus interface clock for VDEC */
#define chipcHw_REG_BUS_CLOCK_ARAM 0x00000004 /* Bus interface clock for ARAM */
#define chipcHw_REG_BUS_CLOCK_HPM 0x00000008 /* Bus interface clock for HPM */
#define chipcHw_REG_BUS_CLOCK_DDRC 0x00000010 /* Bus interface clock for DDRC */
#define chipcHw_REG_BUS_CLOCK_DMAC0 0x00000020 /* Bus interface clock for DMAC0 */
#define chipcHw_REG_BUS_CLOCK_DMAC1 0x00000040 /* Bus interface clock for DMAC1 */
#define chipcHw_REG_BUS_CLOCK_NVI 0x00000080 /* Bus interface clock for NVI */
#define chipcHw_REG_BUS_CLOCK_ESW 0x00000100 /* Bus interface clock for ESW */
#define chipcHw_REG_BUS_CLOCK_GE 0x00000200 /* Bus interface clock for GE */
#define chipcHw_REG_BUS_CLOCK_I2CH 0x00000400 /* Bus interface clock for I2CH */
#define chipcHw_REG_BUS_CLOCK_I2S0 0x00000800 /* Bus interface clock for I2S0 */
#define chipcHw_REG_BUS_CLOCK_I2S1 0x00001000 /* Bus interface clock for I2S1 */
#define chipcHw_REG_BUS_CLOCK_VRAM 0x00002000 /* Bus interface clock for VRAM */
#define chipcHw_REG_BUS_CLOCK_CLCD 0x00004000 /* Bus interface clock for CLCD */
#define chipcHw_REG_BUS_CLOCK_LDK 0x00008000 /* Bus interface clock for LDK */
#define chipcHw_REG_BUS_CLOCK_LED 0x00010000 /* Bus interface clock for LED */
#define chipcHw_REG_BUS_CLOCK_OTP 0x00020000 /* Bus interface clock for OTP */
#define chipcHw_REG_BUS_CLOCK_PIF 0x00040000 /* Bus interface clock for PIF */
#define chipcHw_REG_BUS_CLOCK_SPU 0x00080000 /* Bus interface clock for SPU */
#define chipcHw_REG_BUS_CLOCK_SDIO0 0x00100000 /* Bus interface clock for SDIO0 */
#define chipcHw_REG_BUS_CLOCK_SDIO1 0x00200000 /* Bus interface clock for SDIO1 */
#define chipcHw_REG_BUS_CLOCK_SPIH 0x00400000 /* Bus interface clock for SPIH */
#define chipcHw_REG_BUS_CLOCK_SPIS 0x00800000 /* Bus interface clock for SPIS */
#define chipcHw_REG_BUS_CLOCK_UART0 0x01000000 /* Bus interface clock for UART0 */
#define chipcHw_REG_BUS_CLOCK_UART1 0x02000000 /* Bus interface clock for UART1 */
#define chipcHw_REG_BUS_CLOCK_BBL 0x04000000 /* Bus interface clock for BBL */
#define chipcHw_REG_BUS_CLOCK_I2CS 0x08000000 /* Bus interface clock for I2CS */
#define chipcHw_REG_BUS_CLOCK_USBH 0x10000000 /* Bus interface clock for USB Host */
#define chipcHw_REG_BUS_CLOCK_USBD 0x20000000 /* Bus interface clock for USB Device */
#define chipcHw_REG_BUS_CLOCK_BROM 0x40000000 /* Bus interface clock for Boot ROM */
#define chipcHw_REG_BUS_CLOCK_TSC 0x80000000 /* Bus interface clock for Touch screen */
/* Software resets defines */
#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL_HOLD 0x0000000080000000ULL /* Reset Global VPM and hold */
#define chipcHw_REG_SOFT_RESET_VPM_HOLD 0x0000000040000000ULL /* Reset VPM and hold */
#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL 0x0000000020000000ULL /* Reset Global VPM */
#define chipcHw_REG_SOFT_RESET_VPM 0x0000000010000000ULL /* Reset VPM */
#define chipcHw_REG_SOFT_RESET_KEYPAD 0x0000000008000000ULL /* Reset Key pad */
#define chipcHw_REG_SOFT_RESET_LED 0x0000000004000000ULL /* Reset LED */
#define chipcHw_REG_SOFT_RESET_SPU 0x0000000002000000ULL /* Reset SPU */
#define chipcHw_REG_SOFT_RESET_RNG 0x0000000001000000ULL /* Reset RNG */
#define chipcHw_REG_SOFT_RESET_PKA 0x0000000000800000ULL /* Reset PKA */
#define chipcHw_REG_SOFT_RESET_LCD 0x0000000000400000ULL /* Reset LCD */
#define chipcHw_REG_SOFT_RESET_PIF 0x0000000000200000ULL /* Reset PIF */
#define chipcHw_REG_SOFT_RESET_I2CS 0x0000000000100000ULL /* Reset I2C Slave */
#define chipcHw_REG_SOFT_RESET_I2CH 0x0000000000080000ULL /* Reset I2C Host */
#define chipcHw_REG_SOFT_RESET_SDIO1 0x0000000000040000ULL /* Reset SDIO 1 */
#define chipcHw_REG_SOFT_RESET_SDIO0 0x0000000000020000ULL /* Reset SDIO 0 */
#define chipcHw_REG_SOFT_RESET_BBL 0x0000000000010000ULL /* Reset BBL */
#define chipcHw_REG_SOFT_RESET_I2S1 0x0000000000008000ULL /* Reset I2S1 */
#define chipcHw_REG_SOFT_RESET_I2S0 0x0000000000004000ULL /* Reset I2S0 */
#define chipcHw_REG_SOFT_RESET_SPIS 0x0000000000002000ULL /* Reset SPI Slave */
#define chipcHw_REG_SOFT_RESET_SPIH 0x0000000000001000ULL /* Reset SPI Host */
#define chipcHw_REG_SOFT_RESET_GPIO1 0x0000000000000800ULL /* Reset GPIO block 1 */
#define chipcHw_REG_SOFT_RESET_GPIO0 0x0000000000000400ULL /* Reset GPIO block 0 */
#define chipcHw_REG_SOFT_RESET_UART1 0x0000000000000200ULL /* Reset UART 1 */
#define chipcHw_REG_SOFT_RESET_UART0 0x0000000000000100ULL /* Reset UART 0 */
#define chipcHw_REG_SOFT_RESET_NVI 0x0000000000000080ULL /* Reset NVI */
#define chipcHw_REG_SOFT_RESET_WDOG 0x0000000000000040ULL /* Reset Watch dog */
#define chipcHw_REG_SOFT_RESET_TMR 0x0000000000000020ULL /* Reset Timer */
#define chipcHw_REG_SOFT_RESET_ETM 0x0000000000000010ULL /* Reset ETM */
#define chipcHw_REG_SOFT_RESET_ARM_HOLD 0x0000000000000008ULL /* Reset ARM and HOLD */
#define chipcHw_REG_SOFT_RESET_ARM 0x0000000000000004ULL /* Reset ARM */
#define chipcHw_REG_SOFT_RESET_CHIP_WARM 0x0000000000000002ULL /* Chip warm reset */
#define chipcHw_REG_SOFT_RESET_CHIP_SOFT 0x0000000000000001ULL /* Chip soft reset */
#define chipcHw_REG_SOFT_RESET_VDEC 0x0000100000000000ULL /* Video decoder */
#define chipcHw_REG_SOFT_RESET_GE 0x0000080000000000ULL /* Graphics engine */
#define chipcHw_REG_SOFT_RESET_OTP 0x0000040000000000ULL /* Reset OTP */
#define chipcHw_REG_SOFT_RESET_USB2 0x0000020000000000ULL /* Reset USB2 */
#define chipcHw_REG_SOFT_RESET_USB1 0x0000010000000000ULL /* Reset USB 1 */
#define chipcHw_REG_SOFT_RESET_USB 0x0000008000000000ULL /* Reset USB 1 and USB2 soft reset */
#define chipcHw_REG_SOFT_RESET_ESW 0x0000004000000000ULL /* Reset Ethernet switch */
#define chipcHw_REG_SOFT_RESET_ESWCLK 0x0000002000000000ULL /* Reset Ethernet switch clock */
#define chipcHw_REG_SOFT_RESET_DDRPHY 0x0000001000000000ULL /* Reset DDR Physical */
#define chipcHw_REG_SOFT_RESET_DDR 0x0000000800000000ULL /* Reset DDR Controller */
#define chipcHw_REG_SOFT_RESET_TSC 0x0000000400000000ULL /* Reset Touch screen */
#define chipcHw_REG_SOFT_RESET_PCM 0x0000000200000000ULL /* Reset PCM device */
#define chipcHw_REG_SOFT_RESET_APM 0x0000200100000000ULL /* Reset APM device */
#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD 0x8000000000000000ULL /* Unhold Global VPM */
#define chipcHw_REG_SOFT_RESET_VPM_UNHOLD 0x4000000000000000ULL /* Unhold VPM */
#define chipcHw_REG_SOFT_RESET_ARM_UNHOLD 0x2000000000000000ULL /* Unhold ARM reset */
#define chipcHw_REG_SOFT_RESET_UNHOLD_MASK 0xF000000000000000ULL /* Mask to handle unhold request */
/* Audio channel control defines */
#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_ALL 0x00000001 /* Enable all audio channel */
#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_A 0x00000002 /* Enable channel A */
#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_B 0x00000004 /* Enable channel B */
#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_C 0x00000008 /* Enable channel C */
#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_NTP_CLOCK 0x00000010 /* Enable NTP clock */
#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_PCM0_CLOCK 0x00000020 /* Enable PCM0 clock */
#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_PCM1_CLOCK 0x00000040 /* Enable PCM1 clock */
#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_APM_CLOCK 0x00000080 /* Enable APM clock */
/* Misc. chip control defines */
#define chipcHw_REG_MISC_CTRL_GE_SEL 0x00040000 /* Select GE2/GE3 */
#define chipcHw_REG_MISC_CTRL_I2S1_CLOCK_ONCHIP 0x00000000 /* Use on chip clock for I2S1 */
#define chipcHw_REG_MISC_CTRL_I2S1_CLOCK_GPIO 0x00020000 /* Use external clock via GPIO pin 26 for I2S1 */
#define chipcHw_REG_MISC_CTRL_I2S0_CLOCK_ONCHIP 0x00000000 /* Use on chip clock for I2S0 */
#define chipcHw_REG_MISC_CTRL_I2S0_CLOCK_GPIO 0x00010000 /* Use external clock via GPIO pin 45 for I2S0 */
#define chipcHw_REG_MISC_CTRL_ARM_CP15_DISABLE 0x00008000 /* Disable ARM CP15 bit */
#define chipcHw_REG_MISC_CTRL_RTC_DISABLE 0x00000008 /* Disable RTC registers */
#define chipcHw_REG_MISC_CTRL_BBRAM_DISABLE 0x00000004 /* Disable Battery Backed RAM */
#define chipcHw_REG_MISC_CTRL_USB_MODE_HOST 0x00000002 /* Set USB as host */
#define chipcHw_REG_MISC_CTRL_USB_MODE_DEVICE 0xFFFFFFFD /* Set USB as device */
#define chipcHw_REG_MISC_CTRL_USB_POWERON 0xFFFFFFFE /* Power up USB */
#define chipcHw_REG_MISC_CTRL_USB_POWEROFF 0x00000001 /* Power down USB */
/* OTP configuration defines */
#define chipcHw_REG_OTP_SECURITY_OFF 0x0000020000000000ULL /* Security support is OFF */
#define chipcHw_REG_OTP_SPU_SLOW 0x0000010000000000ULL /* Limited SPU throughput */
#define chipcHw_REG_OTP_LCD_SPEED 0x0000000600000000ULL /* Set VPM speed one */
#define chipcHw_REG_OTP_VPM_SPEED_1 0x0000000100000000ULL /* Set VPM speed one */
#define chipcHw_REG_OTP_VPM_SPEED_0 0x0000000080000000ULL /* Set VPM speed zero */
#define chipcHw_REG_OTP_AXI_SPEED 0x0000000060000000ULL /* Set maximum AXI bus speed */
#define chipcHw_REG_OTP_APM_DISABLE 0x000000001F000000ULL /* Disable APM */
#define chipcHw_REG_OTP_PIF_DISABLE 0x0000000000200000ULL /* Disable PIF */
#define chipcHw_REG_OTP_VDEC_DISABLE 0x0000000000100000ULL /* Disable Video decoder */
#define chipcHw_REG_OTP_BBL_DISABLE 0x0000000000080000ULL /* Disable RTC and BBRAM */
#define chipcHw_REG_OTP_LED_DISABLE 0x0000000000040000ULL /* Disable LED */
#define chipcHw_REG_OTP_GE_DISABLE 0x0000000000020000ULL /* Disable Graphics Engine */
#define chipcHw_REG_OTP_LCD_DISABLE 0x0000000000010000ULL /* Disable LCD */
#define chipcHw_REG_OTP_KEYPAD_DISABLE 0x0000000000008000ULL /* Disable keypad */
#define chipcHw_REG_OTP_UART_DISABLE 0x0000000000004000ULL /* Disable UART */
#define chipcHw_REG_OTP_SDIOH_DISABLE 0x0000000000003000ULL /* Disable SDIO host */
#define chipcHw_REG_OTP_HSS_DISABLE 0x0000000000000C00ULL /* Disable HSS */
#define chipcHw_REG_OTP_TSC_DISABLE 0x0000000000000200ULL /* Disable touch screen */
#define chipcHw_REG_OTP_USB_DISABLE 0x0000000000000180ULL /* Disable USB */
#define chipcHw_REG_OTP_SGMII_DISABLE 0x0000000000000060ULL /* Disable SGMII */
#define chipcHw_REG_OTP_ETH_DISABLE 0x0000000000000018ULL /* Disable gigabit ethernet */
#define chipcHw_REG_OTP_ETH_PHY_DISABLE 0x0000000000000006ULL /* Disable ethernet PHY */
#define chipcHw_REG_OTP_VPM_DISABLE 0x0000000000000001ULL /* Disable VPM */
/* Sticky bit defines */
#define chipcHw_REG_STICKY_BOOT_DONE 0x00000001 /* Boot done */
#define chipcHw_REG_STICKY_SOFT_RESET 0x00000002 /* ARM soft reset */
#define chipcHw_REG_STICKY_GENERAL_1 0x00000004 /* General purpose bit 1 */
#define chipcHw_REG_STICKY_GENERAL_2 0x00000008 /* General purpose bit 2 */
#define chipcHw_REG_STICKY_GENERAL_3 0x00000010 /* General purpose bit 3 */
#define chipcHw_REG_STICKY_GENERAL_4 0x00000020 /* General purpose bit 4 */
#define chipcHw_REG_STICKY_GENERAL_5 0x00000040 /* General purpose bit 5 */
#define chipcHw_REG_STICKY_POR_BROM 0x00000080 /* Special sticky bit for security - set in BROM to avoid other modes being entered */
#define chipcHw_REG_STICKY_ARM_RESET 0x00000100 /* ARM reset */
#define chipcHw_REG_STICKY_CHIP_SOFT_RESET 0x00000200 /* Chip soft reset */
#define chipcHw_REG_STICKY_CHIP_WARM_RESET 0x00000400 /* Chip warm reset */
#define chipcHw_REG_STICKY_WDOG_RESET 0x00000800 /* Watchdog reset */
#define chipcHw_REG_STICKY_OTP_RESET 0x00001000 /* OTP reset */
/* HW phase alignment defines *//* Spare1 register definitions */
#define chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE 0x80000000 /* Enable DDR phase align panic interrupt */
#define chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE 0x40000000 /* Enable VPM phase align panic interrupt */
#define chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE 0x00000002 /* Enable access to VPM using system BUS */
#define chipcHw_REG_SPARE1_DDR_BUS_ACCESS_ENABLE 0x00000001 /* Enable access to DDR using system BUS */
/* DDRPhaseCtrl1 register definitions */
#define chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE 0x80000000 /* Enable DDR SW phase alignment */
#define chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE 0x40000000 /* Enable DDR HW phase alignment */
#define chipcHw_REG_DDR_PHASE_VALUE_GE_MASK 0x0000007F /* DDR lower threshold for phase alignment */
#define chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT 23
#define chipcHw_REG_DDR_PHASE_VALUE_LE_MASK 0x0000007F /* DDR upper threshold for phase alignment */
#define chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT 16
#define chipcHw_REG_DDR_PHASE_ALIGN_WAIT_CYCLE_MASK 0x0000FFFF /* BUS Cycle to wait to run next DDR phase alignment */
#define chipcHw_REG_DDR_PHASE_ALIGN_WAIT_CYCLE_SHIFT 0
/* VPMPhaseCtrl1 register definitions */
#define chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE 0x80000000 /* Enable VPM SW phase alignment */
#define chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE 0x40000000 /* Enable VPM HW phase alignment */
#define chipcHw_REG_VPM_PHASE_VALUE_GE_MASK 0x0000007F /* VPM lower threshold for phase alignment */
#define chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT 23
#define chipcHw_REG_VPM_PHASE_VALUE_LE_MASK 0x0000007F /* VPM upper threshold for phase alignment */
#define chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT 16
#define chipcHw_REG_VPM_PHASE_ALIGN_WAIT_CYCLE_MASK 0x0000FFFF /* BUS Cycle to wait to complete the VPM phase alignment */
#define chipcHw_REG_VPM_PHASE_ALIGN_WAIT_CYCLE_SHIFT 0
/* PhaseAlignStatus register definitions */
#define chipcHw_REG_DDR_TIMEOUT_INTR_STATUS 0x80000000 /* DDR time out interrupt status */
#define chipcHw_REG_DDR_PHASE_STATUS_MASK 0x0000007F /* DDR phase status value */
#define chipcHw_REG_DDR_PHASE_STATUS_SHIFT 24
#define chipcHw_REG_DDR_PHASE_ALIGNED 0x00800000 /* DDR Phase aligned status */
#define chipcHw_REG_DDR_LOAD 0x00400000 /* Load DDR phase status */
#define chipcHw_REG_DDR_PHASE_CTRL_MASK 0x0000003F /* DDR phase control value */
#define chipcHw_REG_DDR_PHASE_CTRL_SHIFT 16
#define chipcHw_REG_VPM_TIMEOUT_INTR_STATUS 0x80000000 /* VPM time out interrupt status */
#define chipcHw_REG_VPM_PHASE_STATUS_MASK 0x0000007F /* VPM phase status value */
#define chipcHw_REG_VPM_PHASE_STATUS_SHIFT 8
#define chipcHw_REG_VPM_PHASE_ALIGNED 0x00000080 /* VPM Phase aligned status */
#define chipcHw_REG_VPM_LOAD 0x00000040 /* Load VPM phase status */
#define chipcHw_REG_VPM_PHASE_CTRL_MASK 0x0000003F /* VPM phase control value */
#define chipcHw_REG_VPM_PHASE_CTRL_SHIFT 0
/* DDRPhaseCtrl2 register definitions */
#define chipcHw_REG_DDR_INTR_SERVICED 0x02000000 /* Acknowledge that interrupt was serviced */
#define chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE 0x01000000 /* Enable time out interrupt */
#define chipcHw_REG_DDR_LOAD_COUNT_PHASE_CTRL_MASK 0x0000000F /* Wait before toggling load_ch */
#define chipcHw_REG_DDR_LOAD_COUNT_PHASE_CTRL_SHIFT 20
#define chipcHw_REG_DDR_TOTAL_LOAD_COUNT_CTRL_MASK 0x0000000F /* Total wait to settle ph_ctrl and load_ch */
#define chipcHw_REG_DDR_TOTAL_LOAD_COUNT_CTRL_SHIFT 16
#define chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK 0x0000FFFF /* Time out value for DDR HW phase alignment */
#define chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT 0
/* VPMPhaseCtrl2 register definitions */
#define chipcHw_REG_VPM_INTR_SELECT_MASK 0x00000003 /* Interrupt select */
#define chipcHw_REG_VPM_INTR_SELECT_SHIFT 26
#define chipcHw_REG_VPM_INTR_DISABLE 0x00000000
#define chipcHw_REG_VPM_INTR_FAST (0x1 << chipcHw_REG_VPM_INTR_SELECT_SHIFT)
#define chipcHw_REG_VPM_INTR_MEDIUM (0x2 << chipcHw_REG_VPM_INTR_SELECT_SHIFT)
#define chipcHw_REG_VPM_INTR_SLOW (0x3 << chipcHw_REG_VPM_INTR_SELECT_SHIFT)
#define chipcHw_REG_VPM_INTR_SERVICED 0x02000000 /* Acknowledge that interrupt was serviced */
#define chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE 0x01000000 /* Enable time out interrupt */
#define chipcHw_REG_VPM_LOAD_COUNT_PHASE_CTRL_MASK 0x0000000F /* Wait before toggling load_ch */
#define chipcHw_REG_VPM_LOAD_COUNT_PHASE_CTRL_SHIFT 20
#define chipcHw_REG_VPM_TOTAL_LOAD_COUNT_CTRL_MASK 0x0000000F /* Total wait cycle to settle ph_ctrl and load_ch */
#define chipcHw_REG_VPM_TOTAL_LOAD_COUNT_CTRL_SHIFT 16
#define chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK 0x0000FFFF /* Time out value for VPM HW phase alignment */
#define chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT 0
#endif /* CHIPCHW_REG_H */

872
arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
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@ -1,872 +0,0 @@
/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/****************************************************************************/
/**
* @file ddrcReg.h
*
* @brief Register definitions for BCMRING DDR2 Controller and PHY
*
*/
/****************************************************************************/
#ifndef DDRC_REG_H
#define DDRC_REG_H
#ifdef __cplusplus
extern "C" {
#endif
/* ---- Include Files ---------------------------------------------------- */
#include <csp/reg.h>
#include <csp/stdint.h>
#include <mach/csp/mm_io.h>
/* ---- Public Constants and Types --------------------------------------- */
/*********************************************************************/
/* DDR2 Controller (ARM PL341) register definitions */
/*********************************************************************/
/* -------------------------------------------------------------------- */
/* -------------------------------------------------------------------- */
/* ARM PL341 DDR2 configuration registers, offset 0x000 */
/* -------------------------------------------------------------------- */
/* -------------------------------------------------------------------- */
typedef struct {
uint32_t memcStatus;
uint32_t memcCmd;
uint32_t directCmd;
uint32_t memoryCfg;
uint32_t refreshPrd;
uint32_t casLatency;
uint32_t writeLatency;
uint32_t tMrd;
uint32_t tRas;
uint32_t tRc;
uint32_t tRcd;
uint32_t tRfc;
uint32_t tRp;
uint32_t tRrd;
uint32_t tWr;
uint32_t tWtr;
uint32_t tXp;
uint32_t tXsr;
uint32_t tEsr;
uint32_t memoryCfg2;
uint32_t memoryCfg3;
uint32_t tFaw;
} ddrcReg_CTLR_MEMC_REG_t;
#define ddrcReg_CTLR_MEMC_REG_OFFSET 0x0000
#define ddrcReg_CTLR_MEMC_REGP ((volatile ddrcReg_CTLR_MEMC_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_MEMC_REG_OFFSET))
/* ----------------------------------------------------- */
#define ddrcReg_CTLR_MEMC_STATUS_BANKS_MASK (0x3 << 12)
#define ddrcReg_CTLR_MEMC_STATUS_BANKS_4 (0x0 << 12)
#define ddrcReg_CTLR_MEMC_STATUS_BANKS_8 (0x3 << 12)
#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_MASK (0x3 << 10)
#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_0 (0x0 << 10)
#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_1 (0x1 << 10)
#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_2 (0x2 << 10)
#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_4 (0x3 << 10)
#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_MASK (0x3 << 7)
#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_1 (0x0 << 7)
#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_2 (0x1 << 7)
#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_3 (0x2 << 7)
#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_4 (0x3 << 7)
#define ddrcReg_CTLR_MEMC_STATUS_TYPE_MASK (0x7 << 4)
#define ddrcReg_CTLR_MEMC_STATUS_TYPE_DDR2 (0x5 << 4)
#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_MASK (0x3 << 2)
#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_16 (0x0 << 2)
#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_32 (0x1 << 2)
#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_64 (0x2 << 2)
#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_128 (0x3 << 2)
#define ddrcReg_CTLR_MEMC_STATUS_STATE_MASK (0x3 << 0)
#define ddrcReg_CTLR_MEMC_STATUS_STATE_CONFIG (0x0 << 0)
#define ddrcReg_CTLR_MEMC_STATUS_STATE_READY (0x1 << 0)
#define ddrcReg_CTLR_MEMC_STATUS_STATE_PAUSED (0x2 << 0)
#define ddrcReg_CTLR_MEMC_STATUS_STATE_LOWPWR (0x3 << 0)
/* ----------------------------------------------------- */
#define ddrcReg_CTLR_MEMC_CMD_MASK (0x7 << 0)
#define ddrcReg_CTLR_MEMC_CMD_GO (0x0 << 0)
#define ddrcReg_CTLR_MEMC_CMD_SLEEP (0x1 << 0)
#define ddrcReg_CTLR_MEMC_CMD_WAKEUP (0x2 << 0)
#define ddrcReg_CTLR_MEMC_CMD_PAUSE (0x3 << 0)
#define ddrcReg_CTLR_MEMC_CMD_CONFIGURE (0x4 << 0)
#define ddrcReg_CTLR_MEMC_CMD_ACTIVE_PAUSE (0x7 << 0)
/* ----------------------------------------------------- */
#define ddrcReg_CTLR_DIRECT_CMD_CHIP_SHIFT 20
#define ddrcReg_CTLR_DIRECT_CMD_CHIP_MASK (0x3 << ddrcReg_CTLR_DIRECT_CMD_CHIP_SHIFT)
#define ddrcReg_CTLR_DIRECT_CMD_TYPE_PRECHARGEALL (0x0 << 18)
#define ddrcReg_CTLR_DIRECT_CMD_TYPE_AUTOREFRESH (0x1 << 18)
#define ddrcReg_CTLR_DIRECT_CMD_TYPE_MODEREG (0x2 << 18)
#define ddrcReg_CTLR_DIRECT_CMD_TYPE_NOP (0x3 << 18)
#define ddrcReg_CTLR_DIRECT_CMD_BANK_SHIFT 16
#define ddrcReg_CTLR_DIRECT_CMD_BANK_MASK (0x3 << ddrcReg_CTLR_DIRECT_CMD_BANK_SHIFT)
#define ddrcReg_CTLR_DIRECT_CMD_ADDR_SHIFT 0
#define ddrcReg_CTLR_DIRECT_CMD_ADDR_MASK (0x1ffff << ddrcReg_CTLR_DIRECT_CMD_ADDR_SHIFT)
/* ----------------------------------------------------- */
#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_MASK (0x3 << 21)
#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_1 (0x0 << 21)
#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_2 (0x1 << 21)
#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_3 (0x2 << 21)
#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_4 (0x3 << 21)
#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_MASK (0x7 << 18)
#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_3_0 (0x0 << 18)
#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_4_1 (0x1 << 18)
#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_5_2 (0x2 << 18)
#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_6_3 (0x3 << 18)
#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_7_4 (0x4 << 18)
#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_8_5 (0x5 << 18)
#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_9_6 (0x6 << 18)
#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_10_7 (0x7 << 18)
#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_MASK (0x7 << 15)
#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_4 (0x2 << 15)
#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_8 (0x3 << 15) /* @note Not supported in PL341 */
#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_ENABLE (0x1 << 13)
#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_SHIFT 7
#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_MASK (0x3f << ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_SHIFT)
#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_MASK (0x7 << 3)
#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_11 (0x0 << 3)
#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_12 (0x1 << 3)
#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_13 (0x2 << 3)
#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_14 (0x3 << 3)
#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_15 (0x4 << 3)
#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_16 (0x5 << 3)
#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_MASK (0x7 << 0)
#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_9 (0x1 << 0)
#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_10 (0x2 << 0)
#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_11 (0x3 << 0)
/* ----------------------------------------------------- */
#define ddrcReg_CTLR_REFRESH_PRD_SHIFT 0
#define ddrcReg_CTLR_REFRESH_PRD_MASK (0x7fff << ddrcReg_CTLR_REFRESH_PRD_SHIFT)
/* ----------------------------------------------------- */
#define ddrcReg_CTLR_CAS_LATENCY_SHIFT 1
#define ddrcReg_CTLR_CAS_LATENCY_MASK (0x7 << ddrcReg_CTLR_CAS_LATENCY_SHIFT)
/* ----------------------------------------------------- */
#define ddrcReg_CTLR_WRITE_LATENCY_SHIFT 0
#define ddrcReg_CTLR_WRITE_LATENCY_MASK (0x7 << ddrcReg_CTLR_WRITE_LATENCY_SHIFT)
/* ----------------------------------------------------- */
#define ddrcReg_CTLR_T_MRD_SHIFT 0
#define ddrcReg_CTLR_T_MRD_MASK (0x7f << ddrcReg_CTLR_T_MRD_SHIFT)
/* ----------------------------------------------------- */
#define ddrcReg_CTLR_T_RAS_SHIFT 0
#define ddrcReg_CTLR_T_RAS_MASK (0x1f << ddrcReg_CTLR_T_RAS_SHIFT)
/* ----------------------------------------------------- */
#define ddrcReg_CTLR_T_RC_SHIFT 0
#define ddrcReg_CTLR_T_RC_MASK (0x1f << ddrcReg_CTLR_T_RC_SHIFT)
/* ----------------------------------------------------- */
#define ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_SHIFT 8
#define ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_MASK (0x7 << ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_SHIFT)
#define ddrcReg_CTLR_T_RCD_SHIFT 0
#define ddrcReg_CTLR_T_RCD_MASK (0x7 << ddrcReg_CTLR_T_RCD_SHIFT)
/* ----------------------------------------------------- */
#define ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_SHIFT 8
#define ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_MASK (0x7f << ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_SHIFT)
#define ddrcReg_CTLR_T_RFC_SHIFT 0
#define ddrcReg_CTLR_T_RFC_MASK (0x7f << ddrcReg_CTLR_T_RFC_SHIFT)
/* ----------------------------------------------------- */
#define ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_SHIFT 8
#define ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_MASK (0x7 << ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_SHIFT)
#define ddrcReg_CTLR_T_RP_SHIFT 0
#define ddrcReg_CTLR_T_RP_MASK (0xf << ddrcReg_CTLR_T_RP_SHIFT)
/* ----------------------------------------------------- */
#define ddrcReg_CTLR_T_RRD_SHIFT 0
#define ddrcReg_CTLR_T_RRD_MASK (0xf << ddrcReg_CTLR_T_RRD_SHIFT)
/* ----------------------------------------------------- */
#define ddrcReg_CTLR_T_WR_SHIFT 0
#define ddrcReg_CTLR_T_WR_MASK (0x7 << ddrcReg_CTLR_T_WR_SHIFT)
/* ----------------------------------------------------- */
#define ddrcReg_CTLR_T_WTR_SHIFT 0
#define ddrcReg_CTLR_T_WTR_MASK (0x7 << ddrcReg_CTLR_T_WTR_SHIFT)
/* ----------------------------------------------------- */
#define ddrcReg_CTLR_T_XP_SHIFT 0
#define ddrcReg_CTLR_T_XP_MASK (0xff << ddrcReg_CTLR_T_XP_SHIFT)
/* ----------------------------------------------------- */
#define ddrcReg_CTLR_T_XSR_SHIFT 0
#define ddrcReg_CTLR_T_XSR_MASK (0xff << ddrcReg_CTLR_T_XSR_SHIFT)
/* ----------------------------------------------------- */
#define ddrcReg_CTLR_T_ESR_SHIFT 0
#define ddrcReg_CTLR_T_ESR_MASK (0xff << ddrcReg_CTLR_T_ESR_SHIFT)
/* ----------------------------------------------------- */
#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_MASK (0x3 << 6)
#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_16BITS (0 << 6)
#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_32BITS (1 << 6)
#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_64BITS (2 << 6)
#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_MASK (0x3 << 4)
#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_2 (0 << 4)
#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_3 (3 << 4)
#define ddrcReg_CTLR_MEMORY_CFG2_CKE_INIT_STATE_LOW (0 << 3)
#define ddrcReg_CTLR_MEMORY_CFG2_CKE_INIT_STATE_HIGH (1 << 3)
#define ddrcReg_CTLR_MEMORY_CFG2_DQM_INIT_STATE_LOW (0 << 2)
#define ddrcReg_CTLR_MEMORY_CFG2_DQM_INIT_STATE_HIGH (1 << 2)
#define ddrcReg_CTLR_MEMORY_CFG2_CLK_MASK (0x3 << 0)
#define ddrcReg_CTLR_MEMORY_CFG2_CLK_ASYNC (0 << 0)
#define ddrcReg_CTLR_MEMORY_CFG2_CLK_SYNC_A_LE_M (1 << 0)
#define ddrcReg_CTLR_MEMORY_CFG2_CLK_SYNC_A_GT_M (3 << 0)
/* ----------------------------------------------------- */
#define ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_SHIFT 0
#define ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_MASK (0x7 << ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_SHIFT)
/* ----------------------------------------------------- */
#define ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_SHIFT 8
#define ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_MASK (0x1f << ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_SHIFT)
#define ddrcReg_CTLR_T_FAW_PERIOD_SHIFT 0
#define ddrcReg_CTLR_T_FAW_PERIOD_MASK (0x1f << ddrcReg_CTLR_T_FAW_PERIOD_SHIFT)
/* -------------------------------------------------------------------- */
/* -------------------------------------------------------------------- */
/* ARM PL341 AXI ID QOS configuration registers, offset 0x100 */
/* -------------------------------------------------------------------- */
/* -------------------------------------------------------------------- */
#define ddrcReg_CTLR_QOS_CNT 16
#define ddrcReg_CTLR_QOS_MAX (ddrcReg_CTLR_QOS_CNT - 1)
typedef struct {
uint32_t cfg[ddrcReg_CTLR_QOS_CNT];
} ddrcReg_CTLR_QOS_REG_t;
#define ddrcReg_CTLR_QOS_REG_OFFSET 0x100
#define ddrcReg_CTLR_QOS_REGP ((volatile ddrcReg_CTLR_QOS_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_QOS_REG_OFFSET))
/* ----------------------------------------------------- */
#define ddrcReg_CTLR_QOS_CFG_MAX_SHIFT 2
#define ddrcReg_CTLR_QOS_CFG_MAX_MASK (0xff << ddrcReg_CTLR_QOS_CFG_MAX_SHIFT)
#define ddrcReg_CTLR_QOS_CFG_MIN_SHIFT 1
#define ddrcReg_CTLR_QOS_CFG_MIN_MASK (1 << ddrcReg_CTLR_QOS_CFG_MIN_SHIFT)
#define ddrcReg_CTLR_QOS_CFG_ENABLE (1 << 0)
/* -------------------------------------------------------------------- */
/* -------------------------------------------------------------------- */
/* ARM PL341 Memory chip configuration registers, offset 0x200 */
/* -------------------------------------------------------------------- */
/* -------------------------------------------------------------------- */
#define ddrcReg_CTLR_CHIP_CNT 4
#define ddrcReg_CTLR_CHIP_MAX (ddrcReg_CTLR_CHIP_CNT - 1)
typedef struct {
uint32_t cfg[ddrcReg_CTLR_CHIP_CNT];
} ddrcReg_CTLR_CHIP_REG_t;
#define ddrcReg_CTLR_CHIP_REG_OFFSET 0x200
#define ddrcReg_CTLR_CHIP_REGP ((volatile ddrcReg_CTLR_CHIP_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_CHIP_REG_OFFSET))
/* ----------------------------------------------------- */
#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_MASK (1 << 16)
#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_ROW_BANK_COL (0 << 16)
#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_BANK_ROW_COL (1 << 16)
#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_SHIFT 8
#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_MASK (0xff << ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_SHIFT)
#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_SHIFT 0
#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_MASK (0xff << ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_SHIFT)
/* -------------------------------------------------------------------- */
/* -------------------------------------------------------------------- */
/* ARM PL341 User configuration registers, offset 0x300 */
/* -------------------------------------------------------------------- */
/* -------------------------------------------------------------------- */
#define ddrcReg_CTLR_USER_OUTPUT_CNT 2
typedef struct {
uint32_t input;
uint32_t output[ddrcReg_CTLR_USER_OUTPUT_CNT];
uint32_t feature;
} ddrcReg_CTLR_USER_REG_t;
#define ddrcReg_CTLR_USER_REG_OFFSET 0x300
#define ddrcReg_CTLR_USER_REGP ((volatile ddrcReg_CTLR_USER_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_USER_REG_OFFSET))
/* ----------------------------------------------------- */
#define ddrcReg_CTLR_USER_INPUT_STATUS_SHIFT 0
#define ddrcReg_CTLR_USER_INPUT_STATUS_MASK (0xff << ddrcReg_CTLR_USER_INPUT_STATUS_SHIFT)
/* ----------------------------------------------------- */
#define ddrcReg_CTLR_USER_OUTPUT_CFG_SHIFT 0
#define ddrcReg_CTLR_USER_OUTPUT_CFG_MASK (0xff << ddrcReg_CTLR_USER_OUTPUT_CFG_SHIFT)
#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT 1
#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_MASK (1 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_BP134 (0 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_PL301 (1 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_REGISTERED ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_PL301
/* ----------------------------------------------------- */
#define ddrcReg_CTLR_FEATURE_WRITE_BLOCK_DISABLE (1 << 2)
#define ddrcReg_CTLR_FEATURE_EARLY_BURST_RSP_DISABLE (1 << 0)
/*********************************************************************/
/* Broadcom DDR23 PHY register definitions */
/*********************************************************************/
/* -------------------------------------------------------------------- */
/* -------------------------------------------------------------------- */
/* Broadcom DDR23 PHY Address and Control register definitions */
/* -------------------------------------------------------------------- */
/* -------------------------------------------------------------------- */
typedef struct {
uint32_t revision;
uint32_t pmCtl;
REG32_RSVD(0x0008, 0x0010);
uint32_t pllStatus;
uint32_t pllCfg;
uint32_t pllPreDiv;
uint32_t pllDiv;
uint32_t pllCtl1;
uint32_t pllCtl2;
uint32_t ssCtl;
uint32_t ssCfg;
uint32_t vdlStatic;
uint32_t vdlDynamic;
uint32_t padIdle;
uint32_t pvtComp;
uint32_t padDrive;
uint32_t clkRgltrCtl;
} ddrcReg_PHY_ADDR_CTL_REG_t;
#define ddrcReg_PHY_ADDR_CTL_REG_OFFSET 0x0400
#define ddrcReg_PHY_ADDR_CTL_REGP ((volatile ddrcReg_PHY_ADDR_CTL_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET))
/* @todo These SS definitions are duplicates of ones below */
#define ddrcReg_PHY_ADDR_SS_CTRL_ENABLE 0x00000001
#define ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_MASK 0xFFFF0000
#define ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT 16
#define ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK 10 /* Higher the value, lower the SS modulation frequency */
#define ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_MASK 0x0000FFFF
#define ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT 0
/* ----------------------------------------------------- */
#define ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_SHIFT 8
#define ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_MASK (0xff << ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_SHIFT)
#define ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_SHIFT 0
#define ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_MASK (0xff << ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_SHIFT)
/* ----------------------------------------------------- */
#define ddrcReg_PHY_ADDR_CTL_CLK_PM_CTL_DDR_CLK_DISABLE (1 << 0)
/* ----------------------------------------------------- */
#define ddrcReg_PHY_ADDR_CTL_PLL_STATUS_LOCKED (1 << 0)
/* ----------------------------------------------------- */
#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_DIV2_CLK_RESET (1 << 31)
#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_SHIFT 17
#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_MASK (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_SHIFT)
#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_ENABLE (1 << 16)
#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_SHIFT 12
#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_SHIFT)
#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_VCO_RNG (1 << 7)
#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_CH1_PWRDWN (1 << 6)
#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BYPASS_ENABLE (1 << 5)
#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_CLKOUT_ENABLE (1 << 4)
#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_D_RESET (1 << 3)
#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_A_RESET (1 << 2)
#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_PWRDWN (1 << 0)
/* ----------------------------------------------------- */
#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_DITHER_MFB (1 << 26)
#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_PWRDWN (1 << 25)
#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_SHIFT 20
#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_MASK (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_SHIFT)
#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_SHIFT 8
#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_MASK (0x1ff << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_SHIFT)
#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_SHIFT 4
#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_SHIFT)
#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_SHIFT 0
#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_SHIFT)
/* ----------------------------------------------------- */
#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_SHIFT 24
#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_MASK (0xff << ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_SHIFT)
#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_SHIFT 0
#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_MASK (0xffffff << ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_SHIFT)
/* ----------------------------------------------------- */
#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_SHIFT 30
#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_SHIFT)
#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_SHIFT 27
#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_MASK (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_SHIFT)
#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_SHIFT 24
#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_MASK (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_SHIFT)
#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_SHIFT 22
#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_SHIFT)
#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LF_ORDER (0x1 << 21)
#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_SHIFT 19
#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_SHIFT)
#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_SHIFT 17
#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_SHIFT)
#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_SHIFT 15
#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_SHIFT)
#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_SHIFT 13
#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_SHIFT)
#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_SHIFT 10
#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_MASK (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_SHIFT)
#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_SHIFT 5
#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_MASK (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_SHIFT)
#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_SHIFT 0
#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_MASK (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_SHIFT)
/* ----------------------------------------------------- */
#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_SHIFT 4
#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_SHIFT)
#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_SHIFT 2
#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_SHIFT)
#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_LOWCUR_ENABLE (0x1 << 1)
#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_BIASIN_ENABLE (0x1 << 0)
/* ----------------------------------------------------- */
#define ddrcReg_PHY_ADDR_CTL_PLL_SS_EN_ENABLE (0x1 << 0)
/* ----------------------------------------------------- */
#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_SHIFT 16
#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_MASK (0xffff << ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_SHIFT)
#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_SHIFT 0
#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_MASK (0xffff << ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_SHIFT)
/* ----------------------------------------------------- */
#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FORCE (1 << 20)
#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_ENABLE (1 << 16)
#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_SHIFT 12
#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_SHIFT)
#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_SHIFT 8
#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_SHIFT)
#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_SHIFT 0
#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_MASK (0x3f << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_SHIFT)
/* ----------------------------------------------------- */
#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_ENABLE (1 << 16)
#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_SHIFT 12
#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_SHIFT)
#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_SHIFT 8
#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_SHIFT)
#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_SHIFT 0
#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_MASK (0x3f << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_SHIFT)
/* ----------------------------------------------------- */
#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_ENABLE (1u << 31)
#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_RXENB_DISABLE (1 << 8)
#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_IDDQ_DISABLE (1 << 6)
#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_REB_DISABLE (1 << 5)
#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_OEB_DISABLE (1 << 4)
#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_IDDQ_DISABLE (1 << 2)
#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_REB_DISABLE (1 << 1)
#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_OEB_DISABLE (1 << 0)
/* ----------------------------------------------------- */
#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_DONE (1 << 30)
#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_DONE (1 << 29)
#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_DONE (1 << 28)
#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_AUTO_ENABLE (1 << 27)
#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_ENABLE (1 << 26)
#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_OVR_ENABLE (1 << 25)
#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_OVR_ENABLE (1 << 24)
#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_SHIFT 20
#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_SHIFT)
#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_SHIFT 16
#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_SHIFT)
#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_SHIFT 12
#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_SHIFT)
#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_SHIFT 8
#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_SHIFT)
#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_SHIFT 4
#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_SHIFT)
#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_SHIFT 0
#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_SHIFT)
/* ----------------------------------------------------- */
#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_RT60B (1 << 4)
#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SEL_SSTL18 (1 << 3)
#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SELTXDRV_CI (1 << 2)
#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SELRXDRV (1 << 1)
#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SLEW (1 << 0)
/* ----------------------------------------------------- */
#define ddrcReg_PHY_ADDR_CTL_CLK_RGLTR_CTL_PWR_HALF (1 << 1)
#define ddrcReg_PHY_ADDR_CTL_CLK_RGLTR_CTL_PWR_OFF (1 << 0)
/* -------------------------------------------------------------------- */
/* -------------------------------------------------------------------- */
/* Broadcom DDR23 PHY Byte Lane register definitions */
/* -------------------------------------------------------------------- */
/* -------------------------------------------------------------------- */
#define ddrcReg_PHY_BYTE_LANE_CNT 2
#define ddrcReg_PHY_BYTE_LANE_MAX (ddrcReg_CTLR_BYTE_LANE_CNT - 1)
#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_CNT 8
typedef struct {
uint32_t revision;
uint32_t vdlCalibrate;
uint32_t vdlStatus;
REG32_RSVD(0x000c, 0x0010);
uint32_t vdlOverride[ddrcReg_PHY_BYTE_LANE_VDL_OVR_CNT];
uint32_t readCtl;
uint32_t readStatus;
uint32_t readClear;
uint32_t padIdleCtl;
uint32_t padDriveCtl;
uint32_t padClkCtl;
uint32_t writeCtl;
uint32_t clkRegCtl;
} ddrcReg_PHY_BYTE_LANE_REG_t;
/* There are 2 instances of the byte Lane registers, one for each byte lane. */
#define ddrcReg_PHY_BYTE_LANE_1_REG_OFFSET 0x0500
#define ddrcReg_PHY_BYTE_LANE_2_REG_OFFSET 0x0600
#define ddrcReg_PHY_BYTE_LANE_1_REGP ((volatile ddrcReg_PHY_BYTE_LANE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_BYTE_LANE_1_REG_OFFSET))
#define ddrcReg_PHY_BYTE_LANE_2_REGP ((volatile ddrcReg_PHY_BYTE_LANE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_BYTE_LANE_2_REG_OFFSET))
/* ----------------------------------------------------- */
#define ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_SHIFT 8
#define ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_MASK (0xff << ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_SHIFT)
#define ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_SHIFT 0
#define ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_MASK (0xff << ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_SHIFT)
/* ----------------------------------------------------- */
#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_CLK_2CYCLE (1 << 4)
#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_CLK_1CYCLE (0 << 4)
#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_TEST (1 << 3)
#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_ALWAYS (1 << 2)
#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_ONCE (1 << 1)
#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_FAST (1 << 0)
/* ----------------------------------------------------- */
/* The byte lane VDL status calibTotal[9:0] is comprised of [9:4] step value, [3:2] fine fall */
/* and [1:0] fine rise. Note that calibTotal[9:0] is located at bit 4 in the VDL status */
/* register. The fine rise and fall are no longer used, so add some definitions for just */
/* the step setting to simplify things. */
#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_SHIFT 8
#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_MASK (0x3f << ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_SHIFT)
#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_SHIFT 4
#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_MASK (0x3ff << ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_SHIFT)
#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_LOCK (1 << 1)
#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_IDLE (1 << 0)
/* ----------------------------------------------------- */
#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_ENABLE (1 << 16)
#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_SHIFT 12
#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_MASK (0x3 << ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_SHIFT)
#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_SHIFT 8
#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_MASK (0x3 << ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_SHIFT)
#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_SHIFT 0
#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_MASK (0x3f << ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_SHIFT)
#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_DQS_P 0
#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_DQS_N 1
#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_EN 2
#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_WRITE_DQ_DQM 3
#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_DQS_P 4
#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_DQS_N 5
#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_EN 6
#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_WRITE_DQ_DQM 7
/* ----------------------------------------------------- */
#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_SHIFT 8
#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_MASK (0x3 << ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_SHIFT)
#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DQ_ODT_ENABLE (1 << 3)
#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DQ_ODT_ADJUST (1 << 2)
#define ddrcReg_PHY_BYTE_LANE_READ_CTL_RD_ODT_ENABLE (1 << 1)
#define ddrcReg_PHY_BYTE_LANE_READ_CTL_RD_ODT_ADJUST (1 << 0)
/* ----------------------------------------------------- */
#define ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_SHIFT 0
#define ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_MASK (0xf << ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_SHIFT)
/* ----------------------------------------------------- */
#define ddrcReg_PHY_BYTE_LANE_READ_CLEAR_STATUS (1 << 0)
/* ----------------------------------------------------- */
#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_ENABLE (1u << 31)
#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_RXENB_DISABLE (1 << 19)
#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_IDDQ_DISABLE (1 << 18)
#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_REB_DISABLE (1 << 17)
#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_OEB_DISABLE (1 << 16)
#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_RXENB_DISABLE (1 << 15)
#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_IDDQ_DISABLE (1 << 14)
#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_REB_DISABLE (1 << 13)
#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_OEB_DISABLE (1 << 12)
#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_RXENB_DISABLE (1 << 11)
#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_IDDQ_DISABLE (1 << 10)
#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_REB_DISABLE (1 << 9)
#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_OEB_DISABLE (1 << 8)
#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_RXENB_DISABLE (1 << 7)
#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_IDDQ_DISABLE (1 << 6)
#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_REB_DISABLE (1 << 5)
#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_OEB_DISABLE (1 << 4)
#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_RXENB_DISABLE (1 << 3)
#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_IDDQ_DISABLE (1 << 2)
#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_REB_DISABLE (1 << 1)
#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_OEB_DISABLE (1 << 0)
/* ----------------------------------------------------- */
#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_RT60B_DDR_READ_ENB (1 << 5)
#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_RT60B (1 << 4)
#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SEL_SSTL18 (1 << 3)
#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SELTXDRV_CI (1 << 2)
#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SELRXDRV (1 << 1)
#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SLEW (1 << 0)
/* ----------------------------------------------------- */
#define ddrcReg_PHY_BYTE_LANE_PAD_CLK_CTL_DISABLE (1 << 0)
/* ----------------------------------------------------- */
#define ddrcReg_PHY_BYTE_LANE_WRITE_CTL_PREAMBLE_DDR3 (1 << 0)
/* ----------------------------------------------------- */
#define ddrcReg_PHY_BYTE_LANE_CLK_REG_CTL_PWR_HALF (1 << 1)
#define ddrcReg_PHY_BYTE_LANE_CLK_REG_CTL_PWR_OFF (1 << 0)
/*********************************************************************/
/* ARM PL341 DDRC to Broadcom DDR23 PHY glue register definitions */
/*********************************************************************/
typedef struct {
uint32_t cfg;
uint32_t actMonCnt;
uint32_t ctl;
uint32_t lbistCtl;
uint32_t lbistSeed;
uint32_t lbistStatus;
uint32_t tieOff;
uint32_t actMonClear;
uint32_t status;
uint32_t user;
} ddrcReg_CTLR_PHY_GLUE_REG_t;
#define ddrcReg_CTLR_PHY_GLUE_OFFSET 0x0700
#define ddrcReg_CTLR_PHY_GLUE_REGP ((volatile ddrcReg_CTLR_PHY_GLUE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_PHY_GLUE_OFFSET))
/* ----------------------------------------------------- */
/* DDR2 / AXI block phase alignment interrupt control */
#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT 18
#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_MASK (0x3 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_OFF (0 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_TIGHT (1 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_MEDIUM (2 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_LOOSE (3 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT 17
#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_MASK (1 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_DIFFERENTIAL (0 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_CMOS (1 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT 16
#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_MASK (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_DEEP (0 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHALLOW (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
#define ddrcReg_CTLR_PHY_GLUE_CFG_HW_FIXED_ALIGNMENT_DISABLED ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHALLOW
#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT 15
#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_MASK (1 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_BP134 (0 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_PL301 (1 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_REGISTERED ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_PL301
/* Software control of PHY VDL updates from control register settings. Bit 13 enables the use of Bit 14. */
/* If software control is not enabled, then updates occur when a refresh command is issued by the hardware */
/* controller. If 2 chips selects are being used, then software control must be enabled. */
#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_VDL_UPDATE_SW_CTL_LOAD (1 << 14)
#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_VDL_UPDATE_SW_CTL_ENABLE (1 << 13)
/* Use these to bypass a pipeline stage. By default the ADDR is off but the BYTE LANE in / out are on. */
#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_ADDR_CTL_IN_BYPASS_PIPELINE_STAGE (1 << 12)
#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_BYTE_LANE_IN_BYPASS_PIPELINE_STAGE (1 << 11)
#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_BYTE_LANE_OUT_BYPASS_PIPELINE_STAGE (1 << 10)
/* Chip select count */
#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT 9
#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_MASK (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_1 (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_2 (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT 8
#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_ASYNC (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT)
#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SYNC (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT)
#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT 7
#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_LOW (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT)
#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_HIGH (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT)
#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT 6
#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_LOW (0 << ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT)
#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_HIGH (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT)
#define ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_SHIFT 0
#define ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_MASK (0x7 << ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_SHIFT)
/* ----------------------------------------------------- */
#define ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_SHIFT 0
#define ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_MASK (0x7f << ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_SHIFT)
/* ---- Public Function Prototypes --------------------------------------- */
#ifdef __cplusplus
} /* end extern "C" */
#endif
#endif /* DDRC_REG_H */

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arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
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@ -1,145 +0,0 @@
/*****************************************************************************
* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/****************************************************************************/
/**
* @file dmacHw_priv.h
*
* @brief Private Definitions for low level DMA driver
*
*/
/****************************************************************************/
#ifndef _DMACHW_PRIV_H
#define _DMACHW_PRIV_H
#include <csp/stdint.h>
/* Data type for DMA Link List Item */
typedef struct {
uint32_t sar; /* Source Address Register.
Address must be aligned to CTLx.SRC_TR_WIDTH. */
uint32_t dar; /* Destination Address Register.
Address must be aligned to CTLx.DST_TR_WIDTH. */
uint32_t llpPhy; /* LLP contains the physical address of the next descriptor for block chaining using linked lists.
Address MUST be aligned to a 32-bit boundary. */
dmacHw_REG64_t ctl; /* Control Register. 64 bits */
uint32_t sstat; /* Source Status Register */
uint32_t dstat; /* Destination Status Register */
uint32_t devCtl; /* Device specific control information */
uint32_t llp; /* LLP contains the virtual address of the next descriptor for block chaining using linked lists. */
} dmacHw_DESC_t;
/*
* Descriptor ring pointers
*/
typedef struct {
int num; /* Number of link items */
dmacHw_DESC_t *pHead; /* Head of descriptor ring (for writing) */
dmacHw_DESC_t *pTail; /* Tail of descriptor ring (for reading) */
dmacHw_DESC_t *pProg; /* Descriptor to program the channel (for programming the channel register) */
dmacHw_DESC_t *pEnd; /* End of current descriptor chain */
dmacHw_DESC_t *pFree; /* Descriptor to free memory (freeing dynamic memory) */
uint32_t virt2PhyOffset; /* Virtual to physical address offset for the descriptor ring */
} dmacHw_DESC_RING_t;
/*
* DMA channel control block
*/
typedef struct {
uint32_t module; /* DMA controller module (0-1) */
uint32_t channel; /* DMA channel (0-7) */
volatile uint32_t varDataStarted; /* Flag indicating variable data channel is enabled */
volatile uint32_t descUpdated; /* Flag to indicate descriptor update is complete */
void *userData; /* Channel specifc user data */
} dmacHw_CBLK_t;
#define dmacHw_ASSERT(a) if (!(a)) while (1)
#define dmacHw_MAX_CHANNEL_COUNT 16
#define dmacHw_FREE_USER_MEMORY 0xFFFFFFFF
#define dmacHw_DESC_FREE dmacHw_REG_CTL_DONE
#define dmacHw_DESC_INIT ((dmacHw_DESC_t *) 0xFFFFFFFF)
#define dmacHw_MAX_BLOCKSIZE 4064
#define dmacHw_GET_DESC_RING(addr) (dmacHw_DESC_RING_t *)(addr)
#define dmacHw_ADDRESS_MASK(byte) ((byte) - 1)
#define dmacHw_NEXT_DESC(rp, dp) ((rp)->dp = (dmacHw_DESC_t *)(rp)->dp->llp)
#define dmacHw_HANDLE_TO_CBLK(handle) ((dmacHw_CBLK_t *) (handle))
#define dmacHw_CBLK_TO_HANDLE(cblkp) ((dmacHw_HANDLE_t) (cblkp))
#define dmacHw_DST_IS_MEMORY(tt) (((tt) == dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM) || ((tt) == dmacHw_TRANSFER_TYPE_MEM_TO_MEM)) ? 1 : 0
/****************************************************************************/
/**
* @brief Get next available transaction width
*
*
* @return On success : Next available transaction width
* On failure : dmacHw_TRANSACTION_WIDTH_8
*
* @note
* None
*/
/****************************************************************************/
static inline dmacHw_TRANSACTION_WIDTH_e dmacHw_GetNextTrWidth(dmacHw_TRANSACTION_WIDTH_e tw /* [ IN ] Current transaction width */
) {
if (tw & dmacHw_REG_CTL_SRC_TR_WIDTH_MASK) {
return ((tw >> dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT) -
1) << dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT;
} else if (tw & dmacHw_REG_CTL_DST_TR_WIDTH_MASK) {
return ((tw >> dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT) -
1) << dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT;
}
/* Default return */
return dmacHw_SRC_TRANSACTION_WIDTH_8;
}
/****************************************************************************/
/**
* @brief Get number of bytes per transaction
*
* @return Number of bytes per transaction
*
*
* @note
* None
*/
/****************************************************************************/
static inline int dmacHw_GetTrWidthInBytes(dmacHw_TRANSACTION_WIDTH_e tw /* [ IN ] Transaction width */
) {
int width = 1;
switch (tw) {
case dmacHw_SRC_TRANSACTION_WIDTH_8:
width = 1;
break;
case dmacHw_SRC_TRANSACTION_WIDTH_16:
case dmacHw_DST_TRANSACTION_WIDTH_16:
width = 2;
break;
case dmacHw_SRC_TRANSACTION_WIDTH_32:
case dmacHw_DST_TRANSACTION_WIDTH_32:
width = 4;
break;
case dmacHw_SRC_TRANSACTION_WIDTH_64:
case dmacHw_DST_TRANSACTION_WIDTH_64:
width = 8;
break;
default:
dmacHw_ASSERT(0);
}
/* Default transaction width */
return width;
}
#endif /* _DMACHW_PRIV_H */

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arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
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@ -1,406 +0,0 @@
/*****************************************************************************
* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/****************************************************************************/
/**
* @file dmacHw_reg.h
*
* @brief Definitions for low level DMA registers
*
*/
/****************************************************************************/
#ifndef _DMACHW_REG_H
#define _DMACHW_REG_H
#include <csp/stdint.h>
#include <mach/csp/mm_io.h>
/* Data type for 64 bit little endian register */
typedef struct {
volatile uint32_t lo; /* Lower 32 bit in little endian mode */
volatile uint32_t hi; /* Upper 32 bit in little endian mode */
} dmacHw_REG64_t;
/* Data type representing DMA channel registers */
typedef struct {
dmacHw_REG64_t ChannelSar; /* Source Address Register. 64 bits (upper 32 bits are reserved)
Address must be aligned to CTLx.SRC_TR_WIDTH.
*/
dmacHw_REG64_t ChannelDar; /* Destination Address Register.64 bits (upper 32 bits are reserved)
Address must be aligned to CTLx.DST_TR_WIDTH.
*/
dmacHw_REG64_t ChannelLlp; /* Link List Pointer.64 bits (upper 32 bits are reserved)
LLP contains the pointer to the next LLI for block chaining using linked lists.
If LLPis set to 0x0, then transfers using linked lists are not enabled.
Address MUST be aligned to a 32-bit boundary.
*/
dmacHw_REG64_t ChannelCtl; /* Control Register. 64 bits */
dmacHw_REG64_t ChannelSstat; /* Source Status Register */
dmacHw_REG64_t ChannelDstat; /* Destination Status Register */
dmacHw_REG64_t ChannelSstatAddr; /* Source Status Address Register */
dmacHw_REG64_t ChannelDstatAddr; /* Destination Status Address Register */
dmacHw_REG64_t ChannelConfig; /* Channel Configuration Register */
dmacHw_REG64_t SrcGather; /* Source gather register */
dmacHw_REG64_t DstScatter; /* Destination scatter register */
} dmacHw_CH_REG_t;
/* Data type for RAW interrupt status registers */
typedef struct {
dmacHw_REG64_t RawTfr; /* Raw Status for IntTfr Interrupt */
dmacHw_REG64_t RawBlock; /* Raw Status for IntBlock Interrupt */
dmacHw_REG64_t RawSrcTran; /* Raw Status for IntSrcTran Interrupt */
dmacHw_REG64_t RawDstTran; /* Raw Status for IntDstTran Interrupt */
dmacHw_REG64_t RawErr; /* Raw Status for IntErr Interrupt */
} dmacHw_INT_RAW_t;
/* Data type for interrupt status registers */
typedef struct {
dmacHw_REG64_t StatusTfr; /* Status for IntTfr Interrupt */
dmacHw_REG64_t StatusBlock; /* Status for IntBlock Interrupt */
dmacHw_REG64_t StatusSrcTran; /* Status for IntSrcTran Interrupt */
dmacHw_REG64_t StatusDstTran; /* Status for IntDstTran Interrupt */
dmacHw_REG64_t StatusErr; /* Status for IntErr Interrupt */
} dmacHw_INT_STATUS_t;
/* Data type for interrupt mask registers*/
typedef struct {
dmacHw_REG64_t MaskTfr; /* Mask for IntTfr Interrupt */
dmacHw_REG64_t MaskBlock; /* Mask for IntBlock Interrupt */
dmacHw_REG64_t MaskSrcTran; /* Mask for IntSrcTran Interrupt */
dmacHw_REG64_t MaskDstTran; /* Mask for IntDstTran Interrupt */
dmacHw_REG64_t MaskErr; /* Mask for IntErr Interrupt */
} dmacHw_INT_MASK_t;
/* Data type for interrupt clear registers */
typedef struct {
dmacHw_REG64_t ClearTfr; /* Clear for IntTfr Interrupt */
dmacHw_REG64_t ClearBlock; /* Clear for IntBlock Interrupt */
dmacHw_REG64_t ClearSrcTran; /* Clear for IntSrcTran Interrupt */
dmacHw_REG64_t ClearDstTran; /* Clear for IntDstTran Interrupt */
dmacHw_REG64_t ClearErr; /* Clear for IntErr Interrupt */
dmacHw_REG64_t StatusInt; /* Status for each interrupt type */
} dmacHw_INT_CLEAR_t;
/* Data type for software handshaking registers */
typedef struct {
dmacHw_REG64_t ReqSrcReg; /* Source Software Transaction Request Register */
dmacHw_REG64_t ReqDstReg; /* Destination Software Transaction Request Register */
dmacHw_REG64_t SglReqSrcReg; /* Single Source Transaction Request Register */
dmacHw_REG64_t SglReqDstReg; /* Single Destination Transaction Request Register */
dmacHw_REG64_t LstSrcReg; /* Last Source Transaction Request Register */
dmacHw_REG64_t LstDstReg; /* Last Destination Transaction Request Register */
} dmacHw_SW_HANDSHAKE_t;
/* Data type for misc. registers */
typedef struct {
dmacHw_REG64_t DmaCfgReg; /* DMA Configuration Register */
dmacHw_REG64_t ChEnReg; /* DMA Channel Enable Register */
dmacHw_REG64_t DmaIdReg; /* DMA ID Register */
dmacHw_REG64_t DmaTestReg; /* DMA Test Register */
dmacHw_REG64_t Reserved0; /* Reserved */
dmacHw_REG64_t Reserved1; /* Reserved */
dmacHw_REG64_t CompParm6; /* Component Parameter 6 */
dmacHw_REG64_t CompParm5; /* Component Parameter 5 */
dmacHw_REG64_t CompParm4; /* Component Parameter 4 */
dmacHw_REG64_t CompParm3; /* Component Parameter 3 */
dmacHw_REG64_t CompParm2; /* Component Parameter 2 */
dmacHw_REG64_t CompParm1; /* Component Parameter 1 */
dmacHw_REG64_t CompId; /* Compoent ID */
} dmacHw_MISC_t;
/* Base registers */
#define dmacHw_0_MODULE_BASE_ADDR (char *) MM_IO_BASE_DMA0 /* DMAC 0 module's base address */
#define dmacHw_1_MODULE_BASE_ADDR (char *) MM_IO_BASE_DMA1 /* DMAC 1 module's base address */
extern uint32_t dmaChannelCount_0;
extern uint32_t dmaChannelCount_1;
/* Define channel specific registers */
#define dmacHw_CHAN_BASE(module, chan) ((dmacHw_CH_REG_t *) ((char *)((module) ? dmacHw_1_MODULE_BASE_ADDR : dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t))))
/* Raw interrupt status registers */
#define dmacHw_REG_INT_RAW_BASE(module) ((char *)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : dmaChannelCount_0)))
#define dmacHw_REG_INT_RAW_TRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo)
#define dmacHw_REG_INT_RAW_BLOCK(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo)
#define dmacHw_REG_INT_RAW_STRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo)
#define dmacHw_REG_INT_RAW_DTRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo)
#define dmacHw_REG_INT_RAW_ERROR(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo)
/* Interrupt status registers */
#define dmacHw_REG_INT_STAT_BASE(module) ((char *)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t)))
#define dmacHw_REG_INT_STAT_TRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo)
#define dmacHw_REG_INT_STAT_BLOCK(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo)
#define dmacHw_REG_INT_STAT_STRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo)
#define dmacHw_REG_INT_STAT_DTRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo)
#define dmacHw_REG_INT_STAT_ERROR(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo)
/* Interrupt status registers */
#define dmacHw_REG_INT_MASK_BASE(module) ((char *)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t)))
#define dmacHw_REG_INT_MASK_TRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo)
#define dmacHw_REG_INT_MASK_BLOCK(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo)
#define dmacHw_REG_INT_MASK_STRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo)
#define dmacHw_REG_INT_MASK_DTRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo)
#define dmacHw_REG_INT_MASK_ERROR(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo)
/* Interrupt clear registers */
#define dmacHw_REG_INT_CLEAR_BASE(module) ((char *)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t)))
#define dmacHw_REG_INT_CLEAR_TRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo)
#define dmacHw_REG_INT_CLEAR_BLOCK(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo)
#define dmacHw_REG_INT_CLEAR_STRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo)
#define dmacHw_REG_INT_CLEAR_DTRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo)
#define dmacHw_REG_INT_CLEAR_ERROR(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo)
#define dmacHw_REG_INT_STATUS(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo)
/* Software handshaking registers */
#define dmacHw_REG_SW_HS_BASE(module) ((char *)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t)))
#define dmacHw_REG_SW_HS_SRC_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo)
#define dmacHw_REG_SW_HS_DST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo)
#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo)
#define dmacHw_REG_SW_HS_DST_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo)
#define dmacHw_REG_SW_HS_SRC_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo)
#define dmacHw_REG_SW_HS_DST_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo)
/* Miscellaneous registers */
#define dmacHw_REG_MISC_BASE(module) ((char *)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t)))
#define dmacHw_REG_MISC_CFG(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo)
#define dmacHw_REG_MISC_CH_ENABLE(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo)
#define dmacHw_REG_MISC_ID(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo)
#define dmacHw_REG_MISC_TEST(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo)
#define dmacHw_REG_MISC_COMP_PARAM1_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.lo)
#define dmacHw_REG_MISC_COMP_PARAM1_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.hi)
#define dmacHw_REG_MISC_COMP_PARAM2_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.lo)
#define dmacHw_REG_MISC_COMP_PARAM2_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.hi)
#define dmacHw_REG_MISC_COMP_PARAM3_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.lo)
#define dmacHw_REG_MISC_COMP_PARAM3_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.hi)
#define dmacHw_REG_MISC_COMP_PARAM4_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.lo)
#define dmacHw_REG_MISC_COMP_PARAM4_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.hi)
#define dmacHw_REG_MISC_COMP_PARAM5_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.lo)
#define dmacHw_REG_MISC_COMP_PARAM5_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.hi)
#define dmacHw_REG_MISC_COMP_PARAM6_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.lo)
#define dmacHw_REG_MISC_COMP_PARAM6_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.hi)
/* Channel control registers */
#define dmacHw_REG_SAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelSar.lo)
#define dmacHw_REG_DAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelDar.lo)
#define dmacHw_REG_LLP(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelLlp.lo)
#define dmacHw_REG_CTL_LO(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelCtl.lo)
#define dmacHw_REG_CTL_HI(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelCtl.hi)
#define dmacHw_REG_SSTAT(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelSstat.lo)
#define dmacHw_REG_DSTAT(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelDstat.lo)
#define dmacHw_REG_SSTATAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelSstatAddr.lo)
#define dmacHw_REG_DSTATAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelDstatAddr.lo)
#define dmacHw_REG_CFG_LO(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelConfig.lo)
#define dmacHw_REG_CFG_HI(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelConfig.hi)
#define dmacHw_REG_SGR_LO(module, chan) (dmacHw_CHAN_BASE((module), (chan))->SrcGather.lo)
#define dmacHw_REG_SGR_HI(module, chan) (dmacHw_CHAN_BASE((module), (chan))->SrcGather.hi)
#define dmacHw_REG_DSR_LO(module, chan) (dmacHw_CHAN_BASE((module), (chan))->DstScatter.lo)
#define dmacHw_REG_DSR_HI(module, chan) (dmacHw_CHAN_BASE((module), (chan))->DstScatter.hi)
#define INT_STATUS_MASK(channel) (0x00000001 << (channel))
#define CHANNEL_BUSY(mod, channel) (dmacHw_REG_MISC_CH_ENABLE((mod)) & (0x00000001 << (channel)))
/* Bit mask for REG_DMACx_CTL_LO */
#define dmacHw_REG_CTL_INT_EN 0x00000001 /* Channel interrupt enable */
#define dmacHw_REG_CTL_DST_TR_WIDTH_MASK 0x0000000E /* Destination transaction width mask */
#define dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT 1
#define dmacHw_REG_CTL_DST_TR_WIDTH_8 0x00000000 /* Destination transaction width 8 bit */
#define dmacHw_REG_CTL_DST_TR_WIDTH_16 0x00000002 /* Destination transaction width 16 bit */
#define dmacHw_REG_CTL_DST_TR_WIDTH_32 0x00000004 /* Destination transaction width 32 bit */
#define dmacHw_REG_CTL_DST_TR_WIDTH_64 0x00000006 /* Destination transaction width 64 bit */
#define dmacHw_REG_CTL_SRC_TR_WIDTH_MASK 0x00000070 /* Source transaction width mask */
#define dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT 4
#define dmacHw_REG_CTL_SRC_TR_WIDTH_8 0x00000000 /* Source transaction width 8 bit */
#define dmacHw_REG_CTL_SRC_TR_WIDTH_16 0x00000010 /* Source transaction width 16 bit */
#define dmacHw_REG_CTL_SRC_TR_WIDTH_32 0x00000020 /* Source transaction width 32 bit */
#define dmacHw_REG_CTL_SRC_TR_WIDTH_64 0x00000030 /* Source transaction width 64 bit */
#define dmacHw_REG_CTL_DS_ENABLE 0x00040000 /* Destination scatter enable */
#define dmacHw_REG_CTL_SG_ENABLE 0x00020000 /* Source gather enable */
#define dmacHw_REG_CTL_DINC_MASK 0x00000180 /* Destination address inc/dec mask */
#define dmacHw_REG_CTL_DINC_INC 0x00000000 /* Destination address increment */
#define dmacHw_REG_CTL_DINC_DEC 0x00000080 /* Destination address decrement */
#define dmacHw_REG_CTL_DINC_NC 0x00000100 /* Destination address no change */
#define dmacHw_REG_CTL_SINC_MASK 0x00000600 /* Source address inc/dec mask */
#define dmacHw_REG_CTL_SINC_INC 0x00000000 /* Source address increment */
#define dmacHw_REG_CTL_SINC_DEC 0x00000200 /* Source address decrement */
#define dmacHw_REG_CTL_SINC_NC 0x00000400 /* Source address no change */
#define dmacHw_REG_CTL_DST_MSIZE_MASK 0x00003800 /* Destination burst transaction length */
#define dmacHw_REG_CTL_DST_MSIZE_0 0x00000000 /* No Destination burst */
#define dmacHw_REG_CTL_DST_MSIZE_4 0x00000800 /* Destination burst transaction length 4 */
#define dmacHw_REG_CTL_DST_MSIZE_8 0x00001000 /* Destination burst transaction length 8 */
#define dmacHw_REG_CTL_DST_MSIZE_16 0x00001800 /* Destination burst transaction length 16 */
#define dmacHw_REG_CTL_SRC_MSIZE_MASK 0x0001C000 /* Source burst transaction length */
#define dmacHw_REG_CTL_SRC_MSIZE_0 0x00000000 /* No Source burst */
#define dmacHw_REG_CTL_SRC_MSIZE_4 0x00004000 /* Source burst transaction length 4 */
#define dmacHw_REG_CTL_SRC_MSIZE_8 0x00008000 /* Source burst transaction length 8 */
#define dmacHw_REG_CTL_SRC_MSIZE_16 0x0000C000 /* Source burst transaction length 16 */
#define dmacHw_REG_CTL_TTFC_MASK 0x00700000 /* Transfer type and flow controller */
#define dmacHw_REG_CTL_TTFC_MM_DMAC 0x00000000 /* Memory to Memory with DMAC as flow controller */
#define dmacHw_REG_CTL_TTFC_MP_DMAC 0x00100000 /* Memory to Peripheral with DMAC as flow controller */
#define dmacHw_REG_CTL_TTFC_PM_DMAC 0x00200000 /* Peripheral to Memory with DMAC as flow controller */
#define dmacHw_REG_CTL_TTFC_PP_DMAC 0x00300000 /* Peripheral to Peripheral with DMAC as flow controller */
#define dmacHw_REG_CTL_TTFC_PM_PERI 0x00400000 /* Peripheral to Memory with Peripheral as flow controller */
#define dmacHw_REG_CTL_TTFC_PP_SPERI 0x00500000 /* Peripheral to Peripheral with Source Peripheral as flow controller */
#define dmacHw_REG_CTL_TTFC_MP_PERI 0x00600000 /* Memory to Peripheral with Peripheral as flow controller */
#define dmacHw_REG_CTL_TTFC_PP_DPERI 0x00700000 /* Peripheral to Peripheral with Destination Peripheral as flow controller */
#define dmacHw_REG_CTL_DMS_MASK 0x01800000 /* Destination AHB master interface */
#define dmacHw_REG_CTL_DMS_1 0x00000000 /* Destination AHB master interface 1 */
#define dmacHw_REG_CTL_DMS_2 0x00800000 /* Destination AHB master interface 2 */
#define dmacHw_REG_CTL_SMS_MASK 0x06000000 /* Source AHB master interface */
#define dmacHw_REG_CTL_SMS_1 0x00000000 /* Source AHB master interface 1 */
#define dmacHw_REG_CTL_SMS_2 0x02000000 /* Source AHB master interface 2 */
#define dmacHw_REG_CTL_LLP_DST_EN 0x08000000 /* Block chaining enable for destination side */
#define dmacHw_REG_CTL_LLP_SRC_EN 0x10000000 /* Block chaining enable for source side */
/* Bit mask for REG_DMACx_CTL_HI */
#define dmacHw_REG_CTL_BLOCK_TS_MASK 0x00000FFF /* Block transfer size */
#define dmacHw_REG_CTL_DONE 0x00001000 /* Block trasnfer done */
/* Bit mask for REG_DMACx_CFG_LO */
#define dmacHw_REG_CFG_LO_CH_PRIORITY_SHIFT 5 /* Channel priority shift */
#define dmacHw_REG_CFG_LO_CH_PRIORITY_MASK 0x000000E0 /* Channel priority mask */
#define dmacHw_REG_CFG_LO_CH_PRIORITY_0 0x00000000 /* Channel priority 0 */
#define dmacHw_REG_CFG_LO_CH_PRIORITY_1 0x00000020 /* Channel priority 1 */
#define dmacHw_REG_CFG_LO_CH_PRIORITY_2 0x00000040 /* Channel priority 2 */
#define dmacHw_REG_CFG_LO_CH_PRIORITY_3 0x00000060 /* Channel priority 3 */
#define dmacHw_REG_CFG_LO_CH_PRIORITY_4 0x00000080 /* Channel priority 4 */
#define dmacHw_REG_CFG_LO_CH_PRIORITY_5 0x000000A0 /* Channel priority 5 */
#define dmacHw_REG_CFG_LO_CH_PRIORITY_6 0x000000C0 /* Channel priority 6 */
#define dmacHw_REG_CFG_LO_CH_PRIORITY_7 0x000000E0 /* Channel priority 7 */
#define dmacHw_REG_CFG_LO_CH_SUSPEND 0x00000100 /* Channel suspend */
#define dmacHw_REG_CFG_LO_CH_FIFO_EMPTY 0x00000200 /* Channel FIFO empty */
#define dmacHw_REG_CFG_LO_DST_CH_SW_HS 0x00000400 /* Destination channel SW handshaking */
#define dmacHw_REG_CFG_LO_SRC_CH_SW_HS 0x00000800 /* Source channel SW handshaking */
#define dmacHw_REG_CFG_LO_CH_LOCK_MASK 0x00003000 /* Channel locking mask */
#define dmacHw_REG_CFG_LO_CH_LOCK_DMA 0x00000000 /* Channel lock over the entire DMA transfer operation */
#define dmacHw_REG_CFG_LO_CH_LOCK_BLOCK 0x00001000 /* Channel lock over the block transfer operation */
#define dmacHw_REG_CFG_LO_CH_LOCK_TRANS 0x00002000 /* Channel lock over the transaction */
#define dmacHw_REG_CFG_LO_CH_LOCK_ENABLE 0x00010000 /* Channel lock enable */
#define dmacHw_REG_CFG_LO_BUS_LOCK_MASK 0x0000C000 /* Bus locking mask */
#define dmacHw_REG_CFG_LO_BUS_LOCK_DMA 0x00000000 /* Bus lock over the entire DMA transfer operation */
#define dmacHw_REG_CFG_LO_BUS_LOCK_BLOCK 0x00004000 /* Bus lock over the block transfer operation */
#define dmacHw_REG_CFG_LO_BUS_LOCK_TRANS 0x00008000 /* Bus lock over the transaction */
#define dmacHw_REG_CFG_LO_BUS_LOCK_ENABLE 0x00020000 /* Bus lock enable */
#define dmacHw_REG_CFG_LO_DST_HS_POLARITY_LOW 0x00040000 /* Destination channel handshaking signal polarity low */
#define dmacHw_REG_CFG_LO_SRC_HS_POLARITY_LOW 0x00080000 /* Source channel handshaking signal polarity low */
#define dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK 0x3FF00000 /* Maximum AMBA burst length */
#define dmacHw_REG_CFG_LO_AUTO_RELOAD_SRC 0x40000000 /* Source address auto reload */
#define dmacHw_REG_CFG_LO_AUTO_RELOAD_DST 0x80000000 /* Destination address auto reload */
/* Bit mask for REG_DMACx_CFG_HI */
#define dmacHw_REG_CFG_HI_FC_DST_READY 0x00000001 /* Source transaction request is serviced when destination is ready */
#define dmacHw_REG_CFG_HI_FIFO_ENOUGH 0x00000002 /* Initiate burst transaction when enough data in available in FIFO */
#define dmacHw_REG_CFG_HI_AHB_HPROT_MASK 0x0000001C /* AHB protection mask */
#define dmacHw_REG_CFG_HI_AHB_HPROT_1 0x00000004 /* AHB protection 1 */
#define dmacHw_REG_CFG_HI_AHB_HPROT_2 0x00000008 /* AHB protection 2 */
#define dmacHw_REG_CFG_HI_AHB_HPROT_3 0x00000010 /* AHB protection 3 */
#define dmacHw_REG_CFG_HI_UPDATE_DST_STAT 0x00000020 /* Destination status update enable */
#define dmacHw_REG_CFG_HI_UPDATE_SRC_STAT 0x00000040 /* Source status update enable */
#define dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK 0x00000780 /* Source peripheral hardware interface mask */
#define dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK 0x00007800 /* Destination peripheral hardware interface mask */
/* DMA Configuration Parameters */
#define dmacHw_REG_COMP_PARAM_NUM_CHANNELS 0x00000700 /* Number of channels */
#define dmacHw_REG_COMP_PARAM_NUM_INTERFACE 0x00001800 /* Number of master interface */
#define dmacHw_REG_COMP_PARAM_MAX_BLK_SIZE 0x0000000f /* Maximum brust size */
#define dmacHw_REG_COMP_PARAM_DATA_WIDTH 0x00006000 /* Data transfer width */
/* Define GET/SET macros to program the registers */
#define dmacHw_SET_SAR(module, channel, addr) (dmacHw_REG_SAR((module), (channel)) = (uint32_t) (addr))
#define dmacHw_SET_DAR(module, channel, addr) (dmacHw_REG_DAR((module), (channel)) = (uint32_t) (addr))
#define dmacHw_SET_LLP(module, channel, ptr) (dmacHw_REG_LLP((module), (channel)) = (uint32_t) (ptr))
#define dmacHw_GET_SSTAT(module, channel) (dmacHw_REG_SSTAT((module), (channel)))
#define dmacHw_GET_DSTAT(module, channel) (dmacHw_REG_DSTAT((module), (channel)))
#define dmacHw_SET_SSTATAR(module, channel, addr) (dmacHw_REG_SSTATAR((module), (channel)) = (uint32_t) (addr))
#define dmacHw_SET_DSTATAR(module, channel, addr) (dmacHw_REG_DSTATAR((module), (channel)) = (uint32_t) (addr))
#define dmacHw_SET_CONTROL_LO(module, channel, ctl) (dmacHw_REG_CTL_LO((module), (channel)) |= (ctl))
#define dmacHw_RESET_CONTROL_LO(module, channel) (dmacHw_REG_CTL_LO((module), (channel)) = 0)
#define dmacHw_GET_CONTROL_LO(module, channel) (dmacHw_REG_CTL_LO((module), (channel)))
#define dmacHw_SET_CONTROL_HI(module, channel, ctl) (dmacHw_REG_CTL_HI((module), (channel)) |= (ctl))
#define dmacHw_RESET_CONTROL_HI(module, channel) (dmacHw_REG_CTL_HI((module), (channel)) = 0)
#define dmacHw_GET_CONTROL_HI(module, channel) (dmacHw_REG_CTL_HI((module), (channel)))
#define dmacHw_GET_BLOCK_SIZE(module, channel) (dmacHw_REG_CTL_HI((module), (channel)) & dmacHw_REG_CTL_BLOCK_TS_MASK)
#define dmacHw_DMA_COMPLETE(module, channel) (dmacHw_REG_CTL_HI((module), (channel)) & dmacHw_REG_CTL_DONE)
#define dmacHw_SET_CONFIG_LO(module, channel, cfg) (dmacHw_REG_CFG_LO((module), (channel)) |= (cfg))
#define dmacHw_RESET_CONFIG_LO(module, channel) (dmacHw_REG_CFG_LO((module), (channel)) = 0)
#define dmacHw_GET_CONFIG_LO(module, channel) (dmacHw_REG_CFG_LO((module), (channel)))
#define dmacHw_SET_AMBA_BUSRT_LEN(module, channel, len) (dmacHw_REG_CFG_LO((module), (channel)) = (dmacHw_REG_CFG_LO((module), (channel)) & ~(dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK)) | (((len) << 20) & dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK))
#define dmacHw_SET_CHANNEL_PRIORITY(module, channel, prio) (dmacHw_REG_CFG_LO((module), (channel)) = (dmacHw_REG_CFG_LO((module), (channel)) & ~(dmacHw_REG_CFG_LO_CH_PRIORITY_MASK)) | (prio))
#define dmacHw_SET_AHB_HPROT(module, channel, protect) (dmacHw_REG_CFG_HI(module, channel) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_AHB_HPROT_MASK)) | (protect))
#define dmacHw_SET_CONFIG_HI(module, channel, cfg) (dmacHw_REG_CFG_HI((module), (channel)) |= (cfg))
#define dmacHw_RESET_CONFIG_HI(module, channel) (dmacHw_REG_CFG_HI((module), (channel)) = 0)
#define dmacHw_GET_CONFIG_HI(module, channel) (dmacHw_REG_CFG_HI((module), (channel)))
#define dmacHw_SET_SRC_PERI_INTF(module, channel, intf) (dmacHw_REG_CFG_HI((module), (channel)) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK)) | (((intf) << 7) & dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK))
#define dmacHw_SRC_PERI_INTF(intf) (((intf) << 7) & dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK)
#define dmacHw_SET_DST_PERI_INTF(module, channel, intf) (dmacHw_REG_CFG_HI((module), (channel)) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK)) | (((intf) << 11) & dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK))
#define dmacHw_DST_PERI_INTF(intf) (((intf) << 11) & dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK)
#define dmacHw_DMA_START(module, channel) (dmacHw_REG_MISC_CH_ENABLE((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
#define dmacHw_DMA_STOP(module, channel) (dmacHw_REG_MISC_CH_ENABLE((module)) = (0x00000001 << ((channel) + 8)))
#define dmacHw_DMA_ENABLE(module) (dmacHw_REG_MISC_CFG((module)) = 1)
#define dmacHw_DMA_DISABLE(module) (dmacHw_REG_MISC_CFG((module)) = 0)
#define dmacHw_TRAN_INT_ENABLE(module, channel) (dmacHw_REG_INT_MASK_TRAN((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
#define dmacHw_BLOCK_INT_ENABLE(module, channel) (dmacHw_REG_INT_MASK_BLOCK((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
#define dmacHw_ERROR_INT_ENABLE(module, channel) (dmacHw_REG_INT_MASK_ERROR((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
#define dmacHw_TRAN_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_TRAN((module)) = (0x00000001 << ((channel) + 8)))
#define dmacHw_BLOCK_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_BLOCK((module)) = (0x00000001 << ((channel) + 8)))
#define dmacHw_ERROR_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_ERROR((module)) = (0x00000001 << ((channel) + 8)))
#define dmacHw_STRAN_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_STRAN((module)) = (0x00000001 << ((channel) + 8)))
#define dmacHw_DTRAN_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_DTRAN((module)) = (0x00000001 << ((channel) + 8)))
#define dmacHw_TRAN_INT_CLEAR(module, channel) (dmacHw_REG_INT_CLEAR_TRAN((module)) = (0x00000001 << (channel)))
#define dmacHw_BLOCK_INT_CLEAR(module, channel) (dmacHw_REG_INT_CLEAR_BLOCK((module)) = (0x00000001 << (channel)))
#define dmacHw_ERROR_INT_CLEAR(module, channel) (dmacHw_REG_INT_CLEAR_ERROR((module)) = (0x00000001 << (channel)))
#define dmacHw_GET_NUM_CHANNEL(module) (((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_NUM_CHANNELS) >> 8) + 1)
#define dmacHw_GET_NUM_INTERFACE(module) (((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_NUM_INTERFACE) >> 11) + 1)
#define dmacHw_GET_MAX_BLOCK_SIZE(module, channel) ((dmacHw_REG_MISC_COMP_PARAM1_LO((module)) >> (4 * (channel))) & dmacHw_REG_COMP_PARAM_MAX_BLK_SIZE)
#define dmacHw_GET_CHANNEL_DATA_WIDTH(module, channel) ((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_DATA_WIDTH) >> 13)
#endif /* _DMACHW_REG_H */

73
arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
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@ -1,73 +0,0 @@
/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
#ifndef CSP_HW_CFG_H
#define CSP_HW_CFG_H
/* ---- Include Files ---------------------------------------------------- */
#include <cfg_global.h>
#include <mach/csp/cap_inline.h>
#if defined(__KERNEL__)
#include <mach/memory_settings.h>
#else
#include <hw_cfg.h>
#endif
/* Some items that can be defined externally, but will be set to default values */
/* if they are not defined. */
/* HW_CFG_PLL_SPREAD_SPECTRUM_DISABLE Default undefined and SS is enabled. */
/* HW_CFG_SDRAM_CAS_LATENCY 5 Default 5, Values [3..6] */
/* HW_CFG_SDRAM_CHIP_SELECT_CNT 1 Default 1, Vaules [1..2] */
/* HW_CFG_SDRAM_SPEED_GRADE 667 Default 667, Values [400,533,667,800] */
/* HW_CFG_SDRAM_WIDTH_BITS 16 Default 16, Vaules [8,16] */
/* HW_CFG_SDRAM_ADDR_BRC Default undefined and Row-Bank-Col (RBC) addressing used. Define to use Bank-Row-Col (BRC). */
/* HW_CFG_SDRAM_CLK_ASYNC Default undefined and DDR clock is synchronous with AXI BUS clock. Define for ASYNC mode. */
#if defined(CFG_GLOBAL_CHIP)
#if (CFG_GLOBAL_CHIP == FPGA11107)
#define HW_CFG_BUS_CLK_HZ 5000000
#define HW_CFG_DDR_CTLR_CLK_HZ 10000000
#define HW_CFG_DDR_PHY_OMIT
#define HW_CFG_UART_CLK_HZ 7500000
#else
#define HW_CFG_PLL_VCO_HZ 2000000000
#define HW_CFG_PLL2_VCO_HZ 1800000000
#define HW_CFG_ARM_CLK_HZ CAP_HW_CFG_ARM_CLK_HZ
#define HW_CFG_BUS_CLK_HZ 166666666
#define HW_CFG_DDR_CTLR_CLK_HZ 333333333
#define HW_CFG_DDR_PHY_CLK_HZ (2 * HW_CFG_DDR_CTLR_CLK_HZ)
#define HW_CFG_UART_CLK_HZ 142857142
#define HW_CFG_VPM_CLK_HZ CAP_HW_CFG_VPM_CLK_HZ
#endif
#else
#define HW_CFG_PLL_VCO_HZ 1800000000
#define HW_CFG_PLL2_VCO_HZ 1800000000
#define HW_CFG_ARM_CLK_HZ 450000000
#define HW_CFG_BUS_CLK_HZ 150000000
#define HW_CFG_DDR_CTLR_CLK_HZ 300000000
#define HW_CFG_DDR_PHY_CLK_HZ (2 * HW_CFG_DDR_CTLR_CLK_HZ)
#define HW_CFG_UART_CLK_HZ 150000000
#define HW_CFG_VPM_CLK_HZ 300000000
#endif
/* ---- Public Constants and Types --------------------------------------- */
/* ---- Public Variable Externs ------------------------------------------ */
/* ---- Public Function Prototypes --------------------------------------- */
#endif /* CSP_HW_CFG_H */

246
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@ -1,246 +0,0 @@
/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/****************************************************************************/
/**
* @file intcHw_reg.h
*
* @brief platform specific interrupt controller bit assignments
*
* @note
* None
*/
/****************************************************************************/
#ifndef _INTCHW_REG_H
#define _INTCHW_REG_H
/* ---- Include Files ---------------------------------------------------- */
#include <csp/stdint.h>
#include <csp/reg.h>
#include <mach/csp/mm_io.h>
/* ---- Public Constants and Types --------------------------------------- */
#define INTCHW_NUM_IRQ_PER_INTC 32 /* Maximum number of interrupt controllers */
#define INTCHW_NUM_INTC 3
/* Defines for interrupt controllers. This simplifies and cleans up the function calls. */
#define INTCHW_INTC0 ((void *)MM_IO_BASE_INTC0)
#define INTCHW_INTC1 ((void *)MM_IO_BASE_INTC1)
#define INTCHW_SINTC ((void *)MM_IO_BASE_SINTC)
/* INTC0 - interrupt controller 0 */
#define INTCHW_INTC0_PIF_BITNUM 31 /* Peripheral interface interrupt */
#define INTCHW_INTC0_CLCD_BITNUM 30 /* LCD Controller interrupt */
#define INTCHW_INTC0_GE_BITNUM 29 /* Graphic engine interrupt */
#define INTCHW_INTC0_APM_BITNUM 28 /* Audio process module interrupt */
#define INTCHW_INTC0_ESW_BITNUM 27 /* Ethernet switch interrupt */
#define INTCHW_INTC0_SPIH_BITNUM 26 /* SPI host interrupt */
#define INTCHW_INTC0_TIMER3_BITNUM 25 /* Timer3 interrupt */
#define INTCHW_INTC0_TIMER2_BITNUM 24 /* Timer2 interrupt */
#define INTCHW_INTC0_TIMER1_BITNUM 23 /* Timer1 interrupt */
#define INTCHW_INTC0_TIMER0_BITNUM 22 /* Timer0 interrupt */
#define INTCHW_INTC0_SDIOH1_BITNUM 21 /* SDIO1 host interrupt */
#define INTCHW_INTC0_SDIOH0_BITNUM 20 /* SDIO0 host interrupt */
#define INTCHW_INTC0_USBD_BITNUM 19 /* USB device interrupt */
#define INTCHW_INTC0_USBH1_BITNUM 18 /* USB1 host interrupt */
#define INTCHW_INTC0_USBHD2_BITNUM 17 /* USB host2/device2 interrupt */
#define INTCHW_INTC0_VPM_BITNUM 16 /* Voice process module interrupt */
#define INTCHW_INTC0_DMA1C7_BITNUM 15 /* DMA1 channel 7 interrupt */
#define INTCHW_INTC0_DMA1C6_BITNUM 14 /* DMA1 channel 6 interrupt */
#define INTCHW_INTC0_DMA1C5_BITNUM 13 /* DMA1 channel 5 interrupt */
#define INTCHW_INTC0_DMA1C4_BITNUM 12 /* DMA1 channel 4 interrupt */
#define INTCHW_INTC0_DMA1C3_BITNUM 11 /* DMA1 channel 3 interrupt */
#define INTCHW_INTC0_DMA1C2_BITNUM 10 /* DMA1 channel 2 interrupt */
#define INTCHW_INTC0_DMA1C1_BITNUM 9 /* DMA1 channel 1 interrupt */
#define INTCHW_INTC0_DMA1C0_BITNUM 8 /* DMA1 channel 0 interrupt */
#define INTCHW_INTC0_DMA0C7_BITNUM 7 /* DMA0 channel 7 interrupt */
#define INTCHW_INTC0_DMA0C6_BITNUM 6 /* DMA0 channel 6 interrupt */
#define INTCHW_INTC0_DMA0C5_BITNUM 5 /* DMA0 channel 5 interrupt */
#define INTCHW_INTC0_DMA0C4_BITNUM 4 /* DMA0 channel 4 interrupt */
#define INTCHW_INTC0_DMA0C3_BITNUM 3 /* DMA0 channel 3 interrupt */
#define INTCHW_INTC0_DMA0C2_BITNUM 2 /* DMA0 channel 2 interrupt */
#define INTCHW_INTC0_DMA0C1_BITNUM 1 /* DMA0 channel 1 interrupt */
#define INTCHW_INTC0_DMA0C0_BITNUM 0 /* DMA0 channel 0 interrupt */
#define INTCHW_INTC0_PIF (1<<INTCHW_INTC0_PIF_BITNUM)
#define INTCHW_INTC0_CLCD (1<<INTCHW_INTC0_CLCD_BITNUM)
#define INTCHW_INTC0_GE (1<<INTCHW_INTC0_GE_BITNUM)
#define INTCHW_INTC0_APM (1<<INTCHW_INTC0_APM_BITNUM)
#define INTCHW_INTC0_ESW (1<<INTCHW_INTC0_ESW_BITNUM)
#define INTCHW_INTC0_SPIH (1<<INTCHW_INTC0_SPIH_BITNUM)
#define INTCHW_INTC0_TIMER3 (1<<INTCHW_INTC0_TIMER3_BITNUM)
#define INTCHW_INTC0_TIMER2 (1<<INTCHW_INTC0_TIMER2_BITNUM)
#define INTCHW_INTC0_TIMER1 (1<<INTCHW_INTC0_TIMER1_BITNUM)
#define INTCHW_INTC0_TIMER0 (1<<INTCHW_INTC0_TIMER0_BITNUM)
#define INTCHW_INTC0_SDIOH1 (1<<INTCHW_INTC0_SDIOH1_BITNUM)
#define INTCHW_INTC0_SDIOH0 (1<<INTCHW_INTC0_SDIOH0_BITNUM)
#define INTCHW_INTC0_USBD (1<<INTCHW_INTC0_USBD_BITNUM)
#define INTCHW_INTC0_USBH1 (1<<INTCHW_INTC0_USBH1_BITNUM)
#define INTCHW_INTC0_USBHD2 (1<<INTCHW_INTC0_USBHD2_BITNUM)
#define INTCHW_INTC0_VPM (1<<INTCHW_INTC0_VPM_BITNUM)
#define INTCHW_INTC0_DMA1C7 (1<<INTCHW_INTC0_DMA1C7_BITNUM)
#define INTCHW_INTC0_DMA1C6 (1<<INTCHW_INTC0_DMA1C6_BITNUM)
#define INTCHW_INTC0_DMA1C5 (1<<INTCHW_INTC0_DMA1C5_BITNUM)
#define INTCHW_INTC0_DMA1C4 (1<<INTCHW_INTC0_DMA1C4_BITNUM)
#define INTCHW_INTC0_DMA1C3 (1<<INTCHW_INTC0_DMA1C3_BITNUM)
#define INTCHW_INTC0_DMA1C2 (1<<INTCHW_INTC0_DMA1C2_BITNUM)
#define INTCHW_INTC0_DMA1C1 (1<<INTCHW_INTC0_DMA1C1_BITNUM)
#define INTCHW_INTC0_DMA1C0 (1<<INTCHW_INTC0_DMA1C0_BITNUM)
#define INTCHW_INTC0_DMA0C7 (1<<INTCHW_INTC0_DMA0C7_BITNUM)
#define INTCHW_INTC0_DMA0C6 (1<<INTCHW_INTC0_DMA0C6_BITNUM)
#define INTCHW_INTC0_DMA0C5 (1<<INTCHW_INTC0_DMA0C5_BITNUM)
#define INTCHW_INTC0_DMA0C4 (1<<INTCHW_INTC0_DMA0C4_BITNUM)
#define INTCHW_INTC0_DMA0C3 (1<<INTCHW_INTC0_DMA0C3_BITNUM)
#define INTCHW_INTC0_DMA0C2 (1<<INTCHW_INTC0_DMA0C2_BITNUM)
#define INTCHW_INTC0_DMA0C1 (1<<INTCHW_INTC0_DMA0C1_BITNUM)
#define INTCHW_INTC0_DMA0C0 (1<<INTCHW_INTC0_DMA0C0_BITNUM)
/* INTC1 - interrupt controller 1 */
#define INTCHW_INTC1_DDRVPMP_BITNUM 27 /* DDR and VPM PLL clock phase relationship interrupt (Not for A0) */
#define INTCHW_INTC1_DDRVPMT_BITNUM 26 /* DDR and VPM HW phase align timeout interrupt (Not for A0) */
#define INTCHW_INTC1_DDRP_BITNUM 26 /* DDR and PLL clock phase relationship interrupt (For A0 only)) */
#define INTCHW_INTC1_RTC2_BITNUM 25 /* Real time clock tamper interrupt */
#define INTCHW_INTC1_VDEC_BITNUM 24 /* Hantro Video Decoder interrupt */
/* Bits 13-23 are non-secure versions of the corresponding secure bits in SINTC bits 0-10. */
#define INTCHW_INTC1_SPUM_BITNUM 23 /* Secure process module interrupt */
#define INTCHW_INTC1_RTC1_BITNUM 22 /* Real time clock one-shot interrupt */
#define INTCHW_INTC1_RTC0_BITNUM 21 /* Real time clock periodic interrupt */
#define INTCHW_INTC1_RNG_BITNUM 20 /* Random number generator interrupt */
#define INTCHW_INTC1_FMPU_BITNUM 19 /* Flash memory parition unit interrupt */
#define INTCHW_INTC1_VMPU_BITNUM 18 /* VRAM memory partition interrupt */
#define INTCHW_INTC1_DMPU_BITNUM 17 /* DDR2 memory partition interrupt */
#define INTCHW_INTC1_KEYC_BITNUM 16 /* Key pad controller interrupt */
#define INTCHW_INTC1_TSC_BITNUM 15 /* Touch screen controller interrupt */
#define INTCHW_INTC1_UART0_BITNUM 14 /* UART 0 */
#define INTCHW_INTC1_WDOG_BITNUM 13 /* Watchdog timer interrupt */
#define INTCHW_INTC1_UART1_BITNUM 12 /* UART 1 */
#define INTCHW_INTC1_PMUIRQ_BITNUM 11 /* ARM performance monitor interrupt */
#define INTCHW_INTC1_COMMRX_BITNUM 10 /* ARM DDC receive interrupt */
#define INTCHW_INTC1_COMMTX_BITNUM 9 /* ARM DDC transmit interrupt */
#define INTCHW_INTC1_FLASHC_BITNUM 8 /* Flash controller interrupt */
#define INTCHW_INTC1_GPHY_BITNUM 7 /* Gigabit Phy interrupt */
#define INTCHW_INTC1_SPIS_BITNUM 6 /* SPI slave interrupt */
#define INTCHW_INTC1_I2CS_BITNUM 5 /* I2C slave interrupt */
#define INTCHW_INTC1_I2CH_BITNUM 4 /* I2C host interrupt */
#define INTCHW_INTC1_I2S1_BITNUM 3 /* I2S1 interrupt */
#define INTCHW_INTC1_I2S0_BITNUM 2 /* I2S0 interrupt */
#define INTCHW_INTC1_GPIO1_BITNUM 1 /* GPIO bit 64//32 combined interrupt */
#define INTCHW_INTC1_GPIO0_BITNUM 0 /* GPIO bit 31//0 combined interrupt */
#define INTCHW_INTC1_DDRVPMT (1<<INTCHW_INTC1_DDRVPMT_BITNUM)
#define INTCHW_INTC1_DDRVPMP (1<<INTCHW_INTC1_DDRVPMP_BITNUM)
#define INTCHW_INTC1_DDRP (1<<INTCHW_INTC1_DDRP_BITNUM)
#define INTCHW_INTC1_VDEC (1<<INTCHW_INTC1_VDEC_BITNUM)
#define INTCHW_INTC1_SPUM (1<<INTCHW_INTC1_SPUM_BITNUM)
#define INTCHW_INTC1_RTC2 (1<<INTCHW_INTC1_RTC2_BITNUM)
#define INTCHW_INTC1_RTC1 (1<<INTCHW_INTC1_RTC1_BITNUM)
#define INTCHW_INTC1_RTC0 (1<<INTCHW_INTC1_RTC0_BITNUM)
#define INTCHW_INTC1_RNG (1<<INTCHW_INTC1_RNG_BITNUM)
#define INTCHW_INTC1_FMPU (1<<INTCHW_INTC1_FMPU_BITNUM)
#define INTCHW_INTC1_IMPU (1<<INTCHW_INTC1_IMPU_BITNUM)
#define INTCHW_INTC1_DMPU (1<<INTCHW_INTC1_DMPU_BITNUM)
#define INTCHW_INTC1_KEYC (1<<INTCHW_INTC1_KEYC_BITNUM)
#define INTCHW_INTC1_TSC (1<<INTCHW_INTC1_TSC_BITNUM)
#define INTCHW_INTC1_UART0 (1<<INTCHW_INTC1_UART0_BITNUM)
#define INTCHW_INTC1_WDOG (1<<INTCHW_INTC1_WDOG_BITNUM)
#define INTCHW_INTC1_UART1 (1<<INTCHW_INTC1_UART1_BITNUM)
#define INTCHW_INTC1_PMUIRQ (1<<INTCHW_INTC1_PMUIRQ_BITNUM)
#define INTCHW_INTC1_COMMRX (1<<INTCHW_INTC1_COMMRX_BITNUM)
#define INTCHW_INTC1_COMMTX (1<<INTCHW_INTC1_COMMTX_BITNUM)
#define INTCHW_INTC1_FLASHC (1<<INTCHW_INTC1_FLASHC_BITNUM)
#define INTCHW_INTC1_GPHY (1<<INTCHW_INTC1_GPHY_BITNUM)
#define INTCHW_INTC1_SPIS (1<<INTCHW_INTC1_SPIS_BITNUM)
#define INTCHW_INTC1_I2CS (1<<INTCHW_INTC1_I2CS_BITNUM)
#define INTCHW_INTC1_I2CH (1<<INTCHW_INTC1_I2CH_BITNUM)
#define INTCHW_INTC1_I2S1 (1<<INTCHW_INTC1_I2S1_BITNUM)
#define INTCHW_INTC1_I2S0 (1<<INTCHW_INTC1_I2S0_BITNUM)
#define INTCHW_INTC1_GPIO1 (1<<INTCHW_INTC1_GPIO1_BITNUM)
#define INTCHW_INTC1_GPIO0 (1<<INTCHW_INTC1_GPIO0_BITNUM)
/* SINTC secure int controller */
#define INTCHW_SINTC_RTC2_BITNUM 15 /* Real time clock tamper interrupt */
#define INTCHW_SINTC_TIMER3_BITNUM 14 /* Secure timer3 interrupt */
#define INTCHW_SINTC_TIMER2_BITNUM 13 /* Secure timer2 interrupt */
#define INTCHW_SINTC_TIMER1_BITNUM 12 /* Secure timer1 interrupt */
#define INTCHW_SINTC_TIMER0_BITNUM 11 /* Secure timer0 interrupt */
#define INTCHW_SINTC_SPUM_BITNUM 10 /* Secure process module interrupt */
#define INTCHW_SINTC_RTC1_BITNUM 9 /* Real time clock one-shot interrupt */
#define INTCHW_SINTC_RTC0_BITNUM 8 /* Real time clock periodic interrupt */
#define INTCHW_SINTC_RNG_BITNUM 7 /* Random number generator interrupt */
#define INTCHW_SINTC_FMPU_BITNUM 6 /* Flash memory parition unit interrupt */
#define INTCHW_SINTC_VMPU_BITNUM 5 /* VRAM memory partition interrupt */
#define INTCHW_SINTC_DMPU_BITNUM 4 /* DDR2 memory partition interrupt */
#define INTCHW_SINTC_KEYC_BITNUM 3 /* Key pad controller interrupt */
#define INTCHW_SINTC_TSC_BITNUM 2 /* Touch screen controller interrupt */
#define INTCHW_SINTC_UART0_BITNUM 1 /* UART0 interrupt */
#define INTCHW_SINTC_WDOG_BITNUM 0 /* Watchdog timer interrupt */
#define INTCHW_SINTC_TIMER3 (1<<INTCHW_SINTC_TIMER3_BITNUM)
#define INTCHW_SINTC_TIMER2 (1<<INTCHW_SINTC_TIMER2_BITNUM)
#define INTCHW_SINTC_TIMER1 (1<<INTCHW_SINTC_TIMER1_BITNUM)
#define INTCHW_SINTC_TIMER0 (1<<INTCHW_SINTC_TIMER0_BITNUM)
#define INTCHW_SINTC_SPUM (1<<INTCHW_SINTC_SPUM_BITNUM)
#define INTCHW_SINTC_RTC2 (1<<INTCHW_SINTC_RTC2_BITNUM)
#define INTCHW_SINTC_RTC1 (1<<INTCHW_SINTC_RTC1_BITNUM)
#define INTCHW_SINTC_RTC0 (1<<INTCHW_SINTC_RTC0_BITNUM)
#define INTCHW_SINTC_RNG (1<<INTCHW_SINTC_RNG_BITNUM)
#define INTCHW_SINTC_FMPU (1<<INTCHW_SINTC_FMPU_BITNUM)
#define INTCHW_SINTC_IMPU (1<<INTCHW_SINTC_IMPU_BITNUM)
#define INTCHW_SINTC_DMPU (1<<INTCHW_SINTC_DMPU_BITNUM)
#define INTCHW_SINTC_KEYC (1<<INTCHW_SINTC_KEYC_BITNUM)
#define INTCHW_SINTC_TSC (1<<INTCHW_SINTC_TSC_BITNUM)
#define INTCHW_SINTC_UART0 (1<<INTCHW_SINTC_UART0_BITNUM)
#define INTCHW_SINTC_WDOG (1<<INTCHW_SINTC_WDOG_BITNUM)
/* PL192 Vectored Interrupt Controller (VIC) layout */
#define INTCHW_IRQSTATUS 0x00 /* IRQ status register */
#define INTCHW_FIQSTATUS 0x04 /* FIQ status register */
#define INTCHW_RAWINTR 0x08 /* Raw Interrupt Status register */
#define INTCHW_INTSELECT 0x0c /* Interrupt Select Register */
#define INTCHW_INTENABLE 0x10 /* Interrupt Enable Register */
#define INTCHW_INTENCLEAR 0x14 /* Interrupt Enable Clear Register */
#define INTCHW_SOFTINT 0x18 /* Soft Interrupt Register */
#define INTCHW_SOFTINTCLEAR 0x1c /* Soft Interrupt Clear Register */
#define INTCHW_PROTECTION 0x20 /* Protection Enable Register */
#define INTCHW_SWPRIOMASK 0x24 /* Software Priority Mask Register */
#define INTCHW_PRIODAISY 0x28 /* Priority Daisy Chain Register */
#define INTCHW_VECTADDR0 0x100 /* Vector Address Registers */
#define INTCHW_VECTPRIO0 0x200 /* Vector Priority Registers 0-31 */
#define INTCHW_ADDRESS 0xf00 /* Vector Address Register 0-31 */
#define INTCHW_PID 0xfe0 /* Peripheral ID Register 0-3 */
#define INTCHW_PCELLID 0xff0 /* PrimeCell ID Register 0-3 */
/* Example Usage: intcHw_irq_enable(INTCHW_INTC0, INTCHW_INTC0_TIMER0); */
/* intcHw_irq_clear(INTCHW_INTC0, INTCHW_INTC0_TIMER0); */
/* uint32_t bits = intcHw_irq_status(INTCHW_INTC0); */
/* uint32_t bits = intcHw_irq_raw_status(INTCHW_INTC0); */
/* ---- Public Variable Externs ------------------------------------------ */
/* ---- Public Function Prototypes --------------------------------------- */
/* Clear one or more IRQ interrupts. */
static inline void intcHw_irq_disable(void *basep, uint32_t mask)
{
__REG32(basep + INTCHW_INTENCLEAR) = mask;
}
/* Enables one or more IRQ interrupts. */
static inline void intcHw_irq_enable(void *basep, uint32_t mask)
{
__REG32(basep + INTCHW_INTENABLE) = mask;
}
#endif /* _INTCHW_REG_H */

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/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/****************************************************************************/
/**
* @file mm_addr.h
*
* @brief Memory Map address definitions
*
* @note
* None
*/
/****************************************************************************/
#ifndef _MM_ADDR_H
#define _MM_ADDR_H
/* ---- Include Files ---------------------------------------------------- */
#if !defined(CSP_SIMULATION)
#include <cfg_global.h>
#endif
/* ---- Public Constants and Types --------------------------------------- */
/* Memory Map address definitions */
#define MM_ADDR_DDR 0x00000000
#define MM_ADDR_IO_VPM_EXTMEM_RSVD 0x0F000000 /* 16 MB - Reserved external memory for VPM use */
#define MM_ADDR_IO_FLASHC 0x20000000
#define MM_ADDR_IO_BROM 0x30000000
#define MM_ADDR_IO_ARAM 0x30100000 /* 64 KB - extra cycle latency - WS switch */
#define MM_ADDR_IO_DMA0 0x30200000
#define MM_ADDR_IO_DMA1 0x30300000
#define MM_ADDR_IO_ESW 0x30400000
#define MM_ADDR_IO_CLCD 0x30500000
#define MM_ADDR_IO_PIF 0x30580000
#define MM_ADDR_IO_APM 0x30600000
#define MM_ADDR_IO_SPUM 0x30700000
#define MM_ADDR_IO_VPM_PROG 0x30800000
#define MM_ADDR_IO_VPM_DATA 0x30A00000
#define MM_ADDR_IO_VRAM 0x40000000 /* 64 KB - security block in front of it */
#define MM_ADDR_IO_CHIPC 0x80000000
#define MM_ADDR_IO_UMI 0x80001000
#define MM_ADDR_IO_NAND 0x80001800
#define MM_ADDR_IO_LEDM 0x80002000
#define MM_ADDR_IO_PWM 0x80002040
#define MM_ADDR_IO_VINTC 0x80003000
#define MM_ADDR_IO_GPIO0 0x80004000
#define MM_ADDR_IO_GPIO1 0x80004800
#define MM_ADDR_IO_I2CS 0x80005000
#define MM_ADDR_IO_SPIS 0x80006000
#define MM_ADDR_IO_HPM 0x80007400
#define MM_ADDR_IO_HPM_REMAP 0x80007800
#define MM_ADDR_IO_TZPC 0x80008000
#define MM_ADDR_IO_MPU 0x80009000
#define MM_ADDR_IO_SPUMP 0x8000a000
#define MM_ADDR_IO_PKA 0x8000b000
#define MM_ADDR_IO_RNG 0x8000c000
#define MM_ADDR_IO_KEYC 0x8000d000
#define MM_ADDR_IO_BBL 0x8000e000
#define MM_ADDR_IO_OTP 0x8000f000
#define MM_ADDR_IO_I2S0 0x80010000
#define MM_ADDR_IO_I2S1 0x80011000
#define MM_ADDR_IO_UARTA 0x80012000
#define MM_ADDR_IO_UARTB 0x80013000
#define MM_ADDR_IO_I2CH 0x80014020
#define MM_ADDR_IO_SPIH 0x80015000
#define MM_ADDR_IO_TSC 0x80016000
#define MM_ADDR_IO_TMR 0x80017000
#define MM_ADDR_IO_WATCHDOG 0x80017800
#define MM_ADDR_IO_ETM 0x80018000
#define MM_ADDR_IO_DDRC 0x80019000
#define MM_ADDR_IO_SINTC 0x80100000
#define MM_ADDR_IO_INTC0 0x80200000
#define MM_ADDR_IO_INTC1 0x80201000
#define MM_ADDR_IO_GE 0x80300000
#define MM_ADDR_IO_USB_CTLR0 0x80400000
#define MM_ADDR_IO_USB_CTLR1 0x80410000
#define MM_ADDR_IO_USB_PHY 0x80420000
#define MM_ADDR_IO_SDIOH0 0x80500000
#define MM_ADDR_IO_SDIOH1 0x80600000
#define MM_ADDR_IO_VDEC 0x80700000
/* ---- Public Variable Externs ------------------------------------------ */
/* ---- Public Function Prototypes --------------------------------------- */
#endif /* _MM_ADDR_H */

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/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/****************************************************************************/
/**
* @file mm_io.h
*
* @brief Memory Map I/O definitions
*
* @note
* None
*/
/****************************************************************************/
#ifndef _MM_IO_H
#define _MM_IO_H
/* ---- Include Files ---------------------------------------------------- */
#include <mach/csp/mm_addr.h>
#if !defined(CSP_SIMULATION)
#include <cfg_global.h>
#endif
/* ---- Public Constants and Types --------------------------------------- */
#if defined(CONFIG_MMU)
/* This macro is referenced in <mach/io.h>
* Phys to Virtual 0xNyxxxxxx => 0xFNxxxxxx
* This macro is referenced in <asm/arch/io.h>
*
* Assume VPM address is the last x MB of memory. For VPM, map to
* 0xf0000000 and up.
*/
#ifndef MM_IO_PHYS_TO_VIRT
#ifdef __ASSEMBLY__
#define MM_IO_PHYS_TO_VIRT(phys) (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF))
#else
#define MM_IO_PHYS_TO_VIRT(phys) (((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \
(0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF)))
#endif
#endif
/* Virtual to Physical 0xFNxxxxxx => 0xN0xxxxxx */
#ifndef MM_IO_VIRT_TO_PHYS
#ifdef __ASSEMBLY__
#define MM_IO_VIRT_TO_PHYS(virt) ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF))
#else
#define MM_IO_VIRT_TO_PHYS(virt) (((virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \
((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF)))
#endif
#endif
#else
#ifndef MM_IO_PHYS_TO_VIRT
#define MM_IO_PHYS_TO_VIRT(phys) (phys)
#endif
#ifndef MM_IO_VIRT_TO_PHYS
#define MM_IO_VIRT_TO_PHYS(virt) (virt)
#endif
#endif
/* Registers in 0xExxxxxxx that should be moved to 0xFxxxxxxx */
#define MM_IO_BASE_FLASHC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_FLASHC)
#define MM_IO_BASE_NAND MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_NAND)
#define MM_IO_BASE_UMI MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UMI)
#define MM_IO_START MM_ADDR_IO_FLASHC /* Physical beginning of IO mapped memory */
#define MM_IO_BASE MM_IO_BASE_FLASHC /* Virtual beginning of IO mapped memory */
#define MM_IO_BASE_BROM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_BROM)
#define MM_IO_BASE_ARAM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ARAM)
#define MM_IO_BASE_DMA0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DMA0)
#define MM_IO_BASE_DMA1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DMA1)
#define MM_IO_BASE_ESW MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ESW)
#define MM_IO_BASE_CLCD MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_CLCD)
#define MM_IO_BASE_PIF MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PIF)
#define MM_IO_BASE_APM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_APM)
#define MM_IO_BASE_SPUM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPUM)
#define MM_IO_BASE_VPM_PROG MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_PROG)
#define MM_IO_BASE_VPM_DATA MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_DATA)
#define MM_IO_BASE_VRAM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VRAM)
#define MM_IO_BASE_CHIPC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_CHIPC)
#define MM_IO_BASE_DDRC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DDRC)
#define MM_IO_BASE_LEDM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_LEDM)
#define MM_IO_BASE_PWM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PWM)
#define MM_IO_BASE_VINTC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VINTC)
#define MM_IO_BASE_GPIO0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GPIO0)
#define MM_IO_BASE_GPIO1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GPIO1)
#define MM_IO_BASE_TMR MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TMR)
#define MM_IO_BASE_WATCHDOG MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_WATCHDOG)
#define MM_IO_BASE_ETM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ETM)
#define MM_IO_BASE_HPM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_HPM)
#define MM_IO_BASE_HPM_REMAP MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_HPM_REMAP)
#define MM_IO_BASE_TZPC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TZPC)
#define MM_IO_BASE_MPU MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_MPU)
#define MM_IO_BASE_SPUMP MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPUMP)
#define MM_IO_BASE_PKA MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PKA)
#define MM_IO_BASE_RNG MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_RNG)
#define MM_IO_BASE_KEYC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_KEYC)
#define MM_IO_BASE_BBL MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_BBL)
#define MM_IO_BASE_OTP MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_OTP)
#define MM_IO_BASE_I2S0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2S0)
#define MM_IO_BASE_I2S1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2S1)
#define MM_IO_BASE_UARTA MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UARTA)
#define MM_IO_BASE_UARTB MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UARTB)
#define MM_IO_BASE_I2CH MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2CH)
#define MM_IO_BASE_SPIH MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPIH)
#define MM_IO_BASE_TSC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TSC)
#define MM_IO_BASE_I2CS MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2CS)
#define MM_IO_BASE_SPIS MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPIS)
#define MM_IO_BASE_SINTC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SINTC)
#define MM_IO_BASE_INTC0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_INTC0)
#define MM_IO_BASE_INTC1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_INTC1)
#define MM_IO_BASE_GE MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GE)
#define MM_IO_BASE_USB_CTLR0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_CTLR0)
#define MM_IO_BASE_USB_CTLR1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_CTLR1)
#define MM_IO_BASE_USB_PHY MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_PHY)
#define MM_IO_BASE_SDIOH0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SDIOH0)
#define MM_IO_BASE_SDIOH1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SDIOH1)
#define MM_IO_BASE_VDEC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VDEC)
#define MM_IO_BASE_VPM_EXTMEM_RSVD MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_EXTMEM_RSVD)
/* ---- Public Variable Externs ------------------------------------------ */
/* ---- Public Function Prototypes --------------------------------------- */
#endif /* _MM_IO_H */

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arch/arm/mach-bcmring/include/mach/csp/secHw_def.h
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/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/****************************************************************************/
/**
* @file secHw_def.h
*
* @brief Definitions for configuring/testing secure blocks
*
* @note
* None
*/
/****************************************************************************/
#ifndef SECHW_DEF_H
#define SECHW_DEF_H
#include <mach/csp/mm_io.h>
/* Bit mask for various secure device */
#define secHw_BLK_MASK_CHIP_CONTROL 0x00000001
#define secHw_BLK_MASK_KEY_SCAN 0x00000002
#define secHw_BLK_MASK_TOUCH_SCREEN 0x00000004
#define secHw_BLK_MASK_UART0 0x00000008
#define secHw_BLK_MASK_UART1 0x00000010
#define secHw_BLK_MASK_WATCHDOG 0x00000020
#define secHw_BLK_MASK_SPUM 0x00000040
#define secHw_BLK_MASK_DDR2 0x00000080
#define secHw_BLK_MASK_EXT_MEM 0x00000100
#define secHw_BLK_MASK_ESW 0x00000200
#define secHw_BLK_MASK_SPU 0x00010000
#define secHw_BLK_MASK_PKA 0x00020000
#define secHw_BLK_MASK_RNG 0x00040000
#define secHw_BLK_MASK_RTC 0x00080000
#define secHw_BLK_MASK_OTP 0x00100000
#define secHw_BLK_MASK_BOOT 0x00200000
#define secHw_BLK_MASK_MPU 0x00400000
#define secHw_BLK_MASK_TZCTRL 0x00800000
#define secHw_BLK_MASK_INTR 0x01000000
/* Trustzone register set */
typedef struct {
volatile uint32_t status; /* read only - reflects status of writes of 2 write registers */
volatile uint32_t setUnsecure; /* write only. reads back as 0 */
volatile uint32_t setSecure; /* write only. reads back as 0 */
} secHw_TZREG_t;
/* There are 2 register sets. The first is for the lower 16 bits, the 2nd */
/* is for the higher 16 bits. */
typedef enum {
secHw_IDX_LS = 0,
secHw_IDX_MS = 1,
secHw_IDX_NUM
} secHw_IDX_e;
typedef struct {
volatile secHw_TZREG_t reg[secHw_IDX_NUM];
} secHw_REGS_t;
/****************************************************************************/
/**
* @brief Configures a device as a secure device
*
*/
/****************************************************************************/
static inline void secHw_setSecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */
);
/****************************************************************************/
/**
* @brief Configures a device as a non-secure device
*
*/
/****************************************************************************/
static inline void secHw_setUnsecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */
);
/****************************************************************************/
/**
* @brief Get the trustzone status for all components. 1 = non-secure, 0 = secure
*
*/
/****************************************************************************/
static inline uint32_t secHw_getStatus(void);
#include <mach/csp/secHw_inline.h>
#endif /* SECHW_DEF_H */

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/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/****************************************************************************/
/**
* @file secHw_inline.h
*
* @brief Definitions for configuring/testing secure blocks
*
* @note
* None
*/
/****************************************************************************/
#ifndef SECHW_INLINE_H
#define SECHW_INLINE_H
/****************************************************************************/
/**
* @brief Configures a device as a secure device
*
*/
/****************************************************************************/
static inline void secHw_setSecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */
) {
secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
if (mask & 0x0000FFFF) {
regp->reg[secHw_IDX_LS].setSecure = mask & 0x0000FFFF;
}
if (mask & 0xFFFF0000) {
regp->reg[secHw_IDX_MS].setSecure = mask >> 16;
}
}
/****************************************************************************/
/**
* @brief Configures a device as a non-secure device
*
*/
/****************************************************************************/
static inline void secHw_setUnsecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */
) {
secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
if (mask & 0x0000FFFF) {
regp->reg[secHw_IDX_LS].setUnsecure = mask & 0x0000FFFF;
}
if (mask & 0xFFFF0000) {
regp->reg[secHw_IDX_MS].setUnsecure = mask >> 16;
}
}
/****************************************************************************/
/**
* @brief Get the trustzone status for all components. 1 = non-secure, 0 = secure
*
*/
/****************************************************************************/
static inline uint32_t secHw_getStatus(void)
{
secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
return (regp->reg[1].status << 16) + regp->reg[0].status;
}
#endif /* SECHW_INLINE_H */

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arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h
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/*****************************************************************************
* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/****************************************************************************/
/**
* @file tmrHw_reg.h
*
* @brief Definitions for low level Timer registers
*
*/
/****************************************************************************/
#ifndef _TMRHW_REG_H
#define _TMRHW_REG_H
#include <mach/csp/mm_io.h>
#include <mach/csp/hw_cfg.h>
/* Base address */
#define tmrHw_MODULE_BASE_ADDR MM_IO_BASE_TMR
/*
This platform has four different timers running at different clock speed
Timer one (Timer ID 0) runs at 25 MHz
Timer two (Timer ID 1) runs at 25 MHz
Timer three (Timer ID 2) runs at 150 MHz
Timer four (Timer ID 3) runs at 150 MHz
*/
#define tmrHw_LOW_FREQUENCY_MHZ 25 /* Always 25MHz from XTAL */
#define tmrHw_LOW_FREQUENCY_HZ 25000000
#if defined(CFG_GLOBAL_CHIP) && (CFG_GLOBAL_CHIP == FPGA11107)
#define tmrHw_HIGH_FREQUENCY_MHZ 150 /* Always 150MHz for FPGA */
#define tmrHw_HIGH_FREQUENCY_HZ 150000000
#else
#define tmrHw_HIGH_FREQUENCY_HZ HW_CFG_BUS_CLK_HZ
#define tmrHw_HIGH_FREQUENCY_MHZ (HW_CFG_BUS_CLK_HZ / 1000000)
#endif
#define tmrHw_LOW_RESOLUTION_CLOCK tmrHw_LOW_FREQUENCY_HZ
#define tmrHw_HIGH_RESOLUTION_CLOCK tmrHw_HIGH_FREQUENCY_HZ
#define tmrHw_MAX_COUNT (0xFFFFFFFF) /* maximum number of count a timer can count */
#define tmrHw_TIMER_NUM_COUNT (4) /* Number of timer module supported */
typedef struct {
uint32_t LoadValue; /* Load value for timer */
uint32_t CurrentValue; /* Current value for timer */
uint32_t Control; /* Control register */
uint32_t InterruptClear; /* Interrupt clear register */
uint32_t RawInterruptStatus; /* Raw interrupt status */
uint32_t InterruptStatus; /* Masked interrupt status */
uint32_t BackgroundLoad; /* Background load value */
uint32_t padding; /* Padding register */
} tmrHw_REG_t;
/* Control bot masks */
#define tmrHw_CONTROL_TIMER_ENABLE 0x00000080
#define tmrHw_CONTROL_PERIODIC 0x00000040
#define tmrHw_CONTROL_INTERRUPT_ENABLE 0x00000020
#define tmrHw_CONTROL_PRESCALE_MASK 0x0000000C
#define tmrHw_CONTROL_PRESCALE_1 0x00000000
#define tmrHw_CONTROL_PRESCALE_16 0x00000004
#define tmrHw_CONTROL_PRESCALE_256 0x00000008
#define tmrHw_CONTROL_32BIT 0x00000002
#define tmrHw_CONTROL_ONESHOT 0x00000001
#define tmrHw_CONTROL_FREE_RUNNING 0x00000000
#define tmrHw_CONTROL_MODE_MASK (tmrHw_CONTROL_PERIODIC | tmrHw_CONTROL_ONESHOT)
#define pTmrHw ((volatile tmrHw_REG_t *)tmrHw_MODULE_BASE_ADDR)
#endif /* _TMRHW_REG_H */

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arch/arm/mach-bcmring/include/mach/dma.h
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/*****************************************************************************
* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/****************************************************************************/
/**
* @file dma.h
*
* @brief API definitions for the linux DMA interface.
*/
/****************************************************************************/
#if !defined(ASM_ARM_ARCH_BCMRING_DMA_H)
#define ASM_ARM_ARCH_BCMRING_DMA_H
/* ---- Include Files ---------------------------------------------------- */
#include <linux/kernel.h>
#include <linux/semaphore.h>
#include <csp/dmacHw.h>
#include <mach/timer.h>
/* ---- Constants and Types ---------------------------------------------- */
/* If DMA_DEBUG_TRACK_RESERVATION is set to a non-zero value, then the filename */
/* and line number of the reservation request will be recorded in the channel table */
#define DMA_DEBUG_TRACK_RESERVATION 1
#define DMA_NUM_CONTROLLERS 2
#define DMA_NUM_CHANNELS 8 /* per controller */
typedef enum {
DMA_DEVICE_MEM_TO_MEM, /* For memory to memory transfers */
DMA_DEVICE_I2S0_DEV_TO_MEM,
DMA_DEVICE_I2S0_MEM_TO_DEV,
DMA_DEVICE_I2S1_DEV_TO_MEM,
DMA_DEVICE_I2S1_MEM_TO_DEV,
DMA_DEVICE_APM_CODEC_A_DEV_TO_MEM,
DMA_DEVICE_APM_CODEC_A_MEM_TO_DEV,
DMA_DEVICE_APM_CODEC_B_DEV_TO_MEM,
DMA_DEVICE_APM_CODEC_B_MEM_TO_DEV,
DMA_DEVICE_APM_CODEC_C_DEV_TO_MEM, /* Additional mic input for beam-forming */
DMA_DEVICE_APM_PCM0_DEV_TO_MEM,
DMA_DEVICE_APM_PCM0_MEM_TO_DEV,
DMA_DEVICE_APM_PCM1_DEV_TO_MEM,
DMA_DEVICE_APM_PCM1_MEM_TO_DEV,
DMA_DEVICE_SPUM_DEV_TO_MEM,
DMA_DEVICE_SPUM_MEM_TO_DEV,
DMA_DEVICE_SPIH_DEV_TO_MEM,
DMA_DEVICE_SPIH_MEM_TO_DEV,
DMA_DEVICE_UART_A_DEV_TO_MEM,
DMA_DEVICE_UART_A_MEM_TO_DEV,
DMA_DEVICE_UART_B_DEV_TO_MEM,
DMA_DEVICE_UART_B_MEM_TO_DEV,
DMA_DEVICE_PIF_MEM_TO_DEV,
DMA_DEVICE_PIF_DEV_TO_MEM,
DMA_DEVICE_ESW_DEV_TO_MEM,
DMA_DEVICE_ESW_MEM_TO_DEV,
DMA_DEVICE_VPM_MEM_TO_MEM,
DMA_DEVICE_CLCD_MEM_TO_MEM,
DMA_DEVICE_NAND_MEM_TO_MEM,
DMA_DEVICE_MEM_TO_VRAM,
DMA_DEVICE_VRAM_TO_MEM,
/* Add new entries before this line. */
DMA_NUM_DEVICE_ENTRIES,
DMA_DEVICE_NONE = 0xff, /* Special value to indicate that no device is currently assigned. */
} DMA_Device_t;
/****************************************************************************
*
* The DMA_Handle_t is the primary object used by callers of the API.
*
*****************************************************************************/
#define DMA_INVALID_HANDLE ((DMA_Handle_t) -1)
typedef int DMA_Handle_t;
/****************************************************************************
*
* The DMA_DescriptorRing_t contains a ring of descriptors which is used
* to point to regions of memory.
*
*****************************************************************************/
typedef struct {
void *virtAddr; /* Virtual Address of the descriptor ring */
dma_addr_t physAddr; /* Physical address of the descriptor ring */
int descriptorsAllocated; /* Number of descriptors allocated in the descriptor ring */
size_t bytesAllocated; /* Number of bytes allocated in the descriptor ring */
} DMA_DescriptorRing_t;
/****************************************************************************
*
* The DMA_DeviceAttribute_t contains information which describes a
* particular DMA device (or peripheral).
*
* It is anticipated that the arrary of DMA_DeviceAttribute_t's will be
* statically initialized.
*
*****************************************************************************/
/* The device handler is called whenever a DMA operation completes. The reaon */
/* for it to be called will be a bitmask with one or more of the following bits */
/* set. */
#define DMA_HANDLER_REASON_BLOCK_COMPLETE dmacHw_INTERRUPT_STATUS_BLOCK
#define DMA_HANDLER_REASON_TRANSFER_COMPLETE dmacHw_INTERRUPT_STATUS_TRANS
#define DMA_HANDLER_REASON_ERROR dmacHw_INTERRUPT_STATUS_ERROR
typedef void (*DMA_DeviceHandler_t) (DMA_Device_t dev, int reason,
void *userData);
#define DMA_DEVICE_FLAG_ON_DMA0 0x00000001
#define DMA_DEVICE_FLAG_ON_DMA1 0x00000002
#define DMA_DEVICE_FLAG_PORT_PER_DMAC 0x00000004 /* If set, it means that the port used on DMAC0 is different from the port used on DMAC1 */
#define DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST 0x00000008 /* If set, allocate from DMA1 before allocating from DMA0 */
#define DMA_DEVICE_FLAG_IS_DEDICATED 0x00000100
#define DMA_DEVICE_FLAG_NO_ISR 0x00000200
#define DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO 0x00000400
#define DMA_DEVICE_FLAG_IN_USE 0x00000800 /* If set, device is in use on a channel */
/* Note: Some DMA devices can be used from multiple DMA Controllers. The bitmask is used to */
/* determine which DMA controllers a given device can be used from, and the interface */
/* array determeines the actual interface number to use for a given controller. */
typedef struct {
uint32_t flags; /* Bitmask of DMA_DEVICE_FLAG_xxx constants */
uint8_t dedicatedController; /* Controller number to use if DMA_DEVICE_FLAG_IS_DEDICATED is set. */
uint8_t dedicatedChannel; /* Channel number to use if DMA_DEVICE_FLAG_IS_DEDICATED is set. */
const char *name; /* Will show up in the /proc entry */
uint32_t dmacPort[DMA_NUM_CONTROLLERS]; /* Specifies the port number when DMA_DEVICE_FLAG_PORT_PER_DMAC flag is set */
dmacHw_CONFIG_t config; /* Configuration to use when DMA'ing using this device */
void *userData; /* Passed to the devHandler */
DMA_DeviceHandler_t devHandler; /* Called when DMA operations finish. */
timer_tick_count_t transferStartTime; /* Time the current transfer was started */
/* The following statistical information will be collected and presented in a proc entry. */
/* Note: With a contiuous bandwidth of 1 Gb/sec, it would take 584 years to overflow */
/* a 64 bit counter. */
uint64_t numTransfers; /* Number of DMA transfers performed */
uint64_t transferTicks; /* Total time spent doing DMA transfers (measured in timer_tick_count_t's) */
uint64_t transferBytes; /* Total bytes transferred */
uint32_t timesBlocked; /* Number of times a channel was unavailable */
uint32_t numBytes; /* Last transfer size */
/* It's not possible to free memory which is allocated for the descriptors from within */
/* the ISR. So make the presumption that a given device will tend to use the */
/* same sized buffers over and over again, and we keep them around. */
DMA_DescriptorRing_t ring; /* Ring of descriptors allocated for this device */
/* We stash away some of the information from the previous transfer. If back-to-back */
/* transfers are performed from the same buffer, then we don't have to keep re-initializing */
/* the descriptor buffers. */
uint32_t prevNumBytes;
dma_addr_t prevSrcData;
dma_addr_t prevDstData;
} DMA_DeviceAttribute_t;
/****************************************************************************
*
* DMA_Channel_t, DMA_Controller_t, and DMA_State_t are really internal
* data structures and don't belong in this header file, but are included
* merely for discussion.
*
* By the time this is implemented, these structures will be moved out into
* the appropriate C source file instead.
*
*****************************************************************************/
/****************************************************************************
*
* The DMA_Channel_t contains state information about each DMA channel. Some
* of the channels are dedicated. Non-dedicated channels are shared
* amongst the other devices.
*
*****************************************************************************/
#define DMA_CHANNEL_FLAG_IN_USE 0x00000001
#define DMA_CHANNEL_FLAG_IS_DEDICATED 0x00000002
#define DMA_CHANNEL_FLAG_NO_ISR 0x00000004
#define DMA_CHANNEL_FLAG_LARGE_FIFO 0x00000008
typedef struct {
uint32_t flags; /* bitmask of DMA_CHANNEL_FLAG_xxx constants */
DMA_Device_t devType; /* Device this channel is currently reserved for */
DMA_Device_t lastDevType; /* Device type that used this previously */
char name[20]; /* Name passed onto request_irq */
#if (DMA_DEBUG_TRACK_RESERVATION)
const char *fileName; /* Place where channel reservation took place */
int lineNum; /* Place where channel reservation took place */
#endif
dmacHw_HANDLE_t dmacHwHandle; /* low level channel handle. */
} DMA_Channel_t;
/****************************************************************************
*
* The DMA_Controller_t contains state information about each DMA controller.
*
* The freeChannelQ is stored in the controller data structure rather than
* the channel data structure since several of the devices are accessible
* from multiple controllers, and there is no way to know which controller
* will become available first.
*
*****************************************************************************/
typedef struct {
DMA_Channel_t channel[DMA_NUM_CHANNELS];
} DMA_Controller_t;
/****************************************************************************
*
* The DMA_Global_t contains all of the global state information used by
* the DMA code.
*
* Callers which need to allocate a shared channel will be queued up
* on the freeChannelQ until a channel becomes available.
*
*****************************************************************************/
typedef struct {
struct semaphore lock; /* acquired when manipulating table entries */
wait_queue_head_t freeChannelQ;
DMA_Controller_t controller[DMA_NUM_CONTROLLERS];
} DMA_Global_t;
/* ---- Variable Externs ------------------------------------------------- */
extern DMA_DeviceAttribute_t DMA_gDeviceAttribute[DMA_NUM_DEVICE_ENTRIES];
/* ---- Function Prototypes ---------------------------------------------- */
#if defined(__KERNEL__)
/****************************************************************************/
/**
* Initializes the DMA module.
*
* @return
* 0 - Success
* < 0 - Error
*/
/****************************************************************************/
int dma_init(void);
#if (DMA_DEBUG_TRACK_RESERVATION)
DMA_Handle_t dma_request_channel_dbg(DMA_Device_t dev, const char *fileName,
int lineNum);
#define dma_request_channel(dev) dma_request_channel_dbg(dev, __FILE__, __LINE__)
#else
/****************************************************************************/
/**
* Reserves a channel for use with @a dev. If the device is setup to use
* a shared channel, then this function will block until a free channel
* becomes available.
*
* @return
* >= 0 - A valid DMA Handle.
* -EBUSY - Device is currently being used.
* -ENODEV - Device handed in is invalid.
*/
/****************************************************************************/
DMA_Handle_t dma_request_channel(DMA_Device_t dev /* Device to use with the allocated channel. */
);
#endif
/****************************************************************************/
/**
* Frees a previously allocated DMA Handle.
*
* @return
* 0 - DMA Handle was released successfully.
* -EINVAL - Invalid DMA handle
*/
/****************************************************************************/
int dma_free_channel(DMA_Handle_t channel /* DMA handle. */
);
/****************************************************************************/
/**
* Determines if a given device has been configured as using a shared
* channel.
*
* @return boolean
* 0 Device uses a dedicated channel
* non-zero Device uses a shared channel
*/
/****************************************************************************/
int dma_device_is_channel_shared(DMA_Device_t dev /* Device to check. */
);
/****************************************************************************/
/**
* Allocates memory to hold a descriptor ring. The descriptor ring then
* needs to be populated by making one or more calls to
* dna_add_descriptors.
*
* The returned descriptor ring will be automatically initialized.
*
* @return
* 0 Descriptor ring was allocated successfully
* -ENOMEM Unable to allocate memory for the desired number of descriptors.
*/
/****************************************************************************/
int dma_alloc_descriptor_ring(DMA_DescriptorRing_t *ring, /* Descriptor ring to populate */
int numDescriptors /* Number of descriptors that need to be allocated. */
);
/****************************************************************************/
/**
* Releases the memory which was previously allocated for a descriptor ring.
*/
/****************************************************************************/
void dma_free_descriptor_ring(DMA_DescriptorRing_t *ring /* Descriptor to release */
);
/****************************************************************************/
/**
* Initializes a descriptor ring, so that descriptors can be added to it.
* Once a descriptor ring has been allocated, it may be reinitialized for
* use with additional/different regions of memory.
*
* Note that if 7 descriptors are allocated, it's perfectly acceptable to
* initialize the ring with a smaller number of descriptors. The amount
* of memory allocated for the descriptor ring will not be reduced, and
* the descriptor ring may be reinitialized later
*
* @return
* 0 Descriptor ring was initialized successfully
* -ENOMEM The descriptor which was passed in has insufficient space
* to hold the desired number of descriptors.
*/
/****************************************************************************/
int dma_init_descriptor_ring(DMA_DescriptorRing_t *ring, /* Descriptor ring to initialize */
int numDescriptors /* Number of descriptors to initialize. */
);
/****************************************************************************/
/**
* Determines the number of descriptors which would be required for a
* transfer of the indicated memory region.
*
* This function also needs to know which DMA device this transfer will
* be destined for, so that the appropriate DMA configuration can be retrieved.
* DMA parameters such as transfer width, and whether this is a memory-to-memory
* or memory-to-peripheral, etc can all affect the actual number of descriptors
* required.
*
* @return
* > 0 Returns the number of descriptors required for the indicated transfer
* -EINVAL Invalid device type for this kind of transfer
* (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
* -ENOMEM Memory exhausted
*/
/****************************************************************************/
int dma_calculate_descriptor_count(DMA_Device_t device, /* DMA Device that this will be associated with */
dma_addr_t srcData, /* Place to get data to write to device */
dma_addr_t dstData, /* Pointer to device data address */
size_t numBytes /* Number of bytes to transfer to the device */
);
/****************************************************************************/
/**
* Adds a region of memory to the descriptor ring. Note that it may take
* multiple descriptors for each region of memory. It is the callers
* responsibility to allocate a sufficiently large descriptor ring.
*
* @return
* 0 Descriptors were added successfully
* -EINVAL Invalid device type for this kind of transfer
* (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
* -ENOMEM Memory exhausted
*/
/****************************************************************************/
int dma_add_descriptors(DMA_DescriptorRing_t *ring, /* Descriptor ring to add descriptors to */
DMA_Device_t device, /* DMA Device that descriptors are for */
dma_addr_t srcData, /* Place to get data (memory or device) */
dma_addr_t dstData, /* Place to put data (memory or device) */
size_t numBytes /* Number of bytes to transfer to the device */
);
/****************************************************************************/
/**
* Sets the descriptor ring associated with a device.
*
* Once set, the descriptor ring will be associated with the device, even
* across channel request/free calls. Passing in a NULL descriptor ring
* will release any descriptor ring currently associated with the device.
*
* Note: If you call dma_transfer, or one of the other dma_alloc_ functions
* the descriptor ring may be released and reallocated.
*
* Note: This function will release the descriptor memory for any current
* descriptor ring associated with this device.
*/
/****************************************************************************/
int dma_set_device_descriptor_ring(DMA_Device_t device, /* Device to update the descriptor ring for. */
DMA_DescriptorRing_t *ring /* Descriptor ring to add descriptors to */
);
/****************************************************************************/
/**
* Retrieves the descriptor ring associated with a device.
*/
/****************************************************************************/
int dma_get_device_descriptor_ring(DMA_Device_t device, /* Device to retrieve the descriptor ring for. */
DMA_DescriptorRing_t *ring /* Place to store retrieved ring */
);
/****************************************************************************/
/**
* Allocates buffers for the descriptors. This is normally done automatically
* but needs to be done explicitly when initiating a dma from interrupt
* context.
*
* @return
* 0 Descriptors were allocated successfully
* -EINVAL Invalid device type for this kind of transfer
* (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
* -ENOMEM Memory exhausted
*/
/****************************************************************************/
int dma_alloc_descriptors(DMA_Handle_t handle, /* DMA Handle */
dmacHw_TRANSFER_TYPE_e transferType, /* Type of transfer being performed */
dma_addr_t srcData, /* Place to get data to write to device */
dma_addr_t dstData, /* Pointer to device data address */
size_t numBytes /* Number of bytes to transfer to the device */
);
/****************************************************************************/
/**
* Allocates and sets up descriptors for a double buffered circular buffer.
*
* This is primarily intended to be used for things like the ingress samples
* from a microphone.
*
* @return
* > 0 Number of descriptors actually allocated.
* -EINVAL Invalid device type for this kind of transfer
* (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
* -ENOMEM Memory exhausted
*/
/****************************************************************************/
int dma_alloc_double_dst_descriptors(DMA_Handle_t handle, /* DMA Handle */
dma_addr_t srcData, /* Physical address of source data */
dma_addr_t dstData1, /* Physical address of first destination buffer */
dma_addr_t dstData2, /* Physical address of second destination buffer */
size_t numBytes /* Number of bytes in each destination buffer */
);
/****************************************************************************/
/**
* Initiates a transfer when the descriptors have already been setup.
*
* This is a special case, and normally, the dma_transfer_xxx functions should
* be used.
*
* @return
* 0 Transfer was started successfully
* -ENODEV Invalid handle
*/
/****************************************************************************/
int dma_start_transfer(DMA_Handle_t handle);
/****************************************************************************/
/**
* Stops a previously started DMA transfer.
*
* @return
* 0 Transfer was stopped successfully
* -ENODEV Invalid handle
*/
/****************************************************************************/
int dma_stop_transfer(DMA_Handle_t handle);
/****************************************************************************/
/**
* Waits for a DMA to complete by polling. This function is only intended
* to be used for testing. Interrupts should be used for most DMA operations.
*/
/****************************************************************************/
int dma_wait_transfer_done(DMA_Handle_t handle);
/****************************************************************************/
/**
* Initiates a DMA transfer
*
* @return
* 0 Transfer was started successfully
* -EINVAL Invalid device type for this kind of transfer
* (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
*/
/****************************************************************************/
int dma_transfer(DMA_Handle_t handle, /* DMA Handle */
dmacHw_TRANSFER_TYPE_e transferType, /* Type of transfer being performed */
dma_addr_t srcData, /* Place to get data to write to device */
dma_addr_t dstData, /* Pointer to device data address */
size_t numBytes /* Number of bytes to transfer to the device */
);
/****************************************************************************/
/**
* Initiates a transfer from memory to a device.
*
* @return
* 0 Transfer was started successfully
* -EINVAL Invalid device type for this kind of transfer
* (i.e. the device is _DEV_TO_MEM and not _MEM_TO_DEV)
*/
/****************************************************************************/
static inline int dma_transfer_to_device(DMA_Handle_t handle, /* DMA Handle */
dma_addr_t srcData, /* Place to get data to write to device (physical address) */
dma_addr_t dstData, /* Pointer to device data address (physical address) */
size_t numBytes /* Number of bytes to transfer to the device */
) {
return dma_transfer(handle,
dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
srcData, dstData, numBytes);
}
/****************************************************************************/
/**
* Initiates a transfer from a device to memory.
*
* @return
* 0 Transfer was started successfully
* -EINVAL Invalid device type for this kind of transfer
* (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
*/
/****************************************************************************/
static inline int dma_transfer_from_device(DMA_Handle_t handle, /* DMA Handle */
dma_addr_t srcData, /* Pointer to the device data address (physical address) */
dma_addr_t dstData, /* Place to store data retrieved from the device (physical address) */
size_t numBytes /* Number of bytes to retrieve from the device */
) {
return dma_transfer(handle,
dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
srcData, dstData, numBytes);
}
/****************************************************************************/
/**
* Initiates a memory to memory transfer.
*
* @return
* 0 Transfer was started successfully
* -EINVAL Invalid device type for this kind of transfer
* (i.e. the device wasn't DMA_DEVICE_MEM_TO_MEM)
*/
/****************************************************************************/
static inline int dma_transfer_mem_to_mem(DMA_Handle_t handle, /* DMA Handle */
dma_addr_t srcData, /* Place to transfer data from (physical address) */
dma_addr_t dstData, /* Place to transfer data to (physical address) */
size_t numBytes /* Number of bytes to transfer */
) {
return dma_transfer(handle,
dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
srcData, dstData, numBytes);
}
/****************************************************************************/
/**
* Set the callback function which will be called when a transfer completes.
* If a NULL callback function is set, then no callback will occur.
*
* @note @a devHandler will be called from IRQ context.
*
* @return
* 0 - Success
* -ENODEV - Device handed in is invalid.
*/
/****************************************************************************/
int dma_set_device_handler(DMA_Device_t dev, /* Device to set the callback for. */
DMA_DeviceHandler_t devHandler, /* Function to call when the DMA completes */
void *userData /* Pointer which will be passed to devHandler. */
);
#endif
#endif /* ASM_ARM_ARCH_BCMRING_DMA_H */

76
arch/arm/mach-bcmring/include/mach/entry-macro.S
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@ -1,76 +0,0 @@
/*****************************************************************************
* Copyright 2006 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/*
*
* Low-level IRQ helper macros for BCMRing-based platforms
*
*/
#include <mach/irqs.h>
#include <mach/hardware.h>
#include <mach/csp/mm_io.h>
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \base, =(MM_IO_BASE_INTC0)
ldr \irqstat, [\base, #0] @ get status
ldr \irqnr, [\base, #0x10] @ mask with enable register
ands \irqstat, \irqstat, \irqnr
mov \irqnr, #IRQ_INTC0_START
cmp \irqstat, #0
bne 1001f
ldr \base, =(MM_IO_BASE_INTC1)
ldr \irqstat, [\base, #0] @ get status
ldr \irqnr, [\base, #0x10] @ mask with enable register
ands \irqstat, \irqstat, \irqnr
mov \irqnr, #IRQ_INTC1_START
cmp \irqstat, #0
bne 1001f
ldr \base, =(MM_IO_BASE_SINTC)
ldr \irqstat, [\base, #0] @ get status
ldr \irqnr, [\base, #0x10] @ mask with enable register
ands \irqstat, \irqstat, \irqnr
mov \irqnr, #0xffffffff @ code meaning no interrupt bits set
cmp \irqstat, #0
beq 1002f
mov \irqnr, #IRQ_SINTC_START @ something is set, so fixup return value
1001:
movs \tmp, \irqstat, lsl #16
movne \irqstat, \tmp
addeq \irqnr, \irqnr, #16
movs \tmp, \irqstat, lsl #8
movne \irqstat, \tmp
addeq \irqnr, \irqnr, #8
movs \tmp, \irqstat, lsl #4
movne \irqstat, \tmp
addeq \irqnr, \irqnr, #4
movs \tmp, \irqstat, lsl #2
movne \irqstat, \tmp
addeq \irqnr, \irqnr, #2
movs \tmp, \irqstat, lsl #1
addeq \irqnr, \irqnr, #1
orrs \base, \base, #1
1002: @ irqnr will be set to 0xffffffff if no irq bits are set
.endm
.macro get_irqnr_preamble, base, tmp
.endm

57
arch/arm/mach-bcmring/include/mach/hardware.h
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@ -1,57 +0,0 @@
/*
*
* This file contains the hardware definitions of the BCMRing.
*
* Copyright (C) 1999 ARM Limited.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include <asm/sizes.h>
#include <cfg_global.h>
#include <mach/csp/mm_io.h>
/* Hardware addresses of major areas.
* *_START is the physical address
* *_SIZE is the size of the region
* *_BASE is the virtual address
*/
#define RAM_START PHYS_OFFSET
#define RAM_SIZE (CFG_GLOBAL_RAM_SIZE-CFG_GLOBAL_RAM_SIZE_RESERVED)
#define RAM_BASE PAGE_OFFSET
/* Macros to make managing spinlocks a bit more controlled in terms of naming. */
/* See reg_gpio.h, reg_irq.h, arch.c, gpio.c for example usage. */
#if defined(__KERNEL__)
#define HW_DECLARE_SPINLOCK(name) DEFINE_SPINLOCK(bcmring_##name##_reg_lock);
#define HW_EXTERN_SPINLOCK(name) extern spinlock_t bcmring_##name##_reg_lock;
#define HW_IRQ_SAVE(name, val) spin_lock_irqsave(&bcmring_##name##_reg_lock, (val))
#define HW_IRQ_RESTORE(name, val) spin_unlock_irqrestore(&bcmring_##name##_reg_lock, (val))
#else
#define HW_DECLARE_SPINLOCK(name)
#define HW_EXTERN_SPINLOCK(name)
#define HW_IRQ_SAVE(name, val) {(void)(name); (void)(val); }
#define HW_IRQ_RESTORE(name, val) {(void)(name); (void)(val); }
#endif
#ifndef HW_IO_PHYS_TO_VIRT
#define HW_IO_PHYS_TO_VIRT MM_IO_PHYS_TO_VIRT
#endif
#define HW_IO_VIRT_TO_PHYS MM_IO_VIRT_TO_PHYS
#endif

132
arch/arm/mach-bcmring/include/mach/irqs.h
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@ -1,132 +0,0 @@
/*
* Copyright (C) 2007 Broadcom
* Copyright (C) 1999 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#if !defined(ARCH_BCMRING_IRQS_H)
#define ARCH_BCMRING_IRQS_H
/* INTC0 - interrupt controller 0 */
#define IRQ_INTC0_START 0
#define IRQ_DMA0C0 0 /* DMA0 channel 0 interrupt */
#define IRQ_DMA0C1 1 /* DMA0 channel 1 interrupt */
#define IRQ_DMA0C2 2 /* DMA0 channel 2 interrupt */
#define IRQ_DMA0C3 3 /* DMA0 channel 3 interrupt */
#define IRQ_DMA0C4 4 /* DMA0 channel 4 interrupt */
#define IRQ_DMA0C5 5 /* DMA0 channel 5 interrupt */
#define IRQ_DMA0C6 6 /* DMA0 channel 6 interrupt */
#define IRQ_DMA0C7 7 /* DMA0 channel 7 interrupt */
#define IRQ_DMA1C0 8 /* DMA1 channel 0 interrupt */
#define IRQ_DMA1C1 9 /* DMA1 channel 1 interrupt */
#define IRQ_DMA1C2 10 /* DMA1 channel 2 interrupt */
#define IRQ_DMA1C3 11 /* DMA1 channel 3 interrupt */
#define IRQ_DMA1C4 12 /* DMA1 channel 4 interrupt */
#define IRQ_DMA1C5 13 /* DMA1 channel 5 interrupt */
#define IRQ_DMA1C6 14 /* DMA1 channel 6 interrupt */
#define IRQ_DMA1C7 15 /* DMA1 channel 7 interrupt */
#define IRQ_VPM 16 /* Voice process module interrupt */
#define IRQ_USBHD2 17 /* USB host2/device2 interrupt */
#define IRQ_USBH1 18 /* USB1 host interrupt */
#define IRQ_USBD 19 /* USB device interrupt */
#define IRQ_SDIOH0 20 /* SDIO0 host interrupt */
#define IRQ_SDIOH1 21 /* SDIO1 host interrupt */
#define IRQ_TIMER0 22 /* Timer0 interrupt */
#define IRQ_TIMER1 23 /* Timer1 interrupt */
#define IRQ_TIMER2 24 /* Timer2 interrupt */
#define IRQ_TIMER3 25 /* Timer3 interrupt */
#define IRQ_SPIH 26 /* SPI host interrupt */
#define IRQ_ESW 27 /* Ethernet switch interrupt */
#define IRQ_APM 28 /* Audio process module interrupt */
#define IRQ_GE 29 /* Graphic engine interrupt */
#define IRQ_CLCD 30 /* LCD Controller interrupt */
#define IRQ_PIF 31 /* Peripheral interface interrupt */
#define IRQ_INTC0_END 31
/* INTC1 - interrupt controller 1 */
#define IRQ_INTC1_START 32
#define IRQ_GPIO0 32 /* 0 GPIO bit 31//0 combined interrupt */
#define IRQ_GPIO1 33 /* 1 GPIO bit 64//32 combined interrupt */
#define IRQ_I2S0 34 /* 2 I2S0 interrupt */
#define IRQ_I2S1 35 /* 3 I2S1 interrupt */
#define IRQ_I2CH 36 /* 4 I2C host interrupt */
#define IRQ_I2CS 37 /* 5 I2C slave interrupt */
#define IRQ_SPIS 38 /* 6 SPI slave interrupt */
#define IRQ_GPHY 39 /* 7 Gigabit Phy interrupt */
#define IRQ_FLASHC 40 /* 8 Flash controller interrupt */
#define IRQ_COMMTX 41 /* 9 ARM DDC transmit interrupt */
#define IRQ_COMMRX 42 /* 10 ARM DDC receive interrupt */
#define IRQ_PMUIRQ 43 /* 11 ARM performance monitor interrupt */
#define IRQ_UARTB 44 /* 12 UARTB */
#define IRQ_WATCHDOG 45 /* 13 Watchdog timer interrupt */
#define IRQ_UARTA 46 /* 14 UARTA */
#define IRQ_TSC 47 /* 15 Touch screen controller interrupt */
#define IRQ_KEYC 48 /* 16 Key pad controller interrupt */
#define IRQ_DMPU 49 /* 17 DDR2 memory partition interrupt */
#define IRQ_VMPU 50 /* 18 VRAM memory partition interrupt */
#define IRQ_FMPU 51 /* 19 Flash memory parition unit interrupt */
#define IRQ_RNG 52 /* 20 Random number generator interrupt */
#define IRQ_RTC0 53 /* 21 Real time clock periodic interrupt */
#define IRQ_RTC1 54 /* 22 Real time clock one-shot interrupt */
#define IRQ_SPUM 55 /* 23 Secure process module interrupt */
#define IRQ_VDEC 56 /* 24 Hantro video decoder interrupt */
#define IRQ_RTC2 57 /* 25 Real time clock tamper interrupt */
#define IRQ_DDRP 58 /* 26 DDR Panic interrupt */
#define IRQ_INTC1_END 58
/* SINTC secure int controller */
#define IRQ_SINTC_START 59
#define IRQ_SEC_WATCHDOG 59 /* 0 Watchdog timer interrupt */
#define IRQ_SEC_UARTA 60 /* 1 UARTA interrupt */
#define IRQ_SEC_TSC 61 /* 2 Touch screen controller interrupt */
#define IRQ_SEC_KEYC 62 /* 3 Key pad controller interrupt */
#define IRQ_SEC_DMPU 63 /* 4 DDR2 memory partition interrupt */
#define IRQ_SEC_VMPU 64 /* 5 VRAM memory partition interrupt */
#define IRQ_SEC_FMPU 65 /* 6 Flash memory parition unit interrupt */
#define IRQ_SEC_RNG 66 /* 7 Random number generator interrupt */
#define IRQ_SEC_RTC0 67 /* 8 Real time clock periodic interrupt */
#define IRQ_SEC_RTC1 68 /* 9 Real time clock one-shot interrupt */
#define IRQ_SEC_SPUM 69 /* 10 Secure process module interrupt */
#define IRQ_SEC_TIMER0 70 /* 11 Secure timer0 interrupt */
#define IRQ_SEC_TIMER1 71 /* 12 Secure timer1 interrupt */
#define IRQ_SEC_TIMER2 72 /* 13 Secure timer2 interrupt */
#define IRQ_SEC_TIMER3 73 /* 14 Secure timer3 interrupt */
#define IRQ_SEC_RTC2 74 /* 15 Real time clock tamper interrupt */
#define IRQ_SINTC_END 74
/* Note: there are 3 INTC registers of 32 bits each. So internal IRQs could go from 0-95 */
/* Since IRQs are typically viewed in decimal, we start the gpio based IRQs off at 100 */
/* to make the mapping easy for humans to decipher. */
#define IRQ_GPIO_0 100
#define NUM_INTERNAL_IRQS (IRQ_SINTC_END+1)
/* I couldn't get the gpioHw_reg.h file to be included cleanly, so I hardcoded it */
/* define NUM_GPIO_IRQS GPIOHW_TOTAL_NUM_PINS */
#define NUM_GPIO_IRQS 62
#define NR_IRQS (IRQ_GPIO_0 + NUM_GPIO_IRQS)
#define IRQ_UNKNOWN -1
/* Tune these bits to preclude noisy or unsupported interrupt sources as required. */
#define IRQ_INTC0_VALID_MASK 0xffffffff
#define IRQ_INTC1_VALID_MASK 0x07ffffff
#define IRQ_SINTC_VALID_MASK 0x0000ffff
#endif /* ARCH_BCMRING_IRQS_H */

67
arch/arm/mach-bcmring/include/mach/memory_settings.h
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@ -1,67 +0,0 @@
/*****************************************************************************
* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
#ifndef MEMORY_SETTINGS_H
#define MEMORY_SETTINGS_H
/* ---- Include Files ---------------------------------------- */
/* ---- Constants and Types ---------------------------------- */
/* Memory devices */
/* NAND Flash timing for 166 MHz setting */
#define HW_CFG_NAND_tBTA (5 << 16) /* Bus turnaround cycle (n) 0-7 (30 ns) */
#define HW_CFG_NAND_tWP (4 << 11) /* Write pulse width cycle (n+1) 0-31 (25 ns) */
#define HW_CFG_NAND_tWR (1 << 9) /* Write recovery cycle (n+1) 0-3 (10 ns) */
#define HW_CFG_NAND_tAS (0 << 7) /* Write address setup cycle (n+1) 0-3 ( 0 ns) */
#define HW_CFG_NAND_tOE (3 << 5) /* Output enable delay cycle (n) 0-3 (15 ns) */
#define HW_CFG_NAND_tRC (7 << 0) /* Read access cycle (n+2) 0-31 (50 ns) */
#define HW_CFG_NAND_TCR (HW_CFG_NAND_tBTA \
| HW_CFG_NAND_tWP \
| HW_CFG_NAND_tWR \
| HW_CFG_NAND_tAS \
| HW_CFG_NAND_tOE \
| HW_CFG_NAND_tRC)
/* NOR Flash timing for 166 MHz setting */
#define HW_CFG_NOR_TPRC_TWLC (0 << 19) /* Page read access cycle / Burst write latency (n+2 / n+1) (max 25ns) */
#define HW_CFG_NOR_TBTA (0 << 16) /* Bus turnaround cycle (n) (DNA) */
#define HW_CFG_NOR_TWP (6 << 11) /* Write pulse width cycle (n+1) (35ns) */
#define HW_CFG_NOR_TWR (0 << 9) /* Write recovery cycle (n+1) (0ns) */
#define HW_CFG_NOR_TAS (0 << 7) /* Write address setup cycle (n+1) (0ns) */
#define HW_CFG_NOR_TOE (0 << 5) /* Output enable delay cycle (n) (max 25ns) */
#define HW_CFG_NOR_TRC_TLC (0x10 << 0) /* Read access cycle / Burst read latency (n+2 / n+1) (100ns) */
#define HW_CFG_FLASH0_TCR (HW_CFG_NOR_TPRC_TWLC \
| HW_CFG_NOR_TBTA \
| HW_CFG_NOR_TWP \
| HW_CFG_NOR_TWR \
| HW_CFG_NOR_TAS \
| HW_CFG_NOR_TOE \
| HW_CFG_NOR_TRC_TLC)
#define HW_CFG_FLASH1_TCR HW_CFG_FLASH0_TCR
#define HW_CFG_FLASH2_TCR HW_CFG_FLASH0_TCR
/* SDRAM Settings */
/* #define HW_CFG_SDRAM_CAS_LATENCY 5 Default 5, Values [3..6] */
/* #define HW_CFG_SDRAM_CHIP_SELECT_CNT 1 Default 1, Vaules [1..2] */
/* #define HW_CFG_SDRAM_SPEED_GRADE 667 Default 667, Values [400,533,667,800] */
/* #define HW_CFG_SDRAM_WIDTH_BITS 16 Default 16, Vaules [8,16] */
#define HW_CFG_SDRAM_SIZE_BYTES 0x10000000 /* Total memory, not per device size */
/* ---- Variable Externs ------------------------------------- */
/* ---- Function Prototypes ---------------------------------- */
#endif /* MEMORY_SETTINGS_H */

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arch/arm/mach-bcmring/include/mach/reg_nand.h
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/*****************************************************************************
* Copyright 2001 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/*
*
*****************************************************************************
*
* REG_NAND.h
*
* PURPOSE:
*
* This file contains definitions for the nand registers:
*
* NOTES:
*
*****************************************************************************/
#if !defined(__ASM_ARCH_REG_NAND_H)
#define __ASM_ARCH_REG_NAND_H
/* ---- Include Files ---------------------------------------------------- */
#include <csp/reg.h>
#include <mach/reg_umi.h>
/* ---- Constants and Types ---------------------------------------------- */
#define HW_NAND_BASE MM_IO_BASE_NAND /* NAND Flash */
/* DMA accesses by the bootstrap need hard nonvirtual addresses */
#define REG_NAND_CMD __REG16(HW_NAND_BASE + 0)
#define REG_NAND_ADDR __REG16(HW_NAND_BASE + 4)
#define REG_NAND_PHYS_DATA16 (HW_NAND_BASE + 8)
#define REG_NAND_PHYS_DATA8 (HW_NAND_BASE + 8)
#define REG_NAND_DATA16 __REG16(REG_NAND_PHYS_DATA16)
#define REG_NAND_DATA8 __REG8(REG_NAND_PHYS_DATA8)
/* use appropriate offset to make sure it start at the 1K boundary */
#define REG_NAND_PHYS_DATA_DMA (HW_NAND_BASE + 0x400)
#define REG_NAND_DATA_DMA __REG32(REG_NAND_PHYS_DATA_DMA)
/* Linux DMA requires physical address of the data register */
#define REG_NAND_DATA16_PADDR HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA16)
#define REG_NAND_DATA8_PADDR HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA8)
#define REG_NAND_DATA_PADDR HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA_DMA)
#define NAND_BUS_16BIT() (0)
#define NAND_BUS_8BIT() (!NAND_BUS_16BIT())
/* Register offsets */
#define REG_NAND_CMD_OFFSET (0)
#define REG_NAND_ADDR_OFFSET (4)
#define REG_NAND_DATA8_OFFSET (8)
#endif

237
arch/arm/mach-bcmring/include/mach/reg_umi.h
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@ -1,237 +0,0 @@
/*****************************************************************************
* Copyright 2005 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/*
*
*****************************************************************************
*
* REG_UMI.h
*
* PURPOSE:
*
* This file contains definitions for the nand registers:
*
* NOTES:
*
*****************************************************************************/
#if !defined(__ASM_ARCH_REG_UMI_H)
#define __ASM_ARCH_REG_UMI_H
/* ---- Include Files ---------------------------------------------------- */
#include <csp/reg.h>
#include <mach/csp/mm_io.h>
/* ---- Constants and Types ---------------------------------------------- */
/* Unified Memory Interface Ctrl Register */
#define HW_UMI_BASE MM_IO_BASE_UMI
/* Flash bank 0 timing and control register */
#define REG_UMI_FLASH0_TCR __REG32(HW_UMI_BASE + 0x00)
/* Flash bank 1 timing and control register */
#define REG_UMI_FLASH1_TCR __REG32(HW_UMI_BASE + 0x04)
/* Flash bank 2 timing and control register */
#define REG_UMI_FLASH2_TCR __REG32(HW_UMI_BASE + 0x08)
/* MMD interface and control register */
#define REG_UMI_MMD_ICR __REG32(HW_UMI_BASE + 0x0c)
/* NAND timing and control register */
#define REG_UMI_NAND_TCR __REG32(HW_UMI_BASE + 0x18)
/* NAND ready/chip select register */
#define REG_UMI_NAND_RCSR __REG32(HW_UMI_BASE + 0x1c)
/* NAND ECC control & status register */
#define REG_UMI_NAND_ECC_CSR __REG32(HW_UMI_BASE + 0x20)
/* NAND ECC data register XXB2B1B0 */
#define REG_UMI_NAND_ECC_DATA __REG32(HW_UMI_BASE + 0x24)
/* BCH ECC Parameter N */
#define REG_UMI_BCH_N __REG32(HW_UMI_BASE + 0x40)
/* BCH ECC Parameter T */
#define REG_UMI_BCH_K __REG32(HW_UMI_BASE + 0x44)
/* BCH ECC Parameter K */
#define REG_UMI_BCH_T __REG32(HW_UMI_BASE + 0x48)
/* BCH ECC Contro Status */
#define REG_UMI_BCH_CTRL_STATUS __REG32(HW_UMI_BASE + 0x4C)
/* BCH WR ECC 31:0 */
#define REG_UMI_BCH_WR_ECC_0 __REG32(HW_UMI_BASE + 0x50)
/* BCH WR ECC 63:32 */
#define REG_UMI_BCH_WR_ECC_1 __REG32(HW_UMI_BASE + 0x54)
/* BCH WR ECC 95:64 */
#define REG_UMI_BCH_WR_ECC_2 __REG32(HW_UMI_BASE + 0x58)
/* BCH WR ECC 127:96 */
#define REG_UMI_BCH_WR_ECC_3 __REG32(HW_UMI_BASE + 0x5c)
/* BCH WR ECC 155:128 */
#define REG_UMI_BCH_WR_ECC_4 __REG32(HW_UMI_BASE + 0x60)
/* BCH Read Error Location 1,0 */
#define REG_UMI_BCH_RD_ERR_LOC_1_0 __REG32(HW_UMI_BASE + 0x64)
/* BCH Read Error Location 3,2 */
#define REG_UMI_BCH_RD_ERR_LOC_3_2 __REG32(HW_UMI_BASE + 0x68)
/* BCH Read Error Location 5,4 */
#define REG_UMI_BCH_RD_ERR_LOC_5_4 __REG32(HW_UMI_BASE + 0x6c)
/* BCH Read Error Location 7,6 */
#define REG_UMI_BCH_RD_ERR_LOC_7_6 __REG32(HW_UMI_BASE + 0x70)
/* BCH Read Error Location 9,8 */
#define REG_UMI_BCH_RD_ERR_LOC_9_8 __REG32(HW_UMI_BASE + 0x74)
/* BCH Read Error Location 11,10 */
#define REG_UMI_BCH_RD_ERR_LOC_B_A __REG32(HW_UMI_BASE + 0x78)
/* REG_UMI_FLASH0/1/2_TCR, REG_UMI_SRAM0/1_TCR bits */
/* Enable wait pin during burst write or read */
#define REG_UMI_TCR_WAITEN 0x80000000
/* Enable mem ctrlr to work with ext mem of lower freq than AHB clk */
#define REG_UMI_TCR_LOWFREQ 0x40000000
/* 1=synch write, 0=async write */
#define REG_UMI_TCR_MEMTYPE_SYNCWRITE 0x20000000
/* 1=synch read, 0=async read */
#define REG_UMI_TCR_MEMTYPE_SYNCREAD 0x10000000
/* 1=page mode read, 0=normal mode read */
#define REG_UMI_TCR_MEMTYPE_PAGEREAD 0x08000000
/* page size/burst size (wrap only) */
#define REG_UMI_TCR_MEMTYPE_PGSZ_MASK 0x07000000
/* 4 word */
#define REG_UMI_TCR_MEMTYPE_PGSZ_4 0x00000000
/* 8 word */
#define REG_UMI_TCR_MEMTYPE_PGSZ_8 0x01000000
/* 16 word */
#define REG_UMI_TCR_MEMTYPE_PGSZ_16 0x02000000
/* 32 word */
#define REG_UMI_TCR_MEMTYPE_PGSZ_32 0x03000000
/* 64 word */
#define REG_UMI_TCR_MEMTYPE_PGSZ_64 0x04000000
/* 128 word */
#define REG_UMI_TCR_MEMTYPE_PGSZ_128 0x05000000
/* 256 word */
#define REG_UMI_TCR_MEMTYPE_PGSZ_256 0x06000000
/* 512 word */
#define REG_UMI_TCR_MEMTYPE_PGSZ_512 0x07000000
/* Page read access cycle / Burst write latency (n+2 / n+1) */
#define REG_UMI_TCR_TPRC_TWLC_MASK 0x00f80000
/* Bus turnaround cycle (n) */
#define REG_UMI_TCR_TBTA_MASK 0x00070000
/* Write pulse width cycle (n+1) */
#define REG_UMI_TCR_TWP_MASK 0x0000f800
/* Write recovery cycle (n+1) */
#define REG_UMI_TCR_TWR_MASK 0x00000600
/* Write address setup cycle (n+1) */
#define REG_UMI_TCR_TAS_MASK 0x00000180
/* Output enable delay cycle (n) */
#define REG_UMI_TCR_TOE_MASK 0x00000060
/* Read access cycle / Burst read latency (n+2 / n+1) */
#define REG_UMI_TCR_TRC_TLC_MASK 0x0000001f
/* REG_UMI_MMD_ICR bits */
/* Flash write protection pin control */
#define REG_UMI_MMD_ICR_FLASH_WP 0x8000
/* Extend hold time for sram0, sram1 csn (39 MHz operation) */
#define REG_UMI_MMD_ICR_XHCS 0x4000
/* Enable SDRAM 2 interface control */
#define REG_UMI_MMD_ICR_SDRAM2EN 0x2000
/* Enable merge of flash banks 0/1 to 512 MBit bank */
#define REG_UMI_MMD_ICR_INST512 0x1000
/* Enable merge of flash banks 1/2 to 512 MBit bank */
#define REG_UMI_MMD_ICR_DATA512 0x0800
/* Enable SDRAM interface control */
#define REG_UMI_MMD_ICR_SDRAMEN 0x0400
/* Polarity of busy state of Burst Wait Signal */
#define REG_UMI_MMD_ICR_WAITPOL 0x0200
/* Enable burst clock stopped when not accessing external burst flash/sram */
#define REG_UMI_MMD_ICR_BCLKSTOP 0x0100
/* Enable the peri1_csn to replace flash1_csn in 512 Mb flash mode */
#define REG_UMI_MMD_ICR_PERI1EN 0x0080
/* Enable the peri2_csn to replace sdram_csn */
#define REG_UMI_MMD_ICR_PERI2EN 0x0040
/* Enable the peri3_csn to replace sdram2_csn */
#define REG_UMI_MMD_ICR_PERI3EN 0x0020
/* Enable sram bank1 for H/W controlled MRS */
#define REG_UMI_MMD_ICR_MRSB1 0x0010
/* Enable sram bank0 for H/W controlled MRS */
#define REG_UMI_MMD_ICR_MRSB0 0x0008
/* Polarity for assert3ed state of H/W controlled MRS */
#define REG_UMI_MMD_ICR_MRSPOL 0x0004
/* 0: S/W controllable ZZ/MRS/CRE/P-Mode pin */
/* 1: H/W controlled ZZ/MRS/CRE/P-Mode, same timing as CS */
#define REG_UMI_MMD_ICR_MRSMODE 0x0002
/* MRS state for S/W controlled mode */
#define REG_UMI_MMD_ICR_MRSSTATE 0x0001
/* REG_UMI_NAND_TCR bits */
/* Enable software to control CS */
#define REG_UMI_NAND_TCR_CS_SWCTRL 0x80000000
/* 16-bit nand wordsize if set */
#define REG_UMI_NAND_TCR_WORD16 0x40000000
/* Bus turnaround cycle (n) */
#define REG_UMI_NAND_TCR_TBTA_MASK 0x00070000
/* Write pulse width cycle (n+1) */
#define REG_UMI_NAND_TCR_TWP_MASK 0x0000f800
/* Write recovery cycle (n+1) */
#define REG_UMI_NAND_TCR_TWR_MASK 0x00000600
/* Write address setup cycle (n+1) */
#define REG_UMI_NAND_TCR_TAS_MASK 0x00000180
/* Output enable delay cycle (n) */
#define REG_UMI_NAND_TCR_TOE_MASK 0x00000060
/* Read access cycle (n+2) */
#define REG_UMI_NAND_TCR_TRC_TLC_MASK 0x0000001f
/* REG_UMI_NAND_RCSR bits */
/* Status: Ready=1, Busy=0 */
#define REG_UMI_NAND_RCSR_RDY 0x02
/* Keep CS asserted during operation */
#define REG_UMI_NAND_RCSR_CS_ASSERTED 0x01
/* REG_UMI_NAND_ECC_CSR bits */
/* Interrupt status - read-only */
#define REG_UMI_NAND_ECC_CSR_NANDINT 0x80000000
/* Read: Status of ECC done, Write: clear ECC interrupt */
#define REG_UMI_NAND_ECC_CSR_ECCINT_RAW 0x00800000
/* Read: Status of R/B, Write: clear R/B interrupt */
#define REG_UMI_NAND_ECC_CSR_RBINT_RAW 0x00400000
/* 1 = Enable ECC Interrupt */
#define REG_UMI_NAND_ECC_CSR_ECCINT_ENABLE 0x00008000
/* 1 = Assert interrupt at rising edge of R/B_ */
#define REG_UMI_NAND_ECC_CSR_RBINT_ENABLE 0x00004000
/* Calculate ECC by 0=512 bytes, 1=256 bytes */
#define REG_UMI_NAND_ECC_CSR_256BYTE 0x00000080
/* Enable ECC in hardware */
#define REG_UMI_NAND_ECC_CSR_ECC_ENABLE 0x00000001
/* REG_UMI_BCH_CTRL_STATUS bits */
/* Shift to Indicate Number of correctable errors detected */
#define REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR_SHIFT 20
/* Indicate Number of correctable errors detected */
#define REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR 0x00F00000
/* Indicate Errors detected during read but uncorrectable */
#define REG_UMI_BCH_CTRL_STATUS_UNCORR_ERR 0x00080000
/* Indicate Errors detected during read and are correctable */
#define REG_UMI_BCH_CTRL_STATUS_CORR_ERR 0x00040000
/* Flag indicates BCH's ECC status of read process are valid */
#define REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID 0x00020000
/* Flag indicates BCH's ECC status of write process are valid */
#define REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID 0x00010000
/* Pause ECC calculation */
#define REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC 0x00000010
/* Enable Interrupt */
#define REG_UMI_BCH_CTRL_STATUS_INT_EN 0x00000004
/* Enable ECC during read */
#define REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN 0x00000002
/* Enable ECC during write */
#define REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN 0x00000001
/* Mask for location */
#define REG_UMI_BCH_ERR_LOC_MASK 0x00001FFF
/* location within a byte */
#define REG_UMI_BCH_ERR_LOC_BYTE 0x00000007
/* location within a word */
#define REG_UMI_BCH_ERR_LOC_WORD 0x00000018
/* location within a page (512 byte) */
#define REG_UMI_BCH_ERR_LOC_PAGE 0x00001FE0
#define REG_UMI_BCH_ERR_LOC_ADDR(index) (__REG32(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16))
#endif

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arch/arm/mach-bcmring/include/mach/timer.h
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@ -1,77 +0,0 @@
/*****************************************************************************
* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
/*
*
*****************************************************************************
*
* timer.h
*
* PURPOSE:
*
*
*
* NOTES:
*
*****************************************************************************/
#if !defined(BCM_LINUX_TIMER_H)
#define BCM_LINUX_TIMER_H
#if defined(__KERNEL__)
/* ---- Include Files ---------------------------------------------------- */
/* ---- Constants and Types ---------------------------------------------- */
typedef unsigned int timer_tick_count_t;
typedef unsigned int timer_tick_rate_t;
typedef unsigned int timer_msec_t;
/* ---- Variable Externs ------------------------------------------------- */
/* ---- Function Prototypes ---------------------------------------------- */
/****************************************************************************
*
* timer_get_tick_count
*
*
***************************************************************************/
timer_tick_count_t timer_get_tick_count(void);
/****************************************************************************
*
* timer_get_tick_rate
*
*
***************************************************************************/
timer_tick_rate_t timer_get_tick_rate(void);
/****************************************************************************
*
* timer_get_msec
*
*
***************************************************************************/
timer_msec_t timer_get_msec(void);
/****************************************************************************
*
* timer_ticks_to_msec
*
*
***************************************************************************/
timer_msec_t timer_ticks_to_msec(timer_tick_count_t ticks);
#endif /* __KERNEL__ */
#endif /* BCM_LINUX_TIMER_H */

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arch/arm/mach-bcmring/include/mach/timex.h
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@ -1,25 +0,0 @@
/*
*
* Integrator architecture timex specifications
*
* Copyright (C) 1999 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/*
* Specifies the number of ticks per second
*/
#define CLOCK_TICK_RATE 100000 /* REG_SMT_TICKS_PER_SEC */

43
arch/arm/mach-bcmring/include/mach/uncompress.h
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@ -1,43 +0,0 @@
/*****************************************************************************
* Copyright 2005 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
#include <mach/csp/mm_addr.h>
#define BCMRING_UART_0_DR (*(volatile unsigned int *)MM_ADDR_IO_UARTA)
#define BCMRING_UART_0_FR (*(volatile unsigned int *)(MM_ADDR_IO_UARTA + 0x18))
/*
* This does not append a newline
*/
static inline void putc(int c)
{
/* Send out UARTA */
while (BCMRING_UART_0_FR & (1 << 5))
;
BCMRING_UART_0_DR = c;
}
static inline void flush(void)
{
/* Wait for the tx fifo to be empty */
while ((BCMRING_UART_0_FR & (1 << 7)) == 0)
;
/* Wait for the final character to be sent on the txd line */
while (BCMRING_UART_0_FR & (1 << 3))
;
}
#define arch_decomp_setup()
#define arch_decomp_wdog()

126
arch/arm/mach-bcmring/irq.c
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@ -1,126 +0,0 @@
/*
*
* Copyright (C) 1999 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/init.h>
#include <linux/stddef.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach/irq.h>
#include <mach/csp/intcHw_reg.h>
#include <mach/csp/mm_io.h>
static void bcmring_mask_irq0(struct irq_data *d)
{
writel(1 << (d->irq - IRQ_INTC0_START),
MM_IO_BASE_INTC0 + INTCHW_INTENCLEAR);
}
static void bcmring_unmask_irq0(struct irq_data *d)
{
writel(1 << (d->irq - IRQ_INTC0_START),
MM_IO_BASE_INTC0 + INTCHW_INTENABLE);
}
static void bcmring_mask_irq1(struct irq_data *d)
{
writel(1 << (d->irq - IRQ_INTC1_START),
MM_IO_BASE_INTC1 + INTCHW_INTENCLEAR);
}
static void bcmring_unmask_irq1(struct irq_data *d)
{
writel(1 << (d->irq - IRQ_INTC1_START),
MM_IO_BASE_INTC1 + INTCHW_INTENABLE);
}
static void bcmring_mask_irq2(struct irq_data *d)
{
writel(1 << (d->irq - IRQ_SINTC_START),
MM_IO_BASE_SINTC + INTCHW_INTENCLEAR);
}
static void bcmring_unmask_irq2(struct irq_data *d)
{
writel(1 << (d->irq - IRQ_SINTC_START),
MM_IO_BASE_SINTC + INTCHW_INTENABLE);
}
static struct irq_chip bcmring_irq0_chip = {
.name = "ARM-INTC0",
.irq_ack = bcmring_mask_irq0,
.irq_mask = bcmring_mask_irq0, /* mask a specific interrupt, blocking its delivery. */
.irq_unmask = bcmring_unmask_irq0, /* unmaks an interrupt */
};
static struct irq_chip bcmring_irq1_chip = {
.name = "ARM-INTC1",
.irq_ack = bcmring_mask_irq1,
.irq_mask = bcmring_mask_irq1,
.irq_unmask = bcmring_unmask_irq1,
};
static struct irq_chip bcmring_irq2_chip = {
.name = "ARM-SINTC",
.irq_ack = bcmring_mask_irq2,
.irq_mask = bcmring_mask_irq2,
.irq_unmask = bcmring_unmask_irq2,
};
static void vic_init(void __iomem *base, struct irq_chip *chip,
unsigned int irq_start, unsigned int vic_sources)
{
unsigned int i;
for (i = 0; i < 32; i++) {
unsigned int irq = irq_start + i;
irq_set_chip(irq, chip);
irq_set_chip_data(irq, base);
if (vic_sources & (1 << i)) {
irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
}
writel(0, base + INTCHW_INTSELECT);
writel(0, base + INTCHW_INTENABLE);
writel(~0, base + INTCHW_INTENCLEAR);
writel(0, base + INTCHW_IRQSTATUS);
writel(~0, base + INTCHW_SOFTINTCLEAR);
}
void __init bcmring_init_irq(void)
{
vic_init((void __iomem *)MM_IO_BASE_INTC0, &bcmring_irq0_chip,
IRQ_INTC0_START, IRQ_INTC0_VALID_MASK);
vic_init((void __iomem *)MM_IO_BASE_INTC1, &bcmring_irq1_chip,
IRQ_INTC1_START, IRQ_INTC1_VALID_MASK);
vic_init((void __iomem *)MM_IO_BASE_SINTC, &bcmring_irq2_chip,
IRQ_SINTC_START, IRQ_SINTC_VALID_MASK);
/* special cases */
if (INTCHW_INTC1_GPIO0 & IRQ_INTC1_VALID_MASK) {
irq_set_handler(IRQ_GPIO0, handle_simple_irq);
}
if (INTCHW_INTC1_GPIO1 & IRQ_INTC1_VALID_MASK) {
irq_set_handler(IRQ_GPIO1, handle_simple_irq);
}
}

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arch/arm/mach-bcmring/mm.c
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@ -1,60 +0,0 @@
/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <asm/page.h>
#include <asm/mach/map.h>
#include <mach/hardware.h>
#include <mach/csp/mm_io.h>
#define IO_DESC(va, sz) { .virtual = va, \
.pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
.length = sz, \
.type = MT_DEVICE }
#define MEM_DESC(va, sz) { .virtual = va, \
.pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
.length = sz, \
.type = MT_MEMORY }
static struct map_desc bcmring_io_desc[] __initdata = {
IO_DESC(MM_IO_BASE_NAND, SZ_64K), /* phys:0x28000000-0x28000FFF virt:0xE8000000-0xE8000FFF size:0x00010000 */
IO_DESC(MM_IO_BASE_UMI, SZ_64K), /* phys:0x2C000000-0x2C000FFF virt:0xEC000000-0xEC000FFF size:0x00010000 */
IO_DESC(MM_IO_BASE_BROM, SZ_64K), /* phys:0x30000000-0x3000FFFF virt:0xF3000000-0xF300FFFF size:0x00010000 */
MEM_DESC(MM_IO_BASE_ARAM, SZ_1M), /* phys:0x31000000-0x31FFFFFF virt:0xF3100000-0xF31FFFFF size:0x01000000 */
IO_DESC(MM_IO_BASE_DMA0, SZ_1M), /* phys:0x32000000-0x32FFFFFF virt:0xF3200000-0xF32FFFFF size:0x01000000 */
IO_DESC(MM_IO_BASE_DMA1, SZ_1M), /* phys:0x33000000-0x33FFFFFF virt:0xF3300000-0xF33FFFFF size:0x01000000 */
IO_DESC(MM_IO_BASE_ESW, SZ_1M), /* phys:0x34000000-0x34FFFFFF virt:0xF3400000-0xF34FFFFF size:0x01000000 */
IO_DESC(MM_IO_BASE_CLCD, SZ_1M), /* phys:0x35000000-0x35FFFFFF virt:0xF3500000-0xF35FFFFF size:0x01000000 */
IO_DESC(MM_IO_BASE_APM, SZ_1M), /* phys:0x36000000-0x36FFFFFF virt:0xF3600000-0xF36FFFFF size:0x01000000 */
IO_DESC(MM_IO_BASE_SPUM, SZ_1M), /* phys:0x37000000-0x37FFFFFF virt:0xF3700000-0xF37FFFFF size:0x01000000 */
IO_DESC(MM_IO_BASE_VPM_PROG, SZ_1M), /* phys:0x38000000-0x38FFFFFF virt:0xF3800000-0xF38FFFFF size:0x01000000 */
IO_DESC(MM_IO_BASE_VPM_DATA, SZ_1M), /* phys:0x3A000000-0x3AFFFFFF virt:0xF3A00000-0xF3AFFFFF size:0x01000000 */
IO_DESC(MM_IO_BASE_VRAM, SZ_64K), /* phys:0x40000000-0x4000FFFF virt:0xF4000000-0xF400FFFF size:0x00010000 */
IO_DESC(MM_IO_BASE_CHIPC, SZ_16M), /* phys:0x80000000-0x80FFFFFF virt:0xF8000000-0xF8FFFFFF size:0x01000000 */
IO_DESC(MM_IO_BASE_VPM_EXTMEM_RSVD,
SZ_16M), /* phys:0x0F000000-0x0FFFFFFF virt:0xF0000000-0xF0FFFFFF size:0x01000000 */
};
void __init bcmring_map_io(void)
{
iotable_init(bcmring_io_desc, ARRAY_SIZE(bcmring_io_desc));
/* Maximum DMA memory allowed is 14M */
init_consistent_dma_size(14 << 20);
}

61
arch/arm/mach-bcmring/timer.c
View file

@ -1,61 +0,0 @@
/*****************************************************************************
* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2, available at
* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a
* license other than the GPL, without Broadcom's express prior written
* consent.
*****************************************************************************/
#include <linux/types.h>
#include <linux/module.h>
#include <csp/tmrHw.h>
#include <mach/timer.h>
/* The core.c file initializes timers 1 and 3 as a linux clocksource. */
/* The real time clock should probably be the real linux clocksource. */
/* In the meantime, this file should agree with core.c as to the */
/* profiling timer. If the clocksource is moved to rtc later, then */
/* we can init the profiling timer here instead. */
/* Timer 1 provides 25MHz resolution syncrhonized to scheduling and APM timing */
/* Timer 3 provides bus freqeuncy sychronized to ACLK, but spread spectrum will */
/* affect synchronization with scheduling and APM timing. */
#define PROF_TIMER 1
timer_tick_rate_t timer_get_tick_rate(void)
{
return tmrHw_getCountRate(PROF_TIMER);
}
timer_tick_count_t timer_get_tick_count(void)
{
return tmrHw_GetCurrentCount(PROF_TIMER); /* change downcounter to upcounter */
}
timer_msec_t timer_ticks_to_msec(timer_tick_count_t ticks)
{
static int tickRateMsec;
if (tickRateMsec == 0) {
tickRateMsec = timer_get_tick_rate() / 1000;
}
return ticks / tickRateMsec;
}
timer_msec_t timer_get_msec(void)
{
return timer_ticks_to_msec(timer_get_tick_count());
}
EXPORT_SYMBOL(timer_get_tick_count);
EXPORT_SYMBOL(timer_ticks_to_msec);
EXPORT_SYMBOL(timer_get_tick_rate);
EXPORT_SYMBOL(timer_get_msec);

12
drivers/mtd/nand/bcm_umi_nand.c
View file

@ -249,20 +249,20 @@ static int nand_dev_ready(struct mtd_info *mtd)
int bcm_umi_nand_inithw(void)
{
/* Configure nand timing parameters */
REG_UMI_NAND_TCR &= ~0x7ffff;
REG_UMI_NAND_TCR |= HW_CFG_NAND_TCR;
writel(readl(&REG_UMI_NAND_TCR) & ~0x7ffff, &REG_UMI_NAND_TCR);
writel(readl(&REG_UMI_NAND_TCR) | HW_CFG_NAND_TCR, &REG_UMI_NAND_TCR);
#if !defined(CONFIG_MTD_NAND_BCM_UMI_HWCS)
/* enable software control of CS */
REG_UMI_NAND_TCR |= REG_UMI_NAND_TCR_CS_SWCTRL;
writel(readl(&REG_UMI_NAND_TCR) | REG_UMI_NAND_TCR_CS_SWCTRL, &REG_UMI_NAND_TCR);
#endif
/* keep NAND chip select asserted */
REG_UMI_NAND_RCSR |= REG_UMI_NAND_RCSR_CS_ASSERTED;
writel(readl(&REG_UMI_NAND_RCSR) | REG_UMI_NAND_RCSR_CS_ASSERTED, &REG_UMI_NAND_RCSR);
REG_UMI_NAND_TCR &= ~REG_UMI_NAND_TCR_WORD16;
writel(readl(&REG_UMI_NAND_TCR) & ~REG_UMI_NAND_TCR_WORD16, &REG_UMI_NAND_TCR);
/* enable writes to flash */
REG_UMI_MMD_ICR |= REG_UMI_MMD_ICR_FLASH_WP;
writel(readl(&REG_UMI_MMD_ICR) | REG_UMI_MMD_ICR_FLASH_WP, &REG_UMI_MMD_ICR);
writel(NAND_CMD_RESET, bcm_umi_io_base + REG_NAND_CMD_OFFSET);
nand_bcm_umi_wait_till_ready();

73
drivers/mtd/nand/nand_bcm_umi.h
View file

@ -17,7 +17,7 @@
/* ---- Include Files ---------------------------------------------------- */
#include <mach/reg_umi.h>
#include <mach/reg_nand.h>
#include <cfg_global.h>
#include <mach/cfg_global.h>
/* ---- Constants and Types ---------------------------------------------- */
#if (CFG_GLOBAL_CHIP_FAMILY == CFG_GLOBAL_CHIP_FAMILY_BCMRING)
@ -48,7 +48,7 @@ int nand_bcm_umi_bch_correct_page(uint8_t *datap, uint8_t *readEccData,
/* Check in device is ready */
static inline int nand_bcm_umi_dev_ready(void)
{
return REG_UMI_NAND_RCSR & REG_UMI_NAND_RCSR_RDY;
return readl(&REG_UMI_NAND_RCSR) & REG_UMI_NAND_RCSR_RDY;
}
/* Wait until device is ready */
@ -62,10 +62,11 @@ static inline void nand_bcm_umi_wait_till_ready(void)
static inline void nand_bcm_umi_hamming_enable_hwecc(void)
{
/* disable and reset ECC, 512 byte page */
REG_UMI_NAND_ECC_CSR &= ~(REG_UMI_NAND_ECC_CSR_ECC_ENABLE |
REG_UMI_NAND_ECC_CSR_256BYTE);
writel(readl(&REG_UMI_NAND_ECC_CSR) & ~(REG_UMI_NAND_ECC_CSR_ECC_ENABLE |
REG_UMI_NAND_ECC_CSR_256BYTE), &REG_UMI_NAND_ECC_CSR);
/* enable ECC */
REG_UMI_NAND_ECC_CSR |= REG_UMI_NAND_ECC_CSR_ECC_ENABLE;
writel(readl(&REG_UMI_NAND_ECC_CSR) | REG_UMI_NAND_ECC_CSR_ECC_ENABLE,
&REG_UMI_NAND_ECC_CSR);
}
#if NAND_ECC_BCH
@ -76,18 +77,18 @@ static inline void nand_bcm_umi_hamming_enable_hwecc(void)
static inline void nand_bcm_umi_bch_enable_read_hwecc(void)
{
/* disable and reset ECC */
REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID;
writel(REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID, &REG_UMI_BCH_CTRL_STATUS);
/* Turn on ECC */
REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN;
writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN, &REG_UMI_BCH_CTRL_STATUS);
}
/* Enable BCH Write ECC */
static inline void nand_bcm_umi_bch_enable_write_hwecc(void)
{
/* disable and reset ECC */
REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID;
writel(REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID, &REG_UMI_BCH_CTRL_STATUS);
/* Turn on ECC */
REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN;
writel(REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN, &REG_UMI_BCH_CTRL_STATUS);
}
/* Config number of BCH ECC bytes */
@ -99,9 +100,9 @@ static inline void nand_bcm_umi_bch_config_ecc(uint8_t numEccBytes)
uint32_t numBits = numEccBytes * 8;
/* disable and reset ECC */
REG_UMI_BCH_CTRL_STATUS =
REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID |
REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID;
writel(REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID |
REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID,
&REG_UMI_BCH_CTRL_STATUS);
/* Every correctible bit requires 13 ECC bits */
tValue = (uint32_t) (numBits / ECC_BITS_PER_CORRECTABLE_BIT);
@ -113,23 +114,21 @@ static inline void nand_bcm_umi_bch_config_ecc(uint8_t numEccBytes)
kValue = nValue - (tValue * ECC_BITS_PER_CORRECTABLE_BIT);
/* Write the settings */
REG_UMI_BCH_N = nValue;
REG_UMI_BCH_T = tValue;
REG_UMI_BCH_K = kValue;
writel(nValue, &REG_UMI_BCH_N);
writel(tValue, &REG_UMI_BCH_T);
writel(kValue, &REG_UMI_BCH_K);
}
/* Pause during ECC read calculation to skip bytes in OOB */
static inline void nand_bcm_umi_bch_pause_read_ecc_calc(void)
{
REG_UMI_BCH_CTRL_STATUS =
REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN |
REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC;
writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN | REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC, &REG_UMI_BCH_CTRL_STATUS);
}
/* Resume during ECC read calculation after skipping bytes in OOB */
static inline void nand_bcm_umi_bch_resume_read_ecc_calc(void)
{
REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN;
writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN, &REG_UMI_BCH_CTRL_STATUS);
}
/* Poll read ECC calc to check when hardware completes */
@ -139,7 +138,7 @@ static inline uint32_t nand_bcm_umi_bch_poll_read_ecc_calc(void)
do {
/* wait for ECC to be valid */
regVal = REG_UMI_BCH_CTRL_STATUS;
regVal = readl(&REG_UMI_BCH_CTRL_STATUS);
} while ((regVal & REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID) == 0);
return regVal;
@ -149,7 +148,7 @@ static inline uint32_t nand_bcm_umi_bch_poll_read_ecc_calc(void)
static inline void nand_bcm_umi_bch_poll_write_ecc_calc(void)
{
/* wait for ECC to be valid */
while ((REG_UMI_BCH_CTRL_STATUS & REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID)
while ((readl(&REG_UMI_BCH_CTRL_STATUS) & REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID)
== 0)
;
}
@ -170,9 +169,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
if (pageSize != NAND_DATA_ACCESS_SIZE) {
/* skip BI */
#if defined(__KERNEL__) && !defined(STANDALONE)
*oobp++ = REG_NAND_DATA8;
*oobp++ = readb(&REG_NAND_DATA8);
#else
REG_NAND_DATA8;
readb(&REG_NAND_DATA8);
#endif
numToRead--;
}
@ -180,9 +179,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
while (numToRead > numEccBytes) {
/* skip free oob region */
#if defined(__KERNEL__) && !defined(STANDALONE)
*oobp++ = REG_NAND_DATA8;
*oobp++ = readb(&REG_NAND_DATA8);
#else
REG_NAND_DATA8;
readb(&REG_NAND_DATA8);
#endif
numToRead--;
}
@ -193,11 +192,11 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
while (numToRead > 11) {
#if defined(__KERNEL__) && !defined(STANDALONE)
*oobp = REG_NAND_DATA8;
*oobp = readb(&REG_NAND_DATA8);
eccCalc[eccPos++] = *oobp;
oobp++;
#else
eccCalc[eccPos++] = REG_NAND_DATA8;
eccCalc[eccPos++] = readb(&REG_NAND_DATA8);
#endif
numToRead--;
}
@ -207,9 +206,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
if (numToRead == 11) {
/* read BI */
#if defined(__KERNEL__) && !defined(STANDALONE)
*oobp++ = REG_NAND_DATA8;
*oobp++ = readb(&REG_NAND_DATA8);
#else
REG_NAND_DATA8;
readb(&REG_NAND_DATA8);
#endif
numToRead--;
}
@ -219,11 +218,11 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
nand_bcm_umi_bch_resume_read_ecc_calc();
while (numToRead) {
#if defined(__KERNEL__) && !defined(STANDALONE)
*oobp = REG_NAND_DATA8;
*oobp = readb(&REG_NAND_DATA8);
eccCalc[eccPos++] = *oobp;
oobp++;
#else
eccCalc[eccPos++] = REG_NAND_DATA8;
eccCalc[eccPos++] = readb(&REG_NAND_DATA8);
#endif
numToRead--;
}
@ -255,7 +254,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
if (pageSize == NAND_DATA_ACCESS_SIZE) {
/* Now fill in the ECC bytes */
if (numEccBytes >= 13)
eccVal = REG_UMI_BCH_WR_ECC_3;
eccVal = readl(&REG_UMI_BCH_WR_ECC_3);
/* Usually we skip CM in oob[0,1] */
NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[0],
@ -268,7 +267,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
eccVal & 0xff); /* ECC 12 */
if (numEccBytes >= 9)
eccVal = REG_UMI_BCH_WR_ECC_2;
eccVal = readl(&REG_UMI_BCH_WR_ECC_2);
NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[3],
(eccVal >> 24) & 0xff); /* ECC11 */
@ -281,7 +280,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
/* Now fill in the ECC bytes */
if (numEccBytes >= 13)
eccVal = REG_UMI_BCH_WR_ECC_3;
eccVal = readl(&REG_UMI_BCH_WR_ECC_3);
/* Usually skip CM in oob[1,2] */
NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[1],
@ -294,7 +293,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
eccVal & 0xff); /* ECC12 */
if (numEccBytes >= 9)
eccVal = REG_UMI_BCH_WR_ECC_2;
eccVal = readl(&REG_UMI_BCH_WR_ECC_2);
NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[4],
(eccVal >> 24) & 0xff); /* ECC11 */
@ -309,7 +308,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
eccVal & 0xff); /* ECC8 */
if (numEccBytes >= 5)
eccVal = REG_UMI_BCH_WR_ECC_1;
eccVal = readl(&REG_UMI_BCH_WR_ECC_1);
NAND_BCM_UMI_ECC_WRITE(numEccBytes, 8, &oobp[8],
(eccVal >> 24) & 0xff); /* ECC7 */
@ -321,7 +320,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
eccVal & 0xff); /* ECC4 */
if (numEccBytes >= 1)
eccVal = REG_UMI_BCH_WR_ECC_0;
eccVal = readl(&REG_UMI_BCH_WR_ECC_0);
NAND_BCM_UMI_ECC_WRITE(numEccBytes, 4, &oobp[12],
(eccVal >> 24) & 0xff); /* ECC3 */