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i.MX SoC update for 5.5:

Browse source 
- Add arm64 Kconfig option for the NXP S32 platform.
  - Drop imx_anatop_usb_chrg_detect_disable() function which becomes
    unneeded, since all the necessary charger setup is done by the USB
    PHY driver now.
  - Add serial number support for i.MX6/7 SoCs by reading 64-bit SoC
    unique ID from OCOTP block.
  - Replace i.MX machine specific coherency exit implementation using
    the generic v7_exit_coherency_flush() function.
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Merge tag 'imx-soc-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/soc

i.MX SoC update for 5.5:
 - Add arm64 Kconfig option for the NXP S32 platform.
 - Drop imx_anatop_usb_chrg_detect_disable() function which becomes
   unneeded, since all the necessary charger setup is done by the USB
   PHY driver now.
 - Add serial number support for i.MX6/7 SoCs by reading 64-bit SoC
   unique ID from OCOTP block.
 - Replace i.MX machine specific coherency exit implementation using
   the generic v7_exit_coherency_flush() function.

* tag 'imx-soc-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  ARM: imx: use generic function to exit coherency
  ARM: imx: Add serial number support for i.MX6/7 SoCs
  ARM: imx: Drop imx_anatop_usb_chrg_detect_disable()
  arm64: Introduce config for S32

Link: https://lore.kernel.org/r/20191105150315.15477-2-shawnguo@kernel.org
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2019-11-06 07:46:41 -08:00
commit 0f3dac6110
4 changed files with 45 additions and 42 deletions
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20
arch/arm/mach-imx/anatop.c
View file

@ -19,8 +19,6 @@
#define ANADIG_REG_2P5 0x130
#define ANADIG_REG_CORE 0x140
#define ANADIG_ANA_MISC0 0x150
#define ANADIG_USB1_CHRG_DETECT 0x1b0
#define ANADIG_USB2_CHRG_DETECT 0x210
#define ANADIG_DIGPROG 0x260
#define ANADIG_DIGPROG_IMX6SL 0x280
#define ANADIG_DIGPROG_IMX7D 0x800
@ -33,8 +31,6 @@
#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x1000
/* Below MISC0_DISCON_HIGH_SNVS is only for i.MX6SL */
#define BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS 0x2000
#define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B 0x80000
#define BM_ANADIG_USB_CHRG_DETECT_EN_B 0x100000
static struct regmap *anatop;
@ -96,16 +92,6 @@ void imx_anatop_post_resume(void)
}
static void imx_anatop_usb_chrg_detect_disable(void)
{
regmap_write(anatop, ANADIG_USB1_CHRG_DETECT,
BM_ANADIG_USB_CHRG_DETECT_EN_B
| BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
regmap_write(anatop, ANADIG_USB2_CHRG_DETECT,
BM_ANADIG_USB_CHRG_DETECT_EN_B |
BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
}
void __init imx_init_revision_from_anatop(void)
{
struct device_node *np;
@ -171,10 +157,6 @@ void __init imx_init_revision_from_anatop(void)
void __init imx_anatop_init(void)
{
anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop");
if (IS_ERR(anatop)) {
if (IS_ERR(anatop))
pr_err("%s: failed to find imx6q-anatop regmap!\n", __func__);
return;
}
imx_anatop_usb_chrg_detect_disable();
}

38
arch/arm/mach-imx/cpu.c
View file

@ -1,15 +1,20 @@
// SPDX-License-Identifier: GPL-2.0
#include <linux/err.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/sys_soc.h>
#include "hardware.h"
#include "common.h"
#define OCOTP_UID_H 0x420
#define OCOTP_UID_L 0x410
unsigned int __mxc_cpu_type;
static unsigned int imx_soc_revision;
@ -76,9 +81,13 @@ void __init imx_aips_allow_unprivileged_access(
struct device * __init imx_soc_device_init(void)
{
struct soc_device_attribute *soc_dev_attr;
const char *ocotp_compat = NULL;
struct soc_device *soc_dev;
struct device_node *root;
struct regmap *ocotp;
const char *soc_id;
u64 soc_uid = 0;
u32 val;
int ret;
soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
@ -119,30 +128,39 @@ struct device * __init imx_soc_device_init(void)
soc_id = "i.MX53";
break;
case MXC_CPU_IMX6SL:
ocotp_compat = "fsl,imx6sl-ocotp";
soc_id = "i.MX6SL";
break;
case MXC_CPU_IMX6DL:
ocotp_compat = "fsl,imx6q-ocotp";
soc_id = "i.MX6DL";
break;
case MXC_CPU_IMX6SX:
ocotp_compat = "fsl,imx6sx-ocotp";
soc_id = "i.MX6SX";
break;
case MXC_CPU_IMX6Q:
ocotp_compat = "fsl,imx6q-ocotp";
soc_id = "i.MX6Q";
break;
case MXC_CPU_IMX6UL:
ocotp_compat = "fsl,imx6ul-ocotp";
soc_id = "i.MX6UL";
break;
case MXC_CPU_IMX6ULL:
ocotp_compat = "fsl,imx6ul-ocotp";
soc_id = "i.MX6ULL";
break;
case MXC_CPU_IMX6ULZ:
ocotp_compat = "fsl,imx6ul-ocotp";
soc_id = "i.MX6ULZ";
break;
case MXC_CPU_IMX6SLL:
ocotp_compat = "fsl,imx6sll-ocotp";
soc_id = "i.MX6SLL";
break;
case MXC_CPU_IMX7D:
ocotp_compat = "fsl,imx7d-ocotp";
soc_id = "i.MX7D";
break;
case MXC_CPU_IMX7ULP:
@ -153,18 +171,36 @@ struct device * __init imx_soc_device_init(void)
}
soc_dev_attr->soc_id = soc_id;
if (ocotp_compat) {
ocotp = syscon_regmap_lookup_by_compatible(ocotp_compat);
if (IS_ERR(ocotp))
pr_err("%s: failed to find %s regmap!\n", __func__, ocotp_compat);
regmap_read(ocotp, OCOTP_UID_H, &val);
soc_uid = val;
regmap_read(ocotp, OCOTP_UID_L, &val);
soc_uid <<= 32;
soc_uid |= val;
}
soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d",
(imx_soc_revision >> 4) & 0xf,
imx_soc_revision & 0xf);
if (!soc_dev_attr->revision)
goto free_soc;
soc_dev_attr->serial_number = kasprintf(GFP_KERNEL, "%016llX", soc_uid);
if (!soc_dev_attr->serial_number)
goto free_rev;
soc_dev = soc_device_register(soc_dev_attr);
if (IS_ERR(soc_dev))
goto free_rev;
goto free_serial_number;
return soc_device_to_device(soc_dev);
free_serial_number:
kfree(soc_dev_attr->serial_number);
free_rev:
kfree(soc_dev_attr->revision);
free_soc:

24
arch/arm/mach-imx/hotplug.c
View file

@ -6,32 +6,12 @@
#include <linux/errno.h>
#include <linux/jiffies.h>
#include <asm/cacheflush.h>
#include <asm/cp15.h>
#include <asm/proc-fns.h>
#include "common.h"
static inline void cpu_enter_lowpower(void)
{
unsigned int v;
asm volatile(
"mcr p15, 0, %1, c7, c5, 0\n"
" mcr p15, 0, %1, c7, c10, 4\n"
/*
* Turn off coherency
*/
" mrc p15, 0, %0, c1, c0, 1\n"
" bic %0, %0, %3\n"
" mcr p15, 0, %0, c1, c0, 1\n"
" mrc p15, 0, %0, c1, c0, 0\n"
" bic %0, %0, %2\n"
" mcr p15, 0, %0, c1, c0, 0\n"
: "=&r" (v)
: "r" (0), "Ir" (CR_C), "Ir" (0x40)
: "cc");
}
/*
* platform-specific code to shutdown a CPU
*
@ -39,7 +19,7 @@ static inline void cpu_enter_lowpower(void)
*/
void imx_cpu_die(unsigned int cpu)
{
cpu_enter_lowpower();
v7_exit_coherency_flush(louis);
/*
* We use the cpu jumping argument register to sync with
* imx_cpu_kill() which is running on cpu0 and waiting for

5
arch/arm64/Kconfig.platforms
View file

@ -214,6 +214,11 @@ config ARCH_ROCKCHIP
This enables support for the ARMv8 based Rockchip chipsets,
like the RK3368.
config ARCH_S32
bool "NXP S32 SoC Family"
help
This enables support for the NXP S32 family of processors.
config ARCH_SEATTLE
bool "AMD Seattle SoC Family"
help