clk: xgene: Add missing parenthesis when clearing divider value
In the initial fix for non-zero divider shift value, the parenthesis
was missing after the negate operation. This patch adds the required
parenthesis. Otherwise, lower bits may be cleared unintentionally.
Signed-off-by: Loc Ho <lho@apm.com>
Acked-by: Toan Le <toanle@apm.com>
Fixes: 1382ea631d
("clk: xgene: Fix divider with non-zero shift value")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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1 changed files with 2 additions and 2 deletions
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@ -376,8 +376,8 @@ static int xgene_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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/* Set new divider */
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/* Set new divider */
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data = xgene_clk_read(pclk->param.divider_reg +
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data = xgene_clk_read(pclk->param.divider_reg +
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pclk->param.reg_divider_offset);
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pclk->param.reg_divider_offset);
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data &= ~((1 << pclk->param.reg_divider_width) - 1)
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data &= ~(((1 << pclk->param.reg_divider_width) - 1)
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<< pclk->param.reg_divider_shift;
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<< pclk->param.reg_divider_shift);
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data |= divider;
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data |= divider;
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xgene_clk_write(data, pclk->param.divider_reg +
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xgene_clk_write(data, pclk->param.divider_reg +
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pclk->param.reg_divider_offset);
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pclk->param.reg_divider_offset);
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