[MTD] Basic NAND driver for AMD/NatSemi CS5535/CS5536 Geode companion chip
This lacks hardware ECC support and a few optimisations we're going to want fairly soon, but it works well enough to mount and use JFFS2. Signed-off-by: David Woodhouse <dwmw2@infradead.org>
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David Woodhouse
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b04ecae3d6
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179fdc3f8d
3 changed files with 298 additions and 0 deletions
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@ -189,6 +189,10 @@ config MTD_NAND_SHARPSL
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tristate "Support for NAND Flash on Sharp SL Series (C7xx + others)"
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depends on MTD_NAND && ARCH_PXA
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config MTD_NAND_CS553X
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tristate "NAND support for CS5535/CS5536 (AMD Geode companion chip)"
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depends on MTD_NAND && X86_PC && PCI
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config MTD_NAND_NANDSIM
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tristate "Support for NAND Flash Simulator"
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depends on MTD_NAND && MTD_PARTITIONS
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@ -19,5 +19,6 @@ obj-$(CONFIG_MTD_NAND_RTC_FROM4) += rtc_from4.o
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obj-$(CONFIG_MTD_NAND_SHARPSL) += sharpsl.o
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obj-$(CONFIG_MTD_NAND_TS7250) += ts7250.o
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obj-$(CONFIG_MTD_NAND_NANDSIM) += nandsim.o
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obj-$(CONFIG_MTD_NAND_CS553X) += cs553x_nand.o
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nand-objs = nand_base.o nand_bbt.o
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293
drivers/mtd/nand/cs553x_nand.c
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293
drivers/mtd/nand/cs553x_nand.c
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@ -0,0 +1,293 @@
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/*
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* drivers/mtd/nand/cs553x_nand.c
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*
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* (C) 2005, 2006 Red Hat Inc.
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*
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* Author: David Woodhouse <dwmw2@infradead.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Overview:
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* This is a device driver for the NAND flash controller found on
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* the AMD CS5535/CS5536 companion chipsets for the Geode processor.
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*
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*/
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <asm/msr.h>
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#include <asm/io.h>
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#define NR_CS553X_CONTROLLERS 4
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/* NAND Timing MSRs */
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#define MSR_NANDF_DATA 0x5140001b /* NAND Flash Data Timing MSR */
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#define MSR_NANDF_CTL 0x5140001c /* NAND Flash Control Timing */
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#define MSR_NANDF_RSVD 0x5140001d /* Reserved */
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/* NAND BAR MSRs */
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#define MSR_DIVIL_LBAR_FLSH0 0x51400010 /* Flash Chip Select 0 */
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#define MSR_DIVIL_LBAR_FLSH1 0x51400011 /* Flash Chip Select 1 */
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#define MSR_DIVIL_LBAR_FLSH2 0x51400012 /* Flash Chip Select 2 */
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#define MSR_DIVIL_LBAR_FLSH3 0x51400013 /* Flash Chip Select 3 */
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/* Each made up of... */
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#define FLSH_LBAR_EN (1ULL<<32)
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#define FLSH_NOR_NAND (1ULL<<33) /* 1 for NAND */
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#define FLSH_MEM_IO (1ULL<<34) /* 1 for MMIO */
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/* I/O BARs have BASE_ADDR in bits 15:4, IO_MASK in 47:36 */
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/* MMIO BARs have BASE_ADDR in bits 31:12, MEM_MASK in 63:44 */
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/* Pin function selection MSR (IDE vs. flash on the IDE pins) */
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#define MSR_DIVIL_BALL_OPTS 0x51400015
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#define PIN_OPT_IDE (1<<0) /* 0 for flash, 1 for IDE */
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/* Registers within the NAND flash controller BAR -- memory mapped */
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#define MM_NAND_DATA 0x00 /* 0 to 0x7ff, in fact */
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#define MM_NAND_CTL 0x800 /* Any even address 0x800-0x80e */
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#define MM_NAND_IO 0x801 /* Any odd address 0x801-0x80f */
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#define MM_NAND_STS 0x810
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#define MM_NAND_ECC_LSB 0x811
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#define MM_NAND_ECC_MSB 0x812
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#define MM_NAND_ECC_COL 0x813
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#define MM_NAND_LAC 0x814
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#define MM_NAND_ECC_CTL 0x815
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/* Registers within the NAND flash controller BAR -- I/O mapped */
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#define IO_NAND_DATA 0x00 /* 0 to 3, in fact */
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#define IO_NAND_CTL 0x04
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#define IO_NAND_IO 0x05
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#define IO_NAND_STS 0x06
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#define IO_NAND_ECC_CTL 0x08
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#define IO_NAND_ECC_LSB 0x09
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#define IO_NAND_ECC_MSB 0x0a
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#define IO_NAND_ECC_COL 0x0b
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#define IO_NAND_LAC 0x0c
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#define CS_NAND_CTL_DIST_EN (1<<4) /* Enable NAND Distract interrupt */
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#define CS_NAND_CTL_RDY_INT_MASK (1<<3) /* Enable RDY/BUSY# interrupt */
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#define CS_NAND_CTL_ALE (1<<2)
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#define CS_NAND_CTL_CLE (1<<1)
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#define CS_NAND_CTL_CE (1<<0) /* Keep low; 1 to reset */
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#define CS_NAND_STS_FLASH_RDY (1<<3)
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#define CS_NAND_CTLR_BUSY (1<<2)
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#define CS_NAND_CMD_COMP (1<<1)
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#define CS_NAND_DIST_ST (1<<0)
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#define CS_NAND_ECC_PARITY (1<<2)
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#define CS_NAND_ECC_CLRECC (1<<1)
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#define CS_NAND_ECC_ENECC (1<<0)
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static unsigned char cs553x_read_byte(struct mtd_info *mtd)
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{
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struct nand_chip *this = mtd->priv;
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unsigned char foo = readb(this->IO_ADDR_R);
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return foo;
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}
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static void cs553x_write_byte(struct mtd_info *mtd, u_char byte)
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{
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struct nand_chip *this = mtd->priv;
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int i = 100000;
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while (i && readb(this->IO_ADDR_R + MM_NAND_STS) & CS_NAND_CTLR_BUSY) {
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udelay(1);
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i--;
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}
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writeb(byte, this->IO_ADDR_W+0x801);
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}
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static void cs553x_hwcontrol(struct mtd_info *mtd, int cmd)
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{
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struct nand_chip *this = mtd->priv;
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void __iomem *mmio_base = this->IO_ADDR_R;
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uint8_t old = readb(mmio_base + MM_NAND_CTL);
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switch(cmd) {
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case NAND_CTL_SETCLE:
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old |= CS_NAND_CTL_CLE;
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break;
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case NAND_CTL_CLRCLE:
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old &= ~CS_NAND_CTL_CLE;
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break;
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case NAND_CTL_SETALE:
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old |= CS_NAND_CTL_ALE;
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break;
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case NAND_CTL_CLRALE:
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old &= ~CS_NAND_CTL_ALE;
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break;
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case NAND_CTL_SETNCE:
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old &= ~CS_NAND_CTL_CE;
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break;
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case NAND_CTL_CLRNCE:
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old |= CS_NAND_CTL_CE;
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break;
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}
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writeb(old, mmio_base + MM_NAND_CTL);
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}
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static int cs553x_device_ready(struct mtd_info *mtd)
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{
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struct nand_chip *this = mtd->priv;
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void __iomem *mmio_base = this->IO_ADDR_R;
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unsigned char foo = readb(mmio_base + MM_NAND_STS);
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return (foo & CS_NAND_STS_FLASH_RDY) && !(foo & CS_NAND_CTLR_BUSY);
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}
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static struct mtd_info *cs553x_mtd[4];
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static int __init cs553x_init_one(int cs, int mmio, unsigned long adr)
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{
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int err = 0;
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struct nand_chip *this;
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struct mtd_info *new_mtd;
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printk(KERN_NOTICE "Probing CS553x NAND controller CS#%d at %sIO 0x%08lx\n", cs, mmio?"MM":"P", adr);
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if (!mmio) {
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printk(KERN_NOTICE "PIO mode not yet implemented for CS553X NAND controller\n");
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return -ENXIO;
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}
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/* Allocate memory for MTD device structure and private data */
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new_mtd = kmalloc (sizeof(struct mtd_info) + sizeof (struct nand_chip), GFP_KERNEL);
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if (!new_mtd) {
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printk(KERN_WARNING "Unable to allocate CS553X NAND MTD device structure.\n");
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err = -ENOMEM;
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goto out;
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}
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/* Get pointer to private data */
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this = (struct nand_chip *) (&new_mtd[1]);
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/* Initialize structures */
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memset((char *) new_mtd, 0, sizeof(struct mtd_info));
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memset((char *) this, 0, sizeof(struct nand_chip));
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/* Link the private data with the MTD structure */
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new_mtd->priv = this;
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/* map physical address */
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this->IO_ADDR_R = this->IO_ADDR_W = ioremap(adr, 4096);
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if (!this->IO_ADDR_R) {
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printk(KERN_WARNING "ioremap cs553x NAND @0x%08lx failed\n", adr);
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err = -EIO;
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goto out_mtd;
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}
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this->hwcontrol = cs553x_hwcontrol;
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this->dev_ready = cs553x_device_ready;
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this->read_byte = cs553x_read_byte;
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this->write_byte = cs553x_write_byte;
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/* 20 us command delay time */
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this->chip_delay = 20;
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this->eccmode = NAND_ECC_SOFT;
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/* Enable the following for a flash based bad block table */
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// this->options = NAND_USE_FLASH_BBT;
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/* Scan to find existance of the device */
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if (nand_scan (new_mtd, 1)) {
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err = -ENXIO;
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goto out_ior;
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}
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cs553x_mtd[cs] = new_mtd;
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goto out;
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out_ior:
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iounmap((void *)this->IO_ADDR_R);
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out_mtd:
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kfree (new_mtd);
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out:
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return err;
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}
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int __init cs553x_init(void)
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{
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int err = -ENXIO;
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int i;
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uint64_t val;
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/* Check whether we actually have a CS5535 or CS5536 */
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if (!pci_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, NULL) &&
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!pci_find_device(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_CS5535_ISA, NULL))
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return -ENXIO;
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rdmsrl(MSR_DIVIL_BALL_OPTS, val);
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if (val & 1) {
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printk(KERN_INFO "CS553x NAND controller: Flash I/O not enabled in MSR_DIVIL_BALL_OPTS.\n");
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return -ENXIO;
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}
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for (i=0; i<NR_CS553X_CONTROLLERS; i++) {
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rdmsrl(MSR_DIVIL_LBAR_FLSH0+i, val);
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if ((val & (FLSH_LBAR_EN|FLSH_NOR_NAND)) == (FLSH_LBAR_EN|FLSH_NOR_NAND))
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err = cs553x_init_one(i, !!(val & FLSH_MEM_IO), val & 0xFFFFFFFF);
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}
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/* Register all devices together here. This means we can easily hack it to
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do mtdconcat etc. if we want to. */
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for (i=0; i<NR_CS553X_CONTROLLERS; i++) {
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if (cs553x_mtd[i]) {
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add_mtd_device(cs553x_mtd[i]);
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/* If any devices registered, return success. Else the last error. */
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err = 0;
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}
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}
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return err;
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}
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module_init(cs553x_init);
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static void __exit cs553x_cleanup (void)
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{
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int i;
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for (i=0; i<NR_CS553X_CONTROLLERS; i++) {
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struct mtd_info *mtd = cs553x_mtd[i];
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struct nand_chip *this;
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void __iomem *mmio_base;
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if (!mtd)
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break;
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this = cs553x_mtd[i]->priv;
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mmio_base = this->IO_ADDR_R;
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/* Release resources, unregister device */
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nand_release (cs553x_mtd[i]);
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cs553x_mtd[i] = NULL;
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/* unmap physical adress */
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iounmap(mmio_base);
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/* Free the MTD device structure */
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kfree (mtd);
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}
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}
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module_exit(cs553x_cleanup);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
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MODULE_DESCRIPTION("NAND controller driver for AMD CS5535/CS5536 companion chip");
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