Merge remote-tracking branches 'spi/topic/pxa', 'spi/topic/pxa2xx', 'spi/topic/qup', 'spi/topic/rockchip' and 'spi/topic/sh' into spi-next
This commit is contained in:
Mark Brown
commit
17c49e53f3
7 changed files with 446 additions and 228 deletions
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@ -6,6 +6,7 @@ and display controllers using the SPI communication interface.
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Required Properties:
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- compatible: should be one of the following.
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"rockchip,rv1108-spi" for rv1108 SoCs.
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"rockchip,rk3036-spi" for rk3036 SoCS.
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"rockchip,rk3066-spi" for rk3066 SoCs.
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"rockchip,rk3188-spi" for rk3188 SoCs.
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@ -517,8 +517,8 @@ config SPI_PPC4xx
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config SPI_PXA2XX
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tristate "PXA2xx SSP SPI master"
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depends on (ARCH_PXA || PCI || ACPI)
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select PXA_SSP if ARCH_PXA
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depends on (ARCH_PXA || ARCH_MMP || PCI || ACPI)
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select PXA_SSP if ARCH_PXA || ARCH_MMP
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help
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This enables using a PXA2xx or Sodaville SSP port as a SPI master
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controller. The driver can be configured to use any SSP port and
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@ -402,8 +402,8 @@ static void cs_assert(struct driver_data *drv_data)
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return;
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}
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if (gpio_is_valid(chip->gpio_cs)) {
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gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
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if (chip->gpiod_cs) {
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gpiod_set_value(chip->gpiod_cs, chip->gpio_cs_inverted);
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return;
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}
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@ -424,8 +424,8 @@ static void cs_deassert(struct driver_data *drv_data)
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return;
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}
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if (gpio_is_valid(chip->gpio_cs)) {
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gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
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if (chip->gpiod_cs) {
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gpiod_set_value(chip->gpiod_cs, !chip->gpio_cs_inverted);
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return;
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}
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@ -1213,17 +1213,16 @@ static int setup_cs(struct spi_device *spi, struct chip_data *chip,
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struct pxa2xx_spi_chip *chip_info)
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{
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struct driver_data *drv_data = spi_master_get_devdata(spi->master);
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struct gpio_desc *gpiod;
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int err = 0;
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if (chip == NULL)
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return 0;
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if (drv_data->cs_gpiods) {
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struct gpio_desc *gpiod;
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gpiod = drv_data->cs_gpiods[spi->chip_select];
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if (gpiod) {
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chip->gpio_cs = desc_to_gpio(gpiod);
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chip->gpiod_cs = gpiod;
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chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
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gpiod_set_value(gpiod, chip->gpio_cs_inverted);
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}
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@ -1237,8 +1236,10 @@ static int setup_cs(struct spi_device *spi, struct chip_data *chip,
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/* NOTE: setup() can be called multiple times, possibly with
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* different chip_info, release previously requested GPIO
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*/
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if (gpio_is_valid(chip->gpio_cs))
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gpio_free(chip->gpio_cs);
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if (chip->gpiod_cs) {
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gpio_free(desc_to_gpio(chip->gpiod_cs));
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chip->gpiod_cs = NULL;
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}
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/* If (*cs_control) is provided, ignore GPIO chip select */
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if (chip_info->cs_control) {
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@ -1254,11 +1255,11 @@ static int setup_cs(struct spi_device *spi, struct chip_data *chip,
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return err;
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}
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chip->gpio_cs = chip_info->gpio_cs;
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gpiod = gpio_to_desc(chip_info->gpio_cs);
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chip->gpiod_cs = gpiod;
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chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
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err = gpio_direction_output(chip->gpio_cs,
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!chip->gpio_cs_inverted);
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err = gpiod_direction_output(gpiod, !chip->gpio_cs_inverted);
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}
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return err;
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@ -1317,8 +1318,7 @@ static int setup(struct spi_device *spi)
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}
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chip->frm = spi->chip_select;
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} else
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chip->gpio_cs = -1;
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}
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chip->enable_dma = drv_data->master_info->enable_dma;
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chip->timeout = TIMOUT_DFLT;
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}
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@ -1416,8 +1416,8 @@ static void cleanup(struct spi_device *spi)
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return;
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if (drv_data->ssp_type != CE4100_SSP && !drv_data->cs_gpiods &&
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gpio_is_valid(chip->gpio_cs))
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gpio_free(chip->gpio_cs);
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chip->gpiod_cs)
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gpio_free(desc_to_gpio(chip->gpiod_cs));
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kfree(chip);
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}
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@ -1769,8 +1769,7 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
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for (i = 0; i < master->num_chipselect; i++) {
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struct gpio_desc *gpiod;
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gpiod = devm_gpiod_get_index(dev, "cs", i,
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GPIOD_OUT_HIGH);
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gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS);
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if (IS_ERR(gpiod)) {
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/* Means use native chip select */
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if (PTR_ERR(gpiod) == -ENOENT)
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@ -83,7 +83,7 @@ struct chip_data {
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u16 lpss_tx_threshold;
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u8 enable_dma;
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union {
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int gpio_cs;
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struct gpio_desc *gpiod_cs;
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unsigned int frm;
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};
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int gpio_cs_inverted;
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@ -19,6 +19,7 @@
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/spi/spi.h>
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@ -82,6 +83,8 @@
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#define QUP_IO_M_MODE_BAM 3
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/* QUP_OPERATIONAL fields */
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#define QUP_OP_IN_BLOCK_READ_REQ BIT(13)
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#define QUP_OP_OUT_BLOCK_WRITE_REQ BIT(12)
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#define QUP_OP_MAX_INPUT_DONE_FLAG BIT(11)
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#define QUP_OP_MAX_OUTPUT_DONE_FLAG BIT(10)
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#define QUP_OP_IN_SERVICE_FLAG BIT(9)
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@ -118,7 +121,7 @@
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#define SPI_NUM_CHIPSELECTS 4
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#define SPI_MAX_DMA_XFER (SZ_64K - 64)
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#define SPI_MAX_XFER (SZ_64K - 64)
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/* high speed mode is when bus rate is greater then 26MHz */
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#define SPI_HS_MIN_RATE 26000000
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@ -147,13 +150,37 @@ struct spi_qup {
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int n_words;
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int tx_bytes;
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int rx_bytes;
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const u8 *tx_buf;
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u8 *rx_buf;
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int qup_v1;
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int use_dma;
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int mode;
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struct dma_slave_config rx_conf;
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struct dma_slave_config tx_conf;
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};
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static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer);
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static inline bool spi_qup_is_flag_set(struct spi_qup *controller, u32 flag)
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{
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u32 opflag = readl_relaxed(controller->base + QUP_OPERATIONAL);
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return (opflag & flag) != 0;
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}
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static inline bool spi_qup_is_dma_xfer(int mode)
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{
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if (mode == QUP_IO_M_MODE_DMOV || mode == QUP_IO_M_MODE_BAM)
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return true;
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return false;
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}
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/* get's the transaction size length */
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static inline unsigned int spi_qup_len(struct spi_qup *controller)
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{
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return controller->n_words * controller->w_size;
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}
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static inline bool spi_qup_is_valid_state(struct spi_qup *controller)
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{
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@ -207,29 +234,26 @@ static int spi_qup_set_state(struct spi_qup *controller, u32 state)
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return 0;
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}
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static void spi_qup_fifo_read(struct spi_qup *controller,
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struct spi_transfer *xfer)
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static void spi_qup_read_from_fifo(struct spi_qup *controller, u32 num_words)
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{
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u8 *rx_buf = xfer->rx_buf;
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u32 word, state;
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int idx, shift, w_size;
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u8 *rx_buf = controller->rx_buf;
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int i, shift, num_bytes;
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u32 word;
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w_size = controller->w_size;
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while (controller->rx_bytes < xfer->len) {
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state = readl_relaxed(controller->base + QUP_OPERATIONAL);
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if (0 == (state & QUP_OP_IN_FIFO_NOT_EMPTY))
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break;
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for (; num_words; num_words--) {
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word = readl_relaxed(controller->base + QUP_INPUT_FIFO);
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num_bytes = min_t(int, spi_qup_len(controller) -
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controller->rx_bytes,
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controller->w_size);
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if (!rx_buf) {
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controller->rx_bytes += w_size;
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controller->rx_bytes += num_bytes;
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continue;
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}
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for (idx = 0; idx < w_size; idx++, controller->rx_bytes++) {
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for (i = 0; i < num_bytes; i++, controller->rx_bytes++) {
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/*
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* The data format depends on bytes per SPI word:
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* 4 bytes: 0x12345678
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@ -237,38 +261,81 @@ static void spi_qup_fifo_read(struct spi_qup *controller,
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* 1 byte : 0x00000012
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*/
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shift = BITS_PER_BYTE;
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shift *= (w_size - idx - 1);
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shift *= (controller->w_size - i - 1);
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rx_buf[controller->rx_bytes] = word >> shift;
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}
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}
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}
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static void spi_qup_fifo_write(struct spi_qup *controller,
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struct spi_transfer *xfer)
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static void spi_qup_read(struct spi_qup *controller, u32 *opflags)
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{
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const u8 *tx_buf = xfer->tx_buf;
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u32 word, state, data;
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int idx, w_size;
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u32 remainder, words_per_block, num_words;
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bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK;
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w_size = controller->w_size;
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remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->rx_bytes,
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controller->w_size);
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words_per_block = controller->in_blk_sz >> 2;
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while (controller->tx_bytes < xfer->len) {
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do {
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/* ACK by clearing service flag */
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writel_relaxed(QUP_OP_IN_SERVICE_FLAG,
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controller->base + QUP_OPERATIONAL);
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state = readl_relaxed(controller->base + QUP_OPERATIONAL);
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if (state & QUP_OP_OUT_FIFO_FULL)
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if (is_block_mode) {
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num_words = (remainder > words_per_block) ?
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words_per_block : remainder;
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} else {
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if (!spi_qup_is_flag_set(controller,
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QUP_OP_IN_FIFO_NOT_EMPTY))
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break;
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num_words = 1;
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}
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/* read up to the maximum transfer size available */
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spi_qup_read_from_fifo(controller, num_words);
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remainder -= num_words;
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/* if block mode, check to see if next block is available */
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if (is_block_mode && !spi_qup_is_flag_set(controller,
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QUP_OP_IN_BLOCK_READ_REQ))
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break;
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word = 0;
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for (idx = 0; idx < w_size; idx++, controller->tx_bytes++) {
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} while (remainder);
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if (!tx_buf) {
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controller->tx_bytes += w_size;
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break;
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/*
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* Due to extra stickiness of the QUP_OP_IN_SERVICE_FLAG during block
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* reads, it has to be cleared again at the very end. However, be sure
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* to refresh opflags value because MAX_INPUT_DONE_FLAG may now be
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* present and this is used to determine if transaction is complete
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*/
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*opflags = readl_relaxed(controller->base + QUP_OPERATIONAL);
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if (is_block_mode && *opflags & QUP_OP_MAX_INPUT_DONE_FLAG)
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writel_relaxed(QUP_OP_IN_SERVICE_FLAG,
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controller->base + QUP_OPERATIONAL);
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}
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static void spi_qup_write_to_fifo(struct spi_qup *controller, u32 num_words)
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{
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const u8 *tx_buf = controller->tx_buf;
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int i, num_bytes;
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u32 word, data;
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for (; num_words; num_words--) {
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word = 0;
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num_bytes = min_t(int, spi_qup_len(controller) -
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controller->tx_bytes,
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controller->w_size);
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if (tx_buf)
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for (i = 0; i < num_bytes; i++) {
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data = tx_buf[controller->tx_bytes + i];
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word |= data << (BITS_PER_BYTE * (3 - i));
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}
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data = tx_buf[controller->tx_bytes];
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word |= data << (BITS_PER_BYTE * (3 - idx));
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}
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controller->tx_bytes += num_bytes;
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writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO);
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}
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@ -281,31 +348,61 @@ static void spi_qup_dma_done(void *data)
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complete(&qup->done);
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}
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static int spi_qup_prep_sg(struct spi_master *master, struct spi_transfer *xfer,
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enum dma_transfer_direction dir,
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static void spi_qup_write(struct spi_qup *controller)
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{
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bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK;
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u32 remainder, words_per_block, num_words;
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remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->tx_bytes,
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controller->w_size);
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words_per_block = controller->out_blk_sz >> 2;
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do {
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/* ACK by clearing service flag */
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writel_relaxed(QUP_OP_OUT_SERVICE_FLAG,
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controller->base + QUP_OPERATIONAL);
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if (is_block_mode) {
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num_words = (remainder > words_per_block) ?
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words_per_block : remainder;
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} else {
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if (spi_qup_is_flag_set(controller,
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QUP_OP_OUT_FIFO_FULL))
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break;
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num_words = 1;
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}
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spi_qup_write_to_fifo(controller, num_words);
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remainder -= num_words;
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/* if block mode, check to see if next block is available */
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if (is_block_mode && !spi_qup_is_flag_set(controller,
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QUP_OP_OUT_BLOCK_WRITE_REQ))
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break;
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} while (remainder);
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}
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static int spi_qup_prep_sg(struct spi_master *master, struct scatterlist *sgl,
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unsigned int nents, enum dma_transfer_direction dir,
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dma_async_tx_callback callback)
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{
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struct spi_qup *qup = spi_master_get_devdata(master);
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unsigned long flags = DMA_PREP_INTERRUPT | DMA_PREP_FENCE;
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struct dma_async_tx_descriptor *desc;
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struct scatterlist *sgl;
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struct dma_chan *chan;
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dma_cookie_t cookie;
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unsigned int nents;
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if (dir == DMA_MEM_TO_DEV) {
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if (dir == DMA_MEM_TO_DEV)
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chan = master->dma_tx;
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nents = xfer->tx_sg.nents;
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sgl = xfer->tx_sg.sgl;
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} else {
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else
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chan = master->dma_rx;
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nents = xfer->rx_sg.nents;
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sgl = xfer->rx_sg.sgl;
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}
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desc = dmaengine_prep_slave_sg(chan, sgl, nents, dir, flags);
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if (!desc)
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return -EINVAL;
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if (IS_ERR_OR_NULL(desc))
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return desc ? PTR_ERR(desc) : -EINVAL;
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desc->callback = callback;
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desc->callback_param = qup;
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@ -324,9 +421,33 @@ static void spi_qup_dma_terminate(struct spi_master *master,
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dmaengine_terminate_all(master->dma_rx);
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}
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static int spi_qup_do_dma(struct spi_master *master, struct spi_transfer *xfer)
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static u32 spi_qup_sgl_get_nents_len(struct scatterlist *sgl, u32 max,
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u32 *nents)
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{
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struct scatterlist *sg;
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u32 total = 0;
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for (sg = sgl; sg; sg = sg_next(sg)) {
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unsigned int len = sg_dma_len(sg);
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/* check for overflow as well as limit */
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if (((total + len) < total) || ((total + len) > max))
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break;
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total += len;
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(*nents)++;
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}
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return total;
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}
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static int spi_qup_do_dma(struct spi_device *spi, struct spi_transfer *xfer,
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unsigned long timeout)
|
||||
{
|
||||
dma_async_tx_callback rx_done = NULL, tx_done = NULL;
|
||||
struct spi_master *master = spi->master;
|
||||
struct spi_qup *qup = spi_master_get_devdata(master);
|
||||
struct scatterlist *tx_sgl, *rx_sgl;
|
||||
int ret;
|
||||
|
||||
if (xfer->rx_buf)
|
||||
|
|
@ -334,43 +455,122 @@ static int spi_qup_do_dma(struct spi_master *master, struct spi_transfer *xfer)
|
|||
else if (xfer->tx_buf)
|
||||
tx_done = spi_qup_dma_done;
|
||||
|
||||
if (xfer->rx_buf) {
|
||||
ret = spi_qup_prep_sg(master, xfer, DMA_DEV_TO_MEM, rx_done);
|
||||
rx_sgl = xfer->rx_sg.sgl;
|
||||
tx_sgl = xfer->tx_sg.sgl;
|
||||
|
||||
do {
|
||||
u32 rx_nents = 0, tx_nents = 0;
|
||||
|
||||
if (rx_sgl)
|
||||
qup->n_words = spi_qup_sgl_get_nents_len(rx_sgl,
|
||||
SPI_MAX_XFER, &rx_nents) / qup->w_size;
|
||||
if (tx_sgl)
|
||||
qup->n_words = spi_qup_sgl_get_nents_len(tx_sgl,
|
||||
SPI_MAX_XFER, &tx_nents) / qup->w_size;
|
||||
if (!qup->n_words)
|
||||
return -EIO;
|
||||
|
||||
ret = spi_qup_io_config(spi, xfer);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
dma_async_issue_pending(master->dma_rx);
|
||||
}
|
||||
|
||||
if (xfer->tx_buf) {
|
||||
ret = spi_qup_prep_sg(master, xfer, DMA_MEM_TO_DEV, tx_done);
|
||||
if (ret)
|
||||
/* before issuing the descriptors, set the QUP to run */
|
||||
ret = spi_qup_set_state(qup, QUP_STATE_RUN);
|
||||
if (ret) {
|
||||
dev_warn(qup->dev, "cannot set RUN state\n");
|
||||
return ret;
|
||||
}
|
||||
if (rx_sgl) {
|
||||
ret = spi_qup_prep_sg(master, rx_sgl, rx_nents,
|
||||
DMA_DEV_TO_MEM, rx_done);
|
||||
if (ret)
|
||||
return ret;
|
||||
dma_async_issue_pending(master->dma_rx);
|
||||
}
|
||||
|
||||
dma_async_issue_pending(master->dma_tx);
|
||||
}
|
||||
if (tx_sgl) {
|
||||
ret = spi_qup_prep_sg(master, tx_sgl, tx_nents,
|
||||
DMA_MEM_TO_DEV, tx_done);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
dma_async_issue_pending(master->dma_tx);
|
||||
}
|
||||
|
||||
if (!wait_for_completion_timeout(&qup->done, timeout))
|
||||
return -ETIMEDOUT;
|
||||
|
||||
for (; rx_sgl && rx_nents--; rx_sgl = sg_next(rx_sgl))
|
||||
;
|
||||
for (; tx_sgl && tx_nents--; tx_sgl = sg_next(tx_sgl))
|
||||
;
|
||||
|
||||
} while (rx_sgl || tx_sgl);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int spi_qup_do_pio(struct spi_master *master, struct spi_transfer *xfer)
|
||||
static int spi_qup_do_pio(struct spi_device *spi, struct spi_transfer *xfer,
|
||||
unsigned long timeout)
|
||||
{
|
||||
struct spi_master *master = spi->master;
|
||||
struct spi_qup *qup = spi_master_get_devdata(master);
|
||||
int ret;
|
||||
int ret, n_words, iterations, offset = 0;
|
||||
|
||||
ret = spi_qup_set_state(qup, QUP_STATE_RUN);
|
||||
if (ret) {
|
||||
dev_warn(qup->dev, "cannot set RUN state\n");
|
||||
return ret;
|
||||
}
|
||||
n_words = qup->n_words;
|
||||
iterations = n_words / SPI_MAX_XFER; /* round down */
|
||||
qup->rx_buf = xfer->rx_buf;
|
||||
qup->tx_buf = xfer->tx_buf;
|
||||
|
||||
ret = spi_qup_set_state(qup, QUP_STATE_PAUSE);
|
||||
if (ret) {
|
||||
dev_warn(qup->dev, "cannot set PAUSE state\n");
|
||||
return ret;
|
||||
}
|
||||
do {
|
||||
if (iterations)
|
||||
qup->n_words = SPI_MAX_XFER;
|
||||
else
|
||||
qup->n_words = n_words % SPI_MAX_XFER;
|
||||
|
||||
spi_qup_fifo_write(qup, xfer);
|
||||
if (qup->tx_buf && offset)
|
||||
qup->tx_buf = xfer->tx_buf + offset * SPI_MAX_XFER;
|
||||
|
||||
if (qup->rx_buf && offset)
|
||||
qup->rx_buf = xfer->rx_buf + offset * SPI_MAX_XFER;
|
||||
|
||||
/*
|
||||
* if the transaction is small enough, we need
|
||||
* to fallback to FIFO mode
|
||||
*/
|
||||
if (qup->n_words <= (qup->in_fifo_sz / sizeof(u32)))
|
||||
qup->mode = QUP_IO_M_MODE_FIFO;
|
||||
|
||||
ret = spi_qup_io_config(spi, xfer);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = spi_qup_set_state(qup, QUP_STATE_RUN);
|
||||
if (ret) {
|
||||
dev_warn(qup->dev, "cannot set RUN state\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = spi_qup_set_state(qup, QUP_STATE_PAUSE);
|
||||
if (ret) {
|
||||
dev_warn(qup->dev, "cannot set PAUSE state\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (qup->mode == QUP_IO_M_MODE_FIFO)
|
||||
spi_qup_write(qup);
|
||||
|
||||
ret = spi_qup_set_state(qup, QUP_STATE_RUN);
|
||||
if (ret) {
|
||||
dev_warn(qup->dev, "cannot set RUN state\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (!wait_for_completion_timeout(&qup->done, timeout))
|
||||
return -ETIMEDOUT;
|
||||
|
||||
offset++;
|
||||
} while (iterations--);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -378,29 +578,15 @@ static int spi_qup_do_pio(struct spi_master *master, struct spi_transfer *xfer)
|
|||
static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id)
|
||||
{
|
||||
struct spi_qup *controller = dev_id;
|
||||
struct spi_transfer *xfer;
|
||||
u32 opflags, qup_err, spi_err;
|
||||
unsigned long flags;
|
||||
int error = 0;
|
||||
|
||||
spin_lock_irqsave(&controller->lock, flags);
|
||||
xfer = controller->xfer;
|
||||
controller->xfer = NULL;
|
||||
spin_unlock_irqrestore(&controller->lock, flags);
|
||||
|
||||
qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS);
|
||||
spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS);
|
||||
opflags = readl_relaxed(controller->base + QUP_OPERATIONAL);
|
||||
|
||||
writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS);
|
||||
writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS);
|
||||
writel_relaxed(opflags, controller->base + QUP_OPERATIONAL);
|
||||
|
||||
if (!xfer) {
|
||||
dev_err_ratelimited(controller->dev, "unexpected irq %08x %08x %08x\n",
|
||||
qup_err, spi_err, opflags);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
if (qup_err) {
|
||||
if (qup_err & QUP_ERROR_OUTPUT_OVER_RUN)
|
||||
|
|
@ -424,54 +610,27 @@ static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id)
|
|||
error = -EIO;
|
||||
}
|
||||
|
||||
if (!controller->use_dma) {
|
||||
if (spi_qup_is_dma_xfer(controller->mode)) {
|
||||
writel_relaxed(opflags, controller->base + QUP_OPERATIONAL);
|
||||
} else {
|
||||
if (opflags & QUP_OP_IN_SERVICE_FLAG)
|
||||
spi_qup_fifo_read(controller, xfer);
|
||||
spi_qup_read(controller, &opflags);
|
||||
|
||||
if (opflags & QUP_OP_OUT_SERVICE_FLAG)
|
||||
spi_qup_fifo_write(controller, xfer);
|
||||
spi_qup_write(controller);
|
||||
}
|
||||
|
||||
spin_lock_irqsave(&controller->lock, flags);
|
||||
controller->error = error;
|
||||
controller->xfer = xfer;
|
||||
spin_unlock_irqrestore(&controller->lock, flags);
|
||||
|
||||
if (controller->rx_bytes == xfer->len || error)
|
||||
if ((opflags & QUP_OP_MAX_INPUT_DONE_FLAG) || error)
|
||||
complete(&controller->done);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static u32
|
||||
spi_qup_get_mode(struct spi_master *master, struct spi_transfer *xfer)
|
||||
{
|
||||
struct spi_qup *qup = spi_master_get_devdata(master);
|
||||
u32 mode;
|
||||
|
||||
qup->w_size = 4;
|
||||
|
||||
if (xfer->bits_per_word <= 8)
|
||||
qup->w_size = 1;
|
||||
else if (xfer->bits_per_word <= 16)
|
||||
qup->w_size = 2;
|
||||
|
||||
qup->n_words = xfer->len / qup->w_size;
|
||||
|
||||
if (qup->n_words <= (qup->in_fifo_sz / sizeof(u32)))
|
||||
mode = QUP_IO_M_MODE_FIFO;
|
||||
else
|
||||
mode = QUP_IO_M_MODE_BLOCK;
|
||||
|
||||
return mode;
|
||||
}
|
||||
|
||||
/* set clock freq ... bits per word */
|
||||
static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
|
||||
/* set clock freq ... bits per word, determine mode */
|
||||
static int spi_qup_io_prep(struct spi_device *spi, struct spi_transfer *xfer)
|
||||
{
|
||||
struct spi_qup *controller = spi_master_get_devdata(spi->master);
|
||||
u32 config, iomode, mode, control;
|
||||
int ret, n_words;
|
||||
int ret;
|
||||
|
||||
if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) {
|
||||
dev_err(controller->dev, "too big size for loopback %d > %d\n",
|
||||
|
|
@ -486,30 +645,59 @@ static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
|
|||
return -EIO;
|
||||
}
|
||||
|
||||
controller->w_size = DIV_ROUND_UP(xfer->bits_per_word, 8);
|
||||
controller->n_words = xfer->len / controller->w_size;
|
||||
|
||||
if (controller->n_words <= (controller->in_fifo_sz / sizeof(u32)))
|
||||
controller->mode = QUP_IO_M_MODE_FIFO;
|
||||
else if (spi->master->can_dma &&
|
||||
spi->master->can_dma(spi->master, spi, xfer) &&
|
||||
spi->master->cur_msg_mapped)
|
||||
controller->mode = QUP_IO_M_MODE_BAM;
|
||||
else
|
||||
controller->mode = QUP_IO_M_MODE_BLOCK;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* prep qup for another spi transaction of specific type */
|
||||
static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
|
||||
{
|
||||
struct spi_qup *controller = spi_master_get_devdata(spi->master);
|
||||
u32 config, iomode, control;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&controller->lock, flags);
|
||||
controller->xfer = xfer;
|
||||
controller->error = 0;
|
||||
controller->rx_bytes = 0;
|
||||
controller->tx_bytes = 0;
|
||||
spin_unlock_irqrestore(&controller->lock, flags);
|
||||
|
||||
|
||||
if (spi_qup_set_state(controller, QUP_STATE_RESET)) {
|
||||
dev_err(controller->dev, "cannot set RESET state\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
mode = spi_qup_get_mode(spi->master, xfer);
|
||||
n_words = controller->n_words;
|
||||
|
||||
if (mode == QUP_IO_M_MODE_FIFO) {
|
||||
writel_relaxed(n_words, controller->base + QUP_MX_READ_CNT);
|
||||
writel_relaxed(n_words, controller->base + QUP_MX_WRITE_CNT);
|
||||
switch (controller->mode) {
|
||||
case QUP_IO_M_MODE_FIFO:
|
||||
writel_relaxed(controller->n_words,
|
||||
controller->base + QUP_MX_READ_CNT);
|
||||
writel_relaxed(controller->n_words,
|
||||
controller->base + QUP_MX_WRITE_CNT);
|
||||
/* must be zero for FIFO */
|
||||
writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
|
||||
writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
|
||||
} else if (!controller->use_dma) {
|
||||
writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT);
|
||||
writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT);
|
||||
break;
|
||||
case QUP_IO_M_MODE_BAM:
|
||||
writel_relaxed(controller->n_words,
|
||||
controller->base + QUP_MX_INPUT_CNT);
|
||||
writel_relaxed(controller->n_words,
|
||||
controller->base + QUP_MX_OUTPUT_CNT);
|
||||
/* must be zero for BLOCK and BAM */
|
||||
writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
|
||||
writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
|
||||
} else {
|
||||
mode = QUP_IO_M_MODE_BAM;
|
||||
writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
|
||||
writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
|
||||
|
||||
if (!controller->qup_v1) {
|
||||
void __iomem *input_cnt;
|
||||
|
|
@ -524,23 +712,38 @@ static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
|
|||
if (xfer->tx_buf)
|
||||
writel_relaxed(0, input_cnt);
|
||||
else
|
||||
writel_relaxed(n_words, input_cnt);
|
||||
writel_relaxed(controller->n_words, input_cnt);
|
||||
|
||||
writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
|
||||
}
|
||||
break;
|
||||
case QUP_IO_M_MODE_BLOCK:
|
||||
reinit_completion(&controller->done);
|
||||
writel_relaxed(controller->n_words,
|
||||
controller->base + QUP_MX_INPUT_CNT);
|
||||
writel_relaxed(controller->n_words,
|
||||
controller->base + QUP_MX_OUTPUT_CNT);
|
||||
/* must be zero for BLOCK and BAM */
|
||||
writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
|
||||
writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
|
||||
break;
|
||||
default:
|
||||
dev_err(controller->dev, "unknown mode = %d\n",
|
||||
controller->mode);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
iomode = readl_relaxed(controller->base + QUP_IO_M_MODES);
|
||||
/* Set input and output transfer mode */
|
||||
iomode &= ~(QUP_IO_M_INPUT_MODE_MASK | QUP_IO_M_OUTPUT_MODE_MASK);
|
||||
|
||||
if (!controller->use_dma)
|
||||
if (!spi_qup_is_dma_xfer(controller->mode))
|
||||
iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN);
|
||||
else
|
||||
iomode |= QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN;
|
||||
|
||||
iomode |= (mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT);
|
||||
iomode |= (mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT);
|
||||
iomode |= (controller->mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT);
|
||||
iomode |= (controller->mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT);
|
||||
|
||||
writel_relaxed(iomode, controller->base + QUP_IO_M_MODES);
|
||||
|
||||
|
|
@ -581,7 +784,7 @@ static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
|
|||
config |= xfer->bits_per_word - 1;
|
||||
config |= QUP_CONFIG_SPI_MODE;
|
||||
|
||||
if (controller->use_dma) {
|
||||
if (spi_qup_is_dma_xfer(controller->mode)) {
|
||||
if (!xfer->tx_buf)
|
||||
config |= QUP_CONFIG_NO_OUTPUT;
|
||||
if (!xfer->rx_buf)
|
||||
|
|
@ -599,7 +802,7 @@ static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
|
|||
* status change in BAM mode
|
||||
*/
|
||||
|
||||
if (mode == QUP_IO_M_MODE_BAM)
|
||||
if (spi_qup_is_dma_xfer(controller->mode))
|
||||
mask = QUP_OP_IN_SERVICE_FLAG | QUP_OP_OUT_SERVICE_FLAG;
|
||||
|
||||
writel_relaxed(mask, controller->base + QUP_OPERATIONAL_MASK);
|
||||
|
|
@ -616,12 +819,13 @@ static int spi_qup_transfer_one(struct spi_master *master,
|
|||
unsigned long timeout, flags;
|
||||
int ret = -EIO;
|
||||
|
||||
ret = spi_qup_io_config(spi, xfer);
|
||||
ret = spi_qup_io_prep(spi, xfer);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
timeout = DIV_ROUND_UP(xfer->speed_hz, MSEC_PER_SEC);
|
||||
timeout = DIV_ROUND_UP(xfer->len * 8, timeout);
|
||||
timeout = DIV_ROUND_UP(min_t(unsigned long, SPI_MAX_XFER,
|
||||
xfer->len) * 8, timeout);
|
||||
timeout = 100 * msecs_to_jiffies(timeout);
|
||||
|
||||
reinit_completion(&controller->done);
|
||||
|
|
@ -633,31 +837,22 @@ static int spi_qup_transfer_one(struct spi_master *master,
|
|||
controller->tx_bytes = 0;
|
||||
spin_unlock_irqrestore(&controller->lock, flags);
|
||||
|
||||
if (controller->use_dma)
|
||||
ret = spi_qup_do_dma(master, xfer);
|
||||
if (spi_qup_is_dma_xfer(controller->mode))
|
||||
ret = spi_qup_do_dma(spi, xfer, timeout);
|
||||
else
|
||||
ret = spi_qup_do_pio(master, xfer);
|
||||
ret = spi_qup_do_pio(spi, xfer, timeout);
|
||||
|
||||
if (ret)
|
||||
goto exit;
|
||||
|
||||
if (spi_qup_set_state(controller, QUP_STATE_RUN)) {
|
||||
dev_warn(controller->dev, "cannot set EXECUTE state\n");
|
||||
goto exit;
|
||||
}
|
||||
|
||||
if (!wait_for_completion_timeout(&controller->done, timeout))
|
||||
ret = -ETIMEDOUT;
|
||||
|
||||
exit:
|
||||
spi_qup_set_state(controller, QUP_STATE_RESET);
|
||||
spin_lock_irqsave(&controller->lock, flags);
|
||||
controller->xfer = NULL;
|
||||
if (!ret)
|
||||
ret = controller->error;
|
||||
spin_unlock_irqrestore(&controller->lock, flags);
|
||||
|
||||
if (ret && controller->use_dma)
|
||||
if (ret && spi_qup_is_dma_xfer(controller->mode))
|
||||
spi_qup_dma_terminate(master, xfer);
|
||||
|
||||
return ret;
|
||||
|
|
@ -668,26 +863,28 @@ static bool spi_qup_can_dma(struct spi_master *master, struct spi_device *spi,
|
|||
{
|
||||
struct spi_qup *qup = spi_master_get_devdata(master);
|
||||
size_t dma_align = dma_get_cache_alignment();
|
||||
u32 mode;
|
||||
int n_words;
|
||||
|
||||
qup->use_dma = 0;
|
||||
if (xfer->rx_buf) {
|
||||
if (!IS_ALIGNED((size_t)xfer->rx_buf, dma_align) ||
|
||||
IS_ERR_OR_NULL(master->dma_rx))
|
||||
return false;
|
||||
if (qup->qup_v1 && (xfer->len % qup->in_blk_sz))
|
||||
return false;
|
||||
}
|
||||
|
||||
if (xfer->rx_buf && (xfer->len % qup->in_blk_sz ||
|
||||
IS_ERR_OR_NULL(master->dma_rx) ||
|
||||
!IS_ALIGNED((size_t)xfer->rx_buf, dma_align)))
|
||||
if (xfer->tx_buf) {
|
||||
if (!IS_ALIGNED((size_t)xfer->tx_buf, dma_align) ||
|
||||
IS_ERR_OR_NULL(master->dma_tx))
|
||||
return false;
|
||||
if (qup->qup_v1 && (xfer->len % qup->out_blk_sz))
|
||||
return false;
|
||||
}
|
||||
|
||||
n_words = xfer->len / DIV_ROUND_UP(xfer->bits_per_word, 8);
|
||||
if (n_words <= (qup->in_fifo_sz / sizeof(u32)))
|
||||
return false;
|
||||
|
||||
if (xfer->tx_buf && (xfer->len % qup->out_blk_sz ||
|
||||
IS_ERR_OR_NULL(master->dma_tx) ||
|
||||
!IS_ALIGNED((size_t)xfer->tx_buf, dma_align)))
|
||||
return false;
|
||||
|
||||
mode = spi_qup_get_mode(master, xfer);
|
||||
if (mode == QUP_IO_M_MODE_FIFO)
|
||||
return false;
|
||||
|
||||
qup->use_dma = 1;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -750,6 +947,24 @@ err_tx:
|
|||
return ret;
|
||||
}
|
||||
|
||||
static void spi_qup_set_cs(struct spi_device *spi, bool val)
|
||||
{
|
||||
struct spi_qup *controller;
|
||||
u32 spi_ioc;
|
||||
u32 spi_ioc_orig;
|
||||
|
||||
controller = spi_master_get_devdata(spi->master);
|
||||
spi_ioc = readl_relaxed(controller->base + SPI_IO_CONTROL);
|
||||
spi_ioc_orig = spi_ioc;
|
||||
if (!val)
|
||||
spi_ioc |= SPI_IO_C_FORCE_CS;
|
||||
else
|
||||
spi_ioc &= ~SPI_IO_C_FORCE_CS;
|
||||
|
||||
if (spi_ioc != spi_ioc_orig)
|
||||
writel_relaxed(spi_ioc, controller->base + SPI_IO_CONTROL);
|
||||
}
|
||||
|
||||
static int spi_qup_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_master *master;
|
||||
|
|
@ -824,7 +1039,7 @@ static int spi_qup_probe(struct platform_device *pdev)
|
|||
master->dev.of_node = pdev->dev.of_node;
|
||||
master->auto_runtime_pm = true;
|
||||
master->dma_alignment = dma_get_cache_alignment();
|
||||
master->max_dma_len = SPI_MAX_DMA_XFER;
|
||||
master->max_dma_len = SPI_MAX_XFER;
|
||||
|
||||
platform_set_drvdata(pdev, master);
|
||||
|
||||
|
|
@ -842,9 +1057,10 @@ static int spi_qup_probe(struct platform_device *pdev)
|
|||
else if (!ret)
|
||||
master->can_dma = spi_qup_can_dma;
|
||||
|
||||
/* set v1 flag if device is version 1 */
|
||||
if (of_device_is_compatible(dev->of_node, "qcom,spi-qup-v1.1.1"))
|
||||
controller->qup_v1 = 1;
|
||||
controller->qup_v1 = (uintptr_t)of_device_get_match_data(dev);
|
||||
|
||||
if (!controller->qup_v1)
|
||||
master->set_cs = spi_qup_set_cs;
|
||||
|
||||
spin_lock_init(&controller->lock);
|
||||
init_completion(&controller->done);
|
||||
|
|
@ -1037,7 +1253,7 @@ static int spi_qup_remove(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
static const struct of_device_id spi_qup_dt_match[] = {
|
||||
{ .compatible = "qcom,spi-qup-v1.1.1", },
|
||||
{ .compatible = "qcom,spi-qup-v1.1.1", .data = (void *)1, },
|
||||
{ .compatible = "qcom,spi-qup-v2.1.1", },
|
||||
{ .compatible = "qcom,spi-qup-v2.2.1", },
|
||||
{ }
|
||||
|
|
|
|||
|
|
@ -568,7 +568,13 @@ static void rockchip_spi_config(struct rockchip_spi *rs)
|
|||
|
||||
writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
|
||||
|
||||
writel_relaxed(rs->len - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
|
||||
if (rs->n_bytes == 1)
|
||||
writel_relaxed(rs->len - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
|
||||
else if (rs->n_bytes == 2)
|
||||
writel_relaxed((rs->len / 2) - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
|
||||
else
|
||||
writel_relaxed((rs->len * 2) - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
|
||||
|
||||
writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_TXFTLR);
|
||||
writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
|
||||
|
||||
|
|
@ -666,7 +672,7 @@ static bool rockchip_spi_can_dma(struct spi_master *master,
|
|||
|
||||
static int rockchip_spi_probe(struct platform_device *pdev)
|
||||
{
|
||||
int ret = 0;
|
||||
int ret;
|
||||
struct rockchip_spi *rs;
|
||||
struct spi_master *master;
|
||||
struct resource *mem;
|
||||
|
|
@ -703,13 +709,13 @@ static int rockchip_spi_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
ret = clk_prepare_enable(rs->apb_pclk);
|
||||
if (ret) {
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "Failed to enable apb_pclk\n");
|
||||
goto err_put_master;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(rs->spiclk);
|
||||
if (ret) {
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "Failed to enable spi_clk\n");
|
||||
goto err_disable_apbclk;
|
||||
}
|
||||
|
|
@ -786,7 +792,7 @@ static int rockchip_spi_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
ret = devm_spi_register_master(&pdev->dev, master);
|
||||
if (ret) {
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "Failed to register master\n");
|
||||
goto err_free_dma_rx;
|
||||
}
|
||||
|
|
@ -816,11 +822,15 @@ static int rockchip_spi_remove(struct platform_device *pdev)
|
|||
struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
|
||||
struct rockchip_spi *rs = spi_master_get_devdata(master);
|
||||
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
pm_runtime_get_sync(&pdev->dev);
|
||||
|
||||
clk_disable_unprepare(rs->spiclk);
|
||||
clk_disable_unprepare(rs->apb_pclk);
|
||||
|
||||
pm_runtime_put_noidle(&pdev->dev);
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
pm_runtime_set_suspended(&pdev->dev);
|
||||
|
||||
if (rs->dma_tx.ch)
|
||||
dma_release_channel(rs->dma_tx.ch);
|
||||
if (rs->dma_rx.ch)
|
||||
|
|
@ -834,43 +844,34 @@ static int rockchip_spi_remove(struct platform_device *pdev)
|
|||
#ifdef CONFIG_PM_SLEEP
|
||||
static int rockchip_spi_suspend(struct device *dev)
|
||||
{
|
||||
int ret = 0;
|
||||
int ret;
|
||||
struct spi_master *master = dev_get_drvdata(dev);
|
||||
struct rockchip_spi *rs = spi_master_get_devdata(master);
|
||||
|
||||
ret = spi_master_suspend(rs->master);
|
||||
if (ret)
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
if (!pm_runtime_suspended(dev)) {
|
||||
clk_disable_unprepare(rs->spiclk);
|
||||
clk_disable_unprepare(rs->apb_pclk);
|
||||
}
|
||||
ret = pm_runtime_force_suspend(dev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
pinctrl_pm_select_sleep_state(dev);
|
||||
|
||||
return ret;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rockchip_spi_resume(struct device *dev)
|
||||
{
|
||||
int ret = 0;
|
||||
int ret;
|
||||
struct spi_master *master = dev_get_drvdata(dev);
|
||||
struct rockchip_spi *rs = spi_master_get_devdata(master);
|
||||
|
||||
pinctrl_pm_select_default_state(dev);
|
||||
|
||||
if (!pm_runtime_suspended(dev)) {
|
||||
ret = clk_prepare_enable(rs->apb_pclk);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = clk_prepare_enable(rs->spiclk);
|
||||
if (ret < 0) {
|
||||
clk_disable_unprepare(rs->apb_pclk);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
ret = pm_runtime_force_resume(dev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = spi_master_resume(rs->master);
|
||||
if (ret < 0) {
|
||||
|
|
@ -878,7 +879,7 @@ static int rockchip_spi_resume(struct device *dev)
|
|||
clk_disable_unprepare(rs->apb_pclk);
|
||||
}
|
||||
|
||||
return ret;
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_PM_SLEEP */
|
||||
|
||||
|
|
@ -901,14 +902,14 @@ static int rockchip_spi_runtime_resume(struct device *dev)
|
|||
struct rockchip_spi *rs = spi_master_get_devdata(master);
|
||||
|
||||
ret = clk_prepare_enable(rs->apb_pclk);
|
||||
if (ret)
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = clk_prepare_enable(rs->spiclk);
|
||||
if (ret)
|
||||
if (ret < 0)
|
||||
clk_disable_unprepare(rs->apb_pclk);
|
||||
|
||||
return ret;
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_PM */
|
||||
|
||||
|
|
@ -919,6 +920,7 @@ static const struct dev_pm_ops rockchip_spi_pm = {
|
|||
};
|
||||
|
||||
static const struct of_device_id rockchip_spi_dt_match[] = {
|
||||
{ .compatible = "rockchip,rv1108-spi", },
|
||||
{ .compatible = "rockchip,rk3036-spi", },
|
||||
{ .compatible = "rockchip,rk3066-spi", },
|
||||
{ .compatible = "rockchip,rk3188-spi", },
|
||||
|
|
|
|||
|
|
@ -446,8 +446,8 @@ static int spi_sh_probe(struct platform_device *pdev)
|
|||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0) {
|
||||
dev_err(&pdev->dev, "platform_get_irq error\n");
|
||||
return -ENODEV;
|
||||
dev_err(&pdev->dev, "platform_get_irq error: %d\n", irq);
|
||||
return irq;
|
||||
}
|
||||
|
||||
master = spi_alloc_master(&pdev->dev, sizeof(struct spi_sh_data));
|
||||
|
|
|
|||
Loading…
Reference in a new issue