Merge branch 'drm-fixes-4.6' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
Misc radeon and amdgpu bug fixes for 4.6. * 'drm-fixes-4.6' of git://people.freedesktop.org/~agd5f/linux: amdgpu/uvd: add uvd fw version for amdgpu drm/amdgpu: forbid mapping of userptr bo through radeon device file drm/radeon: forbid mapping of userptr bo through radeon device file drm/amdgpu: bump the afmt limit for CZ, ST, Polaris drm/amdgpu: use defines for CRTCs and AMFT blocks drm/radeon: print a message if ATPX dGPU power control is missing Revert "drm/radeon: disable runtime pm on PX laptops without dGPU power control" drm/amdgpu/acp: fix resume on CZ systems with AZ audio drm/radeon: add a quirk for a XFX R9 270X drm/radeon: print pci revision as well as pci ids on driver load drm/amdgpu: when suspending, if uvd/vce was running. need to cancel delay work. drm/radeon: fix initial connector audio value
This commit is contained in:
commit
18cdfe751f
12 changed files with 37 additions and 19 deletions
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@ -1591,6 +1591,7 @@ struct amdgpu_uvd {
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struct amdgpu_bo *vcpu_bo;
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void *cpu_addr;
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uint64_t gpu_addr;
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unsigned fw_version;
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void *saved_bo;
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atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
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struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
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@ -425,6 +425,10 @@ static int acp_resume(void *handle)
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struct acp_pm_domain *apd;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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/* return early if no ACP */
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if (!adev->acp.acp_genpd)
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return 0;
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/* SMU block will power on ACP irrespective of ACP runtime status.
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* Power off explicitly based on genpd ACP runtime status so that ACP
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* hw and ACP-genpd status are in sync.
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@ -303,7 +303,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
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fw_info.feature = adev->vce.fb_version;
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break;
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case AMDGPU_INFO_FW_UVD:
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fw_info.ver = 0;
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fw_info.ver = adev->uvd.fw_version;
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fw_info.feature = 0;
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break;
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case AMDGPU_INFO_FW_GMC:
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@ -53,7 +53,7 @@ struct amdgpu_hpd;
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#define AMDGPU_MAX_HPD_PINS 6
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#define AMDGPU_MAX_CRTCS 6
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#define AMDGPU_MAX_AFMT_BLOCKS 7
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#define AMDGPU_MAX_AFMT_BLOCKS 9
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enum amdgpu_rmx_type {
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RMX_OFF,
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@ -309,8 +309,8 @@ struct amdgpu_mode_info {
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struct atom_context *atom_context;
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struct card_info *atom_card_info;
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bool mode_config_initialized;
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struct amdgpu_crtc *crtcs[6];
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struct amdgpu_afmt *afmt[7];
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struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
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struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];
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/* DVI-I properties */
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struct drm_property *coherent_mode_property;
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/* DAC enable load detect */
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@ -223,6 +223,8 @@ static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
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{
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struct amdgpu_bo *rbo = container_of(bo, struct amdgpu_bo, tbo);
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if (amdgpu_ttm_tt_get_usermm(bo->ttm))
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return -EPERM;
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return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);
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}
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@ -158,6 +158,9 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
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DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
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version_major, version_minor, family_id);
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adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) |
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(family_id << 8));
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bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
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+ AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE;
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r = amdgpu_bo_create(adev, bo_size, PAGE_SIZE, true,
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@ -255,6 +258,8 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev)
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if (i == AMDGPU_MAX_UVD_HANDLES)
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return 0;
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cancel_delayed_work_sync(&adev->uvd.idle_work);
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size = amdgpu_bo_size(adev->uvd.vcpu_bo);
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ptr = adev->uvd.cpu_addr;
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@ -234,6 +234,7 @@ int amdgpu_vce_suspend(struct amdgpu_device *adev)
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if (i == AMDGPU_MAX_VCE_HANDLES)
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return 0;
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cancel_delayed_work_sync(&adev->vce.idle_work);
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/* TODO: suspending running encoding sessions isn't supported */
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return -EINVAL;
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}
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@ -62,10 +62,6 @@ bool radeon_has_atpx(void) {
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return radeon_atpx_priv.atpx_detected;
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}
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bool radeon_has_atpx_dgpu_power_cntl(void) {
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return radeon_atpx_priv.atpx.functions.power_cntl;
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}
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/**
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* radeon_atpx_call - call an ATPX method
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*
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@ -145,6 +141,13 @@ static void radeon_atpx_parse_functions(struct radeon_atpx_functions *f, u32 mas
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*/
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static int radeon_atpx_validate(struct radeon_atpx *atpx)
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{
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/* make sure required functions are enabled */
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/* dGPU power control is required */
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if (atpx->functions.power_cntl == false) {
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printk("ATPX dGPU power cntl not present, forcing\n");
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atpx->functions.power_cntl = true;
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}
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if (atpx->functions.px_params) {
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union acpi_object *info;
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struct atpx_px_params output;
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@ -2002,10 +2002,12 @@ radeon_add_atom_connector(struct drm_device *dev,
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rdev->mode_info.dither_property,
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RADEON_FMT_DITHER_DISABLE);
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if (radeon_audio != 0)
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if (radeon_audio != 0) {
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drm_object_attach_property(&radeon_connector->base.base,
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rdev->mode_info.audio_property,
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RADEON_AUDIO_AUTO);
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radeon_connector->audio = RADEON_AUDIO_AUTO;
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}
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if (ASIC_IS_DCE5(rdev))
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drm_object_attach_property(&radeon_connector->base.base,
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rdev->mode_info.output_csc_property,
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@ -2130,6 +2132,7 @@ radeon_add_atom_connector(struct drm_device *dev,
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drm_object_attach_property(&radeon_connector->base.base,
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rdev->mode_info.audio_property,
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RADEON_AUDIO_AUTO);
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radeon_connector->audio = RADEON_AUDIO_AUTO;
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}
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if (connector_type == DRM_MODE_CONNECTOR_DVII) {
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radeon_connector->dac_load_detect = true;
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@ -2185,6 +2188,7 @@ radeon_add_atom_connector(struct drm_device *dev,
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drm_object_attach_property(&radeon_connector->base.base,
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rdev->mode_info.audio_property,
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RADEON_AUDIO_AUTO);
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radeon_connector->audio = RADEON_AUDIO_AUTO;
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}
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if (ASIC_IS_DCE5(rdev))
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drm_object_attach_property(&radeon_connector->base.base,
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@ -2237,6 +2241,7 @@ radeon_add_atom_connector(struct drm_device *dev,
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drm_object_attach_property(&radeon_connector->base.base,
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rdev->mode_info.audio_property,
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RADEON_AUDIO_AUTO);
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radeon_connector->audio = RADEON_AUDIO_AUTO;
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}
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if (ASIC_IS_DCE5(rdev))
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drm_object_attach_property(&radeon_connector->base.base,
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@ -103,12 +103,6 @@ static const char radeon_family_name[][16] = {
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"LAST",
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};
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#if defined(CONFIG_VGA_SWITCHEROO)
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bool radeon_has_atpx_dgpu_power_cntl(void);
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#else
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static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
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#endif
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#define RADEON_PX_QUIRK_DISABLE_PX (1 << 0)
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#define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1)
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@ -1305,9 +1299,9 @@ int radeon_device_init(struct radeon_device *rdev,
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}
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rdev->fence_context = fence_context_alloc(RADEON_NUM_RINGS);
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DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
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radeon_family_name[rdev->family], pdev->vendor, pdev->device,
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pdev->subsystem_vendor, pdev->subsystem_device);
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DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
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radeon_family_name[rdev->family], pdev->vendor, pdev->device,
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pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
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/* mutex initialization are all done here so we
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* can recall function without having locking issues */
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@ -1439,7 +1433,7 @@ int radeon_device_init(struct radeon_device *rdev,
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* ignore it */
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vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
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if ((rdev->flags & RADEON_IS_PX) && radeon_has_atpx_dgpu_power_cntl())
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if (rdev->flags & RADEON_IS_PX)
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runtime = true;
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vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, runtime);
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if (runtime)
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@ -235,6 +235,8 @@ static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp)
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{
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struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
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if (radeon_ttm_tt_has_userptr(bo->ttm))
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return -EPERM;
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return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);
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}
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@ -2931,6 +2931,7 @@ static struct si_dpm_quirk si_dpm_quirk_list[] = {
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{ PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 },
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{ PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 },
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{ PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 },
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{ PCI_VENDOR_ID_ATI, 0x6810, 0x1682, 0x9275, 0, 120000 },
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{ 0, 0, 0, 0 },
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};
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