amd64_edac: add F10h-and-later methods-p1
Borislav: Fail f10_early_channel_count() if error encountered while reading a NB register since those cached register contents are accessed afterwards. - fix/cleanup comments - fix function return value patterns - cleanup debug calls Reviewed-by: Mauro Carvalho Chehab <mchehab@redhat.com> Signed-off-by: Doug Thompson <dougthompson@xmission.com> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
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@ -1185,4 +1185,185 @@ static int k8_dbam_map_to_pages(struct amd64_pvt *pvt, int dram_map)
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return nr_pages;
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}
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/*
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* Get the number of DCT channels in use.
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*
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* Return:
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* number of Memory Channels in operation
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* Pass back:
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* contents of the DCL0_LOW register
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*/
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static int f10_early_channel_count(struct amd64_pvt *pvt)
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{
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int err = 0, channels = 0;
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u32 dbam;
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err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCLR_0, &pvt->dclr0);
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if (err)
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goto err_reg;
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err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCLR_1, &pvt->dclr1);
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if (err)
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goto err_reg;
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/* If we are in 128 bit mode, then we are using 2 channels */
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if (pvt->dclr0 & F10_WIDTH_128) {
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debugf0("Data WIDTH is 128 bits - 2 channels\n");
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channels = 2;
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return channels;
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}
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/*
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* Need to check if in UN-ganged mode: In such, there are 2 channels,
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* but they are NOT in 128 bit mode and thus the above 'dcl0' status bit
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* will be OFF.
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*
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* Need to check DCT0[0] and DCT1[0] to see if only one of them has
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* their CSEnable bit on. If so, then SINGLE DIMM case.
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*/
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debugf0("Data WIDTH is NOT 128 bits - need more decoding\n");
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/*
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* Check DRAM Bank Address Mapping values for each DIMM to see if there
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* is more than just one DIMM present in unganged mode. Need to check
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* both controllers since DIMMs can be placed in either one.
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*/
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channels = 0;
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err = pci_read_config_dword(pvt->dram_f2_ctl, DBAM0, &dbam);
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if (err)
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goto err_reg;
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if (DBAM_DIMM(0, dbam) > 0)
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channels++;
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if (DBAM_DIMM(1, dbam) > 0)
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channels++;
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if (DBAM_DIMM(2, dbam) > 0)
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channels++;
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if (DBAM_DIMM(3, dbam) > 0)
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channels++;
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/* If more than 2 DIMMs are present, then we have 2 channels */
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if (channels > 2)
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channels = 2;
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else if (channels == 0) {
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/* No DIMMs on DCT0, so look at DCT1 */
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err = pci_read_config_dword(pvt->dram_f2_ctl, DBAM1, &dbam);
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if (err)
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goto err_reg;
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if (DBAM_DIMM(0, dbam) > 0)
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channels++;
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if (DBAM_DIMM(1, dbam) > 0)
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channels++;
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if (DBAM_DIMM(2, dbam) > 0)
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channels++;
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if (DBAM_DIMM(3, dbam) > 0)
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channels++;
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if (channels > 2)
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channels = 2;
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}
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/* If we found ALL 0 values, then assume just ONE DIMM-ONE Channel */
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if (channels == 0)
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channels = 1;
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debugf0("DIMM count= %d\n", channels);
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return channels;
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err_reg:
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return -1;
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}
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static int f10_dbam_map_to_pages(struct amd64_pvt *pvt, int dram_map)
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{
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return 1 << (revf_quad_ddr2_shift[dram_map] - PAGE_SHIFT);
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}
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/* Enable extended configuration access via 0xCF8 feature */
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static void amd64_setup(struct amd64_pvt *pvt)
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{
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u32 reg;
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pci_read_config_dword(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, ®);
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pvt->flags.cf8_extcfg = !!(reg & F10_NB_CFG_LOW_ENABLE_EXT_CFG);
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reg |= F10_NB_CFG_LOW_ENABLE_EXT_CFG;
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pci_write_config_dword(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, reg);
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}
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/* Restore the extended configuration access via 0xCF8 feature */
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static void amd64_teardown(struct amd64_pvt *pvt)
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{
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u32 reg;
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pci_read_config_dword(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, ®);
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reg &= ~F10_NB_CFG_LOW_ENABLE_EXT_CFG;
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if (pvt->flags.cf8_extcfg)
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reg |= F10_NB_CFG_LOW_ENABLE_EXT_CFG;
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pci_write_config_dword(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, reg);
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}
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static u64 f10_get_error_address(struct mem_ctl_info *mci,
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struct amd64_error_info_regs *info)
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{
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return (((u64) (info->nbeah & 0xffff)) << 32) +
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(info->nbeal & ~0x01);
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}
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/*
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* Read the Base and Limit registers for F10 based Memory controllers. Extract
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* fields from the 'raw' reg into separate data fields.
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*
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* Isolates: BASE, LIMIT, IntlvEn, IntlvSel, RW_EN.
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*/
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static void f10_read_dram_base_limit(struct amd64_pvt *pvt, int dram)
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{
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u32 high_offset, low_offset, high_base, low_base, high_limit, low_limit;
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low_offset = K8_DRAM_BASE_LOW + (dram << 3);
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high_offset = F10_DRAM_BASE_HIGH + (dram << 3);
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/* read the 'raw' DRAM BASE Address register */
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pci_read_config_dword(pvt->addr_f1_ctl, low_offset, &low_base);
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/* Read from the ECS data register */
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pci_read_config_dword(pvt->addr_f1_ctl, high_offset, &high_base);
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/* Extract parts into separate data entries */
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pvt->dram_rw_en[dram] = (low_base & 0x3);
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if (pvt->dram_rw_en[dram] == 0)
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return;
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pvt->dram_IntlvEn[dram] = (low_base >> 8) & 0x7;
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pvt->dram_base[dram] = (((((u64) high_base & 0x000000FF) << 32) |
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((u64) low_base & 0xFFFF0000))) << 8;
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low_offset = K8_DRAM_LIMIT_LOW + (dram << 3);
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high_offset = F10_DRAM_LIMIT_HIGH + (dram << 3);
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/* read the 'raw' LIMIT registers */
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pci_read_config_dword(pvt->addr_f1_ctl, low_offset, &low_limit);
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/* Read from the ECS data register for the HIGH portion */
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pci_read_config_dword(pvt->addr_f1_ctl, high_offset, &high_limit);
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debugf0(" HW Regs: BASE=0x%08x-%08x LIMIT= 0x%08x-%08x\n",
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high_base, low_base, high_limit, low_limit);
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pvt->dram_DstNode[dram] = (low_limit & 0x7);
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pvt->dram_IntlvSel[dram] = (low_limit >> 8) & 0x7;
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/*
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* Extract address values and form a LIMIT address. Limit is the HIGHEST
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* memory location of the region, so low 24 bits need to be all ones.
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*/
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low_limit |= 0x0000FFFF;
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pvt->dram_limit[dram] =
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((((u64) high_limit << 32) + (u64) low_limit) << 8) | (0xFF);
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}
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