dma40: Improve the logic of stopping logical chan
can be directly stopped by issuing a SUSPEND_REQ on the EE bits. There is no need to suspend the physical channel and restart it. Also, the support for pre-V2 hw is discontinued. EE bits for writing: 00: disable only if AS=11 or AS=00 01: enable 10: suspend_req only if AS=01 & EE=01 or EE=11 11: round / no change for writing Signed-off-by: Narayanan G <narayanan.gopalakrishnan@stericsson.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
This commit is contained in:
Narayanan G
Vinod Koul
parent
ed8b0d67f3
commit
1bdae6f49c
2 changed files with 202 additions and 126 deletions
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@ -68,6 +68,22 @@ enum d40_command {
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D40_DMA_SUSPENDED = 3
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};
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/*
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* enum d40_events - The different Event Enables for the event lines.
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*
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* @D40_DEACTIVATE_EVENTLINE: De-activate Event line, stopping the logical chan.
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* @D40_ACTIVATE_EVENTLINE: Activate the Event line, to start a logical chan.
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* @D40_SUSPEND_REQ_EVENTLINE: Requesting for suspending a event line.
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* @D40_ROUND_EVENTLINE: Status check for event line.
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*/
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enum d40_events {
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D40_DEACTIVATE_EVENTLINE = 0,
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D40_ACTIVATE_EVENTLINE = 1,
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D40_SUSPEND_REQ_EVENTLINE = 2,
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D40_ROUND_EVENTLINE = 3
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};
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/*
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* These are the registers that has to be saved and later restored
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* when the DMA hw is powered off.
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@ -870,8 +886,8 @@ static void d40_save_restore_registers(struct d40_base *base, bool save)
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}
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#endif
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static int d40_channel_execute_command(struct d40_chan *d40c,
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enum d40_command command)
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static int __d40_execute_command_phy(struct d40_chan *d40c,
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enum d40_command command)
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{
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u32 status;
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int i;
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@ -880,6 +896,12 @@ static int d40_channel_execute_command(struct d40_chan *d40c,
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unsigned long flags;
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u32 wmask;
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if (command == D40_DMA_STOP) {
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ret = __d40_execute_command_phy(d40c, D40_DMA_SUSPEND_REQ);
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if (ret)
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return ret;
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}
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spin_lock_irqsave(&d40c->base->execmd_lock, flags);
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if (d40c->phy_chan->num % 2 == 0)
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@ -973,67 +995,109 @@ static void d40_term_all(struct d40_chan *d40c)
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}
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d40c->pending_tx = 0;
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d40c->busy = false;
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}
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static void __d40_config_set_event(struct d40_chan *d40c, bool enable,
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u32 event, int reg)
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static void __d40_config_set_event(struct d40_chan *d40c,
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enum d40_events event_type, u32 event,
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int reg)
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{
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void __iomem *addr = chan_base(d40c) + reg;
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int tries;
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u32 status;
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switch (event_type) {
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case D40_DEACTIVATE_EVENTLINE:
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if (!enable) {
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writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
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| ~D40_EVENTLINE_MASK(event), addr);
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return;
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}
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break;
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case D40_SUSPEND_REQ_EVENTLINE:
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status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
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D40_EVENTLINE_POS(event);
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if (status == D40_DEACTIVATE_EVENTLINE ||
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status == D40_SUSPEND_REQ_EVENTLINE)
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break;
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writel((D40_SUSPEND_REQ_EVENTLINE << D40_EVENTLINE_POS(event))
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| ~D40_EVENTLINE_MASK(event), addr);
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for (tries = 0 ; tries < D40_SUSPEND_MAX_IT; tries++) {
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status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
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D40_EVENTLINE_POS(event);
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cpu_relax();
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/*
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* Reduce the number of bus accesses while
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* waiting for the DMA to suspend.
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*/
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udelay(3);
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if (status == D40_DEACTIVATE_EVENTLINE)
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break;
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}
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if (tries == D40_SUSPEND_MAX_IT) {
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chan_err(d40c,
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"unable to stop the event_line chl %d (log: %d)"
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"status %x\n", d40c->phy_chan->num,
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d40c->log_num, status);
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}
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break;
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case D40_ACTIVATE_EVENTLINE:
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/*
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* The hardware sometimes doesn't register the enable when src and dst
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* event lines are active on the same logical channel. Retry to ensure
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* it does. Usually only one retry is sufficient.
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*/
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tries = 100;
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while (--tries) {
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writel((D40_ACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
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| ~D40_EVENTLINE_MASK(event), addr);
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tries = 100;
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while (--tries) {
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writel((D40_ACTIVATE_EVENTLINE <<
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D40_EVENTLINE_POS(event)) |
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~D40_EVENTLINE_MASK(event), addr);
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if (readl(addr) & D40_EVENTLINE_MASK(event))
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break;
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}
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if (tries != 99)
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dev_dbg(chan2dev(d40c),
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"[%s] workaround enable S%cLNK (%d tries)\n",
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__func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
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100 - tries);
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WARN_ON(!tries);
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break;
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case D40_ROUND_EVENTLINE:
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BUG();
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break;
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if (readl(addr) & D40_EVENTLINE_MASK(event))
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break;
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}
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if (tries != 99)
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dev_dbg(chan2dev(d40c),
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"[%s] workaround enable S%cLNK (%d tries)\n",
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__func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
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100 - tries);
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WARN_ON(!tries);
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}
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static void d40_config_set_event(struct d40_chan *d40c, bool do_enable)
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static void d40_config_set_event(struct d40_chan *d40c,
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enum d40_events event_type)
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{
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unsigned long flags;
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spin_lock_irqsave(&d40c->phy_chan->lock, flags);
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/* Enable event line connected to device (or memcpy) */
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if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
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(d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) {
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u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
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__d40_config_set_event(d40c, do_enable, event,
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__d40_config_set_event(d40c, event_type, event,
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D40_CHAN_REG_SSLNK);
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}
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if (d40c->dma_cfg.dir != STEDMA40_PERIPH_TO_MEM) {
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u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
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__d40_config_set_event(d40c, do_enable, event,
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__d40_config_set_event(d40c, event_type, event,
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D40_CHAN_REG_SDLNK);
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}
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spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
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}
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static u32 d40_chan_has_events(struct d40_chan *d40c)
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@ -1047,6 +1111,64 @@ static u32 d40_chan_has_events(struct d40_chan *d40c)
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return val;
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}
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static int
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__d40_execute_command_log(struct d40_chan *d40c, enum d40_command command)
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{
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unsigned long flags;
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int ret = 0;
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u32 active_status;
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void __iomem *active_reg;
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if (d40c->phy_chan->num % 2 == 0)
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active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
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else
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active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
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spin_lock_irqsave(&d40c->phy_chan->lock, flags);
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switch (command) {
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case D40_DMA_STOP:
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case D40_DMA_SUSPEND_REQ:
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active_status = (readl(active_reg) &
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D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
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D40_CHAN_POS(d40c->phy_chan->num);
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if (active_status == D40_DMA_RUN)
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d40_config_set_event(d40c, D40_SUSPEND_REQ_EVENTLINE);
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else
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d40_config_set_event(d40c, D40_DEACTIVATE_EVENTLINE);
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if (!d40_chan_has_events(d40c) && (command == D40_DMA_STOP))
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ret = __d40_execute_command_phy(d40c, command);
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break;
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case D40_DMA_RUN:
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d40_config_set_event(d40c, D40_ACTIVATE_EVENTLINE);
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ret = __d40_execute_command_phy(d40c, command);
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break;
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case D40_DMA_SUSPENDED:
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BUG();
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break;
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}
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spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
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return ret;
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}
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static int d40_channel_execute_command(struct d40_chan *d40c,
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enum d40_command command)
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{
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if (chan_is_logical(d40c))
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return __d40_execute_command_log(d40c, command);
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else
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return __d40_execute_command_phy(d40c, command);
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}
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static u32 d40_get_prmo(struct d40_chan *d40c)
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{
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static const unsigned int phy_map[] = {
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@ -1149,15 +1271,7 @@ static int d40_pause(struct d40_chan *d40c)
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spin_lock_irqsave(&d40c->lock, flags);
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res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
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if (res == 0) {
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if (chan_is_logical(d40c)) {
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d40_config_set_event(d40c, false);
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/* Resume the other logical channels if any */
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if (d40_chan_has_events(d40c))
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res = d40_channel_execute_command(d40c,
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D40_DMA_RUN);
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}
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}
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pm_runtime_mark_last_busy(d40c->base->dev);
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pm_runtime_put_autosuspend(d40c->base->dev);
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spin_unlock_irqrestore(&d40c->lock, flags);
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@ -1174,45 +1288,17 @@ static int d40_resume(struct d40_chan *d40c)
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spin_lock_irqsave(&d40c->lock, flags);
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pm_runtime_get_sync(d40c->base->dev);
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if (d40c->base->rev == 0)
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if (chan_is_logical(d40c)) {
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res = d40_channel_execute_command(d40c,
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D40_DMA_SUSPEND_REQ);
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goto no_suspend;
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}
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/* If bytes left to transfer or linked tx resume job */
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if (d40_residue(d40c) || d40_tx_is_linked(d40c)) {
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if (chan_is_logical(d40c))
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d40_config_set_event(d40c, true);
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if (d40_residue(d40c) || d40_tx_is_linked(d40c))
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res = d40_channel_execute_command(d40c, D40_DMA_RUN);
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}
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no_suspend:
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pm_runtime_mark_last_busy(d40c->base->dev);
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pm_runtime_put_autosuspend(d40c->base->dev);
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spin_unlock_irqrestore(&d40c->lock, flags);
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return res;
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}
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static int d40_terminate_all(struct d40_chan *chan)
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{
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unsigned long flags;
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int ret = 0;
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ret = d40_pause(chan);
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if (!ret && chan_is_physical(chan))
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ret = d40_channel_execute_command(chan, D40_DMA_STOP);
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spin_lock_irqsave(&chan->lock, flags);
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d40_term_all(chan);
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spin_unlock_irqrestore(&chan->lock, flags);
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return ret;
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}
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static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
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{
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struct d40_chan *d40c = container_of(tx->chan,
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@ -1232,20 +1318,6 @@ static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
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static int d40_start(struct d40_chan *d40c)
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{
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if (d40c->base->rev == 0) {
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int err;
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if (chan_is_logical(d40c)) {
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err = d40_channel_execute_command(d40c,
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D40_DMA_SUSPEND_REQ);
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if (err)
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return err;
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}
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}
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if (chan_is_logical(d40c))
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d40_config_set_event(d40c, true);
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return d40_channel_execute_command(d40c, D40_DMA_RUN);
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}
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@ -1258,10 +1330,10 @@ static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
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d40d = d40_first_queued(d40c);
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if (d40d != NULL) {
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if (!d40c->busy)
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if (!d40c->busy) {
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d40c->busy = true;
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pm_runtime_get_sync(d40c->base->dev);
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pm_runtime_get_sync(d40c->base->dev);
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}
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/* Remove from queue */
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d40_desc_remove(d40d);
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@ -1388,8 +1460,8 @@ static void dma_tasklet(unsigned long data)
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return;
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err:
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/* Rescue manoeuvre if receiving double interrupts */
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err:
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/* Rescue manouver if receiving double interrupts */
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if (d40c->pending_tx > 0)
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d40c->pending_tx--;
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spin_unlock_irqrestore(&d40c->lock, flags);
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@ -1770,7 +1842,6 @@ static int d40_config_memcpy(struct d40_chan *d40c)
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return 0;
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}
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static int d40_free_dma(struct d40_chan *d40c)
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{
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@ -1806,44 +1877,19 @@ static int d40_free_dma(struct d40_chan *d40c)
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}
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pm_runtime_get_sync(d40c->base->dev);
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res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
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if (res) {
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chan_err(d40c, "suspend failed\n");
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goto out;
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}
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if (chan_is_logical(d40c)) {
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/* Release logical channel, deactivate the event line */
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d40_config_set_event(d40c, false);
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d40c->base->lookup_log_chans[d40c->log_num] = NULL;
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/*
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* Check if there are more logical allocation
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* on this phy channel.
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*/
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if (!d40_alloc_mask_free(phy, is_src, event)) {
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/* Resume the other logical channels if any */
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if (d40_chan_has_events(d40c)) {
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res = d40_channel_execute_command(d40c,
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D40_DMA_RUN);
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if (res)
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chan_err(d40c,
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"Executing RUN command\n");
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}
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goto out;
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}
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} else {
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(void) d40_alloc_mask_free(phy, is_src, 0);
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}
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/* Release physical channel */
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res = d40_channel_execute_command(d40c, D40_DMA_STOP);
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if (res) {
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chan_err(d40c, "Failed to stop channel\n");
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chan_err(d40c, "stop failed\n");
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goto out;
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}
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d40_alloc_mask_free(phy, is_src, chan_is_logical(d40c) ? event : 0);
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if (chan_is_logical(d40c))
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d40c->base->lookup_log_chans[d40c->log_num] = NULL;
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else
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d40c->base->lookup_phy_chans[phy->num] = NULL;
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if (d40c->busy) {
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pm_runtime_mark_last_busy(d40c->base->dev);
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pm_runtime_put_autosuspend(d40c->base->dev);
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@ -1852,7 +1898,6 @@ static int d40_free_dma(struct d40_chan *d40c)
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d40c->busy = false;
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d40c->phy_chan = NULL;
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d40c->configured = false;
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d40c->base->lookup_phy_chans[phy->num] = NULL;
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out:
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pm_runtime_mark_last_busy(d40c->base->dev);
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@ -2371,6 +2416,31 @@ static void d40_issue_pending(struct dma_chan *chan)
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spin_unlock_irqrestore(&d40c->lock, flags);
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}
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static void d40_terminate_all(struct dma_chan *chan)
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{
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unsigned long flags;
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struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
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int ret;
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spin_lock_irqsave(&d40c->lock, flags);
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pm_runtime_get_sync(d40c->base->dev);
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||||
ret = d40_channel_execute_command(d40c, D40_DMA_STOP);
|
||||
if (ret)
|
||||
chan_err(d40c, "Failed to stop channel\n");
|
||||
|
||||
d40_term_all(d40c);
|
||||
pm_runtime_mark_last_busy(d40c->base->dev);
|
||||
pm_runtime_put_autosuspend(d40c->base->dev);
|
||||
if (d40c->busy) {
|
||||
pm_runtime_mark_last_busy(d40c->base->dev);
|
||||
pm_runtime_put_autosuspend(d40c->base->dev);
|
||||
}
|
||||
d40c->busy = false;
|
||||
|
||||
spin_unlock_irqrestore(&d40c->lock, flags);
|
||||
}
|
||||
|
||||
static int
|
||||
dma40_config_to_halfchannel(struct d40_chan *d40c,
|
||||
struct stedma40_half_channel_info *info,
|
||||
|
|
@ -2551,7 +2621,8 @@ static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
|
|||
|
||||
switch (cmd) {
|
||||
case DMA_TERMINATE_ALL:
|
||||
return d40_terminate_all(d40c);
|
||||
d40_terminate_all(chan);
|
||||
return 0;
|
||||
case DMA_PAUSE:
|
||||
return d40_pause(d40c);
|
||||
case DMA_RESUME:
|
||||
|
|
@ -2908,6 +2979,12 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
|
|||
dev_info(&pdev->dev, "hardware revision: %d @ 0x%x\n",
|
||||
rev, res->start);
|
||||
|
||||
if (rev < 2) {
|
||||
d40_err(&pdev->dev, "hardware revision: %d is not supported",
|
||||
rev);
|
||||
goto failure;
|
||||
}
|
||||
|
||||
plat_data = pdev->dev.platform_data;
|
||||
|
||||
/* Count the number of logical channels in use */
|
||||
|
|
@ -2998,6 +3075,7 @@ failure:
|
|||
|
||||
if (base) {
|
||||
kfree(base->lcla_pool.alloc_map);
|
||||
kfree(base->reg_val_backup_chan);
|
||||
kfree(base->lookup_log_chans);
|
||||
kfree(base->lookup_phy_chans);
|
||||
kfree(base->phy_res);
|
||||
|
|
|
|||
|
|
@ -62,8 +62,6 @@
|
|||
#define D40_SREG_ELEM_LOG_LIDX_MASK (0xFF << D40_SREG_ELEM_LOG_LIDX_POS)
|
||||
|
||||
/* Link register */
|
||||
#define D40_DEACTIVATE_EVENTLINE 0x0
|
||||
#define D40_ACTIVATE_EVENTLINE 0x1
|
||||
#define D40_EVENTLINE_POS(i) (2 * i)
|
||||
#define D40_EVENTLINE_MASK(i) (0x3 << D40_EVENTLINE_POS(i))
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue