arm64: percpu: rewrite ll/sc loops in assembly
Writing the outer loop of an LL/SC sequence using do {...} while
constructs potentially allows the compiler to hoist memory accesses
between the STXR and the branch back to the LDXR. On CPUs that do not
guarantee forward progress of LL/SC loops when faced with memory
accesses to the same ERG (up to 2k) between the failed STXR and the
branch back, we may end up livelocking.
This patch avoids this issue in our percpu atomics by rewriting the
outer loop as part of the LL/SC inline assembly block.
Cc: <stable@vger.kernel.org>
Fixes: f97fc81079 ("arm64: percpu: Implement this_cpu operations")
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Will Deacon
parent
1c5b51dfb7
commit
1e6e57d9b3
1 changed files with 56 additions and 64 deletions
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@ -44,48 +44,44 @@ static inline unsigned long __percpu_##op(void *ptr, \
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\
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switch (size) { \
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case 1: \
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do { \
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asm ("//__per_cpu_" #op "_1\n" \
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"ldxrb %w[ret], %[ptr]\n" \
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asm ("//__per_cpu_" #op "_1\n" \
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"1: ldxrb %w[ret], %[ptr]\n" \
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#asm_op " %w[ret], %w[ret], %w[val]\n" \
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"stxrb %w[loop], %w[ret], %[ptr]\n" \
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: [loop] "=&r" (loop), [ret] "=&r" (ret), \
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[ptr] "+Q"(*(u8 *)ptr) \
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: [val] "Ir" (val)); \
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} while (loop); \
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" stxrb %w[loop], %w[ret], %[ptr]\n" \
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" cbnz %w[loop], 1b" \
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: [loop] "=&r" (loop), [ret] "=&r" (ret), \
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[ptr] "+Q"(*(u8 *)ptr) \
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: [val] "Ir" (val)); \
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break; \
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case 2: \
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do { \
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asm ("//__per_cpu_" #op "_2\n" \
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"ldxrh %w[ret], %[ptr]\n" \
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asm ("//__per_cpu_" #op "_2\n" \
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"1: ldxrh %w[ret], %[ptr]\n" \
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#asm_op " %w[ret], %w[ret], %w[val]\n" \
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"stxrh %w[loop], %w[ret], %[ptr]\n" \
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: [loop] "=&r" (loop), [ret] "=&r" (ret), \
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[ptr] "+Q"(*(u16 *)ptr) \
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: [val] "Ir" (val)); \
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} while (loop); \
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" stxrh %w[loop], %w[ret], %[ptr]\n" \
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" cbnz %w[loop], 1b" \
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: [loop] "=&r" (loop), [ret] "=&r" (ret), \
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[ptr] "+Q"(*(u16 *)ptr) \
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: [val] "Ir" (val)); \
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break; \
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case 4: \
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do { \
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asm ("//__per_cpu_" #op "_4\n" \
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"ldxr %w[ret], %[ptr]\n" \
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asm ("//__per_cpu_" #op "_4\n" \
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"1: ldxr %w[ret], %[ptr]\n" \
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#asm_op " %w[ret], %w[ret], %w[val]\n" \
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"stxr %w[loop], %w[ret], %[ptr]\n" \
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: [loop] "=&r" (loop), [ret] "=&r" (ret), \
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[ptr] "+Q"(*(u32 *)ptr) \
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: [val] "Ir" (val)); \
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} while (loop); \
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" stxr %w[loop], %w[ret], %[ptr]\n" \
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" cbnz %w[loop], 1b" \
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: [loop] "=&r" (loop), [ret] "=&r" (ret), \
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[ptr] "+Q"(*(u32 *)ptr) \
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: [val] "Ir" (val)); \
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break; \
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case 8: \
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do { \
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asm ("//__per_cpu_" #op "_8\n" \
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"ldxr %[ret], %[ptr]\n" \
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asm ("//__per_cpu_" #op "_8\n" \
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"1: ldxr %[ret], %[ptr]\n" \
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#asm_op " %[ret], %[ret], %[val]\n" \
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"stxr %w[loop], %[ret], %[ptr]\n" \
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: [loop] "=&r" (loop), [ret] "=&r" (ret), \
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[ptr] "+Q"(*(u64 *)ptr) \
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: [val] "Ir" (val)); \
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} while (loop); \
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" stxr %w[loop], %[ret], %[ptr]\n" \
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" cbnz %w[loop], 1b" \
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: [loop] "=&r" (loop), [ret] "=&r" (ret), \
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[ptr] "+Q"(*(u64 *)ptr) \
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: [val] "Ir" (val)); \
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break; \
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default: \
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BUILD_BUG(); \
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@ -150,44 +146,40 @@ static inline unsigned long __percpu_xchg(void *ptr, unsigned long val,
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switch (size) {
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case 1:
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do {
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asm ("//__percpu_xchg_1\n"
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"ldxrb %w[ret], %[ptr]\n"
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"stxrb %w[loop], %w[val], %[ptr]\n"
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: [loop] "=&r"(loop), [ret] "=&r"(ret),
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[ptr] "+Q"(*(u8 *)ptr)
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: [val] "r" (val));
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} while (loop);
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asm ("//__percpu_xchg_1\n"
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"1: ldxrb %w[ret], %[ptr]\n"
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" stxrb %w[loop], %w[val], %[ptr]\n"
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" cbnz %w[loop], 1b"
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: [loop] "=&r"(loop), [ret] "=&r"(ret),
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[ptr] "+Q"(*(u8 *)ptr)
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: [val] "r" (val));
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break;
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case 2:
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do {
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asm ("//__percpu_xchg_2\n"
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"ldxrh %w[ret], %[ptr]\n"
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"stxrh %w[loop], %w[val], %[ptr]\n"
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: [loop] "=&r"(loop), [ret] "=&r"(ret),
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[ptr] "+Q"(*(u16 *)ptr)
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: [val] "r" (val));
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} while (loop);
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asm ("//__percpu_xchg_2\n"
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"1: ldxrh %w[ret], %[ptr]\n"
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" stxrh %w[loop], %w[val], %[ptr]\n"
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" cbnz %w[loop], 1b"
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: [loop] "=&r"(loop), [ret] "=&r"(ret),
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[ptr] "+Q"(*(u16 *)ptr)
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: [val] "r" (val));
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break;
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case 4:
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do {
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asm ("//__percpu_xchg_4\n"
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"ldxr %w[ret], %[ptr]\n"
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"stxr %w[loop], %w[val], %[ptr]\n"
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: [loop] "=&r"(loop), [ret] "=&r"(ret),
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[ptr] "+Q"(*(u32 *)ptr)
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: [val] "r" (val));
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} while (loop);
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asm ("//__percpu_xchg_4\n"
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"1: ldxr %w[ret], %[ptr]\n"
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" stxr %w[loop], %w[val], %[ptr]\n"
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" cbnz %w[loop], 1b"
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: [loop] "=&r"(loop), [ret] "=&r"(ret),
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[ptr] "+Q"(*(u32 *)ptr)
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: [val] "r" (val));
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break;
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case 8:
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do {
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asm ("//__percpu_xchg_8\n"
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"ldxr %[ret], %[ptr]\n"
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"stxr %w[loop], %[val], %[ptr]\n"
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: [loop] "=&r"(loop), [ret] "=&r"(ret),
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[ptr] "+Q"(*(u64 *)ptr)
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: [val] "r" (val));
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} while (loop);
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asm ("//__percpu_xchg_8\n"
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"1: ldxr %[ret], %[ptr]\n"
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" stxr %w[loop], %[val], %[ptr]\n"
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" cbnz %w[loop], 1b"
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: [loop] "=&r"(loop), [ret] "=&r"(ret),
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[ptr] "+Q"(*(u64 *)ptr)
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: [val] "r" (val));
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break;
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default:
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BUILD_BUG();
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