Merge branch 'spi/next' of git://git.secretlab.ca/git/linux-2.6
* 'spi/next' of git://git.secretlab.ca/git/linux-2.6: spi/amba-pl022: work in polling or interrupt mode if pl022_dma_probe fails spi/spi_s3c24xx: Use spi_bitbang_stop instead of spi_unregister_master in s3c24xx_spi_remove spi/spi_nuc900: Use spi_bitbang_stop instead of spi_unregister_master in nuc900_spi_remove spi/spi_tegra: use spi_unregister_master() instead of spi_master_put() spi/spi_sh: use spi_unregister_master instead of spi_master_put in remove path spi: Use void pointers for data in simple SPI I/O operations spi/pl022: use cpu_relax in the busy loop spi/pl022: mark driver non-experimental spi/pl022: timeout on polled transfer v2 spi/dw_spi: improve the interrupt mode with the batch ops spi/dw_spi: change poll mode transfer from byte ops to batch ops spi/dw_spi: remove the un-necessary flush() spi/dw_spi: unify the low level read/write routines
This commit is contained in:
Linus Torvalds
commit
20e0ec119b
10 changed files with 111 additions and 174 deletions
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@ -271,8 +271,8 @@ config SPI_ORION
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This enables using the SPI master controller on the Orion chips.
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config SPI_PL022
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tristate "ARM AMBA PL022 SSP controller (EXPERIMENTAL)"
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depends on ARM_AMBA && EXPERIMENTAL
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tristate "ARM AMBA PL022 SSP controller"
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depends on ARM_AMBA
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default y if MACH_U300
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default y if ARCH_REALVIEW
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default y if INTEGRATOR_IMPD1
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@ -24,11 +24,6 @@
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* GNU General Public License for more details.
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*/
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/*
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* TODO:
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* - add timeout on polled transfers
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/device.h>
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@ -287,6 +282,8 @@
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#define CLEAR_ALL_INTERRUPTS 0x3
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#define SPI_POLLING_TIMEOUT 1000
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/*
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* The type of reading going on on this chip
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@ -1063,7 +1060,7 @@ static int __init pl022_dma_probe(struct pl022 *pl022)
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pl022->master_info->dma_filter,
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pl022->master_info->dma_rx_param);
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if (!pl022->dma_rx_channel) {
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dev_err(&pl022->adev->dev, "no RX DMA channel!\n");
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dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n");
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goto err_no_rxchan;
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}
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@ -1071,13 +1068,13 @@ static int __init pl022_dma_probe(struct pl022 *pl022)
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pl022->master_info->dma_filter,
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pl022->master_info->dma_tx_param);
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if (!pl022->dma_tx_channel) {
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dev_err(&pl022->adev->dev, "no TX DMA channel!\n");
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dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n");
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goto err_no_txchan;
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}
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pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
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if (!pl022->dummypage) {
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dev_err(&pl022->adev->dev, "no DMA dummypage!\n");
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dev_dbg(&pl022->adev->dev, "no DMA dummypage!\n");
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goto err_no_dummypage;
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}
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@ -1093,6 +1090,8 @@ err_no_txchan:
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dma_release_channel(pl022->dma_rx_channel);
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pl022->dma_rx_channel = NULL;
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err_no_rxchan:
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dev_err(&pl022->adev->dev,
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"Failed to work in dma mode, work without dma!\n");
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return -ENODEV;
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}
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@ -1378,6 +1377,7 @@ static void do_polling_transfer(struct pl022 *pl022)
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struct spi_transfer *transfer = NULL;
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struct spi_transfer *previous = NULL;
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struct chip_data *chip;
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unsigned long time, timeout;
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chip = pl022->cur_chip;
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message = pl022->cur_msg;
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@ -1415,9 +1415,19 @@ static void do_polling_transfer(struct pl022 *pl022)
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SSP_CR1(pl022->virtbase));
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dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n");
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/* FIXME: insert a timeout so we don't hang here indefinitely */
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while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end)
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timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT);
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while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) {
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time = jiffies;
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readwriter(pl022);
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if (time_after(time, timeout)) {
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dev_warn(&pl022->adev->dev,
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"%s: timeout!\n", __func__);
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message->state = STATE_ERROR;
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goto out;
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}
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cpu_relax();
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}
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/* Update total byte transferred */
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message->actual_length += pl022->cur_transfer->len;
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@ -1426,7 +1436,7 @@ static void do_polling_transfer(struct pl022 *pl022)
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/* Move to next transfer */
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message->state = next_transfer(pl022);
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}
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out:
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/* Handle end of message */
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if (message->state == STATE_DONE)
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message->status = 0;
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@ -2107,7 +2117,7 @@ pl022_probe(struct amba_device *adev, const struct amba_id *id)
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if (platform_info->enable_dma) {
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status = pl022_dma_probe(pl022);
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if (status != 0)
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goto err_no_dma;
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platform_info->enable_dma = 0;
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}
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/* Initialize and start queue */
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@ -2143,7 +2153,6 @@ pl022_probe(struct amba_device *adev, const struct amba_id *id)
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err_init_queue:
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destroy_queue(pl022);
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pl022_dma_remove(pl022);
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err_no_dma:
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free_irq(adev->irq[0], pl022);
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err_no_irq:
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clk_put(pl022->clk);
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@ -58,8 +58,6 @@ struct chip_data {
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u8 bits_per_word;
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u16 clk_div; /* baud rate divider */
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u32 speed_hz; /* baud rate */
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int (*write)(struct dw_spi *dws);
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int (*read)(struct dw_spi *dws);
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void (*cs_control)(u32 command);
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};
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@ -162,107 +160,70 @@ static inline void mrst_spi_debugfs_remove(struct dw_spi *dws)
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}
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#endif /* CONFIG_DEBUG_FS */
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static void wait_till_not_busy(struct dw_spi *dws)
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/* Return the max entries we can fill into tx fifo */
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static inline u32 tx_max(struct dw_spi *dws)
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{
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unsigned long end = jiffies + 1 + usecs_to_jiffies(5000);
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u32 tx_left, tx_room, rxtx_gap;
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while (time_before(jiffies, end)) {
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if (!(dw_readw(dws, sr) & SR_BUSY))
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return;
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cpu_relax();
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tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
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tx_room = dws->fifo_len - dw_readw(dws, txflr);
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/*
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* Another concern is about the tx/rx mismatch, we
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* though to use (dws->fifo_len - rxflr - txflr) as
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* one maximum value for tx, but it doesn't cover the
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* data which is out of tx/rx fifo and inside the
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* shift registers. So a control from sw point of
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* view is taken.
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*/
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rxtx_gap = ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
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/ dws->n_bytes;
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return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
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}
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/* Return the max entries we should read out of rx fifo */
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static inline u32 rx_max(struct dw_spi *dws)
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{
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u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
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return min(rx_left, (u32)dw_readw(dws, rxflr));
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}
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static void dw_writer(struct dw_spi *dws)
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{
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u32 max = tx_max(dws);
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u16 txw = 0;
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while (max--) {
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/* Set the tx word if the transfer's original "tx" is not null */
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if (dws->tx_end - dws->len) {
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if (dws->n_bytes == 1)
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txw = *(u8 *)(dws->tx);
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else
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txw = *(u16 *)(dws->tx);
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}
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dw_writew(dws, dr, txw);
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dws->tx += dws->n_bytes;
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}
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dev_err(&dws->master->dev,
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"DW SPI: Status keeps busy for 5000us after a read/write!\n");
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}
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static void flush(struct dw_spi *dws)
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static void dw_reader(struct dw_spi *dws)
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{
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while (dw_readw(dws, sr) & SR_RF_NOT_EMPT) {
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dw_readw(dws, dr);
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cpu_relax();
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u32 max = rx_max(dws);
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u16 rxw;
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while (max--) {
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rxw = dw_readw(dws, dr);
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/* Care rx only if the transfer's original "rx" is not null */
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if (dws->rx_end - dws->len) {
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if (dws->n_bytes == 1)
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*(u8 *)(dws->rx) = rxw;
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else
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*(u16 *)(dws->rx) = rxw;
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}
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dws->rx += dws->n_bytes;
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}
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wait_till_not_busy(dws);
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}
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static int null_writer(struct dw_spi *dws)
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{
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u8 n_bytes = dws->n_bytes;
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if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
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|| (dws->tx == dws->tx_end))
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return 0;
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dw_writew(dws, dr, 0);
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dws->tx += n_bytes;
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wait_till_not_busy(dws);
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return 1;
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}
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static int null_reader(struct dw_spi *dws)
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{
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u8 n_bytes = dws->n_bytes;
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while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
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&& (dws->rx < dws->rx_end)) {
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dw_readw(dws, dr);
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dws->rx += n_bytes;
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}
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wait_till_not_busy(dws);
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return dws->rx == dws->rx_end;
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}
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static int u8_writer(struct dw_spi *dws)
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{
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if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
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|| (dws->tx == dws->tx_end))
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return 0;
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dw_writew(dws, dr, *(u8 *)(dws->tx));
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++dws->tx;
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wait_till_not_busy(dws);
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return 1;
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}
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static int u8_reader(struct dw_spi *dws)
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{
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while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
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&& (dws->rx < dws->rx_end)) {
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*(u8 *)(dws->rx) = dw_readw(dws, dr);
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++dws->rx;
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}
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wait_till_not_busy(dws);
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return dws->rx == dws->rx_end;
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}
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static int u16_writer(struct dw_spi *dws)
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{
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if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
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|| (dws->tx == dws->tx_end))
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return 0;
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dw_writew(dws, dr, *(u16 *)(dws->tx));
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dws->tx += 2;
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wait_till_not_busy(dws);
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return 1;
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}
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static int u16_reader(struct dw_spi *dws)
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{
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u16 temp;
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while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
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&& (dws->rx < dws->rx_end)) {
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temp = dw_readw(dws, dr);
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*(u16 *)(dws->rx) = temp;
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dws->rx += 2;
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}
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wait_till_not_busy(dws);
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return dws->rx == dws->rx_end;
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}
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static void *next_transfer(struct dw_spi *dws)
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@ -334,8 +295,7 @@ static void giveback(struct dw_spi *dws)
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static void int_error_stop(struct dw_spi *dws, const char *msg)
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{
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/* Stop and reset hw */
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flush(dws);
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/* Stop the hw */
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spi_enable_chip(dws, 0);
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dev_err(&dws->master->dev, "%s\n", msg);
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@ -362,35 +322,28 @@ EXPORT_SYMBOL_GPL(dw_spi_xfer_done);
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static irqreturn_t interrupt_transfer(struct dw_spi *dws)
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{
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u16 irq_status, irq_mask = 0x3f;
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u32 int_level = dws->fifo_len / 2;
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u32 left;
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u16 irq_status = dw_readw(dws, isr);
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irq_status = dw_readw(dws, isr) & irq_mask;
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/* Error handling */
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if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
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dw_readw(dws, txoicr);
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dw_readw(dws, rxoicr);
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dw_readw(dws, rxuicr);
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int_error_stop(dws, "interrupt_transfer: fifo overrun");
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int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
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return IRQ_HANDLED;
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}
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dw_reader(dws);
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if (dws->rx_end == dws->rx) {
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spi_mask_intr(dws, SPI_INT_TXEI);
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dw_spi_xfer_done(dws);
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return IRQ_HANDLED;
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}
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if (irq_status & SPI_INT_TXEI) {
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spi_mask_intr(dws, SPI_INT_TXEI);
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left = (dws->tx_end - dws->tx) / dws->n_bytes;
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left = (left > int_level) ? int_level : left;
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while (left--)
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dws->write(dws);
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dws->read(dws);
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/* Re-enable the IRQ if there is still data left to tx */
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if (dws->tx_end > dws->tx)
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spi_umask_intr(dws, SPI_INT_TXEI);
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else
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dw_spi_xfer_done(dws);
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dw_writer(dws);
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/* Enable TX irq always, it will be disabled when RX finished */
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spi_umask_intr(dws, SPI_INT_TXEI);
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}
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return IRQ_HANDLED;
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@ -399,15 +352,13 @@ static irqreturn_t interrupt_transfer(struct dw_spi *dws)
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static irqreturn_t dw_spi_irq(int irq, void *dev_id)
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{
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struct dw_spi *dws = dev_id;
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u16 irq_status, irq_mask = 0x3f;
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u16 irq_status = dw_readw(dws, isr) & 0x3f;
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irq_status = dw_readw(dws, isr) & irq_mask;
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if (!irq_status)
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return IRQ_NONE;
|
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|
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if (!dws->cur_msg) {
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spi_mask_intr(dws, SPI_INT_TXEI);
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/* Never fail */
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return IRQ_HANDLED;
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}
|
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|
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|
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@ -417,13 +368,11 @@ static irqreturn_t dw_spi_irq(int irq, void *dev_id)
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/* Must be called inside pump_transfers() */
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static void poll_transfer(struct dw_spi *dws)
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{
|
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while (dws->write(dws))
|
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dws->read(dws);
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/*
|
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* There is a possibility that the last word of a transaction
|
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* will be lost if data is not ready. Re-read to solve this issue.
|
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*/
|
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dws->read(dws);
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do {
|
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dw_writer(dws);
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dw_reader(dws);
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cpu_relax();
|
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} while (dws->rx_end > dws->rx);
|
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|
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dw_spi_xfer_done(dws);
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}
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|
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@ -483,8 +432,6 @@ static void pump_transfers(unsigned long data)
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dws->tx_end = dws->tx + transfer->len;
|
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dws->rx = transfer->rx_buf;
|
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dws->rx_end = dws->rx + transfer->len;
|
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dws->write = dws->tx ? chip->write : null_writer;
|
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dws->read = dws->rx ? chip->read : null_reader;
|
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dws->cs_change = transfer->cs_change;
|
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dws->len = dws->cur_transfer->len;
|
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if (chip != dws->prev_chip)
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|
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@ -518,20 +465,8 @@ static void pump_transfers(unsigned long data)
|
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|
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switch (bits) {
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case 8:
|
||||
dws->n_bytes = 1;
|
||||
dws->dma_width = 1;
|
||||
dws->read = (dws->read != null_reader) ?
|
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u8_reader : null_reader;
|
||||
dws->write = (dws->write != null_writer) ?
|
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u8_writer : null_writer;
|
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break;
|
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case 16:
|
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dws->n_bytes = 2;
|
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dws->dma_width = 2;
|
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dws->read = (dws->read != null_reader) ?
|
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u16_reader : null_reader;
|
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dws->write = (dws->write != null_writer) ?
|
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u16_writer : null_writer;
|
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dws->n_bytes = dws->dma_width = bits >> 3;
|
||||
break;
|
||||
default:
|
||||
printk(KERN_ERR "MRST SPI0: unsupported bits:"
|
||||
|
|
@ -575,7 +510,7 @@ static void pump_transfers(unsigned long data)
|
|||
txint_level = dws->fifo_len / 2;
|
||||
txint_level = (templen > txint_level) ? txint_level : templen;
|
||||
|
||||
imask |= SPI_INT_TXEI;
|
||||
imask |= SPI_INT_TXEI | SPI_INT_TXOI | SPI_INT_RXUI | SPI_INT_RXOI;
|
||||
dws->transfer_handler = interrupt_transfer;
|
||||
}
|
||||
|
||||
|
|
@ -733,13 +668,9 @@ static int dw_spi_setup(struct spi_device *spi)
|
|||
if (spi->bits_per_word <= 8) {
|
||||
chip->n_bytes = 1;
|
||||
chip->dma_width = 1;
|
||||
chip->read = u8_reader;
|
||||
chip->write = u8_writer;
|
||||
} else if (spi->bits_per_word <= 16) {
|
||||
chip->n_bytes = 2;
|
||||
chip->dma_width = 2;
|
||||
chip->read = u16_reader;
|
||||
chip->write = u16_writer;
|
||||
} else {
|
||||
/* Never take >16b case for MRST SPIC */
|
||||
dev_err(&spi->dev, "invalid wordsize\n");
|
||||
|
|
@ -851,7 +782,6 @@ static void spi_hw_init(struct dw_spi *dws)
|
|||
spi_enable_chip(dws, 0);
|
||||
spi_mask_intr(dws, 0xff);
|
||||
spi_enable_chip(dws, 1);
|
||||
flush(dws);
|
||||
|
||||
/*
|
||||
* Try to detect the FIFO depth if not set by interface driver,
|
||||
|
|
|
|||
|
|
@ -137,8 +137,6 @@ struct dw_spi {
|
|||
u8 max_bits_per_word; /* maxim is 16b */
|
||||
u32 dma_width;
|
||||
int cs_change;
|
||||
int (*write)(struct dw_spi *dws);
|
||||
int (*read)(struct dw_spi *dws);
|
||||
irqreturn_t (*transfer_handler)(struct dw_spi *dws);
|
||||
void (*cs_control)(u32 command);
|
||||
|
||||
|
|
|
|||
|
|
@ -1047,8 +1047,8 @@ static u8 *buf;
|
|||
* spi_{async,sync}() calls with dma-safe buffers.
|
||||
*/
|
||||
int spi_write_then_read(struct spi_device *spi,
|
||||
const u8 *txbuf, unsigned n_tx,
|
||||
u8 *rxbuf, unsigned n_rx)
|
||||
const void *txbuf, unsigned n_tx,
|
||||
void *rxbuf, unsigned n_rx)
|
||||
{
|
||||
static DEFINE_MUTEX(lock);
|
||||
|
||||
|
|
|
|||
|
|
@ -463,7 +463,7 @@ static int __devexit nuc900_spi_remove(struct platform_device *dev)
|
|||
|
||||
platform_set_drvdata(dev, NULL);
|
||||
|
||||
spi_unregister_master(hw->master);
|
||||
spi_bitbang_stop(&hw->bitbang);
|
||||
|
||||
clk_disable(hw->clk);
|
||||
clk_put(hw->clk);
|
||||
|
|
|
|||
|
|
@ -668,7 +668,7 @@ static int __exit s3c24xx_spi_remove(struct platform_device *dev)
|
|||
|
||||
platform_set_drvdata(dev, NULL);
|
||||
|
||||
spi_unregister_master(hw->master);
|
||||
spi_bitbang_stop(&hw->bitbang);
|
||||
|
||||
clk_disable(hw->clk);
|
||||
clk_put(hw->clk);
|
||||
|
|
|
|||
|
|
@ -427,10 +427,10 @@ static int __devexit spi_sh_remove(struct platform_device *pdev)
|
|||
{
|
||||
struct spi_sh_data *ss = dev_get_drvdata(&pdev->dev);
|
||||
|
||||
spi_unregister_master(ss->master);
|
||||
destroy_workqueue(ss->workqueue);
|
||||
free_irq(ss->irq, ss);
|
||||
iounmap(ss->addr);
|
||||
spi_master_put(ss->master);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -578,6 +578,7 @@ static int __devexit spi_tegra_remove(struct platform_device *pdev)
|
|||
master = dev_get_drvdata(&pdev->dev);
|
||||
tspi = spi_master_get_devdata(master);
|
||||
|
||||
spi_unregister_master(master);
|
||||
tegra_dma_free_channel(tspi->rx_dma);
|
||||
|
||||
dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
|
||||
|
|
@ -586,7 +587,6 @@ static int __devexit spi_tegra_remove(struct platform_device *pdev)
|
|||
clk_put(tspi->clk);
|
||||
iounmap(tspi->base);
|
||||
|
||||
spi_master_put(master);
|
||||
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
release_mem_region(r->start, (r->end - r->start) + 1);
|
||||
|
||||
|
|
|
|||
|
|
@ -581,7 +581,7 @@ extern int spi_bus_unlock(struct spi_master *master);
|
|||
* Callable only from contexts that can sleep.
|
||||
*/
|
||||
static inline int
|
||||
spi_write(struct spi_device *spi, const u8 *buf, size_t len)
|
||||
spi_write(struct spi_device *spi, const void *buf, size_t len)
|
||||
{
|
||||
struct spi_transfer t = {
|
||||
.tx_buf = buf,
|
||||
|
|
@ -605,7 +605,7 @@ spi_write(struct spi_device *spi, const u8 *buf, size_t len)
|
|||
* Callable only from contexts that can sleep.
|
||||
*/
|
||||
static inline int
|
||||
spi_read(struct spi_device *spi, u8 *buf, size_t len)
|
||||
spi_read(struct spi_device *spi, void *buf, size_t len)
|
||||
{
|
||||
struct spi_transfer t = {
|
||||
.rx_buf = buf,
|
||||
|
|
@ -620,8 +620,8 @@ spi_read(struct spi_device *spi, u8 *buf, size_t len)
|
|||
|
||||
/* this copies txbuf and rxbuf data; for small transfers only! */
|
||||
extern int spi_write_then_read(struct spi_device *spi,
|
||||
const u8 *txbuf, unsigned n_tx,
|
||||
u8 *rxbuf, unsigned n_rx);
|
||||
const void *txbuf, unsigned n_tx,
|
||||
void *rxbuf, unsigned n_rx);
|
||||
|
||||
/**
|
||||
* spi_w8r8 - SPI synchronous 8 bit write followed by 8 bit read
|
||||
|
|
|
|||
Loading…
Reference in a new issue