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drm/amdgpu: Make max_pfn 64-bit

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With 4-level page tables the maximum VM size is 256TB. That's 64G
pages, which can't be represented in 32-bit.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Felix Kuehling 2017-03-28 20:24:53 -04:00 committed by Alex Deucher
parent 43e669d65e
commit 22770e5a75
4 changed files with 9 additions and 7 deletions
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4
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
View file

@ -336,7 +336,7 @@ int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
struct amdgpu_vm *vm,
uint64_t saddr, uint64_t size)
{
unsigned last_pfn;
uint64_t last_pfn;
uint64_t eaddr;
/* validate the parameters */
@ -346,7 +346,7 @@ int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
eaddr = saddr + size - 1;
last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE;
if (last_pfn >= adev->vm_manager.max_pfn) {
dev_err(adev->dev, "va above limit (0x%08X >= 0x%08X)\n",
dev_err(adev->dev, "va above limit (0x%08llX >= 0x%08llX)\n",
last_pfn, adev->vm_manager.max_pfn);
return -EINVAL;
}

2
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
View file

@ -153,7 +153,7 @@ struct amdgpu_vm_manager {
u64 fence_context;
unsigned seqno[AMDGPU_MAX_RINGS];
uint32_t max_pfn;
uint64_t max_pfn;
uint32_t num_level;
/* vram base address for page table entry */
u64 vram_base_offset;

5
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
View file

@ -227,8 +227,9 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32) + i*2, 0);
WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32) + i*2, 0);
WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32) + i*2,
adev->vm_manager.max_pfn - 1);
WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32) + i*2, 0);
lower_32_bits(adev->vm_manager.max_pfn - 1));
WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32) + i*2,
upper_32_bits(adev->vm_manager.max_pfn - 1));
}

5
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
View file

@ -247,8 +247,9 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32) + i*2, 0);
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32) + i*2, 0);
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32) + i*2,
adev->vm_manager.max_pfn - 1);
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32) + i*2, 0);
lower_32_bits(adev->vm_manager.max_pfn - 1));
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32) + i*2,
upper_32_bits(adev->vm_manager.max_pfn - 1));
}
return 0;